1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usb_mfunc.h> 51 #include <dev/usb/usb_error.h> 52 53 #define USB_DEBUG_VAR ehcidebug 54 55 #include <dev/usb/usb_core.h> 56 #include <dev/usb/usb_debug.h> 57 #include <dev/usb/usb_busdma.h> 58 #include <dev/usb/usb_process.h> 59 #include <dev/usb/usb_sw_transfer.h> 60 #include <dev/usb/usb_transfer.h> 61 #include <dev/usb/usb_device.h> 62 #include <dev/usb/usb_hub.h> 63 #include <dev/usb/usb_util.h> 64 65 #include <dev/usb/usb_controller.h> 66 #include <dev/usb/usb_bus.h> 67 #include <dev/usb/controller/ehci.h> 68 69 #define EHCI_BUS2SC(bus) \ 70 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 71 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 72 73 #if USB_DEBUG 74 static int ehcidebug = 0; 75 static int ehcinohighspeed = 0; 76 77 SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 78 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 79 &ehcidebug, 0, "Debug level"); 80 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 81 &ehcinohighspeed, 0, "Disable High Speed USB"); 82 83 static void ehci_dump_regs(ehci_softc_t *sc); 84 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 85 86 #endif 87 88 #define EHCI_INTR_ENDPT 1 89 90 extern struct usb2_bus_methods ehci_bus_methods; 91 extern struct usb2_pipe_methods ehci_device_bulk_methods; 92 extern struct usb2_pipe_methods ehci_device_ctrl_methods; 93 extern struct usb2_pipe_methods ehci_device_intr_methods; 94 extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 95 extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 96 extern struct usb2_pipe_methods ehci_root_ctrl_methods; 97 extern struct usb2_pipe_methods ehci_root_intr_methods; 98 99 static void ehci_do_poll(struct usb2_bus *bus); 100 static void ehci_root_ctrl_poll(ehci_softc_t *sc); 101 static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 103 static void ehci_timeout(void *arg); 104 105 static usb2_sw_transfer_func_t ehci_root_intr_done; 106 static usb2_sw_transfer_func_t ehci_root_ctrl_done; 107 108 struct ehci_std_temp { 109 ehci_softc_t *sc; 110 struct usb2_page_cache *pc; 111 ehci_qtd_t *td; 112 ehci_qtd_t *td_next; 113 uint32_t average; 114 uint32_t qtd_status; 115 uint32_t len; 116 uint16_t max_frame_size; 117 uint8_t shortpkt; 118 uint8_t auto_data_toggle; 119 uint8_t setup_alt_next; 120 uint8_t last_frame; 121 }; 122 123 void 124 ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 125 { 126 ehci_softc_t *sc = EHCI_BUS2SC(bus); 127 uint32_t i; 128 129 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 130 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 131 132 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 133 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 134 135 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 136 cb(bus, sc->sc_hw.intr_start_pc + i, 137 sc->sc_hw.intr_start_pg + i, 138 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 139 } 140 141 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 142 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 143 sc->sc_hw.isoc_hs_start_pg + i, 144 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 145 } 146 147 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 148 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 149 sc->sc_hw.isoc_fs_start_pg + i, 150 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 151 } 152 } 153 154 usb2_error_t 155 ehci_reset(ehci_softc_t *sc) 156 { 157 uint32_t hcr; 158 int i; 159 160 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 161 for (i = 0; i < 100; i++) { 162 usb2_pause_mtx(NULL, hz / 1000); 163 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 164 if (!hcr) { 165 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 166 /* 167 * Force USBMODE as requested. Controllers 168 * may have multiple operating modes. 169 */ 170 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 171 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 172 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 173 device_printf(sc->sc_bus.bdev, 174 "set host controller mode\n"); 175 } 176 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 177 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 178 device_printf(sc->sc_bus.bdev, 179 "set big-endian mode\n"); 180 } 181 EOWRITE4(sc, EHCI_USBMODE, usbmode); 182 } 183 return (0); 184 } 185 } 186 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 187 return (USB_ERR_IOERROR); 188 } 189 190 static usb2_error_t 191 ehci_hcreset(ehci_softc_t *sc) 192 { 193 uint32_t hcr; 194 int i; 195 196 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 197 for (i = 0; i < 100; i++) { 198 usb2_pause_mtx(NULL, hz / 1000); 199 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 200 if (hcr) 201 break; 202 } 203 if (!hcr) 204 /* 205 * Fall through and try reset anyway even though 206 * Table 2-9 in the EHCI spec says this will result 207 * in undefined behavior. 208 */ 209 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 210 211 return ehci_reset(sc); 212 } 213 214 usb2_error_t 215 ehci_init(ehci_softc_t *sc) 216 { 217 struct usb2_page_search buf_res; 218 uint32_t version; 219 uint32_t sparams; 220 uint32_t cparams; 221 uint32_t hcr; 222 uint16_t i; 223 uint16_t x; 224 uint16_t y; 225 uint16_t bit; 226 usb2_error_t err = 0; 227 228 DPRINTF("start\n"); 229 230 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 231 232 #if USB_DEBUG 233 if (ehcidebug > 2) { 234 ehci_dump_regs(sc); 235 } 236 #endif 237 238 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 239 240 version = EREAD2(sc, EHCI_HCIVERSION); 241 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 242 version >> 8, version & 0xff); 243 244 sparams = EREAD4(sc, EHCI_HCSPARAMS); 245 DPRINTF("sparams=0x%x\n", sparams); 246 247 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 248 cparams = EREAD4(sc, EHCI_HCCPARAMS); 249 DPRINTF("cparams=0x%x\n", cparams); 250 251 if (EHCI_HCC_64BIT(cparams)) { 252 DPRINTF("HCC uses 64-bit structures\n"); 253 254 /* MUST clear segment register if 64 bit capable */ 255 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 256 } 257 sc->sc_bus.usbrev = USB_REV_2_0; 258 259 /* Reset the controller */ 260 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 261 262 err = ehci_hcreset(sc); 263 if (err) { 264 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 265 return (err); 266 } 267 /* 268 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 269 * bytes 2: 256*4 bytes 3: unknown 270 */ 271 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 272 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 273 return (USB_ERR_IOERROR); 274 } 275 /* set up the bus struct */ 276 sc->sc_bus.methods = &ehci_bus_methods; 277 278 sc->sc_eintrs = EHCI_NORMAL_INTRS; 279 280 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 281 ehci_qh_t *qh; 282 283 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 284 285 qh = buf_res.buffer; 286 287 /* initialize page cache pointer */ 288 289 qh->page_cache = sc->sc_hw.intr_start_pc + i; 290 291 /* store a pointer to queue head */ 292 293 sc->sc_intr_p_last[i] = qh; 294 295 qh->qh_self = 296 htohc32(sc, buf_res.physaddr) | 297 htohc32(sc, EHCI_LINK_QH); 298 299 qh->qh_endp = 300 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 301 qh->qh_endphub = 302 htohc32(sc, EHCI_QH_SET_MULT(1)); 303 qh->qh_curqtd = 0; 304 305 qh->qh_qtd.qtd_next = 306 htohc32(sc, EHCI_LINK_TERMINATE); 307 qh->qh_qtd.qtd_altnext = 308 htohc32(sc, EHCI_LINK_TERMINATE); 309 qh->qh_qtd.qtd_status = 310 htohc32(sc, EHCI_QTD_HALTED); 311 } 312 313 /* 314 * the QHs are arranged to give poll intervals that are 315 * powers of 2 times 1ms 316 */ 317 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 318 while (bit) { 319 x = bit; 320 while (x & bit) { 321 ehci_qh_t *qh_x; 322 ehci_qh_t *qh_y; 323 324 y = (x ^ bit) | (bit / 2); 325 326 qh_x = sc->sc_intr_p_last[x]; 327 qh_y = sc->sc_intr_p_last[y]; 328 329 /* 330 * the next QH has half the poll interval 331 */ 332 qh_x->qh_link = qh_y->qh_self; 333 334 x++; 335 } 336 bit >>= 1; 337 } 338 339 if (1) { 340 ehci_qh_t *qh; 341 342 qh = sc->sc_intr_p_last[0]; 343 344 /* the last (1ms) QH terminates */ 345 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 346 } 347 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 348 ehci_sitd_t *sitd; 349 ehci_itd_t *itd; 350 351 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 352 353 sitd = buf_res.buffer; 354 355 /* initialize page cache pointer */ 356 357 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 358 359 /* store a pointer to the transfer descriptor */ 360 361 sc->sc_isoc_fs_p_last[i] = sitd; 362 363 /* initialize full speed isochronous */ 364 365 sitd->sitd_self = 366 htohc32(sc, buf_res.physaddr) | 367 htohc32(sc, EHCI_LINK_SITD); 368 369 sitd->sitd_back = 370 htohc32(sc, EHCI_LINK_TERMINATE); 371 372 sitd->sitd_next = 373 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 374 375 376 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 377 378 itd = buf_res.buffer; 379 380 /* initialize page cache pointer */ 381 382 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 383 384 /* store a pointer to the transfer descriptor */ 385 386 sc->sc_isoc_hs_p_last[i] = itd; 387 388 /* initialize high speed isochronous */ 389 390 itd->itd_self = 391 htohc32(sc, buf_res.physaddr) | 392 htohc32(sc, EHCI_LINK_ITD); 393 394 itd->itd_next = 395 sitd->sitd_self; 396 } 397 398 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 399 400 if (1) { 401 uint32_t *pframes; 402 403 pframes = buf_res.buffer; 404 405 /* 406 * execution order: 407 * pframes -> high speed isochronous -> 408 * full speed isochronous -> interrupt QH's 409 */ 410 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 411 pframes[i] = sc->sc_isoc_hs_p_last 412 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 413 } 414 } 415 /* setup sync list pointer */ 416 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 417 418 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 419 420 if (1) { 421 422 ehci_qh_t *qh; 423 424 qh = buf_res.buffer; 425 426 /* initialize page cache pointer */ 427 428 qh->page_cache = &sc->sc_hw.async_start_pc; 429 430 /* store a pointer to the queue head */ 431 432 sc->sc_async_p_last = qh; 433 434 /* init dummy QH that starts the async list */ 435 436 qh->qh_self = 437 htohc32(sc, buf_res.physaddr) | 438 htohc32(sc, EHCI_LINK_QH); 439 440 /* fill the QH */ 441 qh->qh_endp = 442 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 443 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 444 qh->qh_link = qh->qh_self; 445 qh->qh_curqtd = 0; 446 447 /* fill the overlay qTD */ 448 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 449 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 450 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 451 } 452 /* flush all cache into memory */ 453 454 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 455 456 #if USB_DEBUG 457 if (ehcidebug) { 458 ehci_dump_sqh(sc, sc->sc_async_p_last); 459 } 460 #endif 461 462 /* setup async list pointer */ 463 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 464 465 466 /* enable interrupts */ 467 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 468 469 /* turn on controller */ 470 EOWRITE4(sc, EHCI_USBCMD, 471 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 472 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 473 EHCI_CMD_ASE | 474 EHCI_CMD_PSE | 475 EHCI_CMD_RS); 476 477 /* Take over port ownership */ 478 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 479 480 for (i = 0; i < 100; i++) { 481 usb2_pause_mtx(NULL, hz / 1000); 482 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 483 if (!hcr) { 484 break; 485 } 486 } 487 if (hcr) { 488 device_printf(sc->sc_bus.bdev, "run timeout\n"); 489 return (USB_ERR_IOERROR); 490 } 491 492 if (!err) { 493 /* catch any lost interrupts */ 494 ehci_do_poll(&sc->sc_bus); 495 } 496 return (err); 497 } 498 499 /* 500 * shut down the controller when the system is going down 501 */ 502 void 503 ehci_detach(ehci_softc_t *sc) 504 { 505 USB_BUS_LOCK(&sc->sc_bus); 506 507 usb2_callout_stop(&sc->sc_tmo_pcd); 508 509 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 510 USB_BUS_UNLOCK(&sc->sc_bus); 511 512 if (ehci_hcreset(sc)) { 513 DPRINTF("reset failed!\n"); 514 } 515 516 /* XXX let stray task complete */ 517 usb2_pause_mtx(NULL, hz / 20); 518 519 usb2_callout_drain(&sc->sc_tmo_pcd); 520 } 521 522 void 523 ehci_suspend(ehci_softc_t *sc) 524 { 525 uint32_t cmd; 526 uint32_t hcr; 527 uint8_t i; 528 529 USB_BUS_LOCK(&sc->sc_bus); 530 531 for (i = 1; i <= sc->sc_noport; i++) { 532 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 533 if (((cmd & EHCI_PS_PO) == 0) && 534 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 535 EOWRITE4(sc, EHCI_PORTSC(i), 536 cmd | EHCI_PS_SUSP); 537 } 538 } 539 540 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 541 542 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 543 EOWRITE4(sc, EHCI_USBCMD, cmd); 544 545 for (i = 0; i < 100; i++) { 546 hcr = EOREAD4(sc, EHCI_USBSTS) & 547 (EHCI_STS_ASS | EHCI_STS_PSS); 548 549 if (hcr == 0) { 550 break; 551 } 552 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 553 } 554 555 if (hcr != 0) { 556 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 557 } 558 cmd &= ~EHCI_CMD_RS; 559 EOWRITE4(sc, EHCI_USBCMD, cmd); 560 561 for (i = 0; i < 100; i++) { 562 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 563 if (hcr == EHCI_STS_HCH) { 564 break; 565 } 566 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 567 } 568 569 if (hcr != EHCI_STS_HCH) { 570 device_printf(sc->sc_bus.bdev, 571 "config timeout\n"); 572 } 573 USB_BUS_UNLOCK(&sc->sc_bus); 574 } 575 576 void 577 ehci_resume(ehci_softc_t *sc) 578 { 579 struct usb2_page_search buf_res; 580 uint32_t cmd; 581 uint32_t hcr; 582 uint8_t i; 583 584 USB_BUS_LOCK(&sc->sc_bus); 585 586 /* restore things in case the bios doesn't */ 587 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 588 589 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 590 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 591 592 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 593 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 594 595 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 596 597 hcr = 0; 598 for (i = 1; i <= sc->sc_noport; i++) { 599 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 600 if (((cmd & EHCI_PS_PO) == 0) && 601 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 602 EOWRITE4(sc, EHCI_PORTSC(i), 603 cmd | EHCI_PS_FPR); 604 hcr = 1; 605 } 606 } 607 608 if (hcr) { 609 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 610 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 611 612 for (i = 1; i <= sc->sc_noport; i++) { 613 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 614 if (((cmd & EHCI_PS_PO) == 0) && 615 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 616 EOWRITE4(sc, EHCI_PORTSC(i), 617 cmd & ~EHCI_PS_FPR); 618 } 619 } 620 } 621 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 622 623 for (i = 0; i < 100; i++) { 624 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 625 if (hcr != EHCI_STS_HCH) { 626 break; 627 } 628 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 629 } 630 if (hcr == EHCI_STS_HCH) { 631 device_printf(sc->sc_bus.bdev, "config timeout\n"); 632 } 633 634 USB_BUS_UNLOCK(&sc->sc_bus); 635 636 usb2_pause_mtx(NULL, 637 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 638 639 /* catch any lost interrupts */ 640 ehci_do_poll(&sc->sc_bus); 641 } 642 643 void 644 ehci_shutdown(ehci_softc_t *sc) 645 { 646 DPRINTF("stopping the HC\n"); 647 648 if (ehci_hcreset(sc)) { 649 DPRINTF("reset failed!\n"); 650 } 651 } 652 653 #if USB_DEBUG 654 static void 655 ehci_dump_regs(ehci_softc_t *sc) 656 { 657 uint32_t i; 658 659 i = EOREAD4(sc, EHCI_USBCMD); 660 printf("cmd=0x%08x\n", i); 661 662 if (i & EHCI_CMD_ITC_1) 663 printf(" EHCI_CMD_ITC_1\n"); 664 if (i & EHCI_CMD_ITC_2) 665 printf(" EHCI_CMD_ITC_2\n"); 666 if (i & EHCI_CMD_ITC_4) 667 printf(" EHCI_CMD_ITC_4\n"); 668 if (i & EHCI_CMD_ITC_8) 669 printf(" EHCI_CMD_ITC_8\n"); 670 if (i & EHCI_CMD_ITC_16) 671 printf(" EHCI_CMD_ITC_16\n"); 672 if (i & EHCI_CMD_ITC_32) 673 printf(" EHCI_CMD_ITC_32\n"); 674 if (i & EHCI_CMD_ITC_64) 675 printf(" EHCI_CMD_ITC_64\n"); 676 if (i & EHCI_CMD_ASPME) 677 printf(" EHCI_CMD_ASPME\n"); 678 if (i & EHCI_CMD_ASPMC) 679 printf(" EHCI_CMD_ASPMC\n"); 680 if (i & EHCI_CMD_LHCR) 681 printf(" EHCI_CMD_LHCR\n"); 682 if (i & EHCI_CMD_IAAD) 683 printf(" EHCI_CMD_IAAD\n"); 684 if (i & EHCI_CMD_ASE) 685 printf(" EHCI_CMD_ASE\n"); 686 if (i & EHCI_CMD_PSE) 687 printf(" EHCI_CMD_PSE\n"); 688 if (i & EHCI_CMD_FLS_M) 689 printf(" EHCI_CMD_FLS_M\n"); 690 if (i & EHCI_CMD_HCRESET) 691 printf(" EHCI_CMD_HCRESET\n"); 692 if (i & EHCI_CMD_RS) 693 printf(" EHCI_CMD_RS\n"); 694 695 i = EOREAD4(sc, EHCI_USBSTS); 696 697 printf("sts=0x%08x\n", i); 698 699 if (i & EHCI_STS_ASS) 700 printf(" EHCI_STS_ASS\n"); 701 if (i & EHCI_STS_PSS) 702 printf(" EHCI_STS_PSS\n"); 703 if (i & EHCI_STS_REC) 704 printf(" EHCI_STS_REC\n"); 705 if (i & EHCI_STS_HCH) 706 printf(" EHCI_STS_HCH\n"); 707 if (i & EHCI_STS_IAA) 708 printf(" EHCI_STS_IAA\n"); 709 if (i & EHCI_STS_HSE) 710 printf(" EHCI_STS_HSE\n"); 711 if (i & EHCI_STS_FLR) 712 printf(" EHCI_STS_FLR\n"); 713 if (i & EHCI_STS_PCD) 714 printf(" EHCI_STS_PCD\n"); 715 if (i & EHCI_STS_ERRINT) 716 printf(" EHCI_STS_ERRINT\n"); 717 if (i & EHCI_STS_INT) 718 printf(" EHCI_STS_INT\n"); 719 720 printf("ien=0x%08x\n", 721 EOREAD4(sc, EHCI_USBINTR)); 722 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 723 EOREAD4(sc, EHCI_FRINDEX), 724 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 725 EOREAD4(sc, EHCI_PERIODICLISTBASE), 726 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 727 for (i = 1; i <= sc->sc_noport; i++) { 728 printf("port %d status=0x%08x\n", i, 729 EOREAD4(sc, EHCI_PORTSC(i))); 730 } 731 } 732 733 static void 734 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 735 { 736 link = hc32toh(sc, link); 737 printf("0x%08x", link); 738 if (link & EHCI_LINK_TERMINATE) 739 printf("<T>"); 740 else { 741 printf("<"); 742 if (type) { 743 switch (EHCI_LINK_TYPE(link)) { 744 case EHCI_LINK_ITD: 745 printf("ITD"); 746 break; 747 case EHCI_LINK_QH: 748 printf("QH"); 749 break; 750 case EHCI_LINK_SITD: 751 printf("SITD"); 752 break; 753 case EHCI_LINK_FSTN: 754 printf("FSTN"); 755 break; 756 } 757 } 758 printf(">"); 759 } 760 } 761 762 static void 763 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 764 { 765 uint32_t s; 766 767 printf(" next="); 768 ehci_dump_link(sc, qtd->qtd_next, 0); 769 printf(" altnext="); 770 ehci_dump_link(sc, qtd->qtd_altnext, 0); 771 printf("\n"); 772 s = hc32toh(sc, qtd->qtd_status); 773 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 774 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 775 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 776 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 777 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 778 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 779 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 780 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 781 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 782 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 783 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 784 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 785 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 786 787 for (s = 0; s < 5; s++) { 788 printf(" buffer[%d]=0x%08x\n", s, 789 hc32toh(sc, qtd->qtd_buffer[s])); 790 } 791 for (s = 0; s < 5; s++) { 792 printf(" buffer_hi[%d]=0x%08x\n", s, 793 hc32toh(sc, qtd->qtd_buffer_hi[s])); 794 } 795 } 796 797 static uint8_t 798 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 799 { 800 uint8_t temp; 801 802 usb2_pc_cpu_invalidate(sqtd->page_cache); 803 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 804 ehci_dump_qtd(sc, sqtd); 805 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 806 return (temp); 807 } 808 809 static void 810 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 811 { 812 uint16_t i; 813 uint8_t stop; 814 815 stop = 0; 816 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 817 stop = ehci_dump_sqtd(sc, sqtd); 818 } 819 if (sqtd) { 820 printf("dump aborted, too many TDs\n"); 821 } 822 } 823 824 static void 825 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 826 { 827 uint32_t endp; 828 uint32_t endphub; 829 830 usb2_pc_cpu_invalidate(qh->page_cache); 831 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 832 printf(" link="); 833 ehci_dump_link(sc, qh->qh_link, 1); 834 printf("\n"); 835 endp = hc32toh(sc, qh->qh_endp); 836 printf(" endp=0x%08x\n", endp); 837 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 838 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 839 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 840 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 841 printf(" mpl=0x%x ctl=%d nrl=%d\n", 842 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 843 EHCI_QH_GET_NRL(endp)); 844 endphub = hc32toh(sc, qh->qh_endphub); 845 printf(" endphub=0x%08x\n", endphub); 846 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 847 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 848 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 849 EHCI_QH_GET_MULT(endphub)); 850 printf(" curqtd="); 851 ehci_dump_link(sc, qh->qh_curqtd, 0); 852 printf("\n"); 853 printf("Overlay qTD:\n"); 854 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 855 } 856 857 static void 858 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 859 { 860 usb2_pc_cpu_invalidate(sitd->page_cache); 861 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 862 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 863 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 864 hc32toh(sc, sitd->sitd_portaddr), 865 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 866 ? "in" : "out", 867 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 868 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 869 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 870 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 871 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 872 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 873 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 874 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 875 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 876 hc32toh(sc, sitd->sitd_back), 877 hc32toh(sc, sitd->sitd_bp[0]), 878 hc32toh(sc, sitd->sitd_bp[1]), 879 hc32toh(sc, sitd->sitd_bp_hi[0]), 880 hc32toh(sc, sitd->sitd_bp_hi[1])); 881 } 882 883 static void 884 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 885 { 886 usb2_pc_cpu_invalidate(itd->page_cache); 887 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 888 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 889 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 890 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 891 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 892 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 893 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 894 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 896 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 898 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 900 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 901 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 902 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 903 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 904 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 905 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 906 printf(" addr=0x%02x; endpt=0x%01x\n", 907 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 908 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 909 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 910 printf(" dir=%s; mpl=0x%02x\n", 911 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 912 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 913 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 914 hc32toh(sc, itd->itd_bp[2]), 915 hc32toh(sc, itd->itd_bp[3]), 916 hc32toh(sc, itd->itd_bp[4]), 917 hc32toh(sc, itd->itd_bp[5]), 918 hc32toh(sc, itd->itd_bp[6])); 919 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 920 " 0x%08x,0x%08x,0x%08x\n", 921 hc32toh(sc, itd->itd_bp_hi[0]), 922 hc32toh(sc, itd->itd_bp_hi[1]), 923 hc32toh(sc, itd->itd_bp_hi[2]), 924 hc32toh(sc, itd->itd_bp_hi[3]), 925 hc32toh(sc, itd->itd_bp_hi[4]), 926 hc32toh(sc, itd->itd_bp_hi[5]), 927 hc32toh(sc, itd->itd_bp_hi[6])); 928 } 929 930 static void 931 ehci_dump_isoc(ehci_softc_t *sc) 932 { 933 ehci_itd_t *itd; 934 ehci_sitd_t *sitd; 935 uint16_t max = 1000; 936 uint16_t pos; 937 938 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 939 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 940 941 printf("%s: isochronous dump from frame 0x%03x:\n", 942 __FUNCTION__, pos); 943 944 itd = sc->sc_isoc_hs_p_last[pos]; 945 sitd = sc->sc_isoc_fs_p_last[pos]; 946 947 while (itd && max && max--) { 948 ehci_dump_itd(sc, itd); 949 itd = itd->prev; 950 } 951 952 while (sitd && max && max--) { 953 ehci_dump_sitd(sc, sitd); 954 sitd = sitd->prev; 955 } 956 } 957 958 #endif 959 960 static void 961 ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 962 { 963 /* check for early completion */ 964 if (ehci_check_transfer(xfer)) { 965 return; 966 } 967 /* put transfer on interrupt queue */ 968 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 969 970 /* start timeout, if any */ 971 if (xfer->timeout != 0) { 972 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 973 } 974 } 975 976 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 977 static ehci_sitd_t * 978 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 979 { 980 DPRINTFN(11, "%p to %p\n", std, last); 981 982 /* (sc->sc_bus.mtx) must be locked */ 983 984 std->next = last->next; 985 std->sitd_next = last->sitd_next; 986 987 std->prev = last; 988 989 usb2_pc_cpu_flush(std->page_cache); 990 991 /* 992 * the last->next->prev is never followed: std->next->prev = std; 993 */ 994 last->next = std; 995 last->sitd_next = std->sitd_self; 996 997 usb2_pc_cpu_flush(last->page_cache); 998 999 return (std); 1000 } 1001 1002 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1003 static ehci_itd_t * 1004 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1005 { 1006 DPRINTFN(11, "%p to %p\n", std, last); 1007 1008 /* (sc->sc_bus.mtx) must be locked */ 1009 1010 std->next = last->next; 1011 std->itd_next = last->itd_next; 1012 1013 std->prev = last; 1014 1015 usb2_pc_cpu_flush(std->page_cache); 1016 1017 /* 1018 * the last->next->prev is never followed: std->next->prev = std; 1019 */ 1020 last->next = std; 1021 last->itd_next = std->itd_self; 1022 1023 usb2_pc_cpu_flush(last->page_cache); 1024 1025 return (std); 1026 } 1027 1028 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1029 static ehci_qh_t * 1030 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1031 { 1032 DPRINTFN(11, "%p to %p\n", sqh, last); 1033 1034 if (sqh->prev != NULL) { 1035 /* should not happen */ 1036 DPRINTFN(0, "QH already linked!\n"); 1037 return (last); 1038 } 1039 /* (sc->sc_bus.mtx) must be locked */ 1040 1041 sqh->next = last->next; 1042 sqh->qh_link = last->qh_link; 1043 1044 sqh->prev = last; 1045 1046 usb2_pc_cpu_flush(sqh->page_cache); 1047 1048 /* 1049 * the last->next->prev is never followed: sqh->next->prev = sqh; 1050 */ 1051 1052 last->next = sqh; 1053 last->qh_link = sqh->qh_self; 1054 1055 usb2_pc_cpu_flush(last->page_cache); 1056 1057 return (sqh); 1058 } 1059 1060 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1061 static ehci_sitd_t * 1062 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1063 { 1064 DPRINTFN(11, "%p from %p\n", std, last); 1065 1066 /* (sc->sc_bus.mtx) must be locked */ 1067 1068 std->prev->next = std->next; 1069 std->prev->sitd_next = std->sitd_next; 1070 1071 usb2_pc_cpu_flush(std->prev->page_cache); 1072 1073 if (std->next) { 1074 std->next->prev = std->prev; 1075 usb2_pc_cpu_flush(std->next->page_cache); 1076 } 1077 return ((last == std) ? std->prev : last); 1078 } 1079 1080 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1081 static ehci_itd_t * 1082 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1083 { 1084 DPRINTFN(11, "%p from %p\n", std, last); 1085 1086 /* (sc->sc_bus.mtx) must be locked */ 1087 1088 std->prev->next = std->next; 1089 std->prev->itd_next = std->itd_next; 1090 1091 usb2_pc_cpu_flush(std->prev->page_cache); 1092 1093 if (std->next) { 1094 std->next->prev = std->prev; 1095 usb2_pc_cpu_flush(std->next->page_cache); 1096 } 1097 return ((last == std) ? std->prev : last); 1098 } 1099 1100 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1101 static ehci_qh_t * 1102 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1103 { 1104 DPRINTFN(11, "%p from %p\n", sqh, last); 1105 1106 /* (sc->sc_bus.mtx) must be locked */ 1107 1108 /* only remove if not removed from a queue */ 1109 if (sqh->prev) { 1110 1111 sqh->prev->next = sqh->next; 1112 sqh->prev->qh_link = sqh->qh_link; 1113 1114 usb2_pc_cpu_flush(sqh->prev->page_cache); 1115 1116 if (sqh->next) { 1117 sqh->next->prev = sqh->prev; 1118 usb2_pc_cpu_flush(sqh->next->page_cache); 1119 } 1120 last = ((last == sqh) ? sqh->prev : last); 1121 1122 sqh->prev = 0; 1123 1124 usb2_pc_cpu_flush(sqh->page_cache); 1125 } 1126 return (last); 1127 } 1128 1129 static usb2_error_t 1130 ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1131 { 1132 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1133 ehci_qtd_t *td; 1134 ehci_qtd_t *td_alt_next; 1135 uint32_t status; 1136 uint16_t len; 1137 1138 td = xfer->td_transfer_cache; 1139 td_alt_next = td->alt_next; 1140 1141 if (xfer->aframes != xfer->nframes) { 1142 xfer->frlengths[xfer->aframes] = 0; 1143 } 1144 while (1) { 1145 1146 usb2_pc_cpu_invalidate(td->page_cache); 1147 status = hc32toh(sc, td->qtd_status); 1148 1149 len = EHCI_QTD_GET_BYTES(status); 1150 1151 /* 1152 * Verify the status length and 1153 * add the length to "frlengths[]": 1154 */ 1155 if (len > td->len) { 1156 /* should not happen */ 1157 DPRINTF("Invalid status length, " 1158 "0x%04x/0x%04x bytes\n", len, td->len); 1159 status |= EHCI_QTD_HALTED; 1160 } else if (xfer->aframes != xfer->nframes) { 1161 xfer->frlengths[xfer->aframes] += td->len - len; 1162 } 1163 /* Check for last transfer */ 1164 if (((void *)td) == xfer->td_transfer_last) { 1165 if (len == 0) { 1166 /* 1167 * Halt is ok if descriptor is last, 1168 * and complete: 1169 */ 1170 status &= ~EHCI_QTD_HALTED; 1171 } 1172 td = NULL; 1173 break; 1174 } 1175 /* Check for transfer error */ 1176 if (status & EHCI_QTD_HALTED) { 1177 /* the transfer is finished */ 1178 td = NULL; 1179 break; 1180 } 1181 /* Check for short transfer */ 1182 if (len > 0) { 1183 if (xfer->flags_int.short_frames_ok) { 1184 /* follow alt next */ 1185 td = td->alt_next; 1186 } else { 1187 /* the transfer is finished */ 1188 td = NULL; 1189 } 1190 break; 1191 } 1192 td = td->obj_next; 1193 1194 if (td->alt_next != td_alt_next) { 1195 /* this USB frame is complete */ 1196 break; 1197 } 1198 } 1199 1200 /* update transfer cache */ 1201 1202 xfer->td_transfer_cache = td; 1203 1204 /* update data toggle */ 1205 1206 xfer->pipe->toggle_next = 1207 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1208 1209 #if USB_DEBUG 1210 if (status & EHCI_QTD_STATERRS) { 1211 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1212 "status=%s%s%s%s%s%s%s%s\n", 1213 xfer->address, xfer->endpoint, xfer->aframes, 1214 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1215 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1216 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1217 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1218 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1219 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1220 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1221 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1222 } 1223 #endif 1224 1225 return ((status & EHCI_QTD_HALTED) ? 1226 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1227 } 1228 1229 static void 1230 ehci_non_isoc_done(struct usb2_xfer *xfer) 1231 { 1232 usb2_error_t err = 0; 1233 1234 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1235 xfer, xfer->pipe); 1236 1237 #if USB_DEBUG 1238 if (ehcidebug > 10) { 1239 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1240 1241 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1242 } 1243 #endif 1244 1245 /* reset scanner */ 1246 1247 xfer->td_transfer_cache = xfer->td_transfer_first; 1248 1249 if (xfer->flags_int.control_xfr) { 1250 1251 if (xfer->flags_int.control_hdr) { 1252 1253 err = ehci_non_isoc_done_sub(xfer); 1254 } 1255 xfer->aframes = 1; 1256 1257 if (xfer->td_transfer_cache == NULL) { 1258 goto done; 1259 } 1260 } 1261 while (xfer->aframes != xfer->nframes) { 1262 1263 err = ehci_non_isoc_done_sub(xfer); 1264 xfer->aframes++; 1265 1266 if (xfer->td_transfer_cache == NULL) { 1267 goto done; 1268 } 1269 } 1270 1271 if (xfer->flags_int.control_xfr && 1272 !xfer->flags_int.control_act) { 1273 1274 err = ehci_non_isoc_done_sub(xfer); 1275 } 1276 done: 1277 ehci_device_done(xfer, err); 1278 } 1279 1280 /*------------------------------------------------------------------------* 1281 * ehci_check_transfer 1282 * 1283 * Return values: 1284 * 0: USB transfer is not finished 1285 * Else: USB transfer is finished 1286 *------------------------------------------------------------------------*/ 1287 static uint8_t 1288 ehci_check_transfer(struct usb2_xfer *xfer) 1289 { 1290 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1291 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1292 1293 uint32_t status; 1294 1295 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1296 1297 if (methods == &ehci_device_isoc_fs_methods) { 1298 ehci_sitd_t *td; 1299 1300 /* isochronous full speed transfer */ 1301 1302 td = xfer->td_transfer_last; 1303 usb2_pc_cpu_invalidate(td->page_cache); 1304 status = hc32toh(sc, td->sitd_status); 1305 1306 /* also check if first is complete */ 1307 1308 td = xfer->td_transfer_first; 1309 usb2_pc_cpu_invalidate(td->page_cache); 1310 status |= hc32toh(sc, td->sitd_status); 1311 1312 if (!(status & EHCI_SITD_ACTIVE)) { 1313 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1314 goto transferred; 1315 } 1316 } else if (methods == &ehci_device_isoc_hs_methods) { 1317 ehci_itd_t *td; 1318 1319 /* isochronous high speed transfer */ 1320 1321 td = xfer->td_transfer_last; 1322 usb2_pc_cpu_invalidate(td->page_cache); 1323 status = 1324 td->itd_status[0] | td->itd_status[1] | 1325 td->itd_status[2] | td->itd_status[3] | 1326 td->itd_status[4] | td->itd_status[5] | 1327 td->itd_status[6] | td->itd_status[7]; 1328 1329 /* also check first transfer */ 1330 td = xfer->td_transfer_first; 1331 usb2_pc_cpu_invalidate(td->page_cache); 1332 status |= 1333 td->itd_status[0] | td->itd_status[1] | 1334 td->itd_status[2] | td->itd_status[3] | 1335 td->itd_status[4] | td->itd_status[5] | 1336 td->itd_status[6] | td->itd_status[7]; 1337 1338 /* if no transactions are active we continue */ 1339 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1340 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1341 goto transferred; 1342 } 1343 } else { 1344 ehci_qtd_t *td; 1345 1346 /* non-isochronous transfer */ 1347 1348 /* 1349 * check whether there is an error somewhere in the middle, 1350 * or whether there was a short packet (SPD and not ACTIVE) 1351 */ 1352 td = xfer->td_transfer_cache; 1353 1354 while (1) { 1355 usb2_pc_cpu_invalidate(td->page_cache); 1356 status = hc32toh(sc, td->qtd_status); 1357 1358 /* 1359 * if there is an active TD the transfer isn't done 1360 */ 1361 if (status & EHCI_QTD_ACTIVE) { 1362 /* update cache */ 1363 xfer->td_transfer_cache = td; 1364 goto done; 1365 } 1366 /* 1367 * last transfer descriptor makes the transfer done 1368 */ 1369 if (((void *)td) == xfer->td_transfer_last) { 1370 break; 1371 } 1372 /* 1373 * any kind of error makes the transfer done 1374 */ 1375 if (status & EHCI_QTD_HALTED) { 1376 break; 1377 } 1378 /* 1379 * if there is no alternate next transfer, a short 1380 * packet also makes the transfer done 1381 */ 1382 if (EHCI_QTD_GET_BYTES(status)) { 1383 if (xfer->flags_int.short_frames_ok) { 1384 /* follow alt next */ 1385 if (td->alt_next) { 1386 td = td->alt_next; 1387 continue; 1388 } 1389 } 1390 /* transfer is done */ 1391 break; 1392 } 1393 td = td->obj_next; 1394 } 1395 ehci_non_isoc_done(xfer); 1396 goto transferred; 1397 } 1398 1399 done: 1400 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1401 return (0); 1402 1403 transferred: 1404 return (1); 1405 } 1406 1407 static void 1408 ehci_pcd_enable(ehci_softc_t *sc) 1409 { 1410 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1411 1412 sc->sc_eintrs |= EHCI_STS_PCD; 1413 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1414 1415 /* acknowledge any PCD interrupt */ 1416 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1417 1418 usb2_sw_transfer(&sc->sc_root_intr, 1419 &ehci_root_intr_done); 1420 } 1421 1422 static void 1423 ehci_interrupt_poll(ehci_softc_t *sc) 1424 { 1425 struct usb2_xfer *xfer; 1426 1427 repeat: 1428 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1429 /* 1430 * check if transfer is transferred 1431 */ 1432 if (ehci_check_transfer(xfer)) { 1433 /* queue has been modified */ 1434 goto repeat; 1435 } 1436 } 1437 } 1438 1439 /*------------------------------------------------------------------------* 1440 * ehci_interrupt - EHCI interrupt handler 1441 * 1442 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1443 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1444 * is present ! 1445 *------------------------------------------------------------------------*/ 1446 void 1447 ehci_interrupt(ehci_softc_t *sc) 1448 { 1449 uint32_t status; 1450 1451 USB_BUS_LOCK(&sc->sc_bus); 1452 1453 DPRINTFN(16, "real interrupt\n"); 1454 1455 #if USB_DEBUG 1456 if (ehcidebug > 15) { 1457 ehci_dump_regs(sc); 1458 } 1459 #endif 1460 1461 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1462 if (status == 0) { 1463 /* the interrupt was not for us */ 1464 goto done; 1465 } 1466 if (!(status & sc->sc_eintrs)) { 1467 goto done; 1468 } 1469 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1470 1471 status &= sc->sc_eintrs; 1472 1473 if (status & EHCI_STS_HSE) { 1474 printf("%s: unrecoverable error, " 1475 "controller halted\n", __FUNCTION__); 1476 #if USB_DEBUG 1477 ehci_dump_regs(sc); 1478 ehci_dump_isoc(sc); 1479 #endif 1480 } 1481 if (status & EHCI_STS_PCD) { 1482 /* 1483 * Disable PCD interrupt for now, because it will be 1484 * on until the port has been reset. 1485 */ 1486 sc->sc_eintrs &= ~EHCI_STS_PCD; 1487 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1488 1489 usb2_sw_transfer(&sc->sc_root_intr, 1490 &ehci_root_intr_done); 1491 1492 /* do not allow RHSC interrupts > 1 per second */ 1493 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1494 (void *)&ehci_pcd_enable, sc); 1495 } 1496 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1497 1498 if (status != 0) { 1499 /* block unprocessed interrupts */ 1500 sc->sc_eintrs &= ~status; 1501 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1502 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1503 } 1504 /* poll all the USB transfers */ 1505 ehci_interrupt_poll(sc); 1506 1507 done: 1508 USB_BUS_UNLOCK(&sc->sc_bus); 1509 } 1510 1511 /* 1512 * called when a request does not complete 1513 */ 1514 static void 1515 ehci_timeout(void *arg) 1516 { 1517 struct usb2_xfer *xfer = arg; 1518 1519 DPRINTF("xfer=%p\n", xfer); 1520 1521 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1522 1523 /* transfer is transferred */ 1524 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1525 } 1526 1527 static void 1528 ehci_do_poll(struct usb2_bus *bus) 1529 { 1530 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1531 1532 USB_BUS_LOCK(&sc->sc_bus); 1533 ehci_interrupt_poll(sc); 1534 ehci_root_ctrl_poll(sc); 1535 USB_BUS_UNLOCK(&sc->sc_bus); 1536 } 1537 1538 static void 1539 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1540 { 1541 struct usb2_page_search buf_res; 1542 ehci_qtd_t *td; 1543 ehci_qtd_t *td_next; 1544 ehci_qtd_t *td_alt_next; 1545 uint32_t qtd_altnext; 1546 uint32_t buf_offset; 1547 uint32_t average; 1548 uint32_t len_old; 1549 uint32_t terminate; 1550 uint8_t shortpkt_old; 1551 uint8_t precompute; 1552 1553 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE); 1554 qtd_altnext = terminate; 1555 td_alt_next = NULL; 1556 buf_offset = 0; 1557 shortpkt_old = temp->shortpkt; 1558 len_old = temp->len; 1559 precompute = 1; 1560 1561 restart: 1562 1563 td = temp->td; 1564 td_next = temp->td_next; 1565 1566 while (1) { 1567 1568 if (temp->len == 0) { 1569 1570 if (temp->shortpkt) { 1571 break; 1572 } 1573 /* send a Zero Length Packet, ZLP, last */ 1574 1575 temp->shortpkt = 1; 1576 average = 0; 1577 1578 } else { 1579 1580 average = temp->average; 1581 1582 if (temp->len < average) { 1583 if (temp->len % temp->max_frame_size) { 1584 temp->shortpkt = 1; 1585 } 1586 average = temp->len; 1587 } 1588 } 1589 1590 if (td_next == NULL) { 1591 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1592 } 1593 /* get next TD */ 1594 1595 td = td_next; 1596 td_next = td->obj_next; 1597 1598 /* check if we are pre-computing */ 1599 1600 if (precompute) { 1601 1602 /* update remaining length */ 1603 1604 temp->len -= average; 1605 1606 continue; 1607 } 1608 /* fill out current TD */ 1609 1610 td->qtd_status = 1611 temp->qtd_status | 1612 htohc32(temp->sc, EHCI_QTD_SET_BYTES(average)); 1613 1614 if (average == 0) { 1615 1616 if (temp->auto_data_toggle == 0) { 1617 1618 /* update data toggle, ZLP case */ 1619 1620 temp->qtd_status ^= 1621 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1622 } 1623 td->len = 0; 1624 1625 td->qtd_buffer[0] = 0; 1626 td->qtd_buffer_hi[0] = 0; 1627 1628 td->qtd_buffer[1] = 0; 1629 td->qtd_buffer_hi[1] = 0; 1630 1631 } else { 1632 1633 uint8_t x; 1634 1635 if (temp->auto_data_toggle == 0) { 1636 1637 /* update data toggle */ 1638 1639 if (((average + temp->max_frame_size - 1) / 1640 temp->max_frame_size) & 1) { 1641 temp->qtd_status ^= 1642 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1643 } 1644 } 1645 td->len = average; 1646 1647 /* update remaining length */ 1648 1649 temp->len -= average; 1650 1651 /* fill out buffer pointers */ 1652 1653 usb2_get_page(temp->pc, buf_offset, &buf_res); 1654 td->qtd_buffer[0] = 1655 htohc32(temp->sc, buf_res.physaddr); 1656 td->qtd_buffer_hi[0] = 0; 1657 1658 x = 1; 1659 1660 while (average > EHCI_PAGE_SIZE) { 1661 average -= EHCI_PAGE_SIZE; 1662 buf_offset += EHCI_PAGE_SIZE; 1663 usb2_get_page(temp->pc, buf_offset, &buf_res); 1664 td->qtd_buffer[x] = 1665 htohc32(temp->sc, 1666 buf_res.physaddr & (~0xFFF)); 1667 td->qtd_buffer_hi[x] = 0; 1668 x++; 1669 } 1670 1671 /* 1672 * NOTE: The "average" variable is never zero after 1673 * exiting the loop above ! 1674 * 1675 * NOTE: We have to subtract one from the offset to 1676 * ensure that we are computing the physical address 1677 * of a valid page ! 1678 */ 1679 buf_offset += average; 1680 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1681 td->qtd_buffer[x] = 1682 htohc32(temp->sc, 1683 buf_res.physaddr & (~0xFFF)); 1684 td->qtd_buffer_hi[x] = 0; 1685 } 1686 1687 if (td_next) { 1688 /* link the current TD with the next one */ 1689 td->qtd_next = td_next->qtd_self; 1690 } 1691 td->qtd_altnext = qtd_altnext; 1692 td->alt_next = td_alt_next; 1693 1694 usb2_pc_cpu_flush(td->page_cache); 1695 } 1696 1697 if (precompute) { 1698 precompute = 0; 1699 1700 /* setup alt next pointer, if any */ 1701 if (temp->last_frame) { 1702 td_alt_next = NULL; 1703 qtd_altnext = terminate; 1704 } else { 1705 /* we use this field internally */ 1706 td_alt_next = td_next; 1707 if (temp->setup_alt_next) { 1708 qtd_altnext = td_next->qtd_self; 1709 } else { 1710 qtd_altnext = terminate; 1711 } 1712 } 1713 1714 /* restore */ 1715 temp->shortpkt = shortpkt_old; 1716 temp->len = len_old; 1717 goto restart; 1718 } 1719 temp->td = td; 1720 temp->td_next = td_next; 1721 } 1722 1723 static void 1724 ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1725 { 1726 struct ehci_std_temp temp; 1727 struct usb2_pipe_methods *methods; 1728 ehci_qh_t *qh; 1729 ehci_qtd_t *td; 1730 uint32_t qh_endp; 1731 uint32_t qh_endphub; 1732 uint32_t x; 1733 1734 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1735 xfer->address, UE_GET_ADDR(xfer->endpoint), 1736 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1737 1738 temp.average = xfer->max_hc_frame_size; 1739 temp.max_frame_size = xfer->max_frame_size; 1740 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1741 1742 /* toggle the DMA set we are using */ 1743 xfer->flags_int.curr_dma_set ^= 1; 1744 1745 /* get next DMA set */ 1746 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1747 1748 xfer->td_transfer_first = td; 1749 xfer->td_transfer_cache = td; 1750 1751 temp.td = NULL; 1752 temp.td_next = td; 1753 temp.qtd_status = 0; 1754 temp.last_frame = 0; 1755 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1756 1757 if (xfer->flags_int.control_xfr) { 1758 if (xfer->pipe->toggle_next) { 1759 /* DATA1 is next */ 1760 temp.qtd_status |= 1761 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1762 } 1763 temp.auto_data_toggle = 0; 1764 } else { 1765 temp.auto_data_toggle = 1; 1766 } 1767 1768 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1769 /* max 3 retries */ 1770 temp.qtd_status |= 1771 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1772 } 1773 /* check if we should prepend a setup message */ 1774 1775 if (xfer->flags_int.control_xfr) { 1776 if (xfer->flags_int.control_hdr) { 1777 1778 temp.qtd_status &= 1779 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1780 temp.qtd_status |= htohc32(temp.sc, 1781 EHCI_QTD_ACTIVE | 1782 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1783 EHCI_QTD_SET_TOGGLE(0)); 1784 1785 temp.len = xfer->frlengths[0]; 1786 temp.pc = xfer->frbuffers + 0; 1787 temp.shortpkt = temp.len ? 1 : 0; 1788 /* check for last frame */ 1789 if (xfer->nframes == 1) { 1790 /* no STATUS stage yet, SETUP is last */ 1791 if (xfer->flags_int.control_act) { 1792 temp.last_frame = 1; 1793 temp.setup_alt_next = 0; 1794 } 1795 } 1796 ehci_setup_standard_chain_sub(&temp); 1797 } 1798 x = 1; 1799 } else { 1800 x = 0; 1801 } 1802 1803 while (x != xfer->nframes) { 1804 1805 /* DATA0 / DATA1 message */ 1806 1807 temp.len = xfer->frlengths[x]; 1808 temp.pc = xfer->frbuffers + x; 1809 1810 x++; 1811 1812 if (x == xfer->nframes) { 1813 if (xfer->flags_int.control_xfr) { 1814 /* no STATUS stage yet, DATA is last */ 1815 if (xfer->flags_int.control_act) { 1816 temp.last_frame = 1; 1817 temp.setup_alt_next = 0; 1818 } 1819 } else { 1820 temp.last_frame = 1; 1821 temp.setup_alt_next = 0; 1822 } 1823 } 1824 /* keep previous data toggle and error count */ 1825 1826 temp.qtd_status &= 1827 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1828 EHCI_QTD_SET_TOGGLE(1)); 1829 1830 if (temp.len == 0) { 1831 1832 /* make sure that we send an USB packet */ 1833 1834 temp.shortpkt = 0; 1835 1836 } else { 1837 1838 /* regular data transfer */ 1839 1840 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1841 } 1842 1843 /* set endpoint direction */ 1844 1845 temp.qtd_status |= 1846 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1847 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1848 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1849 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1850 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1851 1852 ehci_setup_standard_chain_sub(&temp); 1853 } 1854 1855 /* check if we should append a status stage */ 1856 1857 if (xfer->flags_int.control_xfr && 1858 !xfer->flags_int.control_act) { 1859 1860 /* 1861 * Send a DATA1 message and invert the current endpoint 1862 * direction. 1863 */ 1864 1865 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1866 EHCI_QTD_SET_TOGGLE(1)); 1867 temp.qtd_status |= 1868 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1869 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1870 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1871 EHCI_QTD_SET_TOGGLE(1)) : 1872 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1873 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1874 EHCI_QTD_SET_TOGGLE(1)); 1875 1876 temp.len = 0; 1877 temp.pc = NULL; 1878 temp.shortpkt = 0; 1879 temp.last_frame = 1; 1880 temp.setup_alt_next = 0; 1881 1882 ehci_setup_standard_chain_sub(&temp); 1883 } 1884 td = temp.td; 1885 1886 /* the last TD terminates the transfer: */ 1887 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1888 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1889 td->qtd_status |= htohc32(temp.sc, EHCI_QTD_IOC); 1890 1891 usb2_pc_cpu_flush(td->page_cache); 1892 1893 /* must have at least one frame! */ 1894 1895 xfer->td_transfer_last = td; 1896 1897 #if USB_DEBUG 1898 if (ehcidebug > 8) { 1899 DPRINTF("nexttog=%d; data before transfer:\n", 1900 xfer->pipe->toggle_next); 1901 ehci_dump_sqtds(temp.sc, 1902 xfer->td_transfer_first); 1903 } 1904 #endif 1905 1906 methods = xfer->pipe->methods; 1907 1908 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1909 1910 /* the "qh_link" field is filled when the QH is added */ 1911 1912 qh_endp = 1913 (EHCI_QH_SET_ADDR(xfer->address) | 1914 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1915 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1916 1917 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1918 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1919 EHCI_QH_DTC); 1920 if (methods != &ehci_device_intr_methods) 1921 qh_endp |= EHCI_QH_SET_NRL(8); 1922 } else { 1923 1924 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1925 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1926 EHCI_QH_DTC); 1927 } else { 1928 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1929 EHCI_QH_DTC); 1930 } 1931 1932 if (methods == &ehci_device_ctrl_methods) { 1933 qh_endp |= EHCI_QH_CTL; 1934 } 1935 if (methods != &ehci_device_intr_methods) { 1936 /* Only try one time per microframe! */ 1937 qh_endp |= EHCI_QH_SET_NRL(1); 1938 } 1939 } 1940 1941 qh->qh_endp = htohc32(temp.sc, qh_endp); 1942 1943 qh_endphub = 1944 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1945 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1946 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1947 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1948 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1949 1950 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1951 qh->qh_curqtd = htohc32(temp.sc, 0); 1952 1953 /* fill the overlay qTD */ 1954 qh->qh_qtd.qtd_status = htohc32(temp.sc, 0); 1955 1956 if (temp.auto_data_toggle) { 1957 1958 /* let the hardware compute the data toggle */ 1959 1960 qh->qh_endp &= htohc32(temp.sc, ~EHCI_QH_DTC); 1961 1962 if (xfer->pipe->toggle_next) { 1963 /* DATA1 is next */ 1964 qh->qh_qtd.qtd_status |= 1965 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1966 } 1967 } 1968 td = xfer->td_transfer_first; 1969 1970 qh->qh_qtd.qtd_next = td->qtd_self; 1971 qh->qh_qtd.qtd_altnext = 1972 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1973 1974 usb2_pc_cpu_flush(qh->page_cache); 1975 1976 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1977 EHCI_APPEND_QH(qh, *qh_last); 1978 } 1979 } 1980 1981 static void 1982 ehci_root_intr_done(struct usb2_xfer *xfer, 1983 struct usb2_sw_transfer *std) 1984 { 1985 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1986 uint16_t i; 1987 uint16_t m; 1988 1989 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1990 1991 if (std->state != USB_SW_TR_PRE_DATA) { 1992 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1993 /* transfer transferred */ 1994 ehci_device_done(xfer, std->err); 1995 } 1996 goto done; 1997 } 1998 /* setup buffer */ 1999 std->ptr = sc->sc_hub_idata; 2000 std->len = sizeof(sc->sc_hub_idata); 2001 2002 /* clear any old interrupt data */ 2003 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 2004 2005 /* set bits */ 2006 m = (sc->sc_noport + 1); 2007 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2008 m = (8 * sizeof(sc->sc_hub_idata)); 2009 } 2010 for (i = 1; i < m; i++) { 2011 /* pick out CHANGE bits from the status register */ 2012 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2013 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2014 DPRINTF("port %d changed\n", i); 2015 } 2016 } 2017 done: 2018 return; 2019 } 2020 2021 static void 2022 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2023 { 2024 uint32_t nframes = xfer->nframes; 2025 uint32_t status; 2026 uint32_t *plen = xfer->frlengths; 2027 uint16_t len = 0; 2028 ehci_sitd_t *td = xfer->td_transfer_first; 2029 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2030 2031 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2032 xfer, xfer->pipe); 2033 2034 while (nframes--) { 2035 if (td == NULL) { 2036 panic("%s:%d: out of TD's\n", 2037 __FUNCTION__, __LINE__); 2038 } 2039 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2040 pp_last = &sc->sc_isoc_fs_p_last[0]; 2041 } 2042 #if USB_DEBUG 2043 if (ehcidebug > 15) { 2044 DPRINTF("isoc FS-TD\n"); 2045 ehci_dump_sitd(sc, td); 2046 } 2047 #endif 2048 usb2_pc_cpu_invalidate(td->page_cache); 2049 status = hc32toh(sc, td->sitd_status); 2050 2051 len = EHCI_SITD_GET_LEN(status); 2052 2053 if (*plen >= len) { 2054 len = *plen - len; 2055 } else { 2056 len = 0; 2057 } 2058 2059 *plen = len; 2060 2061 /* remove FS-TD from schedule */ 2062 EHCI_REMOVE_FS_TD(td, *pp_last); 2063 2064 pp_last++; 2065 plen++; 2066 td = td->obj_next; 2067 } 2068 2069 xfer->aframes = xfer->nframes; 2070 } 2071 2072 static void 2073 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2074 { 2075 uint32_t nframes = xfer->nframes; 2076 uint32_t status; 2077 uint32_t *plen = xfer->frlengths; 2078 uint16_t len = 0; 2079 uint8_t td_no = 0; 2080 ehci_itd_t *td = xfer->td_transfer_first; 2081 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2082 2083 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2084 xfer, xfer->pipe); 2085 2086 while (nframes--) { 2087 if (td == NULL) { 2088 panic("%s:%d: out of TD's\n", 2089 __FUNCTION__, __LINE__); 2090 } 2091 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2092 pp_last = &sc->sc_isoc_hs_p_last[0]; 2093 } 2094 #if USB_DEBUG 2095 if (ehcidebug > 15) { 2096 DPRINTF("isoc HS-TD\n"); 2097 ehci_dump_itd(sc, td); 2098 } 2099 #endif 2100 2101 usb2_pc_cpu_invalidate(td->page_cache); 2102 status = hc32toh(sc, td->itd_status[td_no]); 2103 2104 len = EHCI_ITD_GET_LEN(status); 2105 2106 if (*plen >= len) { 2107 /* 2108 * The length is valid. NOTE: The complete 2109 * length is written back into the status 2110 * field, and not the remainder like with 2111 * other transfer descriptor types. 2112 */ 2113 } else { 2114 /* Invalid length - truncate */ 2115 len = 0; 2116 } 2117 2118 *plen = len; 2119 2120 plen++; 2121 td_no++; 2122 2123 if ((td_no == 8) || (nframes == 0)) { 2124 /* remove HS-TD from schedule */ 2125 EHCI_REMOVE_HS_TD(td, *pp_last); 2126 pp_last++; 2127 2128 td_no = 0; 2129 td = td->obj_next; 2130 } 2131 } 2132 xfer->aframes = xfer->nframes; 2133 } 2134 2135 /* NOTE: "done" can be run two times in a row, 2136 * from close and from interrupt 2137 */ 2138 static void 2139 ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2140 { 2141 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2142 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2143 2144 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2145 2146 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2147 xfer, xfer->pipe, error); 2148 2149 if ((methods == &ehci_device_bulk_methods) || 2150 (methods == &ehci_device_ctrl_methods)) { 2151 #if USB_DEBUG 2152 if (ehcidebug > 8) { 2153 DPRINTF("nexttog=%d; data after transfer:\n", 2154 xfer->pipe->toggle_next); 2155 ehci_dump_sqtds(sc, 2156 xfer->td_transfer_first); 2157 } 2158 #endif 2159 2160 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2161 sc->sc_async_p_last); 2162 } 2163 if (methods == &ehci_device_intr_methods) { 2164 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2165 sc->sc_intr_p_last[xfer->qh_pos]); 2166 } 2167 /* 2168 * Only finish isochronous transfers once which will update 2169 * "xfer->frlengths". 2170 */ 2171 if (xfer->td_transfer_first && 2172 xfer->td_transfer_last) { 2173 if (methods == &ehci_device_isoc_fs_methods) { 2174 ehci_isoc_fs_done(sc, xfer); 2175 } 2176 if (methods == &ehci_device_isoc_hs_methods) { 2177 ehci_isoc_hs_done(sc, xfer); 2178 } 2179 xfer->td_transfer_first = NULL; 2180 xfer->td_transfer_last = NULL; 2181 } 2182 /* dequeue transfer and start next transfer */ 2183 usb2_transfer_done(xfer, error); 2184 } 2185 2186 /*------------------------------------------------------------------------* 2187 * ehci bulk support 2188 *------------------------------------------------------------------------*/ 2189 static void 2190 ehci_device_bulk_open(struct usb2_xfer *xfer) 2191 { 2192 return; 2193 } 2194 2195 static void 2196 ehci_device_bulk_close(struct usb2_xfer *xfer) 2197 { 2198 ehci_device_done(xfer, USB_ERR_CANCELLED); 2199 } 2200 2201 static void 2202 ehci_device_bulk_enter(struct usb2_xfer *xfer) 2203 { 2204 return; 2205 } 2206 2207 static void 2208 ehci_device_bulk_start(struct usb2_xfer *xfer) 2209 { 2210 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2211 uint32_t temp; 2212 2213 /* setup TD's and QH */ 2214 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2215 2216 /* put transfer on interrupt queue */ 2217 ehci_transfer_intr_enqueue(xfer); 2218 2219 /* XXX Performance quirk: Some Host Controllers have a too low 2220 * interrupt rate. Issue an IAAD to stimulate the Host 2221 * Controller after queueing the BULK transfer. 2222 */ 2223 temp = EOREAD4(sc, EHCI_USBCMD); 2224 if (!(temp & EHCI_CMD_IAAD)) 2225 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2226 } 2227 2228 struct usb2_pipe_methods ehci_device_bulk_methods = 2229 { 2230 .open = ehci_device_bulk_open, 2231 .close = ehci_device_bulk_close, 2232 .enter = ehci_device_bulk_enter, 2233 .start = ehci_device_bulk_start, 2234 .enter_is_cancelable = 1, 2235 .start_is_cancelable = 1, 2236 }; 2237 2238 /*------------------------------------------------------------------------* 2239 * ehci control support 2240 *------------------------------------------------------------------------*/ 2241 static void 2242 ehci_device_ctrl_open(struct usb2_xfer *xfer) 2243 { 2244 return; 2245 } 2246 2247 static void 2248 ehci_device_ctrl_close(struct usb2_xfer *xfer) 2249 { 2250 ehci_device_done(xfer, USB_ERR_CANCELLED); 2251 } 2252 2253 static void 2254 ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2255 { 2256 return; 2257 } 2258 2259 static void 2260 ehci_device_ctrl_start(struct usb2_xfer *xfer) 2261 { 2262 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2263 2264 /* setup TD's and QH */ 2265 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2266 2267 /* put transfer on interrupt queue */ 2268 ehci_transfer_intr_enqueue(xfer); 2269 } 2270 2271 struct usb2_pipe_methods ehci_device_ctrl_methods = 2272 { 2273 .open = ehci_device_ctrl_open, 2274 .close = ehci_device_ctrl_close, 2275 .enter = ehci_device_ctrl_enter, 2276 .start = ehci_device_ctrl_start, 2277 .enter_is_cancelable = 1, 2278 .start_is_cancelable = 1, 2279 }; 2280 2281 /*------------------------------------------------------------------------* 2282 * ehci interrupt support 2283 *------------------------------------------------------------------------*/ 2284 static void 2285 ehci_device_intr_open(struct usb2_xfer *xfer) 2286 { 2287 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2288 uint16_t best; 2289 uint16_t bit; 2290 uint16_t x; 2291 uint8_t slot; 2292 2293 /* Allocate a microframe slot first: */ 2294 2295 slot = usb2_intr_schedule_adjust 2296 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2297 2298 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2299 xfer->usb2_uframe = slot; 2300 xfer->usb2_smask = (1 << slot) & 0xFF; 2301 xfer->usb2_cmask = 0; 2302 } else { 2303 xfer->usb2_uframe = slot; 2304 xfer->usb2_smask = (1 << slot) & 0x3F; 2305 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2306 } 2307 2308 /* 2309 * Find the best QH position corresponding to the given interval: 2310 */ 2311 2312 best = 0; 2313 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2314 while (bit) { 2315 if (xfer->interval >= bit) { 2316 x = bit; 2317 best = bit; 2318 while (x & bit) { 2319 if (sc->sc_intr_stat[x] < 2320 sc->sc_intr_stat[best]) { 2321 best = x; 2322 } 2323 x++; 2324 } 2325 break; 2326 } 2327 bit >>= 1; 2328 } 2329 2330 sc->sc_intr_stat[best]++; 2331 xfer->qh_pos = best; 2332 2333 DPRINTFN(3, "best=%d interval=%d\n", 2334 best, xfer->interval); 2335 } 2336 2337 static void 2338 ehci_device_intr_close(struct usb2_xfer *xfer) 2339 { 2340 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2341 uint8_t slot; 2342 2343 slot = usb2_intr_schedule_adjust 2344 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2345 2346 sc->sc_intr_stat[xfer->qh_pos]--; 2347 2348 ehci_device_done(xfer, USB_ERR_CANCELLED); 2349 } 2350 2351 static void 2352 ehci_device_intr_enter(struct usb2_xfer *xfer) 2353 { 2354 return; 2355 } 2356 2357 static void 2358 ehci_device_intr_start(struct usb2_xfer *xfer) 2359 { 2360 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2361 2362 /* setup TD's and QH */ 2363 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2364 2365 /* put transfer on interrupt queue */ 2366 ehci_transfer_intr_enqueue(xfer); 2367 } 2368 2369 struct usb2_pipe_methods ehci_device_intr_methods = 2370 { 2371 .open = ehci_device_intr_open, 2372 .close = ehci_device_intr_close, 2373 .enter = ehci_device_intr_enter, 2374 .start = ehci_device_intr_start, 2375 .enter_is_cancelable = 1, 2376 .start_is_cancelable = 1, 2377 }; 2378 2379 /*------------------------------------------------------------------------* 2380 * ehci full speed isochronous support 2381 *------------------------------------------------------------------------*/ 2382 static void 2383 ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2384 { 2385 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2386 ehci_sitd_t *td; 2387 uint32_t sitd_portaddr; 2388 uint8_t ds; 2389 2390 sitd_portaddr = 2391 EHCI_SITD_SET_ADDR(xfer->address) | 2392 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2393 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2394 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2395 2396 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2397 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2398 } 2399 sitd_portaddr = htohc32(sc, sitd_portaddr); 2400 2401 /* initialize all TD's */ 2402 2403 for (ds = 0; ds != 2; ds++) { 2404 2405 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2406 2407 td->sitd_portaddr = sitd_portaddr; 2408 2409 /* 2410 * TODO: make some kind of automatic 2411 * SMASK/CMASK selection based on micro-frame 2412 * usage 2413 * 2414 * micro-frame usage (8 microframes per 1ms) 2415 */ 2416 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2417 2418 usb2_pc_cpu_flush(td->page_cache); 2419 } 2420 } 2421 } 2422 2423 static void 2424 ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2425 { 2426 ehci_device_done(xfer, USB_ERR_CANCELLED); 2427 } 2428 2429 static void 2430 ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2431 { 2432 struct usb2_page_search buf_res; 2433 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2434 struct usb2_fs_isoc_schedule *fss_start; 2435 struct usb2_fs_isoc_schedule *fss_end; 2436 struct usb2_fs_isoc_schedule *fss; 2437 ehci_sitd_t *td; 2438 ehci_sitd_t *td_last = NULL; 2439 ehci_sitd_t **pp_last; 2440 uint32_t *plen; 2441 uint32_t buf_offset; 2442 uint32_t nframes; 2443 uint32_t temp; 2444 uint32_t sitd_mask; 2445 uint16_t tlen; 2446 uint8_t sa; 2447 uint8_t sb; 2448 uint8_t error; 2449 2450 #if USB_DEBUG 2451 uint8_t once = 1; 2452 2453 #endif 2454 2455 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2456 xfer, xfer->pipe->isoc_next, xfer->nframes); 2457 2458 /* get the current frame index */ 2459 2460 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2461 2462 /* 2463 * check if the frame index is within the window where the frames 2464 * will be inserted 2465 */ 2466 buf_offset = (nframes - xfer->pipe->isoc_next) & 2467 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2468 2469 if ((xfer->pipe->is_synced == 0) || 2470 (buf_offset < xfer->nframes)) { 2471 /* 2472 * If there is data underflow or the pipe queue is empty we 2473 * schedule the transfer a few frames ahead of the current 2474 * frame position. Else two isochronous transfers might 2475 * overlap. 2476 */ 2477 xfer->pipe->isoc_next = (nframes + 3) & 2478 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2479 xfer->pipe->is_synced = 1; 2480 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2481 } 2482 /* 2483 * compute how many milliseconds the insertion is ahead of the 2484 * current frame position: 2485 */ 2486 buf_offset = (xfer->pipe->isoc_next - nframes) & 2487 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2488 2489 /* 2490 * pre-compute when the isochronous transfer will be finished: 2491 */ 2492 xfer->isoc_time_complete = 2493 usb2_fs_isoc_schedule_isoc_time_expand 2494 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2495 xfer->nframes; 2496 2497 /* get the real number of frames */ 2498 2499 nframes = xfer->nframes; 2500 2501 buf_offset = 0; 2502 2503 plen = xfer->frlengths; 2504 2505 /* toggle the DMA set we are using */ 2506 xfer->flags_int.curr_dma_set ^= 1; 2507 2508 /* get next DMA set */ 2509 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2510 xfer->td_transfer_first = td; 2511 2512 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2513 2514 /* store starting position */ 2515 2516 xfer->qh_pos = xfer->pipe->isoc_next; 2517 2518 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2519 2520 while (nframes--) { 2521 if (td == NULL) { 2522 panic("%s:%d: out of TD's\n", 2523 __FUNCTION__, __LINE__); 2524 } 2525 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2526 pp_last = &sc->sc_isoc_fs_p_last[0]; 2527 } 2528 if (fss >= fss_end) { 2529 fss = fss_start; 2530 } 2531 /* reuse sitd_portaddr and sitd_back from last transfer */ 2532 2533 if (*plen > xfer->max_frame_size) { 2534 #if USB_DEBUG 2535 if (once) { 2536 once = 0; 2537 printf("%s: frame length(%d) exceeds %d " 2538 "bytes (frame truncated)\n", 2539 __FUNCTION__, *plen, 2540 xfer->max_frame_size); 2541 } 2542 #endif 2543 *plen = xfer->max_frame_size; 2544 } 2545 /* 2546 * We currently don't care if the ISOCHRONOUS schedule is 2547 * full! 2548 */ 2549 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2550 if (error) { 2551 /* 2552 * The FULL speed schedule is FULL! Set length 2553 * to zero. 2554 */ 2555 *plen = 0; 2556 } 2557 if (*plen) { 2558 /* 2559 * only call "usb2_get_page()" when we have a 2560 * non-zero length 2561 */ 2562 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2563 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2564 buf_offset += *plen; 2565 /* 2566 * NOTE: We need to subtract one from the offset so 2567 * that we are on a valid page! 2568 */ 2569 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2570 &buf_res); 2571 temp = buf_res.physaddr & ~0xFFF; 2572 } else { 2573 td->sitd_bp[0] = 0; 2574 temp = 0; 2575 } 2576 2577 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2578 tlen = *plen; 2579 if (tlen <= 188) { 2580 temp |= 1; /* T-count = 1, TP = ALL */ 2581 tlen = 1; 2582 } else { 2583 tlen += 187; 2584 tlen /= 188; 2585 temp |= tlen; /* T-count = [1..6] */ 2586 temp |= 8; /* TP = Begin */ 2587 } 2588 2589 tlen += sa; 2590 2591 if (tlen >= 8) { 2592 sb = 0; 2593 } else { 2594 sb = (1 << tlen); 2595 } 2596 2597 sa = (1 << sa); 2598 sa = (sb - sa) & 0x3F; 2599 sb = 0; 2600 } else { 2601 sb = (-(4 << sa)) & 0xFE; 2602 sa = (1 << sa) & 0x3F; 2603 } 2604 2605 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2606 EHCI_SITD_SET_CMASK(sb)); 2607 2608 td->sitd_bp[1] = htohc32(sc, temp); 2609 2610 td->sitd_mask = htohc32(sc, sitd_mask); 2611 2612 if (nframes == 0) { 2613 td->sitd_status = htohc32(sc, 2614 EHCI_SITD_IOC | 2615 EHCI_SITD_ACTIVE | 2616 EHCI_SITD_SET_LEN(*plen)); 2617 } else { 2618 td->sitd_status = htohc32(sc, 2619 EHCI_SITD_ACTIVE | 2620 EHCI_SITD_SET_LEN(*plen)); 2621 } 2622 usb2_pc_cpu_flush(td->page_cache); 2623 2624 #if USB_DEBUG 2625 if (ehcidebug > 15) { 2626 DPRINTF("FS-TD %d\n", nframes); 2627 ehci_dump_sitd(sc, td); 2628 } 2629 #endif 2630 /* insert TD into schedule */ 2631 EHCI_APPEND_FS_TD(td, *pp_last); 2632 pp_last++; 2633 2634 plen++; 2635 fss++; 2636 td_last = td; 2637 td = td->obj_next; 2638 } 2639 2640 xfer->td_transfer_last = td_last; 2641 2642 /* update isoc_next */ 2643 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2644 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2645 } 2646 2647 static void 2648 ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2649 { 2650 /* put transfer on interrupt queue */ 2651 ehci_transfer_intr_enqueue(xfer); 2652 } 2653 2654 struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2655 { 2656 .open = ehci_device_isoc_fs_open, 2657 .close = ehci_device_isoc_fs_close, 2658 .enter = ehci_device_isoc_fs_enter, 2659 .start = ehci_device_isoc_fs_start, 2660 .enter_is_cancelable = 1, 2661 .start_is_cancelable = 1, 2662 }; 2663 2664 /*------------------------------------------------------------------------* 2665 * ehci high speed isochronous support 2666 *------------------------------------------------------------------------*/ 2667 static void 2668 ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2669 { 2670 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2671 ehci_itd_t *td; 2672 uint32_t temp; 2673 uint8_t ds; 2674 2675 /* initialize all TD's */ 2676 2677 for (ds = 0; ds != 2; ds++) { 2678 2679 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2680 2681 /* set TD inactive */ 2682 td->itd_status[0] = 0; 2683 td->itd_status[1] = 0; 2684 td->itd_status[2] = 0; 2685 td->itd_status[3] = 0; 2686 td->itd_status[4] = 0; 2687 td->itd_status[5] = 0; 2688 td->itd_status[6] = 0; 2689 td->itd_status[7] = 0; 2690 2691 /* set endpoint and address */ 2692 td->itd_bp[0] = htohc32(sc, 2693 EHCI_ITD_SET_ADDR(xfer->address) | 2694 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2695 2696 temp = 2697 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2698 2699 /* set direction */ 2700 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2701 temp |= EHCI_ITD_SET_DIR_IN; 2702 } 2703 /* set maximum packet size */ 2704 td->itd_bp[1] = htohc32(sc, temp); 2705 2706 /* set transfer multiplier */ 2707 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2708 2709 usb2_pc_cpu_flush(td->page_cache); 2710 } 2711 } 2712 } 2713 2714 static void 2715 ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2716 { 2717 ehci_device_done(xfer, USB_ERR_CANCELLED); 2718 } 2719 2720 static void 2721 ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2722 { 2723 struct usb2_page_search buf_res; 2724 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2725 ehci_itd_t *td; 2726 ehci_itd_t *td_last = NULL; 2727 ehci_itd_t **pp_last; 2728 bus_size_t page_addr; 2729 uint32_t *plen; 2730 uint32_t status; 2731 uint32_t buf_offset; 2732 uint32_t nframes; 2733 uint32_t itd_offset[8 + 1]; 2734 uint8_t x; 2735 uint8_t td_no; 2736 uint8_t page_no; 2737 2738 #if USB_DEBUG 2739 uint8_t once = 1; 2740 2741 #endif 2742 2743 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2744 xfer, xfer->pipe->isoc_next, xfer->nframes); 2745 2746 /* get the current frame index */ 2747 2748 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2749 2750 /* 2751 * check if the frame index is within the window where the frames 2752 * will be inserted 2753 */ 2754 buf_offset = (nframes - xfer->pipe->isoc_next) & 2755 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2756 2757 if ((xfer->pipe->is_synced == 0) || 2758 (buf_offset < ((xfer->nframes + 7) / 8))) { 2759 /* 2760 * If there is data underflow or the pipe queue is empty we 2761 * schedule the transfer a few frames ahead of the current 2762 * frame position. Else two isochronous transfers might 2763 * overlap. 2764 */ 2765 xfer->pipe->isoc_next = (nframes + 3) & 2766 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2767 xfer->pipe->is_synced = 1; 2768 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2769 } 2770 /* 2771 * compute how many milliseconds the insertion is ahead of the 2772 * current frame position: 2773 */ 2774 buf_offset = (xfer->pipe->isoc_next - nframes) & 2775 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2776 2777 /* 2778 * pre-compute when the isochronous transfer will be finished: 2779 */ 2780 xfer->isoc_time_complete = 2781 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2782 ((xfer->nframes + 7) / 8); 2783 2784 /* get the real number of frames */ 2785 2786 nframes = xfer->nframes; 2787 2788 buf_offset = 0; 2789 td_no = 0; 2790 2791 plen = xfer->frlengths; 2792 2793 /* toggle the DMA set we are using */ 2794 xfer->flags_int.curr_dma_set ^= 1; 2795 2796 /* get next DMA set */ 2797 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2798 xfer->td_transfer_first = td; 2799 2800 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2801 2802 /* store starting position */ 2803 2804 xfer->qh_pos = xfer->pipe->isoc_next; 2805 2806 while (nframes--) { 2807 if (td == NULL) { 2808 panic("%s:%d: out of TD's\n", 2809 __FUNCTION__, __LINE__); 2810 } 2811 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2812 pp_last = &sc->sc_isoc_hs_p_last[0]; 2813 } 2814 /* range check */ 2815 if (*plen > xfer->max_frame_size) { 2816 #if USB_DEBUG 2817 if (once) { 2818 once = 0; 2819 printf("%s: frame length(%d) exceeds %d bytes " 2820 "(frame truncated)\n", 2821 __FUNCTION__, *plen, xfer->max_frame_size); 2822 } 2823 #endif 2824 *plen = xfer->max_frame_size; 2825 } 2826 status = (EHCI_ITD_SET_LEN(*plen) | 2827 EHCI_ITD_ACTIVE | 2828 EHCI_ITD_SET_PG(0)); 2829 td->itd_status[td_no] = htohc32(sc, status); 2830 itd_offset[td_no] = buf_offset; 2831 buf_offset += *plen; 2832 plen++; 2833 td_no++; 2834 2835 if ((td_no == 8) || (nframes == 0)) { 2836 2837 /* the rest of the transfers are not active, if any */ 2838 for (x = td_no; x != 8; x++) { 2839 td->itd_status[x] = 0; /* not active */ 2840 } 2841 2842 /* check if there is any data to be transferred */ 2843 if (itd_offset[0] != buf_offset) { 2844 page_no = 0; 2845 itd_offset[td_no] = buf_offset; 2846 2847 /* get first page offset */ 2848 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2849 /* get page address */ 2850 page_addr = buf_res.physaddr & ~0xFFF; 2851 /* update page address */ 2852 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2853 td->itd_bp[0] |= htohc32(sc, page_addr); 2854 2855 for (x = 0; x != td_no; x++) { 2856 /* set page number and page offset */ 2857 status = (EHCI_ITD_SET_PG(page_no) | 2858 (buf_res.physaddr & 0xFFF)); 2859 td->itd_status[x] |= htohc32(sc, status); 2860 2861 /* get next page offset */ 2862 if (itd_offset[x + 1] == buf_offset) { 2863 /* 2864 * We subtract one so that 2865 * we don't go off the last 2866 * page! 2867 */ 2868 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2869 } else { 2870 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2871 } 2872 2873 /* check if we need a new page */ 2874 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2875 /* new page needed */ 2876 page_addr = buf_res.physaddr & ~0xFFF; 2877 if (page_no == 6) { 2878 panic("%s: too many pages\n", __FUNCTION__); 2879 } 2880 page_no++; 2881 /* update page address */ 2882 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2883 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2884 } 2885 } 2886 } 2887 /* set IOC bit if we are complete */ 2888 if (nframes == 0) { 2889 td->itd_status[7] |= htohc32(sc, EHCI_ITD_IOC); 2890 } 2891 usb2_pc_cpu_flush(td->page_cache); 2892 #if USB_DEBUG 2893 if (ehcidebug > 15) { 2894 DPRINTF("HS-TD %d\n", nframes); 2895 ehci_dump_itd(sc, td); 2896 } 2897 #endif 2898 /* insert TD into schedule */ 2899 EHCI_APPEND_HS_TD(td, *pp_last); 2900 pp_last++; 2901 2902 td_no = 0; 2903 td_last = td; 2904 td = td->obj_next; 2905 } 2906 } 2907 2908 xfer->td_transfer_last = td_last; 2909 2910 /* update isoc_next */ 2911 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2912 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2913 } 2914 2915 static void 2916 ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2917 { 2918 /* put transfer on interrupt queue */ 2919 ehci_transfer_intr_enqueue(xfer); 2920 } 2921 2922 struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2923 { 2924 .open = ehci_device_isoc_hs_open, 2925 .close = ehci_device_isoc_hs_close, 2926 .enter = ehci_device_isoc_hs_enter, 2927 .start = ehci_device_isoc_hs_start, 2928 .enter_is_cancelable = 1, 2929 .start_is_cancelable = 1, 2930 }; 2931 2932 /*------------------------------------------------------------------------* 2933 * ehci root control support 2934 *------------------------------------------------------------------------* 2935 * simulate a hardware hub by handling 2936 * all the necessary requests 2937 *------------------------------------------------------------------------*/ 2938 2939 static void 2940 ehci_root_ctrl_open(struct usb2_xfer *xfer) 2941 { 2942 return; 2943 } 2944 2945 static void 2946 ehci_root_ctrl_close(struct usb2_xfer *xfer) 2947 { 2948 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2949 2950 if (sc->sc_root_ctrl.xfer == xfer) { 2951 sc->sc_root_ctrl.xfer = NULL; 2952 } 2953 ehci_device_done(xfer, USB_ERR_CANCELLED); 2954 } 2955 2956 /* data structures and routines 2957 * to emulate the root hub: 2958 */ 2959 2960 static const 2961 struct usb2_device_descriptor ehci_devd = 2962 { 2963 sizeof(struct usb2_device_descriptor), 2964 UDESC_DEVICE, /* type */ 2965 {0x00, 0x02}, /* USB version */ 2966 UDCLASS_HUB, /* class */ 2967 UDSUBCLASS_HUB, /* subclass */ 2968 UDPROTO_HSHUBSTT, /* protocol */ 2969 64, /* max packet */ 2970 {0}, {0}, {0x00, 0x01}, /* device id */ 2971 1, 2, 0, /* string indicies */ 2972 1 /* # of configurations */ 2973 }; 2974 2975 static const 2976 struct usb2_device_qualifier ehci_odevd = 2977 { 2978 sizeof(struct usb2_device_qualifier), 2979 UDESC_DEVICE_QUALIFIER, /* type */ 2980 {0x00, 0x02}, /* USB version */ 2981 UDCLASS_HUB, /* class */ 2982 UDSUBCLASS_HUB, /* subclass */ 2983 UDPROTO_FSHUB, /* protocol */ 2984 0, /* max packet */ 2985 0, /* # of configurations */ 2986 0 2987 }; 2988 2989 static const struct ehci_config_desc ehci_confd = { 2990 .confd = { 2991 .bLength = sizeof(struct usb2_config_descriptor), 2992 .bDescriptorType = UDESC_CONFIG, 2993 .wTotalLength[0] = sizeof(ehci_confd), 2994 .bNumInterface = 1, 2995 .bConfigurationValue = 1, 2996 .iConfiguration = 0, 2997 .bmAttributes = UC_SELF_POWERED, 2998 .bMaxPower = 0 /* max power */ 2999 }, 3000 3001 .ifcd = { 3002 .bLength = sizeof(struct usb2_interface_descriptor), 3003 .bDescriptorType = UDESC_INTERFACE, 3004 .bNumEndpoints = 1, 3005 .bInterfaceClass = UICLASS_HUB, 3006 .bInterfaceSubClass = UISUBCLASS_HUB, 3007 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 3008 0 3009 }, 3010 3011 .endpd = { 3012 .bLength = sizeof(struct usb2_endpoint_descriptor), 3013 .bDescriptorType = UDESC_ENDPOINT, 3014 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3015 .bmAttributes = UE_INTERRUPT, 3016 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3017 .bInterval = 255, 3018 }, 3019 }; 3020 3021 static const 3022 struct usb2_hub_descriptor ehci_hubd = 3023 { 3024 0, /* dynamic length */ 3025 UDESC_HUB, 3026 0, 3027 {0, 0}, 3028 0, 3029 0, 3030 {0}, 3031 }; 3032 3033 static void 3034 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3035 { 3036 uint32_t port; 3037 uint32_t v; 3038 3039 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3040 3041 port = EHCI_PORTSC(index); 3042 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3043 EOWRITE4(sc, port, v | EHCI_PS_PO); 3044 } 3045 3046 static void 3047 ehci_root_ctrl_enter(struct usb2_xfer *xfer) 3048 { 3049 return; 3050 } 3051 3052 static void 3053 ehci_root_ctrl_start(struct usb2_xfer *xfer) 3054 { 3055 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3056 3057 DPRINTF("\n"); 3058 3059 sc->sc_root_ctrl.xfer = xfer; 3060 3061 usb2_bus_roothub_exec(xfer->xroot->bus); 3062 } 3063 3064 static void 3065 ehci_root_ctrl_task(struct usb2_bus *bus) 3066 { 3067 ehci_root_ctrl_poll(EHCI_BUS2SC(bus)); 3068 } 3069 3070 static void 3071 ehci_root_ctrl_done(struct usb2_xfer *xfer, 3072 struct usb2_sw_transfer *std) 3073 { 3074 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3075 char *ptr; 3076 uint32_t port; 3077 uint32_t v; 3078 uint16_t i; 3079 uint16_t value; 3080 uint16_t index; 3081 uint8_t l; 3082 3083 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3084 3085 if (std->state != USB_SW_TR_SETUP) { 3086 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3087 /* transfer transferred */ 3088 ehci_device_done(xfer, std->err); 3089 } 3090 goto done; 3091 } 3092 /* buffer reset */ 3093 std->ptr = sc->sc_hub_desc.temp; 3094 std->len = 0; 3095 3096 value = UGETW(std->req.wValue); 3097 index = UGETW(std->req.wIndex); 3098 3099 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3100 "wValue=0x%04x wIndex=0x%04x\n", 3101 std->req.bmRequestType, std->req.bRequest, 3102 UGETW(std->req.wLength), value, index); 3103 3104 #define C(x,y) ((x) | ((y) << 8)) 3105 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3106 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3107 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3108 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3109 /* 3110 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3111 * for the integrated root hub. 3112 */ 3113 break; 3114 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3115 std->len = 1; 3116 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3117 break; 3118 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3119 switch (value >> 8) { 3120 case UDESC_DEVICE: 3121 if ((value & 0xff) != 0) { 3122 std->err = USB_ERR_IOERROR; 3123 goto done; 3124 } 3125 std->len = sizeof(ehci_devd); 3126 sc->sc_hub_desc.devd = ehci_devd; 3127 break; 3128 /* 3129 * We can't really operate at another speed, 3130 * but the specification says we need this 3131 * descriptor: 3132 */ 3133 case UDESC_DEVICE_QUALIFIER: 3134 if ((value & 0xff) != 0) { 3135 std->err = USB_ERR_IOERROR; 3136 goto done; 3137 } 3138 std->len = sizeof(ehci_odevd); 3139 sc->sc_hub_desc.odevd = ehci_odevd; 3140 break; 3141 3142 case UDESC_CONFIG: 3143 if ((value & 0xff) != 0) { 3144 std->err = USB_ERR_IOERROR; 3145 goto done; 3146 } 3147 std->len = sizeof(ehci_confd); 3148 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3149 break; 3150 3151 case UDESC_STRING: 3152 switch (value & 0xff) { 3153 case 0: /* Language table */ 3154 ptr = "\001"; 3155 break; 3156 3157 case 1: /* Vendor */ 3158 ptr = sc->sc_vendor; 3159 break; 3160 3161 case 2: /* Product */ 3162 ptr = "EHCI root HUB"; 3163 break; 3164 3165 default: 3166 ptr = ""; 3167 break; 3168 } 3169 3170 std->len = usb2_make_str_desc 3171 (sc->sc_hub_desc.temp, 3172 sizeof(sc->sc_hub_desc.temp), 3173 ptr); 3174 break; 3175 default: 3176 std->err = USB_ERR_IOERROR; 3177 goto done; 3178 } 3179 break; 3180 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3181 std->len = 1; 3182 sc->sc_hub_desc.temp[0] = 0; 3183 break; 3184 case C(UR_GET_STATUS, UT_READ_DEVICE): 3185 std->len = 2; 3186 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3187 break; 3188 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3189 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3190 std->len = 2; 3191 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3192 break; 3193 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3194 if (value >= EHCI_MAX_DEVICES) { 3195 std->err = USB_ERR_IOERROR; 3196 goto done; 3197 } 3198 sc->sc_addr = value; 3199 break; 3200 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3201 if ((value != 0) && (value != 1)) { 3202 std->err = USB_ERR_IOERROR; 3203 goto done; 3204 } 3205 sc->sc_conf = value; 3206 break; 3207 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3208 break; 3209 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3210 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3211 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3212 std->err = USB_ERR_IOERROR; 3213 goto done; 3214 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3215 break; 3216 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3217 break; 3218 /* Hub requests */ 3219 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3220 break; 3221 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3222 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3223 3224 if ((index < 1) || 3225 (index > sc->sc_noport)) { 3226 std->err = USB_ERR_IOERROR; 3227 goto done; 3228 } 3229 port = EHCI_PORTSC(index); 3230 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3231 switch (value) { 3232 case UHF_PORT_ENABLE: 3233 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3234 break; 3235 case UHF_PORT_SUSPEND: 3236 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3237 3238 /* 3239 * waking up a High Speed device is rather 3240 * complicated if 3241 */ 3242 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3243 } 3244 /* wait 20ms for resume sequence to complete */ 3245 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3246 3247 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3248 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3249 3250 /* 4ms settle time */ 3251 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3252 break; 3253 case UHF_PORT_POWER: 3254 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3255 break; 3256 case UHF_PORT_TEST: 3257 DPRINTFN(3, "clear port test " 3258 "%d\n", index); 3259 break; 3260 case UHF_PORT_INDICATOR: 3261 DPRINTFN(3, "clear port ind " 3262 "%d\n", index); 3263 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3264 break; 3265 case UHF_C_PORT_CONNECTION: 3266 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3267 break; 3268 case UHF_C_PORT_ENABLE: 3269 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3270 break; 3271 case UHF_C_PORT_SUSPEND: 3272 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3273 break; 3274 case UHF_C_PORT_OVER_CURRENT: 3275 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3276 break; 3277 case UHF_C_PORT_RESET: 3278 sc->sc_isreset = 0; 3279 break; 3280 default: 3281 std->err = USB_ERR_IOERROR; 3282 goto done; 3283 } 3284 break; 3285 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3286 if ((value & 0xff) != 0) { 3287 std->err = USB_ERR_IOERROR; 3288 goto done; 3289 } 3290 v = EOREAD4(sc, EHCI_HCSPARAMS); 3291 3292 sc->sc_hub_desc.hubd = ehci_hubd; 3293 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3294 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3295 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3296 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3297 UHD_PORT_IND : 0)); 3298 /* XXX can't find out? */ 3299 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3300 for (l = 0; l < sc->sc_noport; l++) { 3301 /* XXX can't find out? */ 3302 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3303 } 3304 sc->sc_hub_desc.hubd.bDescLength = 3305 8 + ((sc->sc_noport + 7) / 8); 3306 std->len = sc->sc_hub_desc.hubd.bDescLength; 3307 break; 3308 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3309 std->len = 16; 3310 bzero(sc->sc_hub_desc.temp, 16); 3311 break; 3312 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3313 DPRINTFN(9, "get port status i=%d\n", 3314 index); 3315 if ((index < 1) || 3316 (index > sc->sc_noport)) { 3317 std->err = USB_ERR_IOERROR; 3318 goto done; 3319 } 3320 v = EOREAD4(sc, EHCI_PORTSC(index)); 3321 DPRINTFN(9, "port status=0x%04x\n", v); 3322 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3323 if ((v & 0xc000000) == 0x8000000) 3324 i = UPS_HIGH_SPEED; 3325 else if ((v & 0xc000000) == 0x4000000) 3326 i = UPS_LOW_SPEED; 3327 else 3328 i = 0; 3329 } else { 3330 i = UPS_HIGH_SPEED; 3331 } 3332 if (v & EHCI_PS_CS) 3333 i |= UPS_CURRENT_CONNECT_STATUS; 3334 if (v & EHCI_PS_PE) 3335 i |= UPS_PORT_ENABLED; 3336 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3337 i |= UPS_SUSPEND; 3338 if (v & EHCI_PS_OCA) 3339 i |= UPS_OVERCURRENT_INDICATOR; 3340 if (v & EHCI_PS_PR) 3341 i |= UPS_RESET; 3342 if (v & EHCI_PS_PP) 3343 i |= UPS_PORT_POWER; 3344 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3345 i = 0; 3346 if (v & EHCI_PS_CSC) 3347 i |= UPS_C_CONNECT_STATUS; 3348 if (v & EHCI_PS_PEC) 3349 i |= UPS_C_PORT_ENABLED; 3350 if (v & EHCI_PS_OCC) 3351 i |= UPS_C_OVERCURRENT_INDICATOR; 3352 if (v & EHCI_PS_FPR) 3353 i |= UPS_C_SUSPEND; 3354 if (sc->sc_isreset) 3355 i |= UPS_C_PORT_RESET; 3356 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3357 std->len = sizeof(sc->sc_hub_desc.ps); 3358 break; 3359 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3360 std->err = USB_ERR_IOERROR; 3361 goto done; 3362 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3363 break; 3364 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3365 if ((index < 1) || 3366 (index > sc->sc_noport)) { 3367 std->err = USB_ERR_IOERROR; 3368 goto done; 3369 } 3370 port = EHCI_PORTSC(index); 3371 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3372 switch (value) { 3373 case UHF_PORT_ENABLE: 3374 EOWRITE4(sc, port, v | EHCI_PS_PE); 3375 break; 3376 case UHF_PORT_SUSPEND: 3377 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3378 break; 3379 case UHF_PORT_RESET: 3380 DPRINTFN(6, "reset port %d\n", index); 3381 #if USB_DEBUG 3382 if (ehcinohighspeed) { 3383 /* 3384 * Connect USB device to companion 3385 * controller. 3386 */ 3387 ehci_disown(sc, index, 1); 3388 break; 3389 } 3390 #endif 3391 if (EHCI_PS_IS_LOWSPEED(v) && 3392 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3393 /* Low speed device, give up ownership. */ 3394 ehci_disown(sc, index, 1); 3395 break; 3396 } 3397 /* Start reset sequence. */ 3398 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3399 EOWRITE4(sc, port, v | EHCI_PS_PR); 3400 3401 /* Wait for reset to complete. */ 3402 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3403 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3404 3405 /* Terminate reset sequence. */ 3406 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3407 EOWRITE4(sc, port, v); 3408 3409 /* Wait for HC to complete reset. */ 3410 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3411 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3412 3413 v = EOREAD4(sc, port); 3414 DPRINTF("ehci after reset, status=0x%08x\n", v); 3415 if (v & EHCI_PS_PR) { 3416 device_printf(sc->sc_bus.bdev, 3417 "port reset timeout\n"); 3418 std->err = USB_ERR_TIMEOUT; 3419 goto done; 3420 } 3421 if (!(v & EHCI_PS_PE) && 3422 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3423 /* Not a high speed device, give up ownership.*/ 3424 ehci_disown(sc, index, 0); 3425 break; 3426 } 3427 sc->sc_isreset = 1; 3428 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3429 index, v); 3430 break; 3431 3432 case UHF_PORT_POWER: 3433 DPRINTFN(3, "set port power %d\n", index); 3434 EOWRITE4(sc, port, v | EHCI_PS_PP); 3435 break; 3436 3437 case UHF_PORT_TEST: 3438 DPRINTFN(3, "set port test %d\n", index); 3439 break; 3440 3441 case UHF_PORT_INDICATOR: 3442 DPRINTFN(3, "set port ind %d\n", index); 3443 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3444 break; 3445 3446 default: 3447 std->err = USB_ERR_IOERROR; 3448 goto done; 3449 } 3450 break; 3451 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3452 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3453 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3454 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3455 break; 3456 default: 3457 std->err = USB_ERR_IOERROR; 3458 goto done; 3459 } 3460 done: 3461 return; 3462 } 3463 3464 static void 3465 ehci_root_ctrl_poll(ehci_softc_t *sc) 3466 { 3467 usb2_sw_transfer(&sc->sc_root_ctrl, 3468 &ehci_root_ctrl_done); 3469 } 3470 3471 struct usb2_pipe_methods ehci_root_ctrl_methods = 3472 { 3473 .open = ehci_root_ctrl_open, 3474 .close = ehci_root_ctrl_close, 3475 .enter = ehci_root_ctrl_enter, 3476 .start = ehci_root_ctrl_start, 3477 .enter_is_cancelable = 1, 3478 .start_is_cancelable = 0, 3479 }; 3480 3481 /*------------------------------------------------------------------------* 3482 * ehci root interrupt support 3483 *------------------------------------------------------------------------*/ 3484 static void 3485 ehci_root_intr_open(struct usb2_xfer *xfer) 3486 { 3487 return; 3488 } 3489 3490 static void 3491 ehci_root_intr_close(struct usb2_xfer *xfer) 3492 { 3493 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3494 3495 if (sc->sc_root_intr.xfer == xfer) { 3496 sc->sc_root_intr.xfer = NULL; 3497 } 3498 ehci_device_done(xfer, USB_ERR_CANCELLED); 3499 } 3500 3501 static void 3502 ehci_root_intr_enter(struct usb2_xfer *xfer) 3503 { 3504 return; 3505 } 3506 3507 static void 3508 ehci_root_intr_start(struct usb2_xfer *xfer) 3509 { 3510 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3511 3512 sc->sc_root_intr.xfer = xfer; 3513 } 3514 3515 struct usb2_pipe_methods ehci_root_intr_methods = 3516 { 3517 .open = ehci_root_intr_open, 3518 .close = ehci_root_intr_close, 3519 .enter = ehci_root_intr_enter, 3520 .start = ehci_root_intr_start, 3521 .enter_is_cancelable = 1, 3522 .start_is_cancelable = 1, 3523 }; 3524 3525 static void 3526 ehci_xfer_setup(struct usb2_setup_params *parm) 3527 { 3528 struct usb2_page_search page_info; 3529 struct usb2_page_cache *pc; 3530 ehci_softc_t *sc; 3531 struct usb2_xfer *xfer; 3532 void *last_obj; 3533 uint32_t nqtd; 3534 uint32_t nqh; 3535 uint32_t nsitd; 3536 uint32_t nitd; 3537 uint32_t n; 3538 3539 sc = EHCI_BUS2SC(parm->udev->bus); 3540 xfer = parm->curr_xfer; 3541 3542 nqtd = 0; 3543 nqh = 0; 3544 nsitd = 0; 3545 nitd = 0; 3546 3547 /* 3548 * compute maximum number of some structures 3549 */ 3550 if (parm->methods == &ehci_device_ctrl_methods) { 3551 3552 /* 3553 * The proof for the "nqtd" formula is illustrated like 3554 * this: 3555 * 3556 * +------------------------------------+ 3557 * | | 3558 * | |remainder -> | 3559 * | +-----+---+ | 3560 * | | xxx | x | frm 0 | 3561 * | +-----+---++ | 3562 * | | xxx | xx | frm 1 | 3563 * | +-----+----+ | 3564 * | ... | 3565 * +------------------------------------+ 3566 * 3567 * "xxx" means a completely full USB transfer descriptor 3568 * 3569 * "x" and "xx" means a short USB packet 3570 * 3571 * For the remainder of an USB transfer modulo 3572 * "max_data_length" we need two USB transfer descriptors. 3573 * One to transfer the remaining data and one to finalise 3574 * with a zero length packet in case the "force_short_xfer" 3575 * flag is set. We only need two USB transfer descriptors in 3576 * the case where the transfer length of the first one is a 3577 * factor of "max_frame_size". The rest of the needed USB 3578 * transfer descriptors is given by the buffer size divided 3579 * by the maximum data payload. 3580 */ 3581 parm->hc_max_packet_size = 0x400; 3582 parm->hc_max_packet_count = 1; 3583 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3584 xfer->flags_int.bdma_enable = 1; 3585 3586 usb2_transfer_setup_sub(parm); 3587 3588 nqh = 1; 3589 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3590 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3591 3592 } else if (parm->methods == &ehci_device_bulk_methods) { 3593 3594 parm->hc_max_packet_size = 0x400; 3595 parm->hc_max_packet_count = 1; 3596 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3597 xfer->flags_int.bdma_enable = 1; 3598 3599 usb2_transfer_setup_sub(parm); 3600 3601 nqh = 1; 3602 nqtd = ((2 * xfer->nframes) 3603 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3604 3605 } else if (parm->methods == &ehci_device_intr_methods) { 3606 3607 if (parm->speed == USB_SPEED_HIGH) { 3608 parm->hc_max_packet_size = 0x400; 3609 parm->hc_max_packet_count = 3; 3610 } else if (parm->speed == USB_SPEED_FULL) { 3611 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3612 parm->hc_max_packet_count = 1; 3613 } else { 3614 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3615 parm->hc_max_packet_count = 1; 3616 } 3617 3618 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3619 xfer->flags_int.bdma_enable = 1; 3620 3621 usb2_transfer_setup_sub(parm); 3622 3623 nqh = 1; 3624 nqtd = ((2 * xfer->nframes) 3625 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3626 3627 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3628 3629 parm->hc_max_packet_size = 0x3FF; 3630 parm->hc_max_packet_count = 1; 3631 parm->hc_max_frame_size = 0x3FF; 3632 xfer->flags_int.bdma_enable = 1; 3633 3634 usb2_transfer_setup_sub(parm); 3635 3636 nsitd = xfer->nframes; 3637 3638 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3639 3640 parm->hc_max_packet_size = 0x400; 3641 parm->hc_max_packet_count = 3; 3642 parm->hc_max_frame_size = 0xC00; 3643 xfer->flags_int.bdma_enable = 1; 3644 3645 usb2_transfer_setup_sub(parm); 3646 3647 nitd = (xfer->nframes + 7) / 8; 3648 3649 } else { 3650 3651 parm->hc_max_packet_size = 0x400; 3652 parm->hc_max_packet_count = 1; 3653 parm->hc_max_frame_size = 0x400; 3654 3655 usb2_transfer_setup_sub(parm); 3656 } 3657 3658 alloc_dma_set: 3659 3660 if (parm->err) { 3661 return; 3662 } 3663 /* 3664 * Allocate queue heads and transfer descriptors 3665 */ 3666 last_obj = NULL; 3667 3668 if (usb2_transfer_setup_sub_malloc( 3669 parm, &pc, sizeof(ehci_itd_t), 3670 EHCI_ITD_ALIGN, nitd)) { 3671 parm->err = USB_ERR_NOMEM; 3672 return; 3673 } 3674 if (parm->buf) { 3675 for (n = 0; n != nitd; n++) { 3676 ehci_itd_t *td; 3677 3678 usb2_get_page(pc + n, 0, &page_info); 3679 3680 td = page_info.buffer; 3681 3682 /* init TD */ 3683 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3684 td->obj_next = last_obj; 3685 td->page_cache = pc + n; 3686 3687 last_obj = td; 3688 3689 usb2_pc_cpu_flush(pc + n); 3690 } 3691 } 3692 if (usb2_transfer_setup_sub_malloc( 3693 parm, &pc, sizeof(ehci_sitd_t), 3694 EHCI_SITD_ALIGN, nsitd)) { 3695 parm->err = USB_ERR_NOMEM; 3696 return; 3697 } 3698 if (parm->buf) { 3699 for (n = 0; n != nsitd; n++) { 3700 ehci_sitd_t *td; 3701 3702 usb2_get_page(pc + n, 0, &page_info); 3703 3704 td = page_info.buffer; 3705 3706 /* init TD */ 3707 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3708 td->obj_next = last_obj; 3709 td->page_cache = pc + n; 3710 3711 last_obj = td; 3712 3713 usb2_pc_cpu_flush(pc + n); 3714 } 3715 } 3716 if (usb2_transfer_setup_sub_malloc( 3717 parm, &pc, sizeof(ehci_qtd_t), 3718 EHCI_QTD_ALIGN, nqtd)) { 3719 parm->err = USB_ERR_NOMEM; 3720 return; 3721 } 3722 if (parm->buf) { 3723 for (n = 0; n != nqtd; n++) { 3724 ehci_qtd_t *qtd; 3725 3726 usb2_get_page(pc + n, 0, &page_info); 3727 3728 qtd = page_info.buffer; 3729 3730 /* init TD */ 3731 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3732 qtd->obj_next = last_obj; 3733 qtd->page_cache = pc + n; 3734 3735 last_obj = qtd; 3736 3737 usb2_pc_cpu_flush(pc + n); 3738 } 3739 } 3740 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3741 3742 last_obj = NULL; 3743 3744 if (usb2_transfer_setup_sub_malloc( 3745 parm, &pc, sizeof(ehci_qh_t), 3746 EHCI_QH_ALIGN, nqh)) { 3747 parm->err = USB_ERR_NOMEM; 3748 return; 3749 } 3750 if (parm->buf) { 3751 for (n = 0; n != nqh; n++) { 3752 ehci_qh_t *qh; 3753 3754 usb2_get_page(pc + n, 0, &page_info); 3755 3756 qh = page_info.buffer; 3757 3758 /* init QH */ 3759 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3760 qh->obj_next = last_obj; 3761 qh->page_cache = pc + n; 3762 3763 last_obj = qh; 3764 3765 usb2_pc_cpu_flush(pc + n); 3766 } 3767 } 3768 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3769 3770 if (!xfer->flags_int.curr_dma_set) { 3771 xfer->flags_int.curr_dma_set = 1; 3772 goto alloc_dma_set; 3773 } 3774 } 3775 3776 static void 3777 ehci_xfer_unsetup(struct usb2_xfer *xfer) 3778 { 3779 return; 3780 } 3781 3782 static void 3783 ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3784 struct usb2_pipe *pipe) 3785 { 3786 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3787 3788 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3789 pipe, udev->address, 3790 edesc->bEndpointAddress, udev->flags.usb2_mode, 3791 sc->sc_addr); 3792 3793 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3794 /* not supported */ 3795 return; 3796 } 3797 if (udev->device_index == sc->sc_addr) { 3798 switch (edesc->bEndpointAddress) { 3799 case USB_CONTROL_ENDPOINT: 3800 pipe->methods = &ehci_root_ctrl_methods; 3801 break; 3802 case UE_DIR_IN | EHCI_INTR_ENDPT: 3803 pipe->methods = &ehci_root_intr_methods; 3804 break; 3805 default: 3806 /* do nothing */ 3807 break; 3808 } 3809 } else { 3810 if ((udev->speed != USB_SPEED_HIGH) && 3811 ((udev->hs_hub_addr == 0) || 3812 (udev->hs_port_no == 0) || 3813 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3814 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3815 /* We need a transaction translator */ 3816 goto done; 3817 } 3818 switch (edesc->bmAttributes & UE_XFERTYPE) { 3819 case UE_CONTROL: 3820 pipe->methods = &ehci_device_ctrl_methods; 3821 break; 3822 case UE_INTERRUPT: 3823 pipe->methods = &ehci_device_intr_methods; 3824 break; 3825 case UE_ISOCHRONOUS: 3826 if (udev->speed == USB_SPEED_HIGH) { 3827 pipe->methods = &ehci_device_isoc_hs_methods; 3828 } else if (udev->speed == USB_SPEED_FULL) { 3829 pipe->methods = &ehci_device_isoc_fs_methods; 3830 } 3831 break; 3832 case UE_BULK: 3833 if (udev->speed != USB_SPEED_LOW) { 3834 pipe->methods = &ehci_device_bulk_methods; 3835 } 3836 break; 3837 default: 3838 /* do nothing */ 3839 break; 3840 } 3841 } 3842 done: 3843 return; 3844 } 3845 3846 static void 3847 ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3848 { 3849 /* 3850 * Wait until the hardware has finished any possible use of 3851 * the transfer descriptor(s) and QH 3852 */ 3853 *pus = (188); /* microseconds */ 3854 } 3855 3856 static void 3857 ehci_device_resume(struct usb2_device *udev) 3858 { 3859 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3860 struct usb2_xfer *xfer; 3861 struct usb2_pipe_methods *methods; 3862 3863 DPRINTF("\n"); 3864 3865 USB_BUS_LOCK(udev->bus); 3866 3867 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3868 3869 if (xfer->xroot->udev == udev) { 3870 3871 methods = xfer->pipe->methods; 3872 3873 if ((methods == &ehci_device_bulk_methods) || 3874 (methods == &ehci_device_ctrl_methods)) { 3875 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3876 sc->sc_async_p_last); 3877 } 3878 if (methods == &ehci_device_intr_methods) { 3879 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3880 sc->sc_intr_p_last[xfer->qh_pos]); 3881 } 3882 } 3883 } 3884 3885 USB_BUS_UNLOCK(udev->bus); 3886 3887 return; 3888 } 3889 3890 static void 3891 ehci_device_suspend(struct usb2_device *udev) 3892 { 3893 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3894 struct usb2_xfer *xfer; 3895 struct usb2_pipe_methods *methods; 3896 3897 DPRINTF("\n"); 3898 3899 USB_BUS_LOCK(udev->bus); 3900 3901 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3902 3903 if (xfer->xroot->udev == udev) { 3904 3905 methods = xfer->pipe->methods; 3906 3907 if ((methods == &ehci_device_bulk_methods) || 3908 (methods == &ehci_device_ctrl_methods)) { 3909 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3910 sc->sc_async_p_last); 3911 } 3912 if (methods == &ehci_device_intr_methods) { 3913 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3914 sc->sc_intr_p_last[xfer->qh_pos]); 3915 } 3916 } 3917 } 3918 3919 USB_BUS_UNLOCK(udev->bus); 3920 3921 return; 3922 } 3923 3924 static void 3925 ehci_set_hw_power(struct usb2_bus *bus) 3926 { 3927 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3928 uint32_t temp; 3929 uint32_t flags; 3930 3931 DPRINTF("\n"); 3932 3933 USB_BUS_LOCK(bus); 3934 3935 flags = bus->hw_power_state; 3936 3937 temp = EOREAD4(sc, EHCI_USBCMD); 3938 3939 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3940 3941 if (flags & (USB_HW_POWER_CONTROL | 3942 USB_HW_POWER_BULK)) { 3943 DPRINTF("Async is active\n"); 3944 temp |= EHCI_CMD_ASE; 3945 } 3946 if (flags & (USB_HW_POWER_INTERRUPT | 3947 USB_HW_POWER_ISOC)) { 3948 DPRINTF("Periodic is active\n"); 3949 temp |= EHCI_CMD_PSE; 3950 } 3951 EOWRITE4(sc, EHCI_USBCMD, temp); 3952 3953 USB_BUS_UNLOCK(bus); 3954 3955 return; 3956 } 3957 3958 struct usb2_bus_methods ehci_bus_methods = 3959 { 3960 .pipe_init = ehci_pipe_init, 3961 .xfer_setup = ehci_xfer_setup, 3962 .xfer_unsetup = ehci_xfer_unsetup, 3963 .get_dma_delay = ehci_get_dma_delay, 3964 .device_resume = ehci_device_resume, 3965 .device_suspend = ehci_device_suspend, 3966 .set_hw_power = ehci_set_hw_power, 3967 .roothub_exec = ehci_root_ctrl_task, 3968 }; 3969