1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usb_mfunc.h> 51 #include <dev/usb/usb_error.h> 52 #include <dev/usb/usb_defs.h> 53 54 #define USB_DEBUG_VAR ehcidebug 55 56 #include <dev/usb/usb_core.h> 57 #include <dev/usb/usb_debug.h> 58 #include <dev/usb/usb_busdma.h> 59 #include <dev/usb/usb_process.h> 60 #include <dev/usb/usb_sw_transfer.h> 61 #include <dev/usb/usb_transfer.h> 62 #include <dev/usb/usb_device.h> 63 #include <dev/usb/usb_hub.h> 64 #include <dev/usb/usb_util.h> 65 66 #include <dev/usb/usb_controller.h> 67 #include <dev/usb/usb_bus.h> 68 #include <dev/usb/controller/ehci.h> 69 70 #define EHCI_BUS2SC(bus) ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 71 USB_P2U(&(((ehci_softc_t *)0)->sc_bus)))) 72 73 #if USB_DEBUG 74 static int ehcidebug = 0; 75 static int ehcinohighspeed = 0; 76 77 SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 78 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 79 &ehcidebug, 0, "Debug level"); 80 SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 81 &ehcinohighspeed, 0, "Disable High Speed USB"); 82 83 static void ehci_dump_regs(ehci_softc_t *sc); 84 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 85 86 #endif 87 88 #define EHCI_INTR_ENDPT 1 89 90 extern struct usb2_bus_methods ehci_bus_methods; 91 extern struct usb2_pipe_methods ehci_device_bulk_methods; 92 extern struct usb2_pipe_methods ehci_device_ctrl_methods; 93 extern struct usb2_pipe_methods ehci_device_intr_methods; 94 extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 95 extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 96 extern struct usb2_pipe_methods ehci_root_ctrl_methods; 97 extern struct usb2_pipe_methods ehci_root_intr_methods; 98 99 static void ehci_do_poll(struct usb2_bus *bus); 100 static void ehci_root_ctrl_poll(ehci_softc_t *sc); 101 static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102 static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 103 static void ehci_timeout(void *arg); 104 105 static usb2_sw_transfer_func_t ehci_root_intr_done; 106 static usb2_sw_transfer_func_t ehci_root_ctrl_done; 107 108 struct ehci_std_temp { 109 ehci_softc_t *sc; 110 struct usb2_page_cache *pc; 111 ehci_qtd_t *td; 112 ehci_qtd_t *td_next; 113 uint32_t average; 114 uint32_t qtd_status; 115 uint32_t len; 116 uint16_t max_frame_size; 117 uint8_t shortpkt; 118 uint8_t auto_data_toggle; 119 uint8_t setup_alt_next; 120 uint8_t short_frames_ok; 121 }; 122 123 /* 124 * Byte-order conversion functions. 125 */ 126 static uint32_t 127 htoehci32(ehci_softc_t *sc, const uint32_t v) 128 { 129 return ((sc->sc_flags & EHCI_SCFLG_BIGEDESC) ? 130 htobe32(v) : htole32(v)); 131 } 132 133 static uint32_t 134 ehci32toh(ehci_softc_t *sc, const uint32_t v) 135 { 136 return ((sc->sc_flags & EHCI_SCFLG_BIGEDESC) ? 137 be32toh(v) : le32toh(v)); 138 } 139 140 void 141 ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 142 { 143 ehci_softc_t *sc = EHCI_BUS2SC(bus); 144 uint32_t i; 145 146 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 147 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 148 149 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 150 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 151 152 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 153 cb(bus, sc->sc_hw.intr_start_pc + i, 154 sc->sc_hw.intr_start_pg + i, 155 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 156 } 157 158 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 159 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 160 sc->sc_hw.isoc_hs_start_pg + i, 161 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 162 } 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 166 sc->sc_hw.isoc_fs_start_pg + i, 167 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 168 } 169 } 170 171 static usb2_error_t 172 ehci_hc_reset(ehci_softc_t *sc) 173 { 174 uint32_t hcr; 175 uint32_t n; 176 177 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 178 179 for (n = 0; n != 100; n++) { 180 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 181 hcr = EOREAD4(sc, EHCI_USBSTS); 182 if (hcr & EHCI_STS_HCH) { 183 hcr = 0; 184 break; 185 } 186 } 187 188 /* 189 * Fall through and try reset anyway even though 190 * Table 2-9 in the EHCI spec says this will result 191 * in undefined behavior. 192 */ 193 194 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 195 for (n = 0; n != 100; n++) { 196 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 197 hcr = EOREAD4(sc, EHCI_USBCMD); 198 if (!(hcr & EHCI_CMD_HCRESET)) { 199 if (sc->sc_flags & EHCI_SCFLG_SETMODE) 200 EOWRITE4(sc, 0x68, 0x3); 201 hcr = 0; 202 break; 203 } 204 } 205 206 if (hcr) { 207 return (USB_ERR_IOERROR); 208 } 209 return (0); 210 } 211 212 usb2_error_t 213 ehci_init(ehci_softc_t *sc) 214 { 215 struct usb2_page_search buf_res; 216 uint32_t version; 217 uint32_t sparams; 218 uint32_t cparams; 219 uint32_t hcr; 220 uint16_t i; 221 uint16_t x; 222 uint16_t y; 223 uint16_t bit; 224 usb2_error_t err = 0; 225 226 DPRINTF("start\n"); 227 228 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 229 230 #if USB_DEBUG 231 if (ehcidebug > 2) { 232 ehci_dump_regs(sc); 233 } 234 #endif 235 236 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 237 238 version = EREAD2(sc, EHCI_HCIVERSION); 239 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 240 version >> 8, version & 0xff); 241 242 sparams = EREAD4(sc, EHCI_HCSPARAMS); 243 DPRINTF("sparams=0x%x\n", sparams); 244 245 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 246 cparams = EREAD4(sc, EHCI_HCCPARAMS); 247 DPRINTF("cparams=0x%x\n", cparams); 248 249 if (EHCI_HCC_64BIT(cparams)) { 250 DPRINTF("HCC uses 64-bit structures\n"); 251 252 /* MUST clear segment register if 64 bit capable */ 253 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 254 } 255 sc->sc_bus.usbrev = USB_REV_2_0; 256 257 /* Reset the controller */ 258 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 259 260 USB_BUS_LOCK(&sc->sc_bus); 261 err = ehci_hc_reset(sc); 262 USB_BUS_UNLOCK(&sc->sc_bus); 263 if (err) { 264 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 265 return (err); 266 } 267 /* 268 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 269 * bytes 2: 256*4 bytes 3: unknown 270 */ 271 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 272 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 273 return (USB_ERR_IOERROR); 274 } 275 /* set up the bus struct */ 276 sc->sc_bus.methods = &ehci_bus_methods; 277 278 sc->sc_eintrs = EHCI_NORMAL_INTRS; 279 280 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 281 ehci_qh_t *qh; 282 283 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 284 285 qh = buf_res.buffer; 286 287 /* initialize page cache pointer */ 288 289 qh->page_cache = sc->sc_hw.intr_start_pc + i; 290 291 /* store a pointer to queue head */ 292 293 sc->sc_intr_p_last[i] = qh; 294 295 qh->qh_self = 296 htoehci32(sc, buf_res.physaddr) | 297 htoehci32(sc, EHCI_LINK_QH); 298 299 qh->qh_endp = 300 htoehci32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 301 qh->qh_endphub = 302 htoehci32(sc, EHCI_QH_SET_MULT(1)); 303 qh->qh_curqtd = 0; 304 305 qh->qh_qtd.qtd_next = 306 htoehci32(sc, EHCI_LINK_TERMINATE); 307 qh->qh_qtd.qtd_altnext = 308 htoehci32(sc, EHCI_LINK_TERMINATE); 309 qh->qh_qtd.qtd_status = 310 htoehci32(sc, EHCI_QTD_HALTED); 311 } 312 313 /* 314 * the QHs are arranged to give poll intervals that are 315 * powers of 2 times 1ms 316 */ 317 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 318 while (bit) { 319 x = bit; 320 while (x & bit) { 321 ehci_qh_t *qh_x; 322 ehci_qh_t *qh_y; 323 324 y = (x ^ bit) | (bit / 2); 325 326 qh_x = sc->sc_intr_p_last[x]; 327 qh_y = sc->sc_intr_p_last[y]; 328 329 /* 330 * the next QH has half the poll interval 331 */ 332 qh_x->qh_link = qh_y->qh_self; 333 334 x++; 335 } 336 bit >>= 1; 337 } 338 339 if (1) { 340 ehci_qh_t *qh; 341 342 qh = sc->sc_intr_p_last[0]; 343 344 /* the last (1ms) QH terminates */ 345 qh->qh_link = htoehci32(sc, EHCI_LINK_TERMINATE); 346 } 347 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 348 ehci_sitd_t *sitd; 349 ehci_itd_t *itd; 350 351 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 352 353 sitd = buf_res.buffer; 354 355 /* initialize page cache pointer */ 356 357 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 358 359 /* store a pointer to the transfer descriptor */ 360 361 sc->sc_isoc_fs_p_last[i] = sitd; 362 363 /* initialize full speed isochronous */ 364 365 sitd->sitd_self = 366 htoehci32(sc, buf_res.physaddr) | 367 htoehci32(sc, EHCI_LINK_SITD); 368 369 sitd->sitd_back = 370 htoehci32(sc, EHCI_LINK_TERMINATE); 371 372 sitd->sitd_next = 373 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 374 375 376 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 377 378 itd = buf_res.buffer; 379 380 /* initialize page cache pointer */ 381 382 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 383 384 /* store a pointer to the transfer descriptor */ 385 386 sc->sc_isoc_hs_p_last[i] = itd; 387 388 /* initialize high speed isochronous */ 389 390 itd->itd_self = 391 htoehci32(sc, buf_res.physaddr) | 392 htoehci32(sc, EHCI_LINK_ITD); 393 394 itd->itd_next = 395 sitd->sitd_self; 396 } 397 398 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 399 400 if (1) { 401 uint32_t *pframes; 402 403 pframes = buf_res.buffer; 404 405 /* 406 * execution order: 407 * pframes -> high speed isochronous -> 408 * full speed isochronous -> interrupt QH's 409 */ 410 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 411 pframes[i] = sc->sc_isoc_hs_p_last 412 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 413 } 414 } 415 /* setup sync list pointer */ 416 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 417 418 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 419 420 if (1) { 421 422 ehci_qh_t *qh; 423 424 qh = buf_res.buffer; 425 426 /* initialize page cache pointer */ 427 428 qh->page_cache = &sc->sc_hw.async_start_pc; 429 430 /* store a pointer to the queue head */ 431 432 sc->sc_async_p_last = qh; 433 434 /* init dummy QH that starts the async list */ 435 436 qh->qh_self = 437 htoehci32(sc, buf_res.physaddr) | 438 htoehci32(sc, EHCI_LINK_QH); 439 440 /* fill the QH */ 441 qh->qh_endp = 442 htoehci32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 443 qh->qh_endphub = htoehci32(sc, EHCI_QH_SET_MULT(1)); 444 qh->qh_link = qh->qh_self; 445 qh->qh_curqtd = 0; 446 447 /* fill the overlay qTD */ 448 qh->qh_qtd.qtd_next = htoehci32(sc, EHCI_LINK_TERMINATE); 449 qh->qh_qtd.qtd_altnext = htoehci32(sc, EHCI_LINK_TERMINATE); 450 qh->qh_qtd.qtd_status = htoehci32(sc, EHCI_QTD_HALTED); 451 } 452 /* flush all cache into memory */ 453 454 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 455 456 #if USB_DEBUG 457 if (ehcidebug) { 458 ehci_dump_sqh(sc, sc->sc_async_p_last); 459 } 460 #endif 461 462 /* setup async list pointer */ 463 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 464 465 466 /* enable interrupts */ 467 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 468 469 /* turn on controller */ 470 EOWRITE4(sc, EHCI_USBCMD, 471 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 472 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 473 EHCI_CMD_ASE | 474 EHCI_CMD_PSE | 475 EHCI_CMD_RS); 476 477 /* Take over port ownership */ 478 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 479 480 for (i = 0; i < 100; i++) { 481 usb2_pause_mtx(NULL, hz / 1000); 482 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 483 if (!hcr) { 484 break; 485 } 486 } 487 if (hcr) { 488 device_printf(sc->sc_bus.bdev, "run timeout\n"); 489 return (USB_ERR_IOERROR); 490 } 491 492 if (!err) { 493 /* catch any lost interrupts */ 494 ehci_do_poll(&sc->sc_bus); 495 } 496 return (err); 497 } 498 499 /* 500 * shut down the controller when the system is going down 501 */ 502 void 503 ehci_detach(ehci_softc_t *sc) 504 { 505 USB_BUS_LOCK(&sc->sc_bus); 506 507 usb2_callout_stop(&sc->sc_tmo_pcd); 508 509 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 510 511 if (ehci_hc_reset(sc)) { 512 DPRINTF("reset failed!\n"); 513 } 514 515 USB_BUS_UNLOCK(&sc->sc_bus); 516 517 /* XXX let stray task complete */ 518 usb2_pause_mtx(NULL, hz / 20); 519 520 usb2_callout_drain(&sc->sc_tmo_pcd); 521 } 522 523 void 524 ehci_suspend(ehci_softc_t *sc) 525 { 526 uint32_t cmd; 527 uint32_t hcr; 528 uint8_t i; 529 530 USB_BUS_LOCK(&sc->sc_bus); 531 532 for (i = 1; i <= sc->sc_noport; i++) { 533 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 534 if (((cmd & EHCI_PS_PO) == 0) && 535 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 536 EOWRITE4(sc, EHCI_PORTSC(i), 537 cmd | EHCI_PS_SUSP); 538 } 539 } 540 541 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 542 543 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 544 EOWRITE4(sc, EHCI_USBCMD, cmd); 545 546 for (i = 0; i < 100; i++) { 547 hcr = EOREAD4(sc, EHCI_USBSTS) & 548 (EHCI_STS_ASS | EHCI_STS_PSS); 549 550 if (hcr == 0) { 551 break; 552 } 553 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 554 } 555 556 if (hcr != 0) { 557 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 558 } 559 cmd &= ~EHCI_CMD_RS; 560 EOWRITE4(sc, EHCI_USBCMD, cmd); 561 562 for (i = 0; i < 100; i++) { 563 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 564 if (hcr == EHCI_STS_HCH) { 565 break; 566 } 567 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 568 } 569 570 if (hcr != EHCI_STS_HCH) { 571 device_printf(sc->sc_bus.bdev, 572 "config timeout\n"); 573 } 574 USB_BUS_UNLOCK(&sc->sc_bus); 575 } 576 577 void 578 ehci_resume(ehci_softc_t *sc) 579 { 580 struct usb2_page_search buf_res; 581 uint32_t cmd; 582 uint32_t hcr; 583 uint8_t i; 584 585 USB_BUS_LOCK(&sc->sc_bus); 586 587 /* restore things in case the bios doesn't */ 588 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 589 590 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 591 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 592 593 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 594 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 595 596 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 597 598 hcr = 0; 599 for (i = 1; i <= sc->sc_noport; i++) { 600 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 601 if (((cmd & EHCI_PS_PO) == 0) && 602 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 603 EOWRITE4(sc, EHCI_PORTSC(i), 604 cmd | EHCI_PS_FPR); 605 hcr = 1; 606 } 607 } 608 609 if (hcr) { 610 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 611 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 612 613 for (i = 1; i <= sc->sc_noport; i++) { 614 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 615 if (((cmd & EHCI_PS_PO) == 0) && 616 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 617 EOWRITE4(sc, EHCI_PORTSC(i), 618 cmd & ~EHCI_PS_FPR); 619 } 620 } 621 } 622 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 623 624 for (i = 0; i < 100; i++) { 625 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 626 if (hcr != EHCI_STS_HCH) { 627 break; 628 } 629 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 630 } 631 if (hcr == EHCI_STS_HCH) { 632 device_printf(sc->sc_bus.bdev, "config timeout\n"); 633 } 634 635 USB_BUS_UNLOCK(&sc->sc_bus); 636 637 usb2_pause_mtx(NULL, 638 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 639 640 /* catch any lost interrupts */ 641 ehci_do_poll(&sc->sc_bus); 642 } 643 644 void 645 ehci_shutdown(ehci_softc_t *sc) 646 { 647 DPRINTF("stopping the HC\n"); 648 649 USB_BUS_LOCK(&sc->sc_bus); 650 651 if (ehci_hc_reset(sc)) { 652 DPRINTF("reset failed!\n"); 653 } 654 USB_BUS_UNLOCK(&sc->sc_bus); 655 } 656 657 #if USB_DEBUG 658 static void 659 ehci_dump_regs(ehci_softc_t *sc) 660 { 661 uint32_t i; 662 663 i = EOREAD4(sc, EHCI_USBCMD); 664 printf("cmd=0x%08x\n", i); 665 666 if (i & EHCI_CMD_ITC_1) 667 printf(" EHCI_CMD_ITC_1\n"); 668 if (i & EHCI_CMD_ITC_2) 669 printf(" EHCI_CMD_ITC_2\n"); 670 if (i & EHCI_CMD_ITC_4) 671 printf(" EHCI_CMD_ITC_4\n"); 672 if (i & EHCI_CMD_ITC_8) 673 printf(" EHCI_CMD_ITC_8\n"); 674 if (i & EHCI_CMD_ITC_16) 675 printf(" EHCI_CMD_ITC_16\n"); 676 if (i & EHCI_CMD_ITC_32) 677 printf(" EHCI_CMD_ITC_32\n"); 678 if (i & EHCI_CMD_ITC_64) 679 printf(" EHCI_CMD_ITC_64\n"); 680 if (i & EHCI_CMD_ASPME) 681 printf(" EHCI_CMD_ASPME\n"); 682 if (i & EHCI_CMD_ASPMC) 683 printf(" EHCI_CMD_ASPMC\n"); 684 if (i & EHCI_CMD_LHCR) 685 printf(" EHCI_CMD_LHCR\n"); 686 if (i & EHCI_CMD_IAAD) 687 printf(" EHCI_CMD_IAAD\n"); 688 if (i & EHCI_CMD_ASE) 689 printf(" EHCI_CMD_ASE\n"); 690 if (i & EHCI_CMD_PSE) 691 printf(" EHCI_CMD_PSE\n"); 692 if (i & EHCI_CMD_FLS_M) 693 printf(" EHCI_CMD_FLS_M\n"); 694 if (i & EHCI_CMD_HCRESET) 695 printf(" EHCI_CMD_HCRESET\n"); 696 if (i & EHCI_CMD_RS) 697 printf(" EHCI_CMD_RS\n"); 698 699 i = EOREAD4(sc, EHCI_USBSTS); 700 701 printf("sts=0x%08x\n", i); 702 703 if (i & EHCI_STS_ASS) 704 printf(" EHCI_STS_ASS\n"); 705 if (i & EHCI_STS_PSS) 706 printf(" EHCI_STS_PSS\n"); 707 if (i & EHCI_STS_REC) 708 printf(" EHCI_STS_REC\n"); 709 if (i & EHCI_STS_HCH) 710 printf(" EHCI_STS_HCH\n"); 711 if (i & EHCI_STS_IAA) 712 printf(" EHCI_STS_IAA\n"); 713 if (i & EHCI_STS_HSE) 714 printf(" EHCI_STS_HSE\n"); 715 if (i & EHCI_STS_FLR) 716 printf(" EHCI_STS_FLR\n"); 717 if (i & EHCI_STS_PCD) 718 printf(" EHCI_STS_PCD\n"); 719 if (i & EHCI_STS_ERRINT) 720 printf(" EHCI_STS_ERRINT\n"); 721 if (i & EHCI_STS_INT) 722 printf(" EHCI_STS_INT\n"); 723 724 printf("ien=0x%08x\n", 725 EOREAD4(sc, EHCI_USBINTR)); 726 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 727 EOREAD4(sc, EHCI_FRINDEX), 728 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 729 EOREAD4(sc, EHCI_PERIODICLISTBASE), 730 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 731 for (i = 1; i <= sc->sc_noport; i++) { 732 printf("port %d status=0x%08x\n", i, 733 EOREAD4(sc, EHCI_PORTSC(i))); 734 } 735 } 736 737 static void 738 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 739 { 740 link = ehci32toh(sc, link); 741 printf("0x%08x", link); 742 if (link & EHCI_LINK_TERMINATE) 743 printf("<T>"); 744 else { 745 printf("<"); 746 if (type) { 747 switch (EHCI_LINK_TYPE(link)) { 748 case EHCI_LINK_ITD: 749 printf("ITD"); 750 break; 751 case EHCI_LINK_QH: 752 printf("QH"); 753 break; 754 case EHCI_LINK_SITD: 755 printf("SITD"); 756 break; 757 case EHCI_LINK_FSTN: 758 printf("FSTN"); 759 break; 760 } 761 } 762 printf(">"); 763 } 764 } 765 766 static void 767 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 768 { 769 uint32_t s; 770 771 printf(" next="); 772 ehci_dump_link(sc, qtd->qtd_next, 0); 773 printf(" altnext="); 774 ehci_dump_link(sc, qtd->qtd_altnext, 0); 775 printf("\n"); 776 s = ehci32toh(sc, qtd->qtd_status); 777 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 778 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 779 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 780 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 781 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 782 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 783 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 784 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 785 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 786 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 787 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 788 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 789 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 790 791 for (s = 0; s < 5; s++) { 792 printf(" buffer[%d]=0x%08x\n", s, 793 ehci32toh(sc, qtd->qtd_buffer[s])); 794 } 795 for (s = 0; s < 5; s++) { 796 printf(" buffer_hi[%d]=0x%08x\n", s, 797 ehci32toh(sc, qtd->qtd_buffer_hi[s])); 798 } 799 } 800 801 static uint8_t 802 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 803 { 804 uint8_t temp; 805 806 usb2_pc_cpu_invalidate(sqtd->page_cache); 807 printf("QTD(%p) at 0x%08x:\n", sqtd, ehci32toh(sc, sqtd->qtd_self)); 808 ehci_dump_qtd(sc, sqtd); 809 temp = (sqtd->qtd_next & htoehci32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 810 return (temp); 811 } 812 813 static void 814 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 815 { 816 uint16_t i; 817 uint8_t stop; 818 819 stop = 0; 820 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 821 stop = ehci_dump_sqtd(sc, sqtd); 822 } 823 if (sqtd) { 824 printf("dump aborted, too many TDs\n"); 825 } 826 } 827 828 static void 829 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 830 { 831 uint32_t endp; 832 uint32_t endphub; 833 834 usb2_pc_cpu_invalidate(qh->page_cache); 835 printf("QH(%p) at 0x%08x:\n", qh, ehci32toh(sc, qh->qh_self) & ~0x1F); 836 printf(" link="); 837 ehci_dump_link(sc, qh->qh_link, 1); 838 printf("\n"); 839 endp = ehci32toh(sc, qh->qh_endp); 840 printf(" endp=0x%08x\n", endp); 841 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 842 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 843 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 844 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 845 printf(" mpl=0x%x ctl=%d nrl=%d\n", 846 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 847 EHCI_QH_GET_NRL(endp)); 848 endphub = ehci32toh(sc, qh->qh_endphub); 849 printf(" endphub=0x%08x\n", endphub); 850 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 851 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 852 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 853 EHCI_QH_GET_MULT(endphub)); 854 printf(" curqtd="); 855 ehci_dump_link(sc, qh->qh_curqtd, 0); 856 printf("\n"); 857 printf("Overlay qTD:\n"); 858 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 859 } 860 861 static void 862 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 863 { 864 usb2_pc_cpu_invalidate(sitd->page_cache); 865 printf("SITD(%p) at 0x%08x\n", sitd, ehci32toh(sc, sitd->sitd_self) & ~0x1F); 866 printf(" next=0x%08x\n", ehci32toh(sc, sitd->sitd_next)); 867 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 868 ehci32toh(sc, sitd->sitd_portaddr), 869 (sitd->sitd_portaddr & htoehci32(sc, EHCI_SITD_SET_DIR_IN)) 870 ? "in" : "out", 871 EHCI_SITD_GET_ADDR(ehci32toh(sc, sitd->sitd_portaddr)), 872 EHCI_SITD_GET_ENDPT(ehci32toh(sc, sitd->sitd_portaddr)), 873 EHCI_SITD_GET_PORT(ehci32toh(sc, sitd->sitd_portaddr)), 874 EHCI_SITD_GET_HUBA(ehci32toh(sc, sitd->sitd_portaddr))); 875 printf(" mask=0x%08x\n", ehci32toh(sc, sitd->sitd_mask)); 876 printf(" status=0x%08x <%s> len=0x%x\n", ehci32toh(sc, sitd->sitd_status), 877 (sitd->sitd_status & htoehci32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 878 EHCI_SITD_GET_LEN(ehci32toh(sc, sitd->sitd_status))); 879 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 880 ehci32toh(sc, sitd->sitd_back), 881 ehci32toh(sc, sitd->sitd_bp[0]), 882 ehci32toh(sc, sitd->sitd_bp[1]), 883 ehci32toh(sc, sitd->sitd_bp_hi[0]), 884 ehci32toh(sc, sitd->sitd_bp_hi[1])); 885 } 886 887 static void 888 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 889 { 890 usb2_pc_cpu_invalidate(itd->page_cache); 891 printf("ITD(%p) at 0x%08x\n", itd, ehci32toh(sc, itd->itd_self) & ~0x1F); 892 printf(" next=0x%08x\n", ehci32toh(sc, itd->itd_next)); 893 printf(" status[0]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[0]), 894 (itd->itd_status[0] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[1]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[1]), 896 (itd->itd_status[1] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[2]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[2]), 898 (itd->itd_status[2] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" status[3]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[3]), 900 (itd->itd_status[3] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 901 printf(" status[4]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[4]), 902 (itd->itd_status[4] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 903 printf(" status[5]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[5]), 904 (itd->itd_status[5] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 905 printf(" status[6]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[6]), 906 (itd->itd_status[6] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 907 printf(" status[7]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[7]), 908 (itd->itd_status[7] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 909 printf(" bp[0]=0x%08x\n", ehci32toh(sc, itd->itd_bp[0])); 910 printf(" addr=0x%02x; endpt=0x%01x\n", 911 EHCI_ITD_GET_ADDR(ehci32toh(sc, itd->itd_bp[0])), 912 EHCI_ITD_GET_ENDPT(ehci32toh(sc, itd->itd_bp[0]))); 913 printf(" bp[1]=0x%08x\n", ehci32toh(sc, itd->itd_bp[1])); 914 printf(" dir=%s; mpl=0x%02x\n", 915 (ehci32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 916 EHCI_ITD_GET_MPL(ehci32toh(sc, itd->itd_bp[1]))); 917 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 918 ehci32toh(sc, itd->itd_bp[2]), 919 ehci32toh(sc, itd->itd_bp[3]), 920 ehci32toh(sc, itd->itd_bp[4]), 921 ehci32toh(sc, itd->itd_bp[5]), 922 ehci32toh(sc, itd->itd_bp[6])); 923 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 924 " 0x%08x,0x%08x,0x%08x\n", 925 ehci32toh(sc, itd->itd_bp_hi[0]), 926 ehci32toh(sc, itd->itd_bp_hi[1]), 927 ehci32toh(sc, itd->itd_bp_hi[2]), 928 ehci32toh(sc, itd->itd_bp_hi[3]), 929 ehci32toh(sc, itd->itd_bp_hi[4]), 930 ehci32toh(sc, itd->itd_bp_hi[5]), 931 ehci32toh(sc, itd->itd_bp_hi[6])); 932 } 933 934 static void 935 ehci_dump_isoc(ehci_softc_t *sc) 936 { 937 ehci_itd_t *itd; 938 ehci_sitd_t *sitd; 939 uint16_t max = 1000; 940 uint16_t pos; 941 942 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 943 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 944 945 printf("%s: isochronous dump from frame 0x%03x:\n", 946 __FUNCTION__, pos); 947 948 itd = sc->sc_isoc_hs_p_last[pos]; 949 sitd = sc->sc_isoc_fs_p_last[pos]; 950 951 while (itd && max && max--) { 952 ehci_dump_itd(sc, itd); 953 itd = itd->prev; 954 } 955 956 while (sitd && max && max--) { 957 ehci_dump_sitd(sc, sitd); 958 sitd = sitd->prev; 959 } 960 } 961 962 #endif 963 964 static void 965 ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 966 { 967 /* check for early completion */ 968 if (ehci_check_transfer(xfer)) { 969 return; 970 } 971 /* put transfer on interrupt queue */ 972 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 973 974 /* start timeout, if any */ 975 if (xfer->timeout != 0) { 976 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 977 } 978 } 979 980 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 981 static ehci_sitd_t * 982 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 983 { 984 DPRINTFN(11, "%p to %p\n", std, last); 985 986 /* (sc->sc_bus.mtx) must be locked */ 987 988 std->next = last->next; 989 std->sitd_next = last->sitd_next; 990 991 std->prev = last; 992 993 usb2_pc_cpu_flush(std->page_cache); 994 995 /* 996 * the last->next->prev is never followed: std->next->prev = std; 997 */ 998 last->next = std; 999 last->sitd_next = std->sitd_self; 1000 1001 usb2_pc_cpu_flush(last->page_cache); 1002 1003 return (std); 1004 } 1005 1006 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1007 static ehci_itd_t * 1008 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1009 { 1010 DPRINTFN(11, "%p to %p\n", std, last); 1011 1012 /* (sc->sc_bus.mtx) must be locked */ 1013 1014 std->next = last->next; 1015 std->itd_next = last->itd_next; 1016 1017 std->prev = last; 1018 1019 usb2_pc_cpu_flush(std->page_cache); 1020 1021 /* 1022 * the last->next->prev is never followed: std->next->prev = std; 1023 */ 1024 last->next = std; 1025 last->itd_next = std->itd_self; 1026 1027 usb2_pc_cpu_flush(last->page_cache); 1028 1029 return (std); 1030 } 1031 1032 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1033 static ehci_qh_t * 1034 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1035 { 1036 DPRINTFN(11, "%p to %p\n", sqh, last); 1037 1038 if (sqh->prev != NULL) { 1039 /* should not happen */ 1040 DPRINTFN(0, "QH already linked!\n"); 1041 return (last); 1042 } 1043 /* (sc->sc_bus.mtx) must be locked */ 1044 1045 sqh->next = last->next; 1046 sqh->qh_link = last->qh_link; 1047 1048 sqh->prev = last; 1049 1050 usb2_pc_cpu_flush(sqh->page_cache); 1051 1052 /* 1053 * the last->next->prev is never followed: sqh->next->prev = sqh; 1054 */ 1055 1056 last->next = sqh; 1057 last->qh_link = sqh->qh_self; 1058 1059 usb2_pc_cpu_flush(last->page_cache); 1060 1061 return (sqh); 1062 } 1063 1064 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1065 static ehci_sitd_t * 1066 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1067 { 1068 DPRINTFN(11, "%p from %p\n", std, last); 1069 1070 /* (sc->sc_bus.mtx) must be locked */ 1071 1072 std->prev->next = std->next; 1073 std->prev->sitd_next = std->sitd_next; 1074 1075 usb2_pc_cpu_flush(std->prev->page_cache); 1076 1077 if (std->next) { 1078 std->next->prev = std->prev; 1079 usb2_pc_cpu_flush(std->next->page_cache); 1080 } 1081 return ((last == std) ? std->prev : last); 1082 } 1083 1084 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1085 static ehci_itd_t * 1086 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1087 { 1088 DPRINTFN(11, "%p from %p\n", std, last); 1089 1090 /* (sc->sc_bus.mtx) must be locked */ 1091 1092 std->prev->next = std->next; 1093 std->prev->itd_next = std->itd_next; 1094 1095 usb2_pc_cpu_flush(std->prev->page_cache); 1096 1097 if (std->next) { 1098 std->next->prev = std->prev; 1099 usb2_pc_cpu_flush(std->next->page_cache); 1100 } 1101 return ((last == std) ? std->prev : last); 1102 } 1103 1104 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1105 static ehci_qh_t * 1106 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1107 { 1108 DPRINTFN(11, "%p from %p\n", sqh, last); 1109 1110 /* (sc->sc_bus.mtx) must be locked */ 1111 1112 /* only remove if not removed from a queue */ 1113 if (sqh->prev) { 1114 1115 sqh->prev->next = sqh->next; 1116 sqh->prev->qh_link = sqh->qh_link; 1117 1118 usb2_pc_cpu_flush(sqh->prev->page_cache); 1119 1120 if (sqh->next) { 1121 sqh->next->prev = sqh->prev; 1122 usb2_pc_cpu_flush(sqh->next->page_cache); 1123 } 1124 last = ((last == sqh) ? sqh->prev : last); 1125 1126 sqh->prev = 0; 1127 1128 usb2_pc_cpu_flush(sqh->page_cache); 1129 } 1130 return (last); 1131 } 1132 1133 static usb2_error_t 1134 ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1135 { 1136 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1137 ehci_qtd_t *td; 1138 ehci_qtd_t *td_alt_next; 1139 uint32_t status; 1140 uint16_t len; 1141 1142 td = xfer->td_transfer_cache; 1143 td_alt_next = td->alt_next; 1144 1145 if (xfer->aframes != xfer->nframes) { 1146 xfer->frlengths[xfer->aframes] = 0; 1147 } 1148 while (1) { 1149 1150 usb2_pc_cpu_invalidate(td->page_cache); 1151 status = ehci32toh(sc, td->qtd_status); 1152 1153 len = EHCI_QTD_GET_BYTES(status); 1154 1155 /* 1156 * Verify the status length and 1157 * add the length to "frlengths[]": 1158 */ 1159 if (len > td->len) { 1160 /* should not happen */ 1161 DPRINTF("Invalid status length, " 1162 "0x%04x/0x%04x bytes\n", len, td->len); 1163 status |= EHCI_QTD_HALTED; 1164 } else if (xfer->aframes != xfer->nframes) { 1165 xfer->frlengths[xfer->aframes] += td->len - len; 1166 } 1167 /* Check for last transfer */ 1168 if (((void *)td) == xfer->td_transfer_last) { 1169 if (len == 0) { 1170 /* 1171 * Halt is ok if descriptor is last, 1172 * and complete: 1173 */ 1174 status &= ~EHCI_QTD_HALTED; 1175 } 1176 td = NULL; 1177 break; 1178 } 1179 /* Check for transfer error */ 1180 if (status & EHCI_QTD_HALTED) { 1181 /* the transfer is finished */ 1182 td = NULL; 1183 break; 1184 } 1185 /* Check for short transfer */ 1186 if (len > 0) { 1187 if (xfer->flags_int.short_frames_ok) { 1188 /* follow alt next */ 1189 td = td->alt_next; 1190 } else { 1191 /* the transfer is finished */ 1192 td = NULL; 1193 } 1194 break; 1195 } 1196 td = td->obj_next; 1197 1198 if (td->alt_next != td_alt_next) { 1199 /* this USB frame is complete */ 1200 break; 1201 } 1202 } 1203 1204 /* update transfer cache */ 1205 1206 xfer->td_transfer_cache = td; 1207 1208 /* update data toggle */ 1209 1210 xfer->pipe->toggle_next = 1211 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1212 1213 #if USB_DEBUG 1214 if (status & EHCI_QTD_STATERRS) { 1215 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1216 "status=%s%s%s%s%s%s%s%s\n", 1217 xfer->address, xfer->endpoint, xfer->aframes, 1218 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1219 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1220 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1221 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1222 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1223 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1224 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1225 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1226 } 1227 #endif 1228 1229 return ((status & EHCI_QTD_HALTED) ? 1230 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1231 } 1232 1233 static void 1234 ehci_non_isoc_done(struct usb2_xfer *xfer) 1235 { 1236 usb2_error_t err = 0; 1237 1238 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1239 xfer, xfer->pipe); 1240 1241 #if USB_DEBUG 1242 if (ehcidebug > 10) { 1243 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1244 1245 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1246 } 1247 #endif 1248 1249 /* reset scanner */ 1250 1251 xfer->td_transfer_cache = xfer->td_transfer_first; 1252 1253 if (xfer->flags_int.control_xfr) { 1254 1255 if (xfer->flags_int.control_hdr) { 1256 1257 err = ehci_non_isoc_done_sub(xfer); 1258 } 1259 xfer->aframes = 1; 1260 1261 if (xfer->td_transfer_cache == NULL) { 1262 goto done; 1263 } 1264 } 1265 while (xfer->aframes != xfer->nframes) { 1266 1267 err = ehci_non_isoc_done_sub(xfer); 1268 xfer->aframes++; 1269 1270 if (xfer->td_transfer_cache == NULL) { 1271 goto done; 1272 } 1273 } 1274 1275 if (xfer->flags_int.control_xfr && 1276 !xfer->flags_int.control_act) { 1277 1278 err = ehci_non_isoc_done_sub(xfer); 1279 } 1280 done: 1281 ehci_device_done(xfer, err); 1282 } 1283 1284 /*------------------------------------------------------------------------* 1285 * ehci_check_transfer 1286 * 1287 * Return values: 1288 * 0: USB transfer is not finished 1289 * Else: USB transfer is finished 1290 *------------------------------------------------------------------------*/ 1291 static uint8_t 1292 ehci_check_transfer(struct usb2_xfer *xfer) 1293 { 1294 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1295 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1296 1297 uint32_t status; 1298 1299 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1300 1301 if (methods == &ehci_device_isoc_fs_methods) { 1302 ehci_sitd_t *td; 1303 1304 /* isochronous full speed transfer */ 1305 1306 td = xfer->td_transfer_last; 1307 usb2_pc_cpu_invalidate(td->page_cache); 1308 status = ehci32toh(sc, td->sitd_status); 1309 1310 /* also check if first is complete */ 1311 1312 td = xfer->td_transfer_first; 1313 usb2_pc_cpu_invalidate(td->page_cache); 1314 status |= ehci32toh(sc, td->sitd_status); 1315 1316 if (!(status & EHCI_SITD_ACTIVE)) { 1317 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1318 goto transferred; 1319 } 1320 } else if (methods == &ehci_device_isoc_hs_methods) { 1321 ehci_itd_t *td; 1322 1323 /* isochronous high speed transfer */ 1324 1325 td = xfer->td_transfer_last; 1326 usb2_pc_cpu_invalidate(td->page_cache); 1327 status = 1328 td->itd_status[0] | td->itd_status[1] | 1329 td->itd_status[2] | td->itd_status[3] | 1330 td->itd_status[4] | td->itd_status[5] | 1331 td->itd_status[6] | td->itd_status[7]; 1332 1333 /* also check first transfer */ 1334 td = xfer->td_transfer_first; 1335 usb2_pc_cpu_invalidate(td->page_cache); 1336 status |= 1337 td->itd_status[0] | td->itd_status[1] | 1338 td->itd_status[2] | td->itd_status[3] | 1339 td->itd_status[4] | td->itd_status[5] | 1340 td->itd_status[6] | td->itd_status[7]; 1341 1342 /* if no transactions are active we continue */ 1343 if (!(status & htoehci32(sc, EHCI_ITD_ACTIVE))) { 1344 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1345 goto transferred; 1346 } 1347 } else { 1348 ehci_qtd_t *td; 1349 1350 /* non-isochronous transfer */ 1351 1352 /* 1353 * check whether there is an error somewhere in the middle, 1354 * or whether there was a short packet (SPD and not ACTIVE) 1355 */ 1356 td = xfer->td_transfer_cache; 1357 1358 while (1) { 1359 usb2_pc_cpu_invalidate(td->page_cache); 1360 status = ehci32toh(sc, td->qtd_status); 1361 1362 /* 1363 * if there is an active TD the transfer isn't done 1364 */ 1365 if (status & EHCI_QTD_ACTIVE) { 1366 /* update cache */ 1367 xfer->td_transfer_cache = td; 1368 goto done; 1369 } 1370 /* 1371 * last transfer descriptor makes the transfer done 1372 */ 1373 if (((void *)td) == xfer->td_transfer_last) { 1374 break; 1375 } 1376 /* 1377 * any kind of error makes the transfer done 1378 */ 1379 if (status & EHCI_QTD_HALTED) { 1380 break; 1381 } 1382 /* 1383 * if there is no alternate next transfer, a short 1384 * packet also makes the transfer done 1385 */ 1386 if (EHCI_QTD_GET_BYTES(status)) { 1387 if (xfer->flags_int.short_frames_ok) { 1388 /* follow alt next */ 1389 if (td->alt_next) { 1390 td = td->alt_next; 1391 continue; 1392 } 1393 } 1394 /* transfer is done */ 1395 break; 1396 } 1397 td = td->obj_next; 1398 } 1399 ehci_non_isoc_done(xfer); 1400 goto transferred; 1401 } 1402 1403 done: 1404 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1405 return (0); 1406 1407 transferred: 1408 return (1); 1409 } 1410 1411 static void 1412 ehci_pcd_enable(ehci_softc_t *sc) 1413 { 1414 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1415 1416 sc->sc_eintrs |= EHCI_STS_PCD; 1417 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1418 1419 /* acknowledge any PCD interrupt */ 1420 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1421 1422 usb2_sw_transfer(&sc->sc_root_intr, 1423 &ehci_root_intr_done); 1424 } 1425 1426 static void 1427 ehci_interrupt_poll(ehci_softc_t *sc) 1428 { 1429 struct usb2_xfer *xfer; 1430 1431 repeat: 1432 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1433 /* 1434 * check if transfer is transferred 1435 */ 1436 if (ehci_check_transfer(xfer)) { 1437 /* queue has been modified */ 1438 goto repeat; 1439 } 1440 } 1441 } 1442 1443 /*------------------------------------------------------------------------* 1444 * ehci_interrupt - EHCI interrupt handler 1445 * 1446 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1447 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1448 * is present ! 1449 *------------------------------------------------------------------------*/ 1450 void 1451 ehci_interrupt(ehci_softc_t *sc) 1452 { 1453 uint32_t status; 1454 1455 USB_BUS_LOCK(&sc->sc_bus); 1456 1457 DPRINTFN(16, "real interrupt\n"); 1458 1459 #if USB_DEBUG 1460 if (ehcidebug > 15) { 1461 ehci_dump_regs(sc); 1462 } 1463 #endif 1464 1465 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1466 if (status == 0) { 1467 /* the interrupt was not for us */ 1468 goto done; 1469 } 1470 if (!(status & sc->sc_eintrs)) { 1471 goto done; 1472 } 1473 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1474 1475 status &= sc->sc_eintrs; 1476 1477 if (status & EHCI_STS_HSE) { 1478 printf("%s: unrecoverable error, " 1479 "controller halted\n", __FUNCTION__); 1480 #if USB_DEBUG 1481 ehci_dump_regs(sc); 1482 ehci_dump_isoc(sc); 1483 #endif 1484 } 1485 if (status & EHCI_STS_PCD) { 1486 /* 1487 * Disable PCD interrupt for now, because it will be 1488 * on until the port has been reset. 1489 */ 1490 sc->sc_eintrs &= ~EHCI_STS_PCD; 1491 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1492 1493 usb2_sw_transfer(&sc->sc_root_intr, 1494 &ehci_root_intr_done); 1495 1496 /* do not allow RHSC interrupts > 1 per second */ 1497 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1498 (void *)&ehci_pcd_enable, sc); 1499 } 1500 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1501 1502 if (status != 0) { 1503 /* block unprocessed interrupts */ 1504 sc->sc_eintrs &= ~status; 1505 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1506 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1507 } 1508 /* poll all the USB transfers */ 1509 ehci_interrupt_poll(sc); 1510 1511 done: 1512 USB_BUS_UNLOCK(&sc->sc_bus); 1513 } 1514 1515 /* 1516 * called when a request does not complete 1517 */ 1518 static void 1519 ehci_timeout(void *arg) 1520 { 1521 struct usb2_xfer *xfer = arg; 1522 1523 DPRINTF("xfer=%p\n", xfer); 1524 1525 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1526 1527 /* transfer is transferred */ 1528 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1529 } 1530 1531 static void 1532 ehci_do_poll(struct usb2_bus *bus) 1533 { 1534 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1535 1536 USB_BUS_LOCK(&sc->sc_bus); 1537 ehci_interrupt_poll(sc); 1538 ehci_root_ctrl_poll(sc); 1539 USB_BUS_UNLOCK(&sc->sc_bus); 1540 } 1541 1542 static void 1543 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1544 { 1545 struct usb2_page_search buf_res; 1546 ehci_qtd_t *td; 1547 ehci_qtd_t *td_next; 1548 ehci_qtd_t *td_alt_next; 1549 uint32_t qtd_altnext; 1550 uint32_t buf_offset; 1551 uint32_t average; 1552 uint32_t len_old; 1553 uint8_t shortpkt_old; 1554 uint8_t precompute; 1555 1556 qtd_altnext = htoehci32(temp->sc, EHCI_LINK_TERMINATE); 1557 td_alt_next = NULL; 1558 buf_offset = 0; 1559 shortpkt_old = temp->shortpkt; 1560 len_old = temp->len; 1561 precompute = 1; 1562 1563 restart: 1564 1565 td = temp->td; 1566 td_next = temp->td_next; 1567 1568 while (1) { 1569 1570 if (temp->len == 0) { 1571 1572 if (temp->shortpkt) { 1573 break; 1574 } 1575 /* send a Zero Length Packet, ZLP, last */ 1576 1577 temp->shortpkt = 1; 1578 average = 0; 1579 1580 } else { 1581 1582 average = temp->average; 1583 1584 if (temp->len < average) { 1585 if (temp->len % temp->max_frame_size) { 1586 temp->shortpkt = 1; 1587 } 1588 average = temp->len; 1589 } 1590 } 1591 1592 if (td_next == NULL) { 1593 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1594 } 1595 /* get next TD */ 1596 1597 td = td_next; 1598 td_next = td->obj_next; 1599 1600 /* check if we are pre-computing */ 1601 1602 if (precompute) { 1603 1604 /* update remaining length */ 1605 1606 temp->len -= average; 1607 1608 continue; 1609 } 1610 /* fill out current TD */ 1611 1612 td->qtd_status = 1613 temp->qtd_status | 1614 htoehci32(temp->sc, EHCI_QTD_SET_BYTES(average)); 1615 1616 if (average == 0) { 1617 1618 if (temp->auto_data_toggle == 0) { 1619 1620 /* update data toggle, ZLP case */ 1621 1622 temp->qtd_status ^= 1623 htoehci32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1624 } 1625 td->len = 0; 1626 1627 td->qtd_buffer[0] = 0; 1628 td->qtd_buffer_hi[0] = 0; 1629 1630 td->qtd_buffer[1] = 0; 1631 td->qtd_buffer_hi[1] = 0; 1632 1633 } else { 1634 1635 uint8_t x; 1636 1637 if (temp->auto_data_toggle == 0) { 1638 1639 /* update data toggle */ 1640 1641 if (((average + temp->max_frame_size - 1) / 1642 temp->max_frame_size) & 1) { 1643 temp->qtd_status ^= 1644 htoehci32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1645 } 1646 } 1647 td->len = average; 1648 1649 /* update remaining length */ 1650 1651 temp->len -= average; 1652 1653 /* fill out buffer pointers */ 1654 1655 usb2_get_page(temp->pc, buf_offset, &buf_res); 1656 td->qtd_buffer[0] = 1657 htoehci32(temp->sc, buf_res.physaddr); 1658 td->qtd_buffer_hi[0] = 0; 1659 1660 x = 1; 1661 1662 while (average > EHCI_PAGE_SIZE) { 1663 average -= EHCI_PAGE_SIZE; 1664 buf_offset += EHCI_PAGE_SIZE; 1665 usb2_get_page(temp->pc, buf_offset, &buf_res); 1666 td->qtd_buffer[x] = 1667 htoehci32(temp->sc, 1668 buf_res.physaddr & (~0xFFF)); 1669 td->qtd_buffer_hi[x] = 0; 1670 x++; 1671 } 1672 1673 /* 1674 * NOTE: The "average" variable is never zero after 1675 * exiting the loop above ! 1676 * 1677 * NOTE: We have to subtract one from the offset to 1678 * ensure that we are computing the physical address 1679 * of a valid page ! 1680 */ 1681 buf_offset += average; 1682 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1683 td->qtd_buffer[x] = 1684 htoehci32(temp->sc, 1685 buf_res.physaddr & (~0xFFF)); 1686 td->qtd_buffer_hi[x] = 0; 1687 } 1688 1689 if (td_next) { 1690 /* link the current TD with the next one */ 1691 td->qtd_next = td_next->qtd_self; 1692 } 1693 td->qtd_altnext = qtd_altnext; 1694 td->alt_next = td_alt_next; 1695 1696 usb2_pc_cpu_flush(td->page_cache); 1697 } 1698 1699 if (precompute) { 1700 precompute = 0; 1701 1702 /* setup alt next pointer, if any */ 1703 if (temp->short_frames_ok) { 1704 if (temp->setup_alt_next) { 1705 td_alt_next = td_next; 1706 qtd_altnext = td_next->qtd_self; 1707 } 1708 } else { 1709 /* we use this field internally */ 1710 td_alt_next = td_next; 1711 } 1712 1713 /* restore */ 1714 temp->shortpkt = shortpkt_old; 1715 temp->len = len_old; 1716 goto restart; 1717 } 1718 temp->td = td; 1719 temp->td_next = td_next; 1720 } 1721 1722 static void 1723 ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1724 { 1725 struct ehci_std_temp temp; 1726 struct usb2_pipe_methods *methods; 1727 ehci_qh_t *qh; 1728 ehci_qtd_t *td; 1729 uint32_t qh_endp; 1730 uint32_t qh_endphub; 1731 uint32_t x; 1732 1733 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1734 xfer->address, UE_GET_ADDR(xfer->endpoint), 1735 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1736 1737 temp.average = xfer->max_usb2_frame_size; 1738 temp.max_frame_size = xfer->max_frame_size; 1739 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1740 1741 /* toggle the DMA set we are using */ 1742 xfer->flags_int.curr_dma_set ^= 1; 1743 1744 /* get next DMA set */ 1745 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1746 1747 xfer->td_transfer_first = td; 1748 xfer->td_transfer_cache = td; 1749 1750 temp.td = NULL; 1751 temp.td_next = td; 1752 temp.qtd_status = 0; 1753 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1754 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1755 1756 if (xfer->flags_int.control_xfr) { 1757 if (xfer->pipe->toggle_next) { 1758 /* DATA1 is next */ 1759 temp.qtd_status |= 1760 htoehci32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1761 } 1762 temp.auto_data_toggle = 0; 1763 } else { 1764 temp.auto_data_toggle = 1; 1765 } 1766 1767 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1768 /* max 3 retries */ 1769 temp.qtd_status |= 1770 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3)); 1771 } 1772 /* check if we should prepend a setup message */ 1773 1774 if (xfer->flags_int.control_xfr) { 1775 if (xfer->flags_int.control_hdr) { 1776 1777 temp.qtd_status &= 1778 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3)); 1779 temp.qtd_status |= htole32 1780 (EHCI_QTD_ACTIVE | 1781 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1782 EHCI_QTD_SET_TOGGLE(0)); 1783 1784 temp.len = xfer->frlengths[0]; 1785 temp.pc = xfer->frbuffers + 0; 1786 temp.shortpkt = temp.len ? 1 : 0; 1787 1788 ehci_setup_standard_chain_sub(&temp); 1789 } 1790 x = 1; 1791 } else { 1792 x = 0; 1793 } 1794 1795 while (x != xfer->nframes) { 1796 1797 /* DATA0 / DATA1 message */ 1798 1799 temp.len = xfer->frlengths[x]; 1800 temp.pc = xfer->frbuffers + x; 1801 1802 x++; 1803 1804 if (x == xfer->nframes) { 1805 temp.setup_alt_next = 0; 1806 } 1807 /* keep previous data toggle and error count */ 1808 1809 temp.qtd_status &= 1810 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3) | 1811 EHCI_QTD_SET_TOGGLE(1)); 1812 1813 if (temp.len == 0) { 1814 1815 /* make sure that we send an USB packet */ 1816 1817 temp.shortpkt = 0; 1818 1819 } else { 1820 1821 /* regular data transfer */ 1822 1823 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1824 } 1825 1826 /* set endpoint direction */ 1827 1828 temp.qtd_status |= 1829 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1830 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1831 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1832 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1833 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1834 1835 ehci_setup_standard_chain_sub(&temp); 1836 } 1837 1838 /* check if we should append a status stage */ 1839 1840 if (xfer->flags_int.control_xfr && 1841 !xfer->flags_int.control_act) { 1842 1843 /* 1844 * Send a DATA1 message and invert the current endpoint 1845 * direction. 1846 */ 1847 1848 temp.qtd_status &= htoehci32(temp.sc, EHCI_QTD_SET_CERR(3) | 1849 EHCI_QTD_SET_TOGGLE(1)); 1850 temp.qtd_status |= 1851 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1852 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1853 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1854 EHCI_QTD_SET_TOGGLE(1)) : 1855 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1856 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1857 EHCI_QTD_SET_TOGGLE(1)); 1858 1859 temp.len = 0; 1860 temp.pc = NULL; 1861 temp.shortpkt = 0; 1862 1863 ehci_setup_standard_chain_sub(&temp); 1864 } 1865 td = temp.td; 1866 1867 /* the last TD terminates the transfer: */ 1868 td->qtd_next = htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1869 td->qtd_altnext = htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1870 td->qtd_status |= htoehci32(temp.sc, EHCI_QTD_IOC); 1871 1872 usb2_pc_cpu_flush(td->page_cache); 1873 1874 /* must have at least one frame! */ 1875 1876 xfer->td_transfer_last = td; 1877 1878 #if USB_DEBUG 1879 if (ehcidebug > 8) { 1880 DPRINTF("nexttog=%d; data before transfer:\n", 1881 xfer->pipe->toggle_next); 1882 ehci_dump_sqtds(temp.sc, 1883 xfer->td_transfer_first); 1884 } 1885 #endif 1886 1887 methods = xfer->pipe->methods; 1888 1889 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1890 1891 /* the "qh_link" field is filled when the QH is added */ 1892 1893 qh_endp = 1894 (EHCI_QH_SET_ADDR(xfer->address) | 1895 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1896 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1897 1898 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1899 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1900 EHCI_QH_DTC); 1901 if (methods != &ehci_device_intr_methods) 1902 qh_endp |= EHCI_QH_SET_NRL(8); 1903 } else { 1904 1905 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1906 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1907 EHCI_QH_DTC); 1908 } else { 1909 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1910 EHCI_QH_DTC); 1911 } 1912 1913 if (methods == &ehci_device_ctrl_methods) { 1914 qh_endp |= EHCI_QH_CTL; 1915 } 1916 if (methods != &ehci_device_intr_methods) { 1917 /* Only try one time per microframe! */ 1918 qh_endp |= EHCI_QH_SET_NRL(1); 1919 } 1920 } 1921 1922 qh->qh_endp = htoehci32(temp.sc, qh_endp); 1923 1924 qh_endphub = 1925 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1926 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1927 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1928 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1929 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1930 1931 qh->qh_endphub = htoehci32(temp.sc, qh_endphub); 1932 qh->qh_curqtd = htoehci32(temp.sc, 0); 1933 1934 /* fill the overlay qTD */ 1935 qh->qh_qtd.qtd_status = htoehci32(temp.sc, 0); 1936 1937 if (temp.auto_data_toggle) { 1938 1939 /* let the hardware compute the data toggle */ 1940 1941 qh->qh_endp &= htoehci32(temp.sc, ~EHCI_QH_DTC); 1942 1943 if (xfer->pipe->toggle_next) { 1944 /* DATA1 is next */ 1945 qh->qh_qtd.qtd_status |= 1946 htoehci32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1947 } 1948 } 1949 td = xfer->td_transfer_first; 1950 1951 qh->qh_qtd.qtd_next = td->qtd_self; 1952 qh->qh_qtd.qtd_altnext = 1953 htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1954 1955 usb2_pc_cpu_flush(qh->page_cache); 1956 1957 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1958 EHCI_APPEND_QH(qh, *qh_last); 1959 } 1960 } 1961 1962 static void 1963 ehci_root_intr_done(struct usb2_xfer *xfer, 1964 struct usb2_sw_transfer *std) 1965 { 1966 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1967 uint16_t i; 1968 uint16_t m; 1969 1970 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1971 1972 if (std->state != USB_SW_TR_PRE_DATA) { 1973 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1974 /* transfer transferred */ 1975 ehci_device_done(xfer, std->err); 1976 } 1977 goto done; 1978 } 1979 /* setup buffer */ 1980 std->ptr = sc->sc_hub_idata; 1981 std->len = sizeof(sc->sc_hub_idata); 1982 1983 /* clear any old interrupt data */ 1984 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1985 1986 /* set bits */ 1987 m = (sc->sc_noport + 1); 1988 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1989 m = (8 * sizeof(sc->sc_hub_idata)); 1990 } 1991 for (i = 1; i < m; i++) { 1992 /* pick out CHANGE bits from the status register */ 1993 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1994 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1995 DPRINTF("port %d changed\n", i); 1996 } 1997 } 1998 done: 1999 return; 2000 } 2001 2002 static void 2003 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2004 { 2005 uint32_t nframes = xfer->nframes; 2006 uint32_t status; 2007 uint32_t *plen = xfer->frlengths; 2008 uint16_t len = 0; 2009 ehci_sitd_t *td = xfer->td_transfer_first; 2010 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2011 2012 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2013 xfer, xfer->pipe); 2014 2015 while (nframes--) { 2016 if (td == NULL) { 2017 panic("%s:%d: out of TD's\n", 2018 __FUNCTION__, __LINE__); 2019 } 2020 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2021 pp_last = &sc->sc_isoc_fs_p_last[0]; 2022 } 2023 #if USB_DEBUG 2024 if (ehcidebug > 15) { 2025 DPRINTF("isoc FS-TD\n"); 2026 ehci_dump_sitd(sc, td); 2027 } 2028 #endif 2029 usb2_pc_cpu_invalidate(td->page_cache); 2030 status = ehci32toh(sc, td->sitd_status); 2031 2032 len = EHCI_SITD_GET_LEN(status); 2033 2034 if (*plen >= len) { 2035 len = *plen - len; 2036 } else { 2037 len = 0; 2038 } 2039 2040 *plen = len; 2041 2042 /* remove FS-TD from schedule */ 2043 EHCI_REMOVE_FS_TD(td, *pp_last); 2044 2045 pp_last++; 2046 plen++; 2047 td = td->obj_next; 2048 } 2049 2050 xfer->aframes = xfer->nframes; 2051 } 2052 2053 static void 2054 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2055 { 2056 uint32_t nframes = xfer->nframes; 2057 uint32_t status; 2058 uint32_t *plen = xfer->frlengths; 2059 uint16_t len = 0; 2060 uint8_t td_no = 0; 2061 ehci_itd_t *td = xfer->td_transfer_first; 2062 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2063 2064 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2065 xfer, xfer->pipe); 2066 2067 while (nframes--) { 2068 if (td == NULL) { 2069 panic("%s:%d: out of TD's\n", 2070 __FUNCTION__, __LINE__); 2071 } 2072 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2073 pp_last = &sc->sc_isoc_hs_p_last[0]; 2074 } 2075 #if USB_DEBUG 2076 if (ehcidebug > 15) { 2077 DPRINTF("isoc HS-TD\n"); 2078 ehci_dump_itd(sc, td); 2079 } 2080 #endif 2081 2082 usb2_pc_cpu_invalidate(td->page_cache); 2083 status = ehci32toh(sc, td->itd_status[td_no]); 2084 2085 len = EHCI_ITD_GET_LEN(status); 2086 2087 if (*plen >= len) { 2088 /* 2089 * The length is valid. NOTE: The complete 2090 * length is written back into the status 2091 * field, and not the remainder like with 2092 * other transfer descriptor types. 2093 */ 2094 } else { 2095 /* Invalid length - truncate */ 2096 len = 0; 2097 } 2098 2099 *plen = len; 2100 2101 plen++; 2102 td_no++; 2103 2104 if ((td_no == 8) || (nframes == 0)) { 2105 /* remove HS-TD from schedule */ 2106 EHCI_REMOVE_HS_TD(td, *pp_last); 2107 pp_last++; 2108 2109 td_no = 0; 2110 td = td->obj_next; 2111 } 2112 } 2113 xfer->aframes = xfer->nframes; 2114 } 2115 2116 /* NOTE: "done" can be run two times in a row, 2117 * from close and from interrupt 2118 */ 2119 static void 2120 ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2121 { 2122 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2123 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2124 2125 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2126 2127 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2128 xfer, xfer->pipe, error); 2129 2130 if ((methods == &ehci_device_bulk_methods) || 2131 (methods == &ehci_device_ctrl_methods)) { 2132 #if USB_DEBUG 2133 if (ehcidebug > 8) { 2134 DPRINTF("nexttog=%d; data after transfer:\n", 2135 xfer->pipe->toggle_next); 2136 ehci_dump_sqtds(sc, 2137 xfer->td_transfer_first); 2138 } 2139 #endif 2140 2141 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2142 sc->sc_async_p_last); 2143 } 2144 if (methods == &ehci_device_intr_methods) { 2145 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2146 sc->sc_intr_p_last[xfer->qh_pos]); 2147 } 2148 /* 2149 * Only finish isochronous transfers once which will update 2150 * "xfer->frlengths". 2151 */ 2152 if (xfer->td_transfer_first && 2153 xfer->td_transfer_last) { 2154 if (methods == &ehci_device_isoc_fs_methods) { 2155 ehci_isoc_fs_done(sc, xfer); 2156 } 2157 if (methods == &ehci_device_isoc_hs_methods) { 2158 ehci_isoc_hs_done(sc, xfer); 2159 } 2160 xfer->td_transfer_first = NULL; 2161 xfer->td_transfer_last = NULL; 2162 } 2163 /* dequeue transfer and start next transfer */ 2164 usb2_transfer_done(xfer, error); 2165 } 2166 2167 /*------------------------------------------------------------------------* 2168 * ehci bulk support 2169 *------------------------------------------------------------------------*/ 2170 static void 2171 ehci_device_bulk_open(struct usb2_xfer *xfer) 2172 { 2173 return; 2174 } 2175 2176 static void 2177 ehci_device_bulk_close(struct usb2_xfer *xfer) 2178 { 2179 ehci_device_done(xfer, USB_ERR_CANCELLED); 2180 } 2181 2182 static void 2183 ehci_device_bulk_enter(struct usb2_xfer *xfer) 2184 { 2185 return; 2186 } 2187 2188 static void 2189 ehci_device_bulk_start(struct usb2_xfer *xfer) 2190 { 2191 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2192 2193 /* setup TD's and QH */ 2194 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2195 2196 /* put transfer on interrupt queue */ 2197 ehci_transfer_intr_enqueue(xfer); 2198 } 2199 2200 struct usb2_pipe_methods ehci_device_bulk_methods = 2201 { 2202 .open = ehci_device_bulk_open, 2203 .close = ehci_device_bulk_close, 2204 .enter = ehci_device_bulk_enter, 2205 .start = ehci_device_bulk_start, 2206 .enter_is_cancelable = 1, 2207 .start_is_cancelable = 1, 2208 }; 2209 2210 /*------------------------------------------------------------------------* 2211 * ehci control support 2212 *------------------------------------------------------------------------*/ 2213 static void 2214 ehci_device_ctrl_open(struct usb2_xfer *xfer) 2215 { 2216 return; 2217 } 2218 2219 static void 2220 ehci_device_ctrl_close(struct usb2_xfer *xfer) 2221 { 2222 ehci_device_done(xfer, USB_ERR_CANCELLED); 2223 } 2224 2225 static void 2226 ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2227 { 2228 return; 2229 } 2230 2231 static void 2232 ehci_device_ctrl_start(struct usb2_xfer *xfer) 2233 { 2234 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2235 2236 /* setup TD's and QH */ 2237 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2238 2239 /* put transfer on interrupt queue */ 2240 ehci_transfer_intr_enqueue(xfer); 2241 } 2242 2243 struct usb2_pipe_methods ehci_device_ctrl_methods = 2244 { 2245 .open = ehci_device_ctrl_open, 2246 .close = ehci_device_ctrl_close, 2247 .enter = ehci_device_ctrl_enter, 2248 .start = ehci_device_ctrl_start, 2249 .enter_is_cancelable = 1, 2250 .start_is_cancelable = 1, 2251 }; 2252 2253 /*------------------------------------------------------------------------* 2254 * ehci interrupt support 2255 *------------------------------------------------------------------------*/ 2256 static void 2257 ehci_device_intr_open(struct usb2_xfer *xfer) 2258 { 2259 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2260 uint16_t best; 2261 uint16_t bit; 2262 uint16_t x; 2263 uint8_t slot; 2264 2265 /* Allocate a microframe slot first: */ 2266 2267 slot = usb2_intr_schedule_adjust 2268 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2269 2270 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2271 xfer->usb2_uframe = slot; 2272 xfer->usb2_smask = (1 << slot) & 0xFF; 2273 xfer->usb2_cmask = 0; 2274 } else { 2275 xfer->usb2_uframe = slot; 2276 xfer->usb2_smask = (1 << slot) & 0x3F; 2277 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2278 } 2279 2280 /* 2281 * Find the best QH position corresponding to the given interval: 2282 */ 2283 2284 best = 0; 2285 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2286 while (bit) { 2287 if (xfer->interval >= bit) { 2288 x = bit; 2289 best = bit; 2290 while (x & bit) { 2291 if (sc->sc_intr_stat[x] < 2292 sc->sc_intr_stat[best]) { 2293 best = x; 2294 } 2295 x++; 2296 } 2297 break; 2298 } 2299 bit >>= 1; 2300 } 2301 2302 sc->sc_intr_stat[best]++; 2303 xfer->qh_pos = best; 2304 2305 DPRINTFN(3, "best=%d interval=%d\n", 2306 best, xfer->interval); 2307 } 2308 2309 static void 2310 ehci_device_intr_close(struct usb2_xfer *xfer) 2311 { 2312 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2313 uint8_t slot; 2314 2315 slot = usb2_intr_schedule_adjust 2316 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2317 2318 sc->sc_intr_stat[xfer->qh_pos]--; 2319 2320 ehci_device_done(xfer, USB_ERR_CANCELLED); 2321 } 2322 2323 static void 2324 ehci_device_intr_enter(struct usb2_xfer *xfer) 2325 { 2326 return; 2327 } 2328 2329 static void 2330 ehci_device_intr_start(struct usb2_xfer *xfer) 2331 { 2332 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2333 2334 /* setup TD's and QH */ 2335 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2336 2337 /* put transfer on interrupt queue */ 2338 ehci_transfer_intr_enqueue(xfer); 2339 } 2340 2341 struct usb2_pipe_methods ehci_device_intr_methods = 2342 { 2343 .open = ehci_device_intr_open, 2344 .close = ehci_device_intr_close, 2345 .enter = ehci_device_intr_enter, 2346 .start = ehci_device_intr_start, 2347 .enter_is_cancelable = 1, 2348 .start_is_cancelable = 1, 2349 }; 2350 2351 /*------------------------------------------------------------------------* 2352 * ehci full speed isochronous support 2353 *------------------------------------------------------------------------*/ 2354 static void 2355 ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2356 { 2357 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2358 ehci_sitd_t *td; 2359 uint32_t sitd_portaddr; 2360 uint8_t ds; 2361 2362 sitd_portaddr = 2363 EHCI_SITD_SET_ADDR(xfer->address) | 2364 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2365 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2366 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2367 2368 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2369 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2370 } 2371 sitd_portaddr = htoehci32(sc, sitd_portaddr); 2372 2373 /* initialize all TD's */ 2374 2375 for (ds = 0; ds != 2; ds++) { 2376 2377 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2378 2379 td->sitd_portaddr = sitd_portaddr; 2380 2381 /* 2382 * TODO: make some kind of automatic 2383 * SMASK/CMASK selection based on micro-frame 2384 * usage 2385 * 2386 * micro-frame usage (8 microframes per 1ms) 2387 */ 2388 td->sitd_back = htoehci32(sc, EHCI_LINK_TERMINATE); 2389 2390 usb2_pc_cpu_flush(td->page_cache); 2391 } 2392 } 2393 } 2394 2395 static void 2396 ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2397 { 2398 ehci_device_done(xfer, USB_ERR_CANCELLED); 2399 } 2400 2401 static void 2402 ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2403 { 2404 struct usb2_page_search buf_res; 2405 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2406 struct usb2_fs_isoc_schedule *fss_start; 2407 struct usb2_fs_isoc_schedule *fss_end; 2408 struct usb2_fs_isoc_schedule *fss; 2409 ehci_sitd_t *td; 2410 ehci_sitd_t *td_last = NULL; 2411 ehci_sitd_t **pp_last; 2412 uint32_t *plen; 2413 uint32_t buf_offset; 2414 uint32_t nframes; 2415 uint32_t temp; 2416 uint32_t sitd_mask; 2417 uint16_t tlen; 2418 uint8_t sa; 2419 uint8_t sb; 2420 uint8_t error; 2421 2422 #if USB_DEBUG 2423 uint8_t once = 1; 2424 2425 #endif 2426 2427 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2428 xfer, xfer->pipe->isoc_next, xfer->nframes); 2429 2430 /* get the current frame index */ 2431 2432 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2433 2434 /* 2435 * check if the frame index is within the window where the frames 2436 * will be inserted 2437 */ 2438 buf_offset = (nframes - xfer->pipe->isoc_next) & 2439 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2440 2441 if ((xfer->pipe->is_synced == 0) || 2442 (buf_offset < xfer->nframes)) { 2443 /* 2444 * If there is data underflow or the pipe queue is empty we 2445 * schedule the transfer a few frames ahead of the current 2446 * frame position. Else two isochronous transfers might 2447 * overlap. 2448 */ 2449 xfer->pipe->isoc_next = (nframes + 3) & 2450 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2451 xfer->pipe->is_synced = 1; 2452 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2453 } 2454 /* 2455 * compute how many milliseconds the insertion is ahead of the 2456 * current frame position: 2457 */ 2458 buf_offset = (xfer->pipe->isoc_next - nframes) & 2459 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2460 2461 /* 2462 * pre-compute when the isochronous transfer will be finished: 2463 */ 2464 xfer->isoc_time_complete = 2465 usb2_fs_isoc_schedule_isoc_time_expand 2466 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2467 xfer->nframes; 2468 2469 /* get the real number of frames */ 2470 2471 nframes = xfer->nframes; 2472 2473 buf_offset = 0; 2474 2475 plen = xfer->frlengths; 2476 2477 /* toggle the DMA set we are using */ 2478 xfer->flags_int.curr_dma_set ^= 1; 2479 2480 /* get next DMA set */ 2481 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2482 xfer->td_transfer_first = td; 2483 2484 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2485 2486 /* store starting position */ 2487 2488 xfer->qh_pos = xfer->pipe->isoc_next; 2489 2490 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2491 2492 while (nframes--) { 2493 if (td == NULL) { 2494 panic("%s:%d: out of TD's\n", 2495 __FUNCTION__, __LINE__); 2496 } 2497 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2498 pp_last = &sc->sc_isoc_fs_p_last[0]; 2499 } 2500 if (fss >= fss_end) { 2501 fss = fss_start; 2502 } 2503 /* reuse sitd_portaddr and sitd_back from last transfer */ 2504 2505 if (*plen > xfer->max_frame_size) { 2506 #if USB_DEBUG 2507 if (once) { 2508 once = 0; 2509 printf("%s: frame length(%d) exceeds %d " 2510 "bytes (frame truncated)\n", 2511 __FUNCTION__, *plen, 2512 xfer->max_frame_size); 2513 } 2514 #endif 2515 *plen = xfer->max_frame_size; 2516 } 2517 /* 2518 * We currently don't care if the ISOCHRONOUS schedule is 2519 * full! 2520 */ 2521 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2522 if (error) { 2523 /* 2524 * The FULL speed schedule is FULL! Set length 2525 * to zero. 2526 */ 2527 *plen = 0; 2528 } 2529 if (*plen) { 2530 /* 2531 * only call "usb2_get_page()" when we have a 2532 * non-zero length 2533 */ 2534 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2535 td->sitd_bp[0] = htoehci32(sc, buf_res.physaddr); 2536 buf_offset += *plen; 2537 /* 2538 * NOTE: We need to subtract one from the offset so 2539 * that we are on a valid page! 2540 */ 2541 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2542 &buf_res); 2543 temp = buf_res.physaddr & ~0xFFF; 2544 } else { 2545 td->sitd_bp[0] = 0; 2546 temp = 0; 2547 } 2548 2549 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2550 tlen = *plen; 2551 if (tlen <= 188) { 2552 temp |= 1; /* T-count = 1, TP = ALL */ 2553 tlen = 1; 2554 } else { 2555 tlen += 187; 2556 tlen /= 188; 2557 temp |= tlen; /* T-count = [1..6] */ 2558 temp |= 8; /* TP = Begin */ 2559 } 2560 2561 tlen += sa; 2562 2563 if (tlen >= 8) { 2564 sb = 0; 2565 } else { 2566 sb = (1 << tlen); 2567 } 2568 2569 sa = (1 << sa); 2570 sa = (sb - sa) & 0x3F; 2571 sb = 0; 2572 } else { 2573 sb = (-(4 << sa)) & 0xFE; 2574 sa = (1 << sa) & 0x3F; 2575 } 2576 2577 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2578 EHCI_SITD_SET_CMASK(sb)); 2579 2580 td->sitd_bp[1] = htoehci32(sc, temp); 2581 2582 td->sitd_mask = htoehci32(sc, sitd_mask); 2583 2584 if (nframes == 0) { 2585 td->sitd_status = htole32 2586 (EHCI_SITD_IOC | 2587 EHCI_SITD_ACTIVE | 2588 EHCI_SITD_SET_LEN(*plen)); 2589 } else { 2590 td->sitd_status = htole32 2591 (EHCI_SITD_ACTIVE | 2592 EHCI_SITD_SET_LEN(*plen)); 2593 } 2594 usb2_pc_cpu_flush(td->page_cache); 2595 2596 #if USB_DEBUG 2597 if (ehcidebug > 15) { 2598 DPRINTF("FS-TD %d\n", nframes); 2599 ehci_dump_sitd(sc, td); 2600 } 2601 #endif 2602 /* insert TD into schedule */ 2603 EHCI_APPEND_FS_TD(td, *pp_last); 2604 pp_last++; 2605 2606 plen++; 2607 fss++; 2608 td_last = td; 2609 td = td->obj_next; 2610 } 2611 2612 xfer->td_transfer_last = td_last; 2613 2614 /* update isoc_next */ 2615 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2616 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2617 } 2618 2619 static void 2620 ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2621 { 2622 /* put transfer on interrupt queue */ 2623 ehci_transfer_intr_enqueue(xfer); 2624 } 2625 2626 struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2627 { 2628 .open = ehci_device_isoc_fs_open, 2629 .close = ehci_device_isoc_fs_close, 2630 .enter = ehci_device_isoc_fs_enter, 2631 .start = ehci_device_isoc_fs_start, 2632 .enter_is_cancelable = 1, 2633 .start_is_cancelable = 1, 2634 }; 2635 2636 /*------------------------------------------------------------------------* 2637 * ehci high speed isochronous support 2638 *------------------------------------------------------------------------*/ 2639 static void 2640 ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2641 { 2642 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2643 ehci_itd_t *td; 2644 uint32_t temp; 2645 uint8_t ds; 2646 2647 /* initialize all TD's */ 2648 2649 for (ds = 0; ds != 2; ds++) { 2650 2651 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2652 2653 /* set TD inactive */ 2654 td->itd_status[0] = 0; 2655 td->itd_status[1] = 0; 2656 td->itd_status[2] = 0; 2657 td->itd_status[3] = 0; 2658 td->itd_status[4] = 0; 2659 td->itd_status[5] = 0; 2660 td->itd_status[6] = 0; 2661 td->itd_status[7] = 0; 2662 2663 /* set endpoint and address */ 2664 td->itd_bp[0] = htole32 2665 (EHCI_ITD_SET_ADDR(xfer->address) | 2666 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2667 2668 temp = 2669 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2670 2671 /* set direction */ 2672 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2673 temp |= EHCI_ITD_SET_DIR_IN; 2674 } 2675 /* set maximum packet size */ 2676 td->itd_bp[1] = htoehci32(sc, temp); 2677 2678 /* set transfer multiplier */ 2679 td->itd_bp[2] = htoehci32(sc, xfer->max_packet_count & 3); 2680 2681 usb2_pc_cpu_flush(td->page_cache); 2682 } 2683 } 2684 } 2685 2686 static void 2687 ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2688 { 2689 ehci_device_done(xfer, USB_ERR_CANCELLED); 2690 } 2691 2692 static void 2693 ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2694 { 2695 struct usb2_page_search buf_res; 2696 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2697 ehci_itd_t *td; 2698 ehci_itd_t *td_last = NULL; 2699 ehci_itd_t **pp_last; 2700 bus_size_t page_addr; 2701 uint32_t *plen; 2702 uint32_t status; 2703 uint32_t buf_offset; 2704 uint32_t nframes; 2705 uint32_t itd_offset[8 + 1]; 2706 uint8_t x; 2707 uint8_t td_no; 2708 uint8_t page_no; 2709 2710 #if USB_DEBUG 2711 uint8_t once = 1; 2712 2713 #endif 2714 2715 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2716 xfer, xfer->pipe->isoc_next, xfer->nframes); 2717 2718 /* get the current frame index */ 2719 2720 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2721 2722 /* 2723 * check if the frame index is within the window where the frames 2724 * will be inserted 2725 */ 2726 buf_offset = (nframes - xfer->pipe->isoc_next) & 2727 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2728 2729 if ((xfer->pipe->is_synced == 0) || 2730 (buf_offset < ((xfer->nframes + 7) / 8))) { 2731 /* 2732 * If there is data underflow or the pipe queue is empty we 2733 * schedule the transfer a few frames ahead of the current 2734 * frame position. Else two isochronous transfers might 2735 * overlap. 2736 */ 2737 xfer->pipe->isoc_next = (nframes + 3) & 2738 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2739 xfer->pipe->is_synced = 1; 2740 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2741 } 2742 /* 2743 * compute how many milliseconds the insertion is ahead of the 2744 * current frame position: 2745 */ 2746 buf_offset = (xfer->pipe->isoc_next - nframes) & 2747 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2748 2749 /* 2750 * pre-compute when the isochronous transfer will be finished: 2751 */ 2752 xfer->isoc_time_complete = 2753 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2754 ((xfer->nframes + 7) / 8); 2755 2756 /* get the real number of frames */ 2757 2758 nframes = xfer->nframes; 2759 2760 buf_offset = 0; 2761 td_no = 0; 2762 2763 plen = xfer->frlengths; 2764 2765 /* toggle the DMA set we are using */ 2766 xfer->flags_int.curr_dma_set ^= 1; 2767 2768 /* get next DMA set */ 2769 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2770 xfer->td_transfer_first = td; 2771 2772 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2773 2774 /* store starting position */ 2775 2776 xfer->qh_pos = xfer->pipe->isoc_next; 2777 2778 while (nframes--) { 2779 if (td == NULL) { 2780 panic("%s:%d: out of TD's\n", 2781 __FUNCTION__, __LINE__); 2782 } 2783 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2784 pp_last = &sc->sc_isoc_hs_p_last[0]; 2785 } 2786 /* range check */ 2787 if (*plen > xfer->max_frame_size) { 2788 #if USB_DEBUG 2789 if (once) { 2790 once = 0; 2791 printf("%s: frame length(%d) exceeds %d bytes " 2792 "(frame truncated)\n", 2793 __FUNCTION__, *plen, xfer->max_frame_size); 2794 } 2795 #endif 2796 *plen = xfer->max_frame_size; 2797 } 2798 status = (EHCI_ITD_SET_LEN(*plen) | 2799 EHCI_ITD_ACTIVE | 2800 EHCI_ITD_SET_PG(0)); 2801 td->itd_status[td_no] = htoehci32(sc, status); 2802 itd_offset[td_no] = buf_offset; 2803 buf_offset += *plen; 2804 plen++; 2805 td_no++; 2806 2807 if ((td_no == 8) || (nframes == 0)) { 2808 2809 /* the rest of the transfers are not active, if any */ 2810 for (x = td_no; x != 8; x++) { 2811 td->itd_status[x] = 0; /* not active */ 2812 } 2813 2814 /* check if there is any data to be transferred */ 2815 if (itd_offset[0] != buf_offset) { 2816 page_no = 0; 2817 itd_offset[td_no] = buf_offset; 2818 2819 /* get first page offset */ 2820 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2821 /* get page address */ 2822 page_addr = buf_res.physaddr & ~0xFFF; 2823 /* update page address */ 2824 td->itd_bp[0] &= htoehci32(sc, 0xFFF); 2825 td->itd_bp[0] |= htoehci32(sc, page_addr); 2826 2827 for (x = 0; x != td_no; x++) { 2828 /* set page number and page offset */ 2829 status = (EHCI_ITD_SET_PG(page_no) | 2830 (buf_res.physaddr & 0xFFF)); 2831 td->itd_status[x] |= htoehci32(sc, status); 2832 2833 /* get next page offset */ 2834 if (itd_offset[x + 1] == buf_offset) { 2835 /* 2836 * We subtract one so that 2837 * we don't go off the last 2838 * page! 2839 */ 2840 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2841 } else { 2842 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2843 } 2844 2845 /* check if we need a new page */ 2846 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2847 /* new page needed */ 2848 page_addr = buf_res.physaddr & ~0xFFF; 2849 if (page_no == 6) { 2850 panic("%s: too many pages\n", __FUNCTION__); 2851 } 2852 page_no++; 2853 /* update page address */ 2854 td->itd_bp[page_no] &= htoehci32(sc, 0xFFF); 2855 td->itd_bp[page_no] |= htoehci32(sc, page_addr); 2856 } 2857 } 2858 } 2859 /* set IOC bit if we are complete */ 2860 if (nframes == 0) { 2861 td->itd_status[7] |= htoehci32(sc, EHCI_ITD_IOC); 2862 } 2863 usb2_pc_cpu_flush(td->page_cache); 2864 #if USB_DEBUG 2865 if (ehcidebug > 15) { 2866 DPRINTF("HS-TD %d\n", nframes); 2867 ehci_dump_itd(sc, td); 2868 } 2869 #endif 2870 /* insert TD into schedule */ 2871 EHCI_APPEND_HS_TD(td, *pp_last); 2872 pp_last++; 2873 2874 td_no = 0; 2875 td_last = td; 2876 td = td->obj_next; 2877 } 2878 } 2879 2880 xfer->td_transfer_last = td_last; 2881 2882 /* update isoc_next */ 2883 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2884 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2885 } 2886 2887 static void 2888 ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2889 { 2890 /* put transfer on interrupt queue */ 2891 ehci_transfer_intr_enqueue(xfer); 2892 } 2893 2894 struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2895 { 2896 .open = ehci_device_isoc_hs_open, 2897 .close = ehci_device_isoc_hs_close, 2898 .enter = ehci_device_isoc_hs_enter, 2899 .start = ehci_device_isoc_hs_start, 2900 .enter_is_cancelable = 1, 2901 .start_is_cancelable = 1, 2902 }; 2903 2904 /*------------------------------------------------------------------------* 2905 * ehci root control support 2906 *------------------------------------------------------------------------* 2907 * simulate a hardware hub by handling 2908 * all the necessary requests 2909 *------------------------------------------------------------------------*/ 2910 2911 static void 2912 ehci_root_ctrl_open(struct usb2_xfer *xfer) 2913 { 2914 return; 2915 } 2916 2917 static void 2918 ehci_root_ctrl_close(struct usb2_xfer *xfer) 2919 { 2920 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2921 2922 if (sc->sc_root_ctrl.xfer == xfer) { 2923 sc->sc_root_ctrl.xfer = NULL; 2924 } 2925 ehci_device_done(xfer, USB_ERR_CANCELLED); 2926 } 2927 2928 /* data structures and routines 2929 * to emulate the root hub: 2930 */ 2931 2932 static const 2933 struct usb2_device_descriptor ehci_devd = 2934 { 2935 sizeof(struct usb2_device_descriptor), 2936 UDESC_DEVICE, /* type */ 2937 {0x00, 0x02}, /* USB version */ 2938 UDCLASS_HUB, /* class */ 2939 UDSUBCLASS_HUB, /* subclass */ 2940 UDPROTO_HSHUBSTT, /* protocol */ 2941 64, /* max packet */ 2942 {0}, {0}, {0x00, 0x01}, /* device id */ 2943 1, 2, 0, /* string indicies */ 2944 1 /* # of configurations */ 2945 }; 2946 2947 static const 2948 struct usb2_device_qualifier ehci_odevd = 2949 { 2950 sizeof(struct usb2_device_qualifier), 2951 UDESC_DEVICE_QUALIFIER, /* type */ 2952 {0x00, 0x02}, /* USB version */ 2953 UDCLASS_HUB, /* class */ 2954 UDSUBCLASS_HUB, /* subclass */ 2955 UDPROTO_FSHUB, /* protocol */ 2956 0, /* max packet */ 2957 0, /* # of configurations */ 2958 0 2959 }; 2960 2961 static const struct ehci_config_desc ehci_confd = { 2962 .confd = { 2963 .bLength = sizeof(struct usb2_config_descriptor), 2964 .bDescriptorType = UDESC_CONFIG, 2965 .wTotalLength[0] = sizeof(ehci_confd), 2966 .bNumInterface = 1, 2967 .bConfigurationValue = 1, 2968 .iConfiguration = 0, 2969 .bmAttributes = UC_SELF_POWERED, 2970 .bMaxPower = 0 /* max power */ 2971 }, 2972 2973 .ifcd = { 2974 .bLength = sizeof(struct usb2_interface_descriptor), 2975 .bDescriptorType = UDESC_INTERFACE, 2976 .bNumEndpoints = 1, 2977 .bInterfaceClass = UICLASS_HUB, 2978 .bInterfaceSubClass = UISUBCLASS_HUB, 2979 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2980 0 2981 }, 2982 2983 .endpd = { 2984 .bLength = sizeof(struct usb2_endpoint_descriptor), 2985 .bDescriptorType = UDESC_ENDPOINT, 2986 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2987 .bmAttributes = UE_INTERRUPT, 2988 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2989 .bInterval = 255, 2990 }, 2991 }; 2992 2993 static const 2994 struct usb2_hub_descriptor ehci_hubd = 2995 { 2996 0, /* dynamic length */ 2997 UDESC_HUB, 2998 0, 2999 {0, 0}, 3000 0, 3001 0, 3002 {0}, 3003 }; 3004 3005 static void 3006 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3007 { 3008 uint32_t port; 3009 uint32_t v; 3010 3011 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3012 3013 port = EHCI_PORTSC(index); 3014 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3015 EOWRITE4(sc, port, v | EHCI_PS_PO); 3016 } 3017 3018 static void 3019 ehci_root_ctrl_enter(struct usb2_xfer *xfer) 3020 { 3021 return; 3022 } 3023 3024 static void 3025 ehci_root_ctrl_start(struct usb2_xfer *xfer) 3026 { 3027 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3028 3029 DPRINTF("\n"); 3030 3031 sc->sc_root_ctrl.xfer = xfer; 3032 3033 usb2_bus_roothub_exec(xfer->xroot->bus); 3034 } 3035 3036 static void 3037 ehci_root_ctrl_task(struct usb2_bus *bus) 3038 { 3039 ehci_root_ctrl_poll(EHCI_BUS2SC(bus)); 3040 } 3041 3042 static void 3043 ehci_root_ctrl_done(struct usb2_xfer *xfer, 3044 struct usb2_sw_transfer *std) 3045 { 3046 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3047 char *ptr; 3048 uint32_t port; 3049 uint32_t v; 3050 uint16_t i; 3051 uint16_t value; 3052 uint16_t index; 3053 uint8_t l; 3054 3055 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3056 3057 if (std->state != USB_SW_TR_SETUP) { 3058 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3059 /* transfer transferred */ 3060 ehci_device_done(xfer, std->err); 3061 } 3062 goto done; 3063 } 3064 /* buffer reset */ 3065 std->ptr = sc->sc_hub_desc.temp; 3066 std->len = 0; 3067 3068 value = UGETW(std->req.wValue); 3069 index = UGETW(std->req.wIndex); 3070 3071 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3072 "wValue=0x%04x wIndex=0x%04x\n", 3073 std->req.bmRequestType, std->req.bRequest, 3074 UGETW(std->req.wLength), value, index); 3075 3076 #define C(x,y) ((x) | ((y) << 8)) 3077 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3078 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3079 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3080 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3081 /* 3082 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3083 * for the integrated root hub. 3084 */ 3085 break; 3086 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3087 std->len = 1; 3088 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3089 break; 3090 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3091 switch (value >> 8) { 3092 case UDESC_DEVICE: 3093 if ((value & 0xff) != 0) { 3094 std->err = USB_ERR_IOERROR; 3095 goto done; 3096 } 3097 std->len = sizeof(ehci_devd); 3098 sc->sc_hub_desc.devd = ehci_devd; 3099 break; 3100 /* 3101 * We can't really operate at another speed, 3102 * but the specification says we need this 3103 * descriptor: 3104 */ 3105 case UDESC_DEVICE_QUALIFIER: 3106 if ((value & 0xff) != 0) { 3107 std->err = USB_ERR_IOERROR; 3108 goto done; 3109 } 3110 std->len = sizeof(ehci_odevd); 3111 sc->sc_hub_desc.odevd = ehci_odevd; 3112 break; 3113 3114 case UDESC_CONFIG: 3115 if ((value & 0xff) != 0) { 3116 std->err = USB_ERR_IOERROR; 3117 goto done; 3118 } 3119 std->len = sizeof(ehci_confd); 3120 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3121 break; 3122 3123 case UDESC_STRING: 3124 switch (value & 0xff) { 3125 case 0: /* Language table */ 3126 ptr = "\001"; 3127 break; 3128 3129 case 1: /* Vendor */ 3130 ptr = sc->sc_vendor; 3131 break; 3132 3133 case 2: /* Product */ 3134 ptr = "EHCI root HUB"; 3135 break; 3136 3137 default: 3138 ptr = ""; 3139 break; 3140 } 3141 3142 std->len = usb2_make_str_desc 3143 (sc->sc_hub_desc.temp, 3144 sizeof(sc->sc_hub_desc.temp), 3145 ptr); 3146 break; 3147 default: 3148 std->err = USB_ERR_IOERROR; 3149 goto done; 3150 } 3151 break; 3152 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3153 std->len = 1; 3154 sc->sc_hub_desc.temp[0] = 0; 3155 break; 3156 case C(UR_GET_STATUS, UT_READ_DEVICE): 3157 std->len = 2; 3158 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3159 break; 3160 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3161 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3162 std->len = 2; 3163 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3164 break; 3165 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3166 if (value >= USB_MAX_DEVICES) { 3167 std->err = USB_ERR_IOERROR; 3168 goto done; 3169 } 3170 sc->sc_addr = value; 3171 break; 3172 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3173 if ((value != 0) && (value != 1)) { 3174 std->err = USB_ERR_IOERROR; 3175 goto done; 3176 } 3177 sc->sc_conf = value; 3178 break; 3179 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3180 break; 3181 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3182 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3183 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3184 std->err = USB_ERR_IOERROR; 3185 goto done; 3186 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3187 break; 3188 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3189 break; 3190 /* Hub requests */ 3191 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3192 break; 3193 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3194 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3195 3196 if ((index < 1) || 3197 (index > sc->sc_noport)) { 3198 std->err = USB_ERR_IOERROR; 3199 goto done; 3200 } 3201 port = EHCI_PORTSC(index); 3202 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3203 switch (value) { 3204 case UHF_PORT_ENABLE: 3205 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3206 break; 3207 case UHF_PORT_SUSPEND: 3208 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3209 3210 /* 3211 * waking up a High Speed device is rather 3212 * complicated if 3213 */ 3214 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3215 } 3216 /* wait 20ms for resume sequence to complete */ 3217 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3218 3219 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3220 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3221 3222 /* 4ms settle time */ 3223 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3224 break; 3225 case UHF_PORT_POWER: 3226 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3227 break; 3228 case UHF_PORT_TEST: 3229 DPRINTFN(3, "clear port test " 3230 "%d\n", index); 3231 break; 3232 case UHF_PORT_INDICATOR: 3233 DPRINTFN(3, "clear port ind " 3234 "%d\n", index); 3235 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3236 break; 3237 case UHF_C_PORT_CONNECTION: 3238 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3239 break; 3240 case UHF_C_PORT_ENABLE: 3241 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3242 break; 3243 case UHF_C_PORT_SUSPEND: 3244 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3245 break; 3246 case UHF_C_PORT_OVER_CURRENT: 3247 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3248 break; 3249 case UHF_C_PORT_RESET: 3250 sc->sc_isreset = 0; 3251 break; 3252 default: 3253 std->err = USB_ERR_IOERROR; 3254 goto done; 3255 } 3256 break; 3257 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3258 if ((value & 0xff) != 0) { 3259 std->err = USB_ERR_IOERROR; 3260 goto done; 3261 } 3262 v = EOREAD4(sc, EHCI_HCSPARAMS); 3263 3264 sc->sc_hub_desc.hubd = ehci_hubd; 3265 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3266 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3267 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3268 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3269 UHD_PORT_IND : 0)); 3270 /* XXX can't find out? */ 3271 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3272 for (l = 0; l < sc->sc_noport; l++) { 3273 /* XXX can't find out? */ 3274 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3275 } 3276 sc->sc_hub_desc.hubd.bDescLength = 3277 8 + ((sc->sc_noport + 7) / 8); 3278 std->len = sc->sc_hub_desc.hubd.bDescLength; 3279 break; 3280 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3281 std->len = 16; 3282 bzero(sc->sc_hub_desc.temp, 16); 3283 break; 3284 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3285 DPRINTFN(9, "get port status i=%d\n", 3286 index); 3287 if ((index < 1) || 3288 (index > sc->sc_noport)) { 3289 std->err = USB_ERR_IOERROR; 3290 goto done; 3291 } 3292 v = EOREAD4(sc, EHCI_PORTSC(index)); 3293 DPRINTFN(9, "port status=0x%04x\n", v); 3294 if (sc->sc_flags & EHCI_SCFLG_FORCESPEED) { 3295 if ((v & 0xc000000) == 0x8000000) 3296 i = UPS_HIGH_SPEED; 3297 else if ((v & 0xc000000) == 0x4000000) 3298 i = UPS_LOW_SPEED; 3299 else 3300 i = 0; 3301 } else { 3302 i = UPS_HIGH_SPEED; 3303 } 3304 if (v & EHCI_PS_CS) 3305 i |= UPS_CURRENT_CONNECT_STATUS; 3306 if (v & EHCI_PS_PE) 3307 i |= UPS_PORT_ENABLED; 3308 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3309 i |= UPS_SUSPEND; 3310 if (v & EHCI_PS_OCA) 3311 i |= UPS_OVERCURRENT_INDICATOR; 3312 if (v & EHCI_PS_PR) 3313 i |= UPS_RESET; 3314 if (v & EHCI_PS_PP) 3315 i |= UPS_PORT_POWER; 3316 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3317 i = 0; 3318 if (v & EHCI_PS_CSC) 3319 i |= UPS_C_CONNECT_STATUS; 3320 if (v & EHCI_PS_PEC) 3321 i |= UPS_C_PORT_ENABLED; 3322 if (v & EHCI_PS_OCC) 3323 i |= UPS_C_OVERCURRENT_INDICATOR; 3324 if (v & EHCI_PS_FPR) 3325 i |= UPS_C_SUSPEND; 3326 if (sc->sc_isreset) 3327 i |= UPS_C_PORT_RESET; 3328 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3329 std->len = sizeof(sc->sc_hub_desc.ps); 3330 break; 3331 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3332 std->err = USB_ERR_IOERROR; 3333 goto done; 3334 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3335 break; 3336 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3337 if ((index < 1) || 3338 (index > sc->sc_noport)) { 3339 std->err = USB_ERR_IOERROR; 3340 goto done; 3341 } 3342 port = EHCI_PORTSC(index); 3343 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3344 switch (value) { 3345 case UHF_PORT_ENABLE: 3346 EOWRITE4(sc, port, v | EHCI_PS_PE); 3347 break; 3348 case UHF_PORT_SUSPEND: 3349 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3350 break; 3351 case UHF_PORT_RESET: 3352 DPRINTFN(6, "reset port %d\n", index); 3353 #if USB_DEBUG 3354 if (ehcinohighspeed) { 3355 /* 3356 * Connect USB device to companion 3357 * controller. 3358 */ 3359 ehci_disown(sc, index, 1); 3360 break; 3361 } 3362 #endif 3363 if (EHCI_PS_IS_LOWSPEED(v)) { 3364 /* Low speed device, give up ownership. */ 3365 ehci_disown(sc, index, 1); 3366 break; 3367 } 3368 /* Start reset sequence. */ 3369 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3370 EOWRITE4(sc, port, v | EHCI_PS_PR); 3371 3372 /* Wait for reset to complete. */ 3373 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3374 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3375 3376 /* Terminate reset sequence. */ 3377 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3378 EOWRITE4(sc, port, v); 3379 3380 /* Wait for HC to complete reset. */ 3381 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3382 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3383 3384 v = EOREAD4(sc, port); 3385 DPRINTF("ehci after reset, status=0x%08x\n", v); 3386 if (v & EHCI_PS_PR) { 3387 device_printf(sc->sc_bus.bdev, 3388 "port reset timeout\n"); 3389 std->err = USB_ERR_TIMEOUT; 3390 goto done; 3391 } 3392 if (!(v & EHCI_PS_PE)) { 3393 /* 3394 * Not a high speed device, give up 3395 * ownership. 3396 */ 3397 ehci_disown(sc, index, 0); 3398 break; 3399 } 3400 sc->sc_isreset = 1; 3401 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3402 index, v); 3403 break; 3404 3405 case UHF_PORT_POWER: 3406 DPRINTFN(3, "set port power %d\n", index); 3407 EOWRITE4(sc, port, v | EHCI_PS_PP); 3408 break; 3409 3410 case UHF_PORT_TEST: 3411 DPRINTFN(3, "set port test %d\n", index); 3412 break; 3413 3414 case UHF_PORT_INDICATOR: 3415 DPRINTFN(3, "set port ind %d\n", index); 3416 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3417 break; 3418 3419 default: 3420 std->err = USB_ERR_IOERROR; 3421 goto done; 3422 } 3423 break; 3424 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3425 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3426 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3427 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3428 break; 3429 default: 3430 std->err = USB_ERR_IOERROR; 3431 goto done; 3432 } 3433 done: 3434 return; 3435 } 3436 3437 static void 3438 ehci_root_ctrl_poll(ehci_softc_t *sc) 3439 { 3440 usb2_sw_transfer(&sc->sc_root_ctrl, 3441 &ehci_root_ctrl_done); 3442 } 3443 3444 struct usb2_pipe_methods ehci_root_ctrl_methods = 3445 { 3446 .open = ehci_root_ctrl_open, 3447 .close = ehci_root_ctrl_close, 3448 .enter = ehci_root_ctrl_enter, 3449 .start = ehci_root_ctrl_start, 3450 .enter_is_cancelable = 1, 3451 .start_is_cancelable = 0, 3452 }; 3453 3454 /*------------------------------------------------------------------------* 3455 * ehci root interrupt support 3456 *------------------------------------------------------------------------*/ 3457 static void 3458 ehci_root_intr_open(struct usb2_xfer *xfer) 3459 { 3460 return; 3461 } 3462 3463 static void 3464 ehci_root_intr_close(struct usb2_xfer *xfer) 3465 { 3466 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3467 3468 if (sc->sc_root_intr.xfer == xfer) { 3469 sc->sc_root_intr.xfer = NULL; 3470 } 3471 ehci_device_done(xfer, USB_ERR_CANCELLED); 3472 } 3473 3474 static void 3475 ehci_root_intr_enter(struct usb2_xfer *xfer) 3476 { 3477 return; 3478 } 3479 3480 static void 3481 ehci_root_intr_start(struct usb2_xfer *xfer) 3482 { 3483 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3484 3485 sc->sc_root_intr.xfer = xfer; 3486 } 3487 3488 struct usb2_pipe_methods ehci_root_intr_methods = 3489 { 3490 .open = ehci_root_intr_open, 3491 .close = ehci_root_intr_close, 3492 .enter = ehci_root_intr_enter, 3493 .start = ehci_root_intr_start, 3494 .enter_is_cancelable = 1, 3495 .start_is_cancelable = 1, 3496 }; 3497 3498 static void 3499 ehci_xfer_setup(struct usb2_setup_params *parm) 3500 { 3501 struct usb2_page_search page_info; 3502 struct usb2_page_cache *pc; 3503 ehci_softc_t *sc; 3504 struct usb2_xfer *xfer; 3505 void *last_obj; 3506 uint32_t nqtd; 3507 uint32_t nqh; 3508 uint32_t nsitd; 3509 uint32_t nitd; 3510 uint32_t n; 3511 3512 sc = EHCI_BUS2SC(parm->udev->bus); 3513 xfer = parm->curr_xfer; 3514 3515 nqtd = 0; 3516 nqh = 0; 3517 nsitd = 0; 3518 nitd = 0; 3519 3520 /* 3521 * compute maximum number of some structures 3522 */ 3523 if (parm->methods == &ehci_device_ctrl_methods) { 3524 3525 /* 3526 * The proof for the "nqtd" formula is illustrated like 3527 * this: 3528 * 3529 * +------------------------------------+ 3530 * | | 3531 * | |remainder -> | 3532 * | +-----+---+ | 3533 * | | xxx | x | frm 0 | 3534 * | +-----+---++ | 3535 * | | xxx | xx | frm 1 | 3536 * | +-----+----+ | 3537 * | ... | 3538 * +------------------------------------+ 3539 * 3540 * "xxx" means a completely full USB transfer descriptor 3541 * 3542 * "x" and "xx" means a short USB packet 3543 * 3544 * For the remainder of an USB transfer modulo 3545 * "max_data_length" we need two USB transfer descriptors. 3546 * One to transfer the remaining data and one to finalise 3547 * with a zero length packet in case the "force_short_xfer" 3548 * flag is set. We only need two USB transfer descriptors in 3549 * the case where the transfer length of the first one is a 3550 * factor of "max_frame_size". The rest of the needed USB 3551 * transfer descriptors is given by the buffer size divided 3552 * by the maximum data payload. 3553 */ 3554 parm->hc_max_packet_size = 0x400; 3555 parm->hc_max_packet_count = 1; 3556 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3557 xfer->flags_int.bdma_enable = 1; 3558 3559 usb2_transfer_setup_sub(parm); 3560 3561 nqh = 1; 3562 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3563 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3564 3565 } else if (parm->methods == &ehci_device_bulk_methods) { 3566 3567 parm->hc_max_packet_size = 0x400; 3568 parm->hc_max_packet_count = 1; 3569 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3570 xfer->flags_int.bdma_enable = 1; 3571 3572 usb2_transfer_setup_sub(parm); 3573 3574 nqh = 1; 3575 nqtd = ((2 * xfer->nframes) 3576 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3577 3578 } else if (parm->methods == &ehci_device_intr_methods) { 3579 3580 if (parm->speed == USB_SPEED_HIGH) { 3581 parm->hc_max_packet_size = 0x400; 3582 parm->hc_max_packet_count = 3; 3583 } else if (parm->speed == USB_SPEED_FULL) { 3584 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3585 parm->hc_max_packet_count = 1; 3586 } else { 3587 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3588 parm->hc_max_packet_count = 1; 3589 } 3590 3591 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3592 xfer->flags_int.bdma_enable = 1; 3593 3594 usb2_transfer_setup_sub(parm); 3595 3596 nqh = 1; 3597 nqtd = ((2 * xfer->nframes) 3598 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3599 3600 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3601 3602 parm->hc_max_packet_size = 0x3FF; 3603 parm->hc_max_packet_count = 1; 3604 parm->hc_max_frame_size = 0x3FF; 3605 xfer->flags_int.bdma_enable = 1; 3606 3607 usb2_transfer_setup_sub(parm); 3608 3609 nsitd = xfer->nframes; 3610 3611 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3612 3613 parm->hc_max_packet_size = 0x400; 3614 parm->hc_max_packet_count = 3; 3615 parm->hc_max_frame_size = 0xC00; 3616 xfer->flags_int.bdma_enable = 1; 3617 3618 usb2_transfer_setup_sub(parm); 3619 3620 nitd = (xfer->nframes + 7) / 8; 3621 3622 } else { 3623 3624 parm->hc_max_packet_size = 0x400; 3625 parm->hc_max_packet_count = 1; 3626 parm->hc_max_frame_size = 0x400; 3627 3628 usb2_transfer_setup_sub(parm); 3629 } 3630 3631 alloc_dma_set: 3632 3633 if (parm->err) { 3634 return; 3635 } 3636 /* 3637 * Allocate queue heads and transfer descriptors 3638 */ 3639 last_obj = NULL; 3640 3641 if (usb2_transfer_setup_sub_malloc( 3642 parm, &pc, sizeof(ehci_itd_t), 3643 EHCI_ITD_ALIGN, nitd)) { 3644 parm->err = USB_ERR_NOMEM; 3645 return; 3646 } 3647 if (parm->buf) { 3648 for (n = 0; n != nitd; n++) { 3649 ehci_itd_t *td; 3650 3651 usb2_get_page(pc + n, 0, &page_info); 3652 3653 td = page_info.buffer; 3654 3655 /* init TD */ 3656 td->itd_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_ITD); 3657 td->obj_next = last_obj; 3658 td->page_cache = pc + n; 3659 3660 last_obj = td; 3661 3662 usb2_pc_cpu_flush(pc + n); 3663 } 3664 } 3665 if (usb2_transfer_setup_sub_malloc( 3666 parm, &pc, sizeof(ehci_sitd_t), 3667 EHCI_SITD_ALIGN, nsitd)) { 3668 parm->err = USB_ERR_NOMEM; 3669 return; 3670 } 3671 if (parm->buf) { 3672 for (n = 0; n != nsitd; n++) { 3673 ehci_sitd_t *td; 3674 3675 usb2_get_page(pc + n, 0, &page_info); 3676 3677 td = page_info.buffer; 3678 3679 /* init TD */ 3680 td->sitd_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_SITD); 3681 td->obj_next = last_obj; 3682 td->page_cache = pc + n; 3683 3684 last_obj = td; 3685 3686 usb2_pc_cpu_flush(pc + n); 3687 } 3688 } 3689 if (usb2_transfer_setup_sub_malloc( 3690 parm, &pc, sizeof(ehci_qtd_t), 3691 EHCI_QTD_ALIGN, nqtd)) { 3692 parm->err = USB_ERR_NOMEM; 3693 return; 3694 } 3695 if (parm->buf) { 3696 for (n = 0; n != nqtd; n++) { 3697 ehci_qtd_t *qtd; 3698 3699 usb2_get_page(pc + n, 0, &page_info); 3700 3701 qtd = page_info.buffer; 3702 3703 /* init TD */ 3704 qtd->qtd_self = htoehci32(sc, page_info.physaddr); 3705 qtd->obj_next = last_obj; 3706 qtd->page_cache = pc + n; 3707 3708 last_obj = qtd; 3709 3710 usb2_pc_cpu_flush(pc + n); 3711 } 3712 } 3713 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3714 3715 last_obj = NULL; 3716 3717 if (usb2_transfer_setup_sub_malloc( 3718 parm, &pc, sizeof(ehci_qh_t), 3719 EHCI_QH_ALIGN, nqh)) { 3720 parm->err = USB_ERR_NOMEM; 3721 return; 3722 } 3723 if (parm->buf) { 3724 for (n = 0; n != nqh; n++) { 3725 ehci_qh_t *qh; 3726 3727 usb2_get_page(pc + n, 0, &page_info); 3728 3729 qh = page_info.buffer; 3730 3731 /* init QH */ 3732 qh->qh_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_QH); 3733 qh->obj_next = last_obj; 3734 qh->page_cache = pc + n; 3735 3736 last_obj = qh; 3737 3738 usb2_pc_cpu_flush(pc + n); 3739 } 3740 } 3741 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3742 3743 if (!xfer->flags_int.curr_dma_set) { 3744 xfer->flags_int.curr_dma_set = 1; 3745 goto alloc_dma_set; 3746 } 3747 } 3748 3749 static void 3750 ehci_xfer_unsetup(struct usb2_xfer *xfer) 3751 { 3752 return; 3753 } 3754 3755 static void 3756 ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3757 struct usb2_pipe *pipe) 3758 { 3759 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3760 3761 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3762 pipe, udev->address, 3763 edesc->bEndpointAddress, udev->flags.usb2_mode, 3764 sc->sc_addr); 3765 3766 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3767 /* not supported */ 3768 return; 3769 } 3770 if (udev->device_index == sc->sc_addr) { 3771 switch (edesc->bEndpointAddress) { 3772 case USB_CONTROL_ENDPOINT: 3773 pipe->methods = &ehci_root_ctrl_methods; 3774 break; 3775 case UE_DIR_IN | EHCI_INTR_ENDPT: 3776 pipe->methods = &ehci_root_intr_methods; 3777 break; 3778 default: 3779 /* do nothing */ 3780 break; 3781 } 3782 } else { 3783 if ((udev->speed != USB_SPEED_HIGH) && 3784 ((udev->hs_hub_addr == 0) || 3785 (udev->hs_port_no == 0) || 3786 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3787 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3788 /* We need a transaction translator */ 3789 goto done; 3790 } 3791 switch (edesc->bmAttributes & UE_XFERTYPE) { 3792 case UE_CONTROL: 3793 pipe->methods = &ehci_device_ctrl_methods; 3794 break; 3795 case UE_INTERRUPT: 3796 pipe->methods = &ehci_device_intr_methods; 3797 break; 3798 case UE_ISOCHRONOUS: 3799 if (udev->speed == USB_SPEED_HIGH) { 3800 pipe->methods = &ehci_device_isoc_hs_methods; 3801 } else if (udev->speed == USB_SPEED_FULL) { 3802 pipe->methods = &ehci_device_isoc_fs_methods; 3803 } 3804 break; 3805 case UE_BULK: 3806 if (udev->speed != USB_SPEED_LOW) { 3807 pipe->methods = &ehci_device_bulk_methods; 3808 } 3809 break; 3810 default: 3811 /* do nothing */ 3812 break; 3813 } 3814 } 3815 done: 3816 return; 3817 } 3818 3819 static void 3820 ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3821 { 3822 /* 3823 * Wait until the hardware has finished any possible use of 3824 * the transfer descriptor(s) and QH 3825 */ 3826 *pus = (188); /* microseconds */ 3827 } 3828 3829 static void 3830 ehci_device_resume(struct usb2_device *udev) 3831 { 3832 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3833 struct usb2_xfer *xfer; 3834 struct usb2_pipe_methods *methods; 3835 3836 DPRINTF("\n"); 3837 3838 USB_BUS_LOCK(udev->bus); 3839 3840 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3841 3842 if (xfer->xroot->udev == udev) { 3843 3844 methods = xfer->pipe->methods; 3845 3846 if ((methods == &ehci_device_bulk_methods) || 3847 (methods == &ehci_device_ctrl_methods)) { 3848 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3849 sc->sc_async_p_last); 3850 } 3851 if (methods == &ehci_device_intr_methods) { 3852 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3853 sc->sc_intr_p_last[xfer->qh_pos]); 3854 } 3855 } 3856 } 3857 3858 USB_BUS_UNLOCK(udev->bus); 3859 3860 return; 3861 } 3862 3863 static void 3864 ehci_device_suspend(struct usb2_device *udev) 3865 { 3866 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3867 struct usb2_xfer *xfer; 3868 struct usb2_pipe_methods *methods; 3869 3870 DPRINTF("\n"); 3871 3872 USB_BUS_LOCK(udev->bus); 3873 3874 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3875 3876 if (xfer->xroot->udev == udev) { 3877 3878 methods = xfer->pipe->methods; 3879 3880 if ((methods == &ehci_device_bulk_methods) || 3881 (methods == &ehci_device_ctrl_methods)) { 3882 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3883 sc->sc_async_p_last); 3884 } 3885 if (methods == &ehci_device_intr_methods) { 3886 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3887 sc->sc_intr_p_last[xfer->qh_pos]); 3888 } 3889 } 3890 } 3891 3892 USB_BUS_UNLOCK(udev->bus); 3893 3894 return; 3895 } 3896 3897 static void 3898 ehci_set_hw_power(struct usb2_bus *bus) 3899 { 3900 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3901 uint32_t temp; 3902 uint32_t flags; 3903 3904 DPRINTF("\n"); 3905 3906 USB_BUS_LOCK(bus); 3907 3908 flags = bus->hw_power_state; 3909 3910 temp = EOREAD4(sc, EHCI_USBCMD); 3911 3912 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3913 3914 if (flags & (USB_HW_POWER_CONTROL | 3915 USB_HW_POWER_BULK)) { 3916 DPRINTF("Async is active\n"); 3917 temp |= EHCI_CMD_ASE; 3918 } 3919 if (flags & (USB_HW_POWER_INTERRUPT | 3920 USB_HW_POWER_ISOC)) { 3921 DPRINTF("Periodic is active\n"); 3922 temp |= EHCI_CMD_PSE; 3923 } 3924 EOWRITE4(sc, EHCI_USBCMD, temp); 3925 3926 USB_BUS_UNLOCK(bus); 3927 3928 return; 3929 } 3930 3931 struct usb2_bus_methods ehci_bus_methods = 3932 { 3933 .pipe_init = ehci_pipe_init, 3934 .xfer_setup = ehci_xfer_setup, 3935 .xfer_unsetup = ehci_xfer_unsetup, 3936 .get_dma_delay = ehci_get_dma_delay, 3937 .device_resume = ehci_device_resume, 3938 .device_suspend = ehci_device_suspend, 3939 .set_hw_power = ehci_set_hw_power, 3940 .roothub_exec = ehci_root_ctrl_task, 3941 }; 3942