1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR ehcidebug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #include <dev/usb/controller/ehci.h> 85 #include <dev/usb/controller/ehcireg.h> 86 87 #define EHCI_BUS2SC(bus) \ 88 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 89 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 90 91 #ifdef USB_DEBUG 92 static int ehcidebug = 0; 93 static int ehcinohighspeed = 0; 94 static int ehciiaadbug = 0; 95 static int ehcilostintrbug = 0; 96 97 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 99 &ehcidebug, 0, "Debug level"); 100 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 101 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW | CTLFLAG_TUN, 102 &ehcinohighspeed, 0, "Disable High Speed USB"); 103 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW | CTLFLAG_TUN, 105 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 106 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW | CTLFLAG_TUN, 108 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 109 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 110 111 112 static void ehci_dump_regs(ehci_softc_t *sc); 113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115 #endif 116 117 #define EHCI_INTR_ENDPT 1 118 119 extern struct usb_bus_methods ehci_bus_methods; 120 extern struct usb_pipe_methods ehci_device_bulk_methods; 121 extern struct usb_pipe_methods ehci_device_ctrl_methods; 122 extern struct usb_pipe_methods ehci_device_intr_methods; 123 extern struct usb_pipe_methods ehci_device_isoc_fs_methods; 124 extern struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126 static void ehci_do_poll(struct usb_bus *); 127 static void ehci_device_done(struct usb_xfer *, usb_error_t); 128 static uint8_t ehci_check_transfer(struct usb_xfer *); 129 static void ehci_timeout(void *); 130 static void ehci_poll_timeout(void *); 131 132 static void ehci_root_intr(ehci_softc_t *sc); 133 134 struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147 }; 148 149 void 150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151 { 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181 } 182 183 usb_error_t 184 ehci_reset(ehci_softc_t *sc) 185 { 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 128); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 195 /* 196 * Force USBMODE as requested. Controllers 197 * may have multiple operating modes. 198 */ 199 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 200 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 201 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 202 device_printf(sc->sc_bus.bdev, 203 "set host controller mode\n"); 204 } 205 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 206 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 207 device_printf(sc->sc_bus.bdev, 208 "set big-endian mode\n"); 209 } 210 EOWRITE4(sc, EHCI_USBMODE, usbmode); 211 } 212 return (0); 213 } 214 } 215 device_printf(sc->sc_bus.bdev, "Reset timeout\n"); 216 return (USB_ERR_IOERROR); 217 } 218 219 static usb_error_t 220 ehci_hcreset(ehci_softc_t *sc) 221 { 222 uint32_t hcr; 223 int i; 224 225 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 226 for (i = 0; i < 100; i++) { 227 usb_pause_mtx(NULL, hz / 128); 228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 229 if (hcr) 230 break; 231 } 232 if (!hcr) 233 /* 234 * Fall through and try reset anyway even though 235 * Table 2-9 in the EHCI spec says this will result 236 * in undefined behavior. 237 */ 238 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 239 240 return (ehci_reset(sc)); 241 } 242 243 static int 244 ehci_init_sub(struct ehci_softc *sc) 245 { 246 struct usb_page_search buf_res; 247 uint32_t cparams; 248 uint32_t hcr; 249 uint8_t i; 250 251 cparams = EREAD4(sc, EHCI_HCCPARAMS); 252 253 DPRINTF("cparams=0x%x\n", cparams); 254 255 if (EHCI_HCC_64BIT(cparams)) { 256 DPRINTF("HCC uses 64-bit structures\n"); 257 258 /* MUST clear segment register if 64 bit capable */ 259 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 260 } 261 262 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 263 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 264 265 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 266 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 267 268 /* enable interrupts */ 269 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 270 271 /* turn on controller */ 272 EOWRITE4(sc, EHCI_USBCMD, 273 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 274 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 275 EHCI_CMD_ASE | 276 EHCI_CMD_PSE | 277 EHCI_CMD_RS); 278 279 /* Take over port ownership */ 280 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 281 282 for (i = 0; i < 100; i++) { 283 usb_pause_mtx(NULL, hz / 128); 284 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 285 if (!hcr) { 286 break; 287 } 288 } 289 if (hcr) { 290 device_printf(sc->sc_bus.bdev, "Run timeout\n"); 291 return (USB_ERR_IOERROR); 292 } 293 return (USB_ERR_NORMAL_COMPLETION); 294 } 295 296 usb_error_t 297 ehci_init(ehci_softc_t *sc) 298 { 299 struct usb_page_search buf_res; 300 uint32_t version; 301 uint32_t sparams; 302 uint16_t i; 303 uint16_t x; 304 uint16_t y; 305 uint16_t bit; 306 usb_error_t err = 0; 307 308 DPRINTF("start\n"); 309 310 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 311 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 312 313 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 314 315 #ifdef USB_DEBUG 316 if (ehciiaadbug) 317 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 318 if (ehcilostintrbug) 319 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 320 if (ehcidebug > 2) { 321 ehci_dump_regs(sc); 322 } 323 #endif 324 325 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 326 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 327 version >> 8, version & 0xff); 328 329 sparams = EREAD4(sc, EHCI_HCSPARAMS); 330 DPRINTF("sparams=0x%x\n", sparams); 331 332 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 333 sc->sc_bus.usbrev = USB_REV_2_0; 334 335 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 336 /* Reset the controller */ 337 DPRINTF("%s: resetting\n", 338 device_get_nameunit(sc->sc_bus.bdev)); 339 340 err = ehci_hcreset(sc); 341 if (err) { 342 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 343 return (err); 344 } 345 } 346 347 /* 348 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 349 * bytes 2: 256*4 bytes 3: unknown 350 */ 351 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 352 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 353 return (USB_ERR_IOERROR); 354 } 355 /* set up the bus struct */ 356 sc->sc_bus.methods = &ehci_bus_methods; 357 358 sc->sc_eintrs = EHCI_NORMAL_INTRS; 359 360 if (1) { 361 struct ehci_qh_sub *qh; 362 363 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 364 365 qh = buf_res.buffer; 366 367 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 368 369 /* init terminate TD */ 370 qh->qtd_next = 371 htohc32(sc, EHCI_LINK_TERMINATE); 372 qh->qtd_altnext = 373 htohc32(sc, EHCI_LINK_TERMINATE); 374 qh->qtd_status = 375 htohc32(sc, EHCI_QTD_HALTED); 376 } 377 378 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 379 ehci_qh_t *qh; 380 381 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 382 383 qh = buf_res.buffer; 384 385 /* initialize page cache pointer */ 386 387 qh->page_cache = sc->sc_hw.intr_start_pc + i; 388 389 /* store a pointer to queue head */ 390 391 sc->sc_intr_p_last[i] = qh; 392 393 qh->qh_self = 394 htohc32(sc, buf_res.physaddr) | 395 htohc32(sc, EHCI_LINK_QH); 396 397 qh->qh_endp = 398 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 399 qh->qh_endphub = 400 htohc32(sc, EHCI_QH_SET_MULT(1)); 401 qh->qh_curqtd = 0; 402 403 qh->qh_qtd.qtd_next = 404 htohc32(sc, EHCI_LINK_TERMINATE); 405 qh->qh_qtd.qtd_altnext = 406 htohc32(sc, EHCI_LINK_TERMINATE); 407 qh->qh_qtd.qtd_status = 408 htohc32(sc, EHCI_QTD_HALTED); 409 } 410 411 /* 412 * the QHs are arranged to give poll intervals that are 413 * powers of 2 times 1ms 414 */ 415 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 416 while (bit) { 417 x = bit; 418 while (x & bit) { 419 ehci_qh_t *qh_x; 420 ehci_qh_t *qh_y; 421 422 y = (x ^ bit) | (bit / 2); 423 424 qh_x = sc->sc_intr_p_last[x]; 425 qh_y = sc->sc_intr_p_last[y]; 426 427 /* 428 * the next QH has half the poll interval 429 */ 430 qh_x->qh_link = qh_y->qh_self; 431 432 x++; 433 } 434 bit >>= 1; 435 } 436 437 if (1) { 438 ehci_qh_t *qh; 439 440 qh = sc->sc_intr_p_last[0]; 441 442 /* the last (1ms) QH terminates */ 443 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 444 } 445 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 446 ehci_sitd_t *sitd; 447 ehci_itd_t *itd; 448 449 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 450 451 sitd = buf_res.buffer; 452 453 /* initialize page cache pointer */ 454 455 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 456 457 /* store a pointer to the transfer descriptor */ 458 459 sc->sc_isoc_fs_p_last[i] = sitd; 460 461 /* initialize full speed isochronous */ 462 463 sitd->sitd_self = 464 htohc32(sc, buf_res.physaddr) | 465 htohc32(sc, EHCI_LINK_SITD); 466 467 sitd->sitd_back = 468 htohc32(sc, EHCI_LINK_TERMINATE); 469 470 sitd->sitd_next = 471 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 472 473 474 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 475 476 itd = buf_res.buffer; 477 478 /* initialize page cache pointer */ 479 480 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 481 482 /* store a pointer to the transfer descriptor */ 483 484 sc->sc_isoc_hs_p_last[i] = itd; 485 486 /* initialize high speed isochronous */ 487 488 itd->itd_self = 489 htohc32(sc, buf_res.physaddr) | 490 htohc32(sc, EHCI_LINK_ITD); 491 492 itd->itd_next = 493 sitd->sitd_self; 494 } 495 496 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 497 498 if (1) { 499 uint32_t *pframes; 500 501 pframes = buf_res.buffer; 502 503 /* 504 * execution order: 505 * pframes -> high speed isochronous -> 506 * full speed isochronous -> interrupt QH's 507 */ 508 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 509 pframes[i] = sc->sc_isoc_hs_p_last 510 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 511 } 512 } 513 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 514 515 if (1) { 516 517 ehci_qh_t *qh; 518 519 qh = buf_res.buffer; 520 521 /* initialize page cache pointer */ 522 523 qh->page_cache = &sc->sc_hw.async_start_pc; 524 525 /* store a pointer to the queue head */ 526 527 sc->sc_async_p_last = qh; 528 529 /* init dummy QH that starts the async list */ 530 531 qh->qh_self = 532 htohc32(sc, buf_res.physaddr) | 533 htohc32(sc, EHCI_LINK_QH); 534 535 /* fill the QH */ 536 qh->qh_endp = 537 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 538 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 539 qh->qh_link = qh->qh_self; 540 qh->qh_curqtd = 0; 541 542 /* fill the overlay qTD */ 543 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 544 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 545 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 546 } 547 /* flush all cache into memory */ 548 549 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 550 551 #ifdef USB_DEBUG 552 if (ehcidebug) { 553 ehci_dump_sqh(sc, sc->sc_async_p_last); 554 } 555 #endif 556 557 /* finial setup */ 558 err = ehci_init_sub(sc); 559 560 if (!err) { 561 /* catch any lost interrupts */ 562 ehci_do_poll(&sc->sc_bus); 563 } 564 return (err); 565 } 566 567 /* 568 * shut down the controller when the system is going down 569 */ 570 void 571 ehci_detach(ehci_softc_t *sc) 572 { 573 USB_BUS_LOCK(&sc->sc_bus); 574 575 usb_callout_stop(&sc->sc_tmo_pcd); 576 usb_callout_stop(&sc->sc_tmo_poll); 577 578 EOWRITE4(sc, EHCI_USBINTR, 0); 579 USB_BUS_UNLOCK(&sc->sc_bus); 580 581 if (ehci_hcreset(sc)) { 582 DPRINTF("reset failed!\n"); 583 } 584 585 /* XXX let stray task complete */ 586 usb_pause_mtx(NULL, hz / 20); 587 588 usb_callout_drain(&sc->sc_tmo_pcd); 589 usb_callout_drain(&sc->sc_tmo_poll); 590 } 591 592 static void 593 ehci_suspend(ehci_softc_t *sc) 594 { 595 DPRINTF("stopping the HC\n"); 596 597 /* reset HC */ 598 ehci_hcreset(sc); 599 } 600 601 static void 602 ehci_resume(ehci_softc_t *sc) 603 { 604 /* reset HC */ 605 ehci_hcreset(sc); 606 607 /* setup HC */ 608 ehci_init_sub(sc); 609 610 /* catch any lost interrupts */ 611 ehci_do_poll(&sc->sc_bus); 612 } 613 614 #ifdef USB_DEBUG 615 static void 616 ehci_dump_regs(ehci_softc_t *sc) 617 { 618 uint32_t i; 619 620 i = EOREAD4(sc, EHCI_USBCMD); 621 printf("cmd=0x%08x\n", i); 622 623 if (i & EHCI_CMD_ITC_1) 624 printf(" EHCI_CMD_ITC_1\n"); 625 if (i & EHCI_CMD_ITC_2) 626 printf(" EHCI_CMD_ITC_2\n"); 627 if (i & EHCI_CMD_ITC_4) 628 printf(" EHCI_CMD_ITC_4\n"); 629 if (i & EHCI_CMD_ITC_8) 630 printf(" EHCI_CMD_ITC_8\n"); 631 if (i & EHCI_CMD_ITC_16) 632 printf(" EHCI_CMD_ITC_16\n"); 633 if (i & EHCI_CMD_ITC_32) 634 printf(" EHCI_CMD_ITC_32\n"); 635 if (i & EHCI_CMD_ITC_64) 636 printf(" EHCI_CMD_ITC_64\n"); 637 if (i & EHCI_CMD_ASPME) 638 printf(" EHCI_CMD_ASPME\n"); 639 if (i & EHCI_CMD_ASPMC) 640 printf(" EHCI_CMD_ASPMC\n"); 641 if (i & EHCI_CMD_LHCR) 642 printf(" EHCI_CMD_LHCR\n"); 643 if (i & EHCI_CMD_IAAD) 644 printf(" EHCI_CMD_IAAD\n"); 645 if (i & EHCI_CMD_ASE) 646 printf(" EHCI_CMD_ASE\n"); 647 if (i & EHCI_CMD_PSE) 648 printf(" EHCI_CMD_PSE\n"); 649 if (i & EHCI_CMD_FLS_M) 650 printf(" EHCI_CMD_FLS_M\n"); 651 if (i & EHCI_CMD_HCRESET) 652 printf(" EHCI_CMD_HCRESET\n"); 653 if (i & EHCI_CMD_RS) 654 printf(" EHCI_CMD_RS\n"); 655 656 i = EOREAD4(sc, EHCI_USBSTS); 657 658 printf("sts=0x%08x\n", i); 659 660 if (i & EHCI_STS_ASS) 661 printf(" EHCI_STS_ASS\n"); 662 if (i & EHCI_STS_PSS) 663 printf(" EHCI_STS_PSS\n"); 664 if (i & EHCI_STS_REC) 665 printf(" EHCI_STS_REC\n"); 666 if (i & EHCI_STS_HCH) 667 printf(" EHCI_STS_HCH\n"); 668 if (i & EHCI_STS_IAA) 669 printf(" EHCI_STS_IAA\n"); 670 if (i & EHCI_STS_HSE) 671 printf(" EHCI_STS_HSE\n"); 672 if (i & EHCI_STS_FLR) 673 printf(" EHCI_STS_FLR\n"); 674 if (i & EHCI_STS_PCD) 675 printf(" EHCI_STS_PCD\n"); 676 if (i & EHCI_STS_ERRINT) 677 printf(" EHCI_STS_ERRINT\n"); 678 if (i & EHCI_STS_INT) 679 printf(" EHCI_STS_INT\n"); 680 681 printf("ien=0x%08x\n", 682 EOREAD4(sc, EHCI_USBINTR)); 683 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 684 EOREAD4(sc, EHCI_FRINDEX), 685 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 686 EOREAD4(sc, EHCI_PERIODICLISTBASE), 687 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 688 for (i = 1; i <= sc->sc_noport; i++) { 689 printf("port %d status=0x%08x\n", i, 690 EOREAD4(sc, EHCI_PORTSC(i))); 691 } 692 } 693 694 static void 695 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 696 { 697 link = hc32toh(sc, link); 698 printf("0x%08x", link); 699 if (link & EHCI_LINK_TERMINATE) 700 printf("<T>"); 701 else { 702 printf("<"); 703 if (type) { 704 switch (EHCI_LINK_TYPE(link)) { 705 case EHCI_LINK_ITD: 706 printf("ITD"); 707 break; 708 case EHCI_LINK_QH: 709 printf("QH"); 710 break; 711 case EHCI_LINK_SITD: 712 printf("SITD"); 713 break; 714 case EHCI_LINK_FSTN: 715 printf("FSTN"); 716 break; 717 } 718 } 719 printf(">"); 720 } 721 } 722 723 static void 724 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 725 { 726 uint32_t s; 727 728 printf(" next="); 729 ehci_dump_link(sc, qtd->qtd_next, 0); 730 printf(" altnext="); 731 ehci_dump_link(sc, qtd->qtd_altnext, 0); 732 printf("\n"); 733 s = hc32toh(sc, qtd->qtd_status); 734 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 735 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 736 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 737 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 738 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 739 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 740 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 741 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 742 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 743 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 744 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 745 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 746 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 747 748 for (s = 0; s < 5; s++) { 749 printf(" buffer[%d]=0x%08x\n", s, 750 hc32toh(sc, qtd->qtd_buffer[s])); 751 } 752 for (s = 0; s < 5; s++) { 753 printf(" buffer_hi[%d]=0x%08x\n", s, 754 hc32toh(sc, qtd->qtd_buffer_hi[s])); 755 } 756 } 757 758 static uint8_t 759 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 760 { 761 uint8_t temp; 762 763 usb_pc_cpu_invalidate(sqtd->page_cache); 764 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 765 ehci_dump_qtd(sc, sqtd); 766 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 767 return (temp); 768 } 769 770 static void 771 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 772 { 773 uint16_t i; 774 uint8_t stop; 775 776 stop = 0; 777 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 778 stop = ehci_dump_sqtd(sc, sqtd); 779 } 780 if (sqtd) { 781 printf("dump aborted, too many TDs\n"); 782 } 783 } 784 785 static void 786 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 787 { 788 uint32_t endp; 789 uint32_t endphub; 790 791 usb_pc_cpu_invalidate(qh->page_cache); 792 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 793 printf(" link="); 794 ehci_dump_link(sc, qh->qh_link, 1); 795 printf("\n"); 796 endp = hc32toh(sc, qh->qh_endp); 797 printf(" endp=0x%08x\n", endp); 798 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 799 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 800 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 801 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 802 printf(" mpl=0x%x ctl=%d nrl=%d\n", 803 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 804 EHCI_QH_GET_NRL(endp)); 805 endphub = hc32toh(sc, qh->qh_endphub); 806 printf(" endphub=0x%08x\n", endphub); 807 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 808 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 809 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 810 EHCI_QH_GET_MULT(endphub)); 811 printf(" curqtd="); 812 ehci_dump_link(sc, qh->qh_curqtd, 0); 813 printf("\n"); 814 printf("Overlay qTD:\n"); 815 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 816 } 817 818 static void 819 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 820 { 821 usb_pc_cpu_invalidate(sitd->page_cache); 822 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 823 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 824 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 825 hc32toh(sc, sitd->sitd_portaddr), 826 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 827 ? "in" : "out", 828 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 829 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 830 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 831 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 832 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 833 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 834 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 835 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 836 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 837 hc32toh(sc, sitd->sitd_back), 838 hc32toh(sc, sitd->sitd_bp[0]), 839 hc32toh(sc, sitd->sitd_bp[1]), 840 hc32toh(sc, sitd->sitd_bp_hi[0]), 841 hc32toh(sc, sitd->sitd_bp_hi[1])); 842 } 843 844 static void 845 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 846 { 847 usb_pc_cpu_invalidate(itd->page_cache); 848 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 849 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 850 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 851 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 852 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 853 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 854 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 855 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 856 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 857 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 858 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 859 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 860 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 861 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 862 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 863 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 864 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 865 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 866 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 867 printf(" addr=0x%02x; endpt=0x%01x\n", 868 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 869 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 870 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 871 printf(" dir=%s; mpl=0x%02x\n", 872 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 873 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 874 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 875 hc32toh(sc, itd->itd_bp[2]), 876 hc32toh(sc, itd->itd_bp[3]), 877 hc32toh(sc, itd->itd_bp[4]), 878 hc32toh(sc, itd->itd_bp[5]), 879 hc32toh(sc, itd->itd_bp[6])); 880 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 881 " 0x%08x,0x%08x,0x%08x\n", 882 hc32toh(sc, itd->itd_bp_hi[0]), 883 hc32toh(sc, itd->itd_bp_hi[1]), 884 hc32toh(sc, itd->itd_bp_hi[2]), 885 hc32toh(sc, itd->itd_bp_hi[3]), 886 hc32toh(sc, itd->itd_bp_hi[4]), 887 hc32toh(sc, itd->itd_bp_hi[5]), 888 hc32toh(sc, itd->itd_bp_hi[6])); 889 } 890 891 static void 892 ehci_dump_isoc(ehci_softc_t *sc) 893 { 894 ehci_itd_t *itd; 895 ehci_sitd_t *sitd; 896 uint16_t max = 1000; 897 uint16_t pos; 898 899 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 900 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 901 902 printf("%s: isochronous dump from frame 0x%03x:\n", 903 __FUNCTION__, pos); 904 905 itd = sc->sc_isoc_hs_p_last[pos]; 906 sitd = sc->sc_isoc_fs_p_last[pos]; 907 908 while (itd && max && max--) { 909 ehci_dump_itd(sc, itd); 910 itd = itd->prev; 911 } 912 913 while (sitd && max && max--) { 914 ehci_dump_sitd(sc, sitd); 915 sitd = sitd->prev; 916 } 917 } 918 919 #endif 920 921 static void 922 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 923 { 924 /* check for early completion */ 925 if (ehci_check_transfer(xfer)) { 926 return; 927 } 928 /* put transfer on interrupt queue */ 929 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 930 931 /* start timeout, if any */ 932 if (xfer->timeout != 0) { 933 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 934 } 935 } 936 937 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 938 static ehci_sitd_t * 939 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 940 { 941 DPRINTFN(11, "%p to %p\n", std, last); 942 943 /* (sc->sc_bus.mtx) must be locked */ 944 945 std->next = last->next; 946 std->sitd_next = last->sitd_next; 947 948 std->prev = last; 949 950 usb_pc_cpu_flush(std->page_cache); 951 952 /* 953 * the last->next->prev is never followed: std->next->prev = std; 954 */ 955 last->next = std; 956 last->sitd_next = std->sitd_self; 957 958 usb_pc_cpu_flush(last->page_cache); 959 960 return (std); 961 } 962 963 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 964 static ehci_itd_t * 965 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 966 { 967 DPRINTFN(11, "%p to %p\n", std, last); 968 969 /* (sc->sc_bus.mtx) must be locked */ 970 971 std->next = last->next; 972 std->itd_next = last->itd_next; 973 974 std->prev = last; 975 976 usb_pc_cpu_flush(std->page_cache); 977 978 /* 979 * the last->next->prev is never followed: std->next->prev = std; 980 */ 981 last->next = std; 982 last->itd_next = std->itd_self; 983 984 usb_pc_cpu_flush(last->page_cache); 985 986 return (std); 987 } 988 989 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 990 static ehci_qh_t * 991 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 992 { 993 DPRINTFN(11, "%p to %p\n", sqh, last); 994 995 if (sqh->prev != NULL) { 996 /* should not happen */ 997 DPRINTFN(0, "QH already linked!\n"); 998 return (last); 999 } 1000 /* (sc->sc_bus.mtx) must be locked */ 1001 1002 sqh->next = last->next; 1003 sqh->qh_link = last->qh_link; 1004 1005 sqh->prev = last; 1006 1007 usb_pc_cpu_flush(sqh->page_cache); 1008 1009 /* 1010 * the last->next->prev is never followed: sqh->next->prev = sqh; 1011 */ 1012 1013 last->next = sqh; 1014 last->qh_link = sqh->qh_self; 1015 1016 usb_pc_cpu_flush(last->page_cache); 1017 1018 return (sqh); 1019 } 1020 1021 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1022 static ehci_sitd_t * 1023 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1024 { 1025 DPRINTFN(11, "%p from %p\n", std, last); 1026 1027 /* (sc->sc_bus.mtx) must be locked */ 1028 1029 std->prev->next = std->next; 1030 std->prev->sitd_next = std->sitd_next; 1031 1032 usb_pc_cpu_flush(std->prev->page_cache); 1033 1034 if (std->next) { 1035 std->next->prev = std->prev; 1036 usb_pc_cpu_flush(std->next->page_cache); 1037 } 1038 return ((last == std) ? std->prev : last); 1039 } 1040 1041 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1042 static ehci_itd_t * 1043 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1044 { 1045 DPRINTFN(11, "%p from %p\n", std, last); 1046 1047 /* (sc->sc_bus.mtx) must be locked */ 1048 1049 std->prev->next = std->next; 1050 std->prev->itd_next = std->itd_next; 1051 1052 usb_pc_cpu_flush(std->prev->page_cache); 1053 1054 if (std->next) { 1055 std->next->prev = std->prev; 1056 usb_pc_cpu_flush(std->next->page_cache); 1057 } 1058 return ((last == std) ? std->prev : last); 1059 } 1060 1061 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1062 static ehci_qh_t * 1063 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1064 { 1065 DPRINTFN(11, "%p from %p\n", sqh, last); 1066 1067 /* (sc->sc_bus.mtx) must be locked */ 1068 1069 /* only remove if not removed from a queue */ 1070 if (sqh->prev) { 1071 1072 sqh->prev->next = sqh->next; 1073 sqh->prev->qh_link = sqh->qh_link; 1074 1075 usb_pc_cpu_flush(sqh->prev->page_cache); 1076 1077 if (sqh->next) { 1078 sqh->next->prev = sqh->prev; 1079 usb_pc_cpu_flush(sqh->next->page_cache); 1080 } 1081 last = ((last == sqh) ? sqh->prev : last); 1082 1083 sqh->prev = 0; 1084 1085 usb_pc_cpu_flush(sqh->page_cache); 1086 } 1087 return (last); 1088 } 1089 1090 static void 1091 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1092 { 1093 uint16_t rem; 1094 uint8_t dt; 1095 1096 /* count number of full packets */ 1097 dt = (actlen / xfer->max_packet_size) & 1; 1098 1099 /* compute remainder */ 1100 rem = actlen % xfer->max_packet_size; 1101 1102 if (rem > 0) 1103 dt ^= 1; /* short packet at the end */ 1104 else if (actlen != xlen) 1105 dt ^= 1; /* zero length packet at the end */ 1106 else if (xlen == 0) 1107 dt ^= 1; /* zero length transfer */ 1108 1109 xfer->endpoint->toggle_next ^= dt; 1110 } 1111 1112 static usb_error_t 1113 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1114 { 1115 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1116 ehci_qtd_t *td; 1117 ehci_qtd_t *td_alt_next; 1118 uint32_t status; 1119 uint16_t len; 1120 1121 td = xfer->td_transfer_cache; 1122 td_alt_next = td->alt_next; 1123 1124 if (xfer->aframes != xfer->nframes) { 1125 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1126 } 1127 while (1) { 1128 1129 usb_pc_cpu_invalidate(td->page_cache); 1130 status = hc32toh(sc, td->qtd_status); 1131 1132 len = EHCI_QTD_GET_BYTES(status); 1133 1134 /* 1135 * Verify the status length and 1136 * add the length to "frlengths[]": 1137 */ 1138 if (len > td->len) { 1139 /* should not happen */ 1140 DPRINTF("Invalid status length, " 1141 "0x%04x/0x%04x bytes\n", len, td->len); 1142 status |= EHCI_QTD_HALTED; 1143 } else if (xfer->aframes != xfer->nframes) { 1144 xfer->frlengths[xfer->aframes] += td->len - len; 1145 /* manually update data toggle */ 1146 ehci_data_toggle_update(xfer, td->len - len, td->len); 1147 } 1148 1149 /* Check for last transfer */ 1150 if (((void *)td) == xfer->td_transfer_last) { 1151 td = NULL; 1152 break; 1153 } 1154 /* Check for transfer error */ 1155 if (status & EHCI_QTD_HALTED) { 1156 /* the transfer is finished */ 1157 td = NULL; 1158 break; 1159 } 1160 /* Check for short transfer */ 1161 if (len > 0) { 1162 if (xfer->flags_int.short_frames_ok) { 1163 /* follow alt next */ 1164 td = td->alt_next; 1165 } else { 1166 /* the transfer is finished */ 1167 td = NULL; 1168 } 1169 break; 1170 } 1171 td = td->obj_next; 1172 1173 if (td->alt_next != td_alt_next) { 1174 /* this USB frame is complete */ 1175 break; 1176 } 1177 } 1178 1179 /* update transfer cache */ 1180 1181 xfer->td_transfer_cache = td; 1182 1183 #ifdef USB_DEBUG 1184 if (status & EHCI_QTD_STATERRS) { 1185 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1186 "status=%s%s%s%s%s%s%s%s\n", 1187 xfer->address, xfer->endpointno, xfer->aframes, 1188 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1189 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1190 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1191 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1192 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1193 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1194 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1195 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1196 } 1197 #endif 1198 1199 return ((status & EHCI_QTD_HALTED) ? 1200 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1201 } 1202 1203 static void 1204 ehci_non_isoc_done(struct usb_xfer *xfer) 1205 { 1206 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1207 ehci_qh_t *qh; 1208 uint32_t status; 1209 usb_error_t err = 0; 1210 1211 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1212 xfer, xfer->endpoint); 1213 1214 #ifdef USB_DEBUG 1215 if (ehcidebug > 10) { 1216 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1217 1218 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1219 } 1220 #endif 1221 1222 /* extract data toggle directly from the QH's overlay area */ 1223 1224 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1225 1226 usb_pc_cpu_invalidate(qh->page_cache); 1227 1228 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1229 1230 /* reset scanner */ 1231 1232 xfer->td_transfer_cache = xfer->td_transfer_first; 1233 1234 if (xfer->flags_int.control_xfr) { 1235 1236 if (xfer->flags_int.control_hdr) { 1237 1238 err = ehci_non_isoc_done_sub(xfer); 1239 } 1240 xfer->aframes = 1; 1241 1242 if (xfer->td_transfer_cache == NULL) { 1243 goto done; 1244 } 1245 } 1246 while (xfer->aframes != xfer->nframes) { 1247 1248 err = ehci_non_isoc_done_sub(xfer); 1249 xfer->aframes++; 1250 1251 if (xfer->td_transfer_cache == NULL) { 1252 goto done; 1253 } 1254 } 1255 1256 if (xfer->flags_int.control_xfr && 1257 !xfer->flags_int.control_act) { 1258 1259 err = ehci_non_isoc_done_sub(xfer); 1260 } 1261 done: 1262 ehci_device_done(xfer, err); 1263 } 1264 1265 /*------------------------------------------------------------------------* 1266 * ehci_check_transfer 1267 * 1268 * Return values: 1269 * 0: USB transfer is not finished 1270 * Else: USB transfer is finished 1271 *------------------------------------------------------------------------*/ 1272 static uint8_t 1273 ehci_check_transfer(struct usb_xfer *xfer) 1274 { 1275 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1276 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1277 1278 uint32_t status; 1279 1280 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1281 1282 if (methods == &ehci_device_isoc_fs_methods) { 1283 ehci_sitd_t *td; 1284 1285 /* isochronous full speed transfer */ 1286 1287 td = xfer->td_transfer_last; 1288 usb_pc_cpu_invalidate(td->page_cache); 1289 status = hc32toh(sc, td->sitd_status); 1290 1291 /* also check if first is complete */ 1292 1293 td = xfer->td_transfer_first; 1294 usb_pc_cpu_invalidate(td->page_cache); 1295 status |= hc32toh(sc, td->sitd_status); 1296 1297 if (!(status & EHCI_SITD_ACTIVE)) { 1298 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1299 goto transferred; 1300 } 1301 } else if (methods == &ehci_device_isoc_hs_methods) { 1302 ehci_itd_t *td; 1303 1304 /* isochronous high speed transfer */ 1305 1306 /* check last transfer */ 1307 td = xfer->td_transfer_last; 1308 usb_pc_cpu_invalidate(td->page_cache); 1309 status = td->itd_status[0]; 1310 status |= td->itd_status[1]; 1311 status |= td->itd_status[2]; 1312 status |= td->itd_status[3]; 1313 status |= td->itd_status[4]; 1314 status |= td->itd_status[5]; 1315 status |= td->itd_status[6]; 1316 status |= td->itd_status[7]; 1317 1318 /* also check first transfer */ 1319 td = xfer->td_transfer_first; 1320 usb_pc_cpu_invalidate(td->page_cache); 1321 status |= td->itd_status[0]; 1322 status |= td->itd_status[1]; 1323 status |= td->itd_status[2]; 1324 status |= td->itd_status[3]; 1325 status |= td->itd_status[4]; 1326 status |= td->itd_status[5]; 1327 status |= td->itd_status[6]; 1328 status |= td->itd_status[7]; 1329 1330 /* if no transactions are active we continue */ 1331 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1332 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1333 goto transferred; 1334 } 1335 } else { 1336 ehci_qtd_t *td; 1337 ehci_qh_t *qh; 1338 1339 /* non-isochronous transfer */ 1340 1341 /* 1342 * check whether there is an error somewhere in the middle, 1343 * or whether there was a short packet (SPD and not ACTIVE) 1344 */ 1345 td = xfer->td_transfer_cache; 1346 1347 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1348 1349 usb_pc_cpu_invalidate(qh->page_cache); 1350 1351 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1352 if (status & EHCI_QTD_ACTIVE) { 1353 /* transfer is pending */ 1354 goto done; 1355 } 1356 1357 while (1) { 1358 usb_pc_cpu_invalidate(td->page_cache); 1359 status = hc32toh(sc, td->qtd_status); 1360 1361 /* 1362 * Check if there is an active TD which 1363 * indicates that the transfer isn't done. 1364 */ 1365 if (status & EHCI_QTD_ACTIVE) { 1366 /* update cache */ 1367 xfer->td_transfer_cache = td; 1368 goto done; 1369 } 1370 /* 1371 * last transfer descriptor makes the transfer done 1372 */ 1373 if (((void *)td) == xfer->td_transfer_last) { 1374 break; 1375 } 1376 /* 1377 * any kind of error makes the transfer done 1378 */ 1379 if (status & EHCI_QTD_HALTED) { 1380 break; 1381 } 1382 /* 1383 * if there is no alternate next transfer, a short 1384 * packet also makes the transfer done 1385 */ 1386 if (EHCI_QTD_GET_BYTES(status)) { 1387 if (xfer->flags_int.short_frames_ok) { 1388 /* follow alt next */ 1389 if (td->alt_next) { 1390 td = td->alt_next; 1391 continue; 1392 } 1393 } 1394 /* transfer is done */ 1395 break; 1396 } 1397 td = td->obj_next; 1398 } 1399 ehci_non_isoc_done(xfer); 1400 goto transferred; 1401 } 1402 1403 done: 1404 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1405 return (0); 1406 1407 transferred: 1408 return (1); 1409 } 1410 1411 static void 1412 ehci_pcd_enable(ehci_softc_t *sc) 1413 { 1414 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1415 1416 sc->sc_eintrs |= EHCI_STS_PCD; 1417 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1418 1419 /* acknowledge any PCD interrupt */ 1420 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1421 1422 ehci_root_intr(sc); 1423 } 1424 1425 static void 1426 ehci_interrupt_poll(ehci_softc_t *sc) 1427 { 1428 struct usb_xfer *xfer; 1429 1430 repeat: 1431 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1432 /* 1433 * check if transfer is transferred 1434 */ 1435 if (ehci_check_transfer(xfer)) { 1436 /* queue has been modified */ 1437 goto repeat; 1438 } 1439 } 1440 } 1441 1442 /* 1443 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1444 * writing back the qTD status, or miss signalling occasionally under 1445 * heavy load. If the host machine is too fast, we can miss 1446 * transaction completion - when we scan the active list the 1447 * transaction still seems to be active. This generally exhibits 1448 * itself as a umass stall that never recovers. 1449 * 1450 * We work around this behaviour by setting up this callback after any 1451 * softintr that completes with transactions still pending, giving us 1452 * another chance to check for completion after the writeback has 1453 * taken place. 1454 */ 1455 static void 1456 ehci_poll_timeout(void *arg) 1457 { 1458 ehci_softc_t *sc = arg; 1459 1460 DPRINTFN(3, "\n"); 1461 ehci_interrupt_poll(sc); 1462 } 1463 1464 /*------------------------------------------------------------------------* 1465 * ehci_interrupt - EHCI interrupt handler 1466 * 1467 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1468 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1469 * is present ! 1470 *------------------------------------------------------------------------*/ 1471 void 1472 ehci_interrupt(ehci_softc_t *sc) 1473 { 1474 uint32_t status; 1475 1476 USB_BUS_LOCK(&sc->sc_bus); 1477 1478 DPRINTFN(16, "real interrupt\n"); 1479 1480 #ifdef USB_DEBUG 1481 if (ehcidebug > 15) { 1482 ehci_dump_regs(sc); 1483 } 1484 #endif 1485 1486 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1487 if (status == 0) { 1488 /* the interrupt was not for us */ 1489 goto done; 1490 } 1491 if (!(status & sc->sc_eintrs)) { 1492 goto done; 1493 } 1494 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1495 1496 status &= sc->sc_eintrs; 1497 1498 if (status & EHCI_STS_HSE) { 1499 printf("%s: unrecoverable error, " 1500 "controller halted\n", __FUNCTION__); 1501 #ifdef USB_DEBUG 1502 ehci_dump_regs(sc); 1503 ehci_dump_isoc(sc); 1504 #endif 1505 } 1506 if (status & EHCI_STS_PCD) { 1507 /* 1508 * Disable PCD interrupt for now, because it will be 1509 * on until the port has been reset. 1510 */ 1511 sc->sc_eintrs &= ~EHCI_STS_PCD; 1512 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1513 1514 ehci_root_intr(sc); 1515 1516 /* do not allow RHSC interrupts > 1 per second */ 1517 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1518 (void *)&ehci_pcd_enable, sc); 1519 } 1520 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1521 1522 if (status != 0) { 1523 /* block unprocessed interrupts */ 1524 sc->sc_eintrs &= ~status; 1525 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1526 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1527 } 1528 /* poll all the USB transfers */ 1529 ehci_interrupt_poll(sc); 1530 1531 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1532 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1533 (void *)&ehci_poll_timeout, sc); 1534 } 1535 1536 done: 1537 USB_BUS_UNLOCK(&sc->sc_bus); 1538 } 1539 1540 /* 1541 * called when a request does not complete 1542 */ 1543 static void 1544 ehci_timeout(void *arg) 1545 { 1546 struct usb_xfer *xfer = arg; 1547 1548 DPRINTF("xfer=%p\n", xfer); 1549 1550 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1551 1552 /* transfer is transferred */ 1553 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1554 } 1555 1556 static void 1557 ehci_do_poll(struct usb_bus *bus) 1558 { 1559 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1560 1561 USB_BUS_LOCK(&sc->sc_bus); 1562 ehci_interrupt_poll(sc); 1563 USB_BUS_UNLOCK(&sc->sc_bus); 1564 } 1565 1566 static void 1567 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1568 { 1569 struct usb_page_search buf_res; 1570 ehci_qtd_t *td; 1571 ehci_qtd_t *td_next; 1572 ehci_qtd_t *td_alt_next; 1573 uint32_t buf_offset; 1574 uint32_t average; 1575 uint32_t len_old; 1576 uint32_t terminate; 1577 uint32_t qtd_altnext; 1578 uint8_t shortpkt_old; 1579 uint8_t precompute; 1580 1581 terminate = temp->sc->sc_terminate_self; 1582 qtd_altnext = temp->sc->sc_terminate_self; 1583 td_alt_next = NULL; 1584 buf_offset = 0; 1585 shortpkt_old = temp->shortpkt; 1586 len_old = temp->len; 1587 precompute = 1; 1588 1589 restart: 1590 1591 td = temp->td; 1592 td_next = temp->td_next; 1593 1594 while (1) { 1595 1596 if (temp->len == 0) { 1597 1598 if (temp->shortpkt) { 1599 break; 1600 } 1601 /* send a Zero Length Packet, ZLP, last */ 1602 1603 temp->shortpkt = 1; 1604 average = 0; 1605 1606 } else { 1607 1608 average = temp->average; 1609 1610 if (temp->len < average) { 1611 if (temp->len % temp->max_frame_size) { 1612 temp->shortpkt = 1; 1613 } 1614 average = temp->len; 1615 } 1616 } 1617 1618 if (td_next == NULL) { 1619 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1620 } 1621 /* get next TD */ 1622 1623 td = td_next; 1624 td_next = td->obj_next; 1625 1626 /* check if we are pre-computing */ 1627 1628 if (precompute) { 1629 1630 /* update remaining length */ 1631 1632 temp->len -= average; 1633 1634 continue; 1635 } 1636 /* fill out current TD */ 1637 1638 td->qtd_status = 1639 temp->qtd_status | 1640 htohc32(temp->sc, EHCI_QTD_IOC | 1641 EHCI_QTD_SET_BYTES(average)); 1642 1643 if (average == 0) { 1644 1645 if (temp->auto_data_toggle == 0) { 1646 1647 /* update data toggle, ZLP case */ 1648 1649 temp->qtd_status ^= 1650 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1651 } 1652 td->len = 0; 1653 1654 td->qtd_buffer[0] = 0; 1655 td->qtd_buffer_hi[0] = 0; 1656 1657 td->qtd_buffer[1] = 0; 1658 td->qtd_buffer_hi[1] = 0; 1659 1660 } else { 1661 1662 uint8_t x; 1663 1664 if (temp->auto_data_toggle == 0) { 1665 1666 /* update data toggle */ 1667 1668 if (((average + temp->max_frame_size - 1) / 1669 temp->max_frame_size) & 1) { 1670 temp->qtd_status ^= 1671 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1672 } 1673 } 1674 td->len = average; 1675 1676 /* update remaining length */ 1677 1678 temp->len -= average; 1679 1680 /* fill out buffer pointers */ 1681 1682 usbd_get_page(temp->pc, buf_offset, &buf_res); 1683 td->qtd_buffer[0] = 1684 htohc32(temp->sc, buf_res.physaddr); 1685 td->qtd_buffer_hi[0] = 0; 1686 1687 x = 1; 1688 1689 while (average > EHCI_PAGE_SIZE) { 1690 average -= EHCI_PAGE_SIZE; 1691 buf_offset += EHCI_PAGE_SIZE; 1692 usbd_get_page(temp->pc, buf_offset, &buf_res); 1693 td->qtd_buffer[x] = 1694 htohc32(temp->sc, 1695 buf_res.physaddr & (~0xFFF)); 1696 td->qtd_buffer_hi[x] = 0; 1697 x++; 1698 } 1699 1700 /* 1701 * NOTE: The "average" variable is never zero after 1702 * exiting the loop above ! 1703 * 1704 * NOTE: We have to subtract one from the offset to 1705 * ensure that we are computing the physical address 1706 * of a valid page ! 1707 */ 1708 buf_offset += average; 1709 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1710 td->qtd_buffer[x] = 1711 htohc32(temp->sc, 1712 buf_res.physaddr & (~0xFFF)); 1713 td->qtd_buffer_hi[x] = 0; 1714 } 1715 1716 if (td_next) { 1717 /* link the current TD with the next one */ 1718 td->qtd_next = td_next->qtd_self; 1719 } 1720 td->qtd_altnext = qtd_altnext; 1721 td->alt_next = td_alt_next; 1722 1723 usb_pc_cpu_flush(td->page_cache); 1724 } 1725 1726 if (precompute) { 1727 precompute = 0; 1728 1729 /* setup alt next pointer, if any */ 1730 if (temp->last_frame) { 1731 td_alt_next = NULL; 1732 qtd_altnext = terminate; 1733 } else { 1734 /* we use this field internally */ 1735 td_alt_next = td_next; 1736 if (temp->setup_alt_next) { 1737 qtd_altnext = td_next->qtd_self; 1738 } else { 1739 qtd_altnext = terminate; 1740 } 1741 } 1742 1743 /* restore */ 1744 temp->shortpkt = shortpkt_old; 1745 temp->len = len_old; 1746 goto restart; 1747 } 1748 temp->td = td; 1749 temp->td_next = td_next; 1750 } 1751 1752 static void 1753 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1754 { 1755 struct ehci_std_temp temp; 1756 struct usb_pipe_methods *methods; 1757 ehci_qh_t *qh; 1758 ehci_qtd_t *td; 1759 uint32_t qh_endp; 1760 uint32_t qh_endphub; 1761 uint32_t x; 1762 1763 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1764 xfer->address, UE_GET_ADDR(xfer->endpointno), 1765 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1766 1767 temp.average = xfer->max_hc_frame_size; 1768 temp.max_frame_size = xfer->max_frame_size; 1769 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1770 1771 /* toggle the DMA set we are using */ 1772 xfer->flags_int.curr_dma_set ^= 1; 1773 1774 /* get next DMA set */ 1775 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1776 1777 xfer->td_transfer_first = td; 1778 xfer->td_transfer_cache = td; 1779 1780 temp.td = NULL; 1781 temp.td_next = td; 1782 temp.qtd_status = 0; 1783 temp.last_frame = 0; 1784 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1785 1786 if (xfer->flags_int.control_xfr) { 1787 if (xfer->endpoint->toggle_next) { 1788 /* DATA1 is next */ 1789 temp.qtd_status |= 1790 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1791 } 1792 temp.auto_data_toggle = 0; 1793 } else { 1794 temp.auto_data_toggle = 1; 1795 } 1796 1797 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1798 (xfer->xroot->udev->address != 0)) { 1799 /* max 3 retries */ 1800 temp.qtd_status |= 1801 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1802 } 1803 /* check if we should prepend a setup message */ 1804 1805 if (xfer->flags_int.control_xfr) { 1806 if (xfer->flags_int.control_hdr) { 1807 1808 xfer->endpoint->toggle_next = 0; 1809 1810 temp.qtd_status &= 1811 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1812 temp.qtd_status |= htohc32(temp.sc, 1813 EHCI_QTD_ACTIVE | 1814 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1815 EHCI_QTD_SET_TOGGLE(0)); 1816 1817 temp.len = xfer->frlengths[0]; 1818 temp.pc = xfer->frbuffers + 0; 1819 temp.shortpkt = temp.len ? 1 : 0; 1820 /* check for last frame */ 1821 if (xfer->nframes == 1) { 1822 /* no STATUS stage yet, SETUP is last */ 1823 if (xfer->flags_int.control_act) { 1824 temp.last_frame = 1; 1825 temp.setup_alt_next = 0; 1826 } 1827 } 1828 ehci_setup_standard_chain_sub(&temp); 1829 } 1830 x = 1; 1831 } else { 1832 x = 0; 1833 } 1834 1835 while (x != xfer->nframes) { 1836 1837 /* DATA0 / DATA1 message */ 1838 1839 temp.len = xfer->frlengths[x]; 1840 temp.pc = xfer->frbuffers + x; 1841 1842 x++; 1843 1844 if (x == xfer->nframes) { 1845 if (xfer->flags_int.control_xfr) { 1846 /* no STATUS stage yet, DATA is last */ 1847 if (xfer->flags_int.control_act) { 1848 temp.last_frame = 1; 1849 temp.setup_alt_next = 0; 1850 } 1851 } else { 1852 temp.last_frame = 1; 1853 temp.setup_alt_next = 0; 1854 } 1855 } 1856 /* keep previous data toggle and error count */ 1857 1858 temp.qtd_status &= 1859 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1860 EHCI_QTD_SET_TOGGLE(1)); 1861 1862 if (temp.len == 0) { 1863 1864 /* make sure that we send an USB packet */ 1865 1866 temp.shortpkt = 0; 1867 1868 } else { 1869 1870 /* regular data transfer */ 1871 1872 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1873 } 1874 1875 /* set endpoint direction */ 1876 1877 temp.qtd_status |= 1878 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1879 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1880 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1881 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1882 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1883 1884 ehci_setup_standard_chain_sub(&temp); 1885 } 1886 1887 /* check if we should append a status stage */ 1888 1889 if (xfer->flags_int.control_xfr && 1890 !xfer->flags_int.control_act) { 1891 1892 /* 1893 * Send a DATA1 message and invert the current endpoint 1894 * direction. 1895 */ 1896 1897 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1898 EHCI_QTD_SET_TOGGLE(1)); 1899 temp.qtd_status |= 1900 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1901 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1902 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1903 EHCI_QTD_SET_TOGGLE(1)) : 1904 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1905 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1906 EHCI_QTD_SET_TOGGLE(1)); 1907 1908 temp.len = 0; 1909 temp.pc = NULL; 1910 temp.shortpkt = 0; 1911 temp.last_frame = 1; 1912 temp.setup_alt_next = 0; 1913 1914 ehci_setup_standard_chain_sub(&temp); 1915 } 1916 td = temp.td; 1917 1918 /* the last TD terminates the transfer: */ 1919 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1920 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1921 1922 usb_pc_cpu_flush(td->page_cache); 1923 1924 /* must have at least one frame! */ 1925 1926 xfer->td_transfer_last = td; 1927 1928 #ifdef USB_DEBUG 1929 if (ehcidebug > 8) { 1930 DPRINTF("nexttog=%d; data before transfer:\n", 1931 xfer->endpoint->toggle_next); 1932 ehci_dump_sqtds(temp.sc, 1933 xfer->td_transfer_first); 1934 } 1935 #endif 1936 1937 methods = xfer->endpoint->methods; 1938 1939 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1940 1941 /* the "qh_link" field is filled when the QH is added */ 1942 1943 qh_endp = 1944 (EHCI_QH_SET_ADDR(xfer->address) | 1945 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1946 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1947 1948 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1949 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1950 if (methods != &ehci_device_intr_methods) 1951 qh_endp |= EHCI_QH_SET_NRL(8); 1952 } else { 1953 1954 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1955 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1956 } else { 1957 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1958 } 1959 1960 if (methods == &ehci_device_ctrl_methods) { 1961 qh_endp |= EHCI_QH_CTL; 1962 } 1963 if (methods != &ehci_device_intr_methods) { 1964 /* Only try one time per microframe! */ 1965 qh_endp |= EHCI_QH_SET_NRL(1); 1966 } 1967 } 1968 1969 if (temp.auto_data_toggle == 0) { 1970 /* software computes the data toggle */ 1971 qh_endp |= EHCI_QH_DTC; 1972 } 1973 1974 qh->qh_endp = htohc32(temp.sc, qh_endp); 1975 1976 qh_endphub = 1977 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1978 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1979 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1980 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1981 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1982 1983 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1984 qh->qh_curqtd = 0; 1985 1986 /* fill the overlay qTD */ 1987 1988 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1989 /* DATA1 is next */ 1990 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1991 } else { 1992 qh->qh_qtd.qtd_status = 0; 1993 } 1994 1995 td = xfer->td_transfer_first; 1996 1997 qh->qh_qtd.qtd_next = td->qtd_self; 1998 qh->qh_qtd.qtd_altnext = 1999 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2000 2001 usb_pc_cpu_flush(qh->page_cache); 2002 2003 if (xfer->xroot->udev->flags.self_suspended == 0) { 2004 EHCI_APPEND_QH(qh, *qh_last); 2005 } 2006 } 2007 2008 static void 2009 ehci_root_intr(ehci_softc_t *sc) 2010 { 2011 uint16_t i; 2012 uint16_t m; 2013 2014 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2015 2016 /* clear any old interrupt data */ 2017 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2018 2019 /* set bits */ 2020 m = (sc->sc_noport + 1); 2021 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2022 m = (8 * sizeof(sc->sc_hub_idata)); 2023 } 2024 for (i = 1; i < m; i++) { 2025 /* pick out CHANGE bits from the status register */ 2026 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2027 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2028 DPRINTF("port %d changed\n", i); 2029 } 2030 } 2031 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2032 sizeof(sc->sc_hub_idata)); 2033 } 2034 2035 static void 2036 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2037 { 2038 uint32_t nframes = xfer->nframes; 2039 uint32_t status; 2040 uint32_t *plen = xfer->frlengths; 2041 uint16_t len = 0; 2042 ehci_sitd_t *td = xfer->td_transfer_first; 2043 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2044 2045 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2046 xfer, xfer->endpoint); 2047 2048 while (nframes--) { 2049 if (td == NULL) { 2050 panic("%s:%d: out of TD's\n", 2051 __FUNCTION__, __LINE__); 2052 } 2053 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2054 pp_last = &sc->sc_isoc_fs_p_last[0]; 2055 } 2056 #ifdef USB_DEBUG 2057 if (ehcidebug > 15) { 2058 DPRINTF("isoc FS-TD\n"); 2059 ehci_dump_sitd(sc, td); 2060 } 2061 #endif 2062 usb_pc_cpu_invalidate(td->page_cache); 2063 status = hc32toh(sc, td->sitd_status); 2064 2065 len = EHCI_SITD_GET_LEN(status); 2066 2067 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2068 2069 if (*plen >= len) { 2070 len = *plen - len; 2071 } else { 2072 len = 0; 2073 } 2074 2075 *plen = len; 2076 2077 /* remove FS-TD from schedule */ 2078 EHCI_REMOVE_FS_TD(td, *pp_last); 2079 2080 pp_last++; 2081 plen++; 2082 td = td->obj_next; 2083 } 2084 2085 xfer->aframes = xfer->nframes; 2086 } 2087 2088 static void 2089 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2090 { 2091 uint32_t nframes = xfer->nframes; 2092 uint32_t status; 2093 uint32_t *plen = xfer->frlengths; 2094 uint16_t len = 0; 2095 uint8_t td_no = 0; 2096 ehci_itd_t *td = xfer->td_transfer_first; 2097 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2098 2099 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2100 xfer, xfer->endpoint); 2101 2102 while (nframes) { 2103 if (td == NULL) { 2104 panic("%s:%d: out of TD's\n", 2105 __FUNCTION__, __LINE__); 2106 } 2107 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2108 pp_last = &sc->sc_isoc_hs_p_last[0]; 2109 } 2110 #ifdef USB_DEBUG 2111 if (ehcidebug > 15) { 2112 DPRINTF("isoc HS-TD\n"); 2113 ehci_dump_itd(sc, td); 2114 } 2115 #endif 2116 2117 usb_pc_cpu_invalidate(td->page_cache); 2118 status = hc32toh(sc, td->itd_status[td_no]); 2119 2120 len = EHCI_ITD_GET_LEN(status); 2121 2122 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2123 2124 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2125 2126 if (*plen >= len) { 2127 /* 2128 * The length is valid. NOTE: The 2129 * complete length is written back 2130 * into the status field, and not the 2131 * remainder like with other transfer 2132 * descriptor types. 2133 */ 2134 } else { 2135 /* Invalid length - truncate */ 2136 len = 0; 2137 } 2138 2139 *plen = len; 2140 plen++; 2141 nframes--; 2142 } 2143 2144 td_no++; 2145 2146 if ((td_no == 8) || (nframes == 0)) { 2147 /* remove HS-TD from schedule */ 2148 EHCI_REMOVE_HS_TD(td, *pp_last); 2149 pp_last++; 2150 2151 td_no = 0; 2152 td = td->obj_next; 2153 } 2154 } 2155 xfer->aframes = xfer->nframes; 2156 } 2157 2158 /* NOTE: "done" can be run two times in a row, 2159 * from close and from interrupt 2160 */ 2161 static void 2162 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2163 { 2164 struct usb_pipe_methods *methods = xfer->endpoint->methods; 2165 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2166 2167 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2168 2169 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2170 xfer, xfer->endpoint, error); 2171 2172 if ((methods == &ehci_device_bulk_methods) || 2173 (methods == &ehci_device_ctrl_methods)) { 2174 #ifdef USB_DEBUG 2175 if (ehcidebug > 8) { 2176 DPRINTF("nexttog=%d; data after transfer:\n", 2177 xfer->endpoint->toggle_next); 2178 ehci_dump_sqtds(sc, 2179 xfer->td_transfer_first); 2180 } 2181 #endif 2182 2183 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2184 sc->sc_async_p_last); 2185 } 2186 if (methods == &ehci_device_intr_methods) { 2187 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2188 sc->sc_intr_p_last[xfer->qh_pos]); 2189 } 2190 /* 2191 * Only finish isochronous transfers once which will update 2192 * "xfer->frlengths". 2193 */ 2194 if (xfer->td_transfer_first && 2195 xfer->td_transfer_last) { 2196 if (methods == &ehci_device_isoc_fs_methods) { 2197 ehci_isoc_fs_done(sc, xfer); 2198 } 2199 if (methods == &ehci_device_isoc_hs_methods) { 2200 ehci_isoc_hs_done(sc, xfer); 2201 } 2202 xfer->td_transfer_first = NULL; 2203 xfer->td_transfer_last = NULL; 2204 } 2205 /* dequeue transfer and start next transfer */ 2206 usbd_transfer_done(xfer, error); 2207 } 2208 2209 /*------------------------------------------------------------------------* 2210 * ehci bulk support 2211 *------------------------------------------------------------------------*/ 2212 static void 2213 ehci_device_bulk_open(struct usb_xfer *xfer) 2214 { 2215 return; 2216 } 2217 2218 static void 2219 ehci_device_bulk_close(struct usb_xfer *xfer) 2220 { 2221 ehci_device_done(xfer, USB_ERR_CANCELLED); 2222 } 2223 2224 static void 2225 ehci_device_bulk_enter(struct usb_xfer *xfer) 2226 { 2227 return; 2228 } 2229 2230 static void 2231 ehci_device_bulk_start(struct usb_xfer *xfer) 2232 { 2233 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2234 uint32_t temp; 2235 2236 /* setup TD's and QH */ 2237 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2238 2239 /* put transfer on interrupt queue */ 2240 ehci_transfer_intr_enqueue(xfer); 2241 2242 /* 2243 * XXX Certain nVidia chipsets choke when using the IAAD 2244 * feature too frequently. 2245 */ 2246 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2247 return; 2248 2249 /* XXX Performance quirk: Some Host Controllers have a too low 2250 * interrupt rate. Issue an IAAD to stimulate the Host 2251 * Controller after queueing the BULK transfer. 2252 */ 2253 temp = EOREAD4(sc, EHCI_USBCMD); 2254 if (!(temp & EHCI_CMD_IAAD)) 2255 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2256 } 2257 2258 struct usb_pipe_methods ehci_device_bulk_methods = 2259 { 2260 .open = ehci_device_bulk_open, 2261 .close = ehci_device_bulk_close, 2262 .enter = ehci_device_bulk_enter, 2263 .start = ehci_device_bulk_start, 2264 }; 2265 2266 /*------------------------------------------------------------------------* 2267 * ehci control support 2268 *------------------------------------------------------------------------*/ 2269 static void 2270 ehci_device_ctrl_open(struct usb_xfer *xfer) 2271 { 2272 return; 2273 } 2274 2275 static void 2276 ehci_device_ctrl_close(struct usb_xfer *xfer) 2277 { 2278 ehci_device_done(xfer, USB_ERR_CANCELLED); 2279 } 2280 2281 static void 2282 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2283 { 2284 return; 2285 } 2286 2287 static void 2288 ehci_device_ctrl_start(struct usb_xfer *xfer) 2289 { 2290 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2291 2292 /* setup TD's and QH */ 2293 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2294 2295 /* put transfer on interrupt queue */ 2296 ehci_transfer_intr_enqueue(xfer); 2297 } 2298 2299 struct usb_pipe_methods ehci_device_ctrl_methods = 2300 { 2301 .open = ehci_device_ctrl_open, 2302 .close = ehci_device_ctrl_close, 2303 .enter = ehci_device_ctrl_enter, 2304 .start = ehci_device_ctrl_start, 2305 }; 2306 2307 /*------------------------------------------------------------------------* 2308 * ehci interrupt support 2309 *------------------------------------------------------------------------*/ 2310 static void 2311 ehci_device_intr_open(struct usb_xfer *xfer) 2312 { 2313 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2314 uint16_t best; 2315 uint16_t bit; 2316 uint16_t x; 2317 2318 usb_hs_bandwidth_alloc(xfer); 2319 2320 /* 2321 * Find the best QH position corresponding to the given interval: 2322 */ 2323 2324 best = 0; 2325 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2326 while (bit) { 2327 if (xfer->interval >= bit) { 2328 x = bit; 2329 best = bit; 2330 while (x & bit) { 2331 if (sc->sc_intr_stat[x] < 2332 sc->sc_intr_stat[best]) { 2333 best = x; 2334 } 2335 x++; 2336 } 2337 break; 2338 } 2339 bit >>= 1; 2340 } 2341 2342 sc->sc_intr_stat[best]++; 2343 xfer->qh_pos = best; 2344 2345 DPRINTFN(3, "best=%d interval=%d\n", 2346 best, xfer->interval); 2347 } 2348 2349 static void 2350 ehci_device_intr_close(struct usb_xfer *xfer) 2351 { 2352 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2353 2354 sc->sc_intr_stat[xfer->qh_pos]--; 2355 2356 ehci_device_done(xfer, USB_ERR_CANCELLED); 2357 2358 /* bandwidth must be freed after device done */ 2359 usb_hs_bandwidth_free(xfer); 2360 } 2361 2362 static void 2363 ehci_device_intr_enter(struct usb_xfer *xfer) 2364 { 2365 return; 2366 } 2367 2368 static void 2369 ehci_device_intr_start(struct usb_xfer *xfer) 2370 { 2371 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2372 2373 /* setup TD's and QH */ 2374 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2375 2376 /* put transfer on interrupt queue */ 2377 ehci_transfer_intr_enqueue(xfer); 2378 } 2379 2380 struct usb_pipe_methods ehci_device_intr_methods = 2381 { 2382 .open = ehci_device_intr_open, 2383 .close = ehci_device_intr_close, 2384 .enter = ehci_device_intr_enter, 2385 .start = ehci_device_intr_start, 2386 }; 2387 2388 /*------------------------------------------------------------------------* 2389 * ehci full speed isochronous support 2390 *------------------------------------------------------------------------*/ 2391 static void 2392 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2393 { 2394 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2395 ehci_sitd_t *td; 2396 uint32_t sitd_portaddr; 2397 uint8_t ds; 2398 2399 sitd_portaddr = 2400 EHCI_SITD_SET_ADDR(xfer->address) | 2401 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2402 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2403 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2404 2405 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2406 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2407 2408 sitd_portaddr = htohc32(sc, sitd_portaddr); 2409 2410 /* initialize all TD's */ 2411 2412 for (ds = 0; ds != 2; ds++) { 2413 2414 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2415 2416 td->sitd_portaddr = sitd_portaddr; 2417 2418 /* 2419 * TODO: make some kind of automatic 2420 * SMASK/CMASK selection based on micro-frame 2421 * usage 2422 * 2423 * micro-frame usage (8 microframes per 1ms) 2424 */ 2425 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2426 2427 usb_pc_cpu_flush(td->page_cache); 2428 } 2429 } 2430 } 2431 2432 static void 2433 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2434 { 2435 ehci_device_done(xfer, USB_ERR_CANCELLED); 2436 } 2437 2438 static void 2439 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2440 { 2441 struct usb_page_search buf_res; 2442 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2443 ehci_sitd_t *td; 2444 ehci_sitd_t *td_last = NULL; 2445 ehci_sitd_t **pp_last; 2446 uint32_t *plen; 2447 uint32_t buf_offset; 2448 uint32_t nframes; 2449 uint32_t temp; 2450 uint32_t sitd_mask; 2451 uint16_t tlen; 2452 uint8_t sa; 2453 uint8_t sb; 2454 2455 #ifdef USB_DEBUG 2456 uint8_t once = 1; 2457 2458 #endif 2459 2460 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2461 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2462 2463 /* get the current frame index */ 2464 2465 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2466 2467 /* 2468 * check if the frame index is within the window where the frames 2469 * will be inserted 2470 */ 2471 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2472 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2473 2474 if ((xfer->endpoint->is_synced == 0) || 2475 (buf_offset < xfer->nframes)) { 2476 /* 2477 * If there is data underflow or the pipe queue is empty we 2478 * schedule the transfer a few frames ahead of the current 2479 * frame position. Else two isochronous transfers might 2480 * overlap. 2481 */ 2482 xfer->endpoint->isoc_next = (nframes + 3) & 2483 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2484 xfer->endpoint->is_synced = 1; 2485 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2486 } 2487 /* 2488 * compute how many milliseconds the insertion is ahead of the 2489 * current frame position: 2490 */ 2491 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2492 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2493 2494 /* 2495 * pre-compute when the isochronous transfer will be finished: 2496 */ 2497 xfer->isoc_time_complete = 2498 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2499 buf_offset + xfer->nframes; 2500 2501 /* get the real number of frames */ 2502 2503 nframes = xfer->nframes; 2504 2505 buf_offset = 0; 2506 2507 plen = xfer->frlengths; 2508 2509 /* toggle the DMA set we are using */ 2510 xfer->flags_int.curr_dma_set ^= 1; 2511 2512 /* get next DMA set */ 2513 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2514 xfer->td_transfer_first = td; 2515 2516 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2517 2518 /* store starting position */ 2519 2520 xfer->qh_pos = xfer->endpoint->isoc_next; 2521 2522 while (nframes--) { 2523 if (td == NULL) { 2524 panic("%s:%d: out of TD's\n", 2525 __FUNCTION__, __LINE__); 2526 } 2527 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2528 pp_last = &sc->sc_isoc_fs_p_last[0]; 2529 2530 /* reuse sitd_portaddr and sitd_back from last transfer */ 2531 2532 if (*plen > xfer->max_frame_size) { 2533 #ifdef USB_DEBUG 2534 if (once) { 2535 once = 0; 2536 printf("%s: frame length(%d) exceeds %d " 2537 "bytes (frame truncated)\n", 2538 __FUNCTION__, *plen, 2539 xfer->max_frame_size); 2540 } 2541 #endif 2542 *plen = xfer->max_frame_size; 2543 } 2544 2545 /* allocate a slot */ 2546 2547 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2548 xfer->isoc_time_complete - nframes - 1); 2549 2550 if (sa == 255) { 2551 /* 2552 * Schedule is FULL, set length to zero: 2553 */ 2554 2555 *plen = 0; 2556 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2557 } 2558 if (*plen) { 2559 /* 2560 * only call "usbd_get_page()" when we have a 2561 * non-zero length 2562 */ 2563 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2564 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2565 buf_offset += *plen; 2566 /* 2567 * NOTE: We need to subtract one from the offset so 2568 * that we are on a valid page! 2569 */ 2570 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2571 &buf_res); 2572 temp = buf_res.physaddr & ~0xFFF; 2573 } else { 2574 td->sitd_bp[0] = 0; 2575 temp = 0; 2576 } 2577 2578 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2579 tlen = *plen; 2580 if (tlen <= 188) { 2581 temp |= 1; /* T-count = 1, TP = ALL */ 2582 tlen = 1; 2583 } else { 2584 tlen += 187; 2585 tlen /= 188; 2586 temp |= tlen; /* T-count = [1..6] */ 2587 temp |= 8; /* TP = Begin */ 2588 } 2589 2590 tlen += sa; 2591 2592 if (tlen >= 8) { 2593 sb = 0; 2594 } else { 2595 sb = (1 << tlen); 2596 } 2597 2598 sa = (1 << sa); 2599 sa = (sb - sa) & 0x3F; 2600 sb = 0; 2601 } else { 2602 sb = (-(4 << sa)) & 0xFE; 2603 sa = (1 << sa) & 0x3F; 2604 } 2605 2606 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2607 EHCI_SITD_SET_CMASK(sb)); 2608 2609 td->sitd_bp[1] = htohc32(sc, temp); 2610 2611 td->sitd_mask = htohc32(sc, sitd_mask); 2612 2613 if (nframes == 0) { 2614 td->sitd_status = htohc32(sc, 2615 EHCI_SITD_IOC | 2616 EHCI_SITD_ACTIVE | 2617 EHCI_SITD_SET_LEN(*plen)); 2618 } else { 2619 td->sitd_status = htohc32(sc, 2620 EHCI_SITD_ACTIVE | 2621 EHCI_SITD_SET_LEN(*plen)); 2622 } 2623 usb_pc_cpu_flush(td->page_cache); 2624 2625 #ifdef USB_DEBUG 2626 if (ehcidebug > 15) { 2627 DPRINTF("FS-TD %d\n", nframes); 2628 ehci_dump_sitd(sc, td); 2629 } 2630 #endif 2631 /* insert TD into schedule */ 2632 EHCI_APPEND_FS_TD(td, *pp_last); 2633 pp_last++; 2634 2635 plen++; 2636 td_last = td; 2637 td = td->obj_next; 2638 } 2639 2640 xfer->td_transfer_last = td_last; 2641 2642 /* update isoc_next */ 2643 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2644 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2645 2646 /* 2647 * We don't allow cancelling of the SPLIT transaction USB FULL 2648 * speed transfer, because it disturbs the bandwidth 2649 * computation algorithm. 2650 */ 2651 xfer->flags_int.can_cancel_immed = 0; 2652 } 2653 2654 static void 2655 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2656 { 2657 /* 2658 * We don't allow cancelling of the SPLIT transaction USB FULL 2659 * speed transfer, because it disturbs the bandwidth 2660 * computation algorithm. 2661 */ 2662 xfer->flags_int.can_cancel_immed = 0; 2663 2664 /* set a default timeout */ 2665 if (xfer->timeout == 0) 2666 xfer->timeout = 500; /* ms */ 2667 2668 /* put transfer on interrupt queue */ 2669 ehci_transfer_intr_enqueue(xfer); 2670 } 2671 2672 struct usb_pipe_methods ehci_device_isoc_fs_methods = 2673 { 2674 .open = ehci_device_isoc_fs_open, 2675 .close = ehci_device_isoc_fs_close, 2676 .enter = ehci_device_isoc_fs_enter, 2677 .start = ehci_device_isoc_fs_start, 2678 }; 2679 2680 /*------------------------------------------------------------------------* 2681 * ehci high speed isochronous support 2682 *------------------------------------------------------------------------*/ 2683 static void 2684 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2685 { 2686 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2687 ehci_itd_t *td; 2688 uint32_t temp; 2689 uint8_t ds; 2690 2691 usb_hs_bandwidth_alloc(xfer); 2692 2693 /* initialize all TD's */ 2694 2695 for (ds = 0; ds != 2; ds++) { 2696 2697 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2698 2699 /* set TD inactive */ 2700 td->itd_status[0] = 0; 2701 td->itd_status[1] = 0; 2702 td->itd_status[2] = 0; 2703 td->itd_status[3] = 0; 2704 td->itd_status[4] = 0; 2705 td->itd_status[5] = 0; 2706 td->itd_status[6] = 0; 2707 td->itd_status[7] = 0; 2708 2709 /* set endpoint and address */ 2710 td->itd_bp[0] = htohc32(sc, 2711 EHCI_ITD_SET_ADDR(xfer->address) | 2712 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2713 2714 temp = 2715 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2716 2717 /* set direction */ 2718 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2719 temp |= EHCI_ITD_SET_DIR_IN; 2720 } 2721 /* set maximum packet size */ 2722 td->itd_bp[1] = htohc32(sc, temp); 2723 2724 /* set transfer multiplier */ 2725 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2726 2727 usb_pc_cpu_flush(td->page_cache); 2728 } 2729 } 2730 } 2731 2732 static void 2733 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2734 { 2735 ehci_device_done(xfer, USB_ERR_CANCELLED); 2736 2737 /* bandwidth must be freed after device done */ 2738 usb_hs_bandwidth_free(xfer); 2739 } 2740 2741 static void 2742 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2743 { 2744 struct usb_page_search buf_res; 2745 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2746 ehci_itd_t *td; 2747 ehci_itd_t *td_last = NULL; 2748 ehci_itd_t **pp_last; 2749 bus_size_t page_addr; 2750 uint32_t *plen; 2751 uint32_t status; 2752 uint32_t buf_offset; 2753 uint32_t nframes; 2754 uint32_t itd_offset[8 + 1]; 2755 uint8_t x; 2756 uint8_t td_no; 2757 uint8_t page_no; 2758 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2759 2760 #ifdef USB_DEBUG 2761 uint8_t once = 1; 2762 2763 #endif 2764 2765 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2766 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2767 2768 /* get the current frame index */ 2769 2770 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2771 2772 /* 2773 * check if the frame index is within the window where the frames 2774 * will be inserted 2775 */ 2776 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2777 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2778 2779 if ((xfer->endpoint->is_synced == 0) || 2780 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2781 /* 2782 * If there is data underflow or the pipe queue is empty we 2783 * schedule the transfer a few frames ahead of the current 2784 * frame position. Else two isochronous transfers might 2785 * overlap. 2786 */ 2787 xfer->endpoint->isoc_next = (nframes + 3) & 2788 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2789 xfer->endpoint->is_synced = 1; 2790 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2791 } 2792 /* 2793 * compute how many milliseconds the insertion is ahead of the 2794 * current frame position: 2795 */ 2796 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2797 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2798 2799 /* 2800 * pre-compute when the isochronous transfer will be finished: 2801 */ 2802 xfer->isoc_time_complete = 2803 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2804 (((xfer->nframes << shift) + 7) / 8); 2805 2806 /* get the real number of frames */ 2807 2808 nframes = xfer->nframes; 2809 2810 buf_offset = 0; 2811 td_no = 0; 2812 2813 plen = xfer->frlengths; 2814 2815 /* toggle the DMA set we are using */ 2816 xfer->flags_int.curr_dma_set ^= 1; 2817 2818 /* get next DMA set */ 2819 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2820 xfer->td_transfer_first = td; 2821 2822 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2823 2824 /* store starting position */ 2825 2826 xfer->qh_pos = xfer->endpoint->isoc_next; 2827 2828 while (nframes) { 2829 if (td == NULL) { 2830 panic("%s:%d: out of TD's\n", 2831 __FUNCTION__, __LINE__); 2832 } 2833 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2834 pp_last = &sc->sc_isoc_hs_p_last[0]; 2835 } 2836 /* range check */ 2837 if (*plen > xfer->max_frame_size) { 2838 #ifdef USB_DEBUG 2839 if (once) { 2840 once = 0; 2841 printf("%s: frame length(%d) exceeds %d bytes " 2842 "(frame truncated)\n", 2843 __FUNCTION__, *plen, xfer->max_frame_size); 2844 } 2845 #endif 2846 *plen = xfer->max_frame_size; 2847 } 2848 2849 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2850 status = (EHCI_ITD_SET_LEN(*plen) | 2851 EHCI_ITD_ACTIVE | 2852 EHCI_ITD_SET_PG(0)); 2853 td->itd_status[td_no] = htohc32(sc, status); 2854 itd_offset[td_no] = buf_offset; 2855 buf_offset += *plen; 2856 plen++; 2857 nframes --; 2858 } else { 2859 td->itd_status[td_no] = 0; /* not active */ 2860 itd_offset[td_no] = buf_offset; 2861 } 2862 2863 td_no++; 2864 2865 if ((td_no == 8) || (nframes == 0)) { 2866 2867 /* the rest of the transfers are not active, if any */ 2868 for (x = td_no; x != 8; x++) { 2869 td->itd_status[x] = 0; /* not active */ 2870 } 2871 2872 /* check if there is any data to be transferred */ 2873 if (itd_offset[0] != buf_offset) { 2874 page_no = 0; 2875 itd_offset[td_no] = buf_offset; 2876 2877 /* get first page offset */ 2878 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2879 /* get page address */ 2880 page_addr = buf_res.physaddr & ~0xFFF; 2881 /* update page address */ 2882 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2883 td->itd_bp[0] |= htohc32(sc, page_addr); 2884 2885 for (x = 0; x != td_no; x++) { 2886 /* set page number and page offset */ 2887 status = (EHCI_ITD_SET_PG(page_no) | 2888 (buf_res.physaddr & 0xFFF)); 2889 td->itd_status[x] |= htohc32(sc, status); 2890 2891 /* get next page offset */ 2892 if (itd_offset[x + 1] == buf_offset) { 2893 /* 2894 * We subtract one so that 2895 * we don't go off the last 2896 * page! 2897 */ 2898 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2899 } else { 2900 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2901 } 2902 2903 /* check if we need a new page */ 2904 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2905 /* new page needed */ 2906 page_addr = buf_res.physaddr & ~0xFFF; 2907 if (page_no == 6) { 2908 panic("%s: too many pages\n", __FUNCTION__); 2909 } 2910 page_no++; 2911 /* update page address */ 2912 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2913 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2914 } 2915 } 2916 } 2917 /* set IOC bit if we are complete */ 2918 if (nframes == 0) { 2919 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2920 } 2921 usb_pc_cpu_flush(td->page_cache); 2922 #ifdef USB_DEBUG 2923 if (ehcidebug > 15) { 2924 DPRINTF("HS-TD %d\n", nframes); 2925 ehci_dump_itd(sc, td); 2926 } 2927 #endif 2928 /* insert TD into schedule */ 2929 EHCI_APPEND_HS_TD(td, *pp_last); 2930 pp_last++; 2931 2932 td_no = 0; 2933 td_last = td; 2934 td = td->obj_next; 2935 } 2936 } 2937 2938 xfer->td_transfer_last = td_last; 2939 2940 /* update isoc_next */ 2941 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2942 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2943 } 2944 2945 static void 2946 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2947 { 2948 /* put transfer on interrupt queue */ 2949 ehci_transfer_intr_enqueue(xfer); 2950 } 2951 2952 struct usb_pipe_methods ehci_device_isoc_hs_methods = 2953 { 2954 .open = ehci_device_isoc_hs_open, 2955 .close = ehci_device_isoc_hs_close, 2956 .enter = ehci_device_isoc_hs_enter, 2957 .start = ehci_device_isoc_hs_start, 2958 }; 2959 2960 /*------------------------------------------------------------------------* 2961 * ehci root control support 2962 *------------------------------------------------------------------------* 2963 * Simulate a hardware hub by handling all the necessary requests. 2964 *------------------------------------------------------------------------*/ 2965 2966 static const 2967 struct usb_device_descriptor ehci_devd = 2968 { 2969 sizeof(struct usb_device_descriptor), 2970 UDESC_DEVICE, /* type */ 2971 {0x00, 0x02}, /* USB version */ 2972 UDCLASS_HUB, /* class */ 2973 UDSUBCLASS_HUB, /* subclass */ 2974 UDPROTO_HSHUBSTT, /* protocol */ 2975 64, /* max packet */ 2976 {0}, {0}, {0x00, 0x01}, /* device id */ 2977 1, 2, 0, /* string indicies */ 2978 1 /* # of configurations */ 2979 }; 2980 2981 static const 2982 struct usb_device_qualifier ehci_odevd = 2983 { 2984 sizeof(struct usb_device_qualifier), 2985 UDESC_DEVICE_QUALIFIER, /* type */ 2986 {0x00, 0x02}, /* USB version */ 2987 UDCLASS_HUB, /* class */ 2988 UDSUBCLASS_HUB, /* subclass */ 2989 UDPROTO_FSHUB, /* protocol */ 2990 0, /* max packet */ 2991 0, /* # of configurations */ 2992 0 2993 }; 2994 2995 static const struct ehci_config_desc ehci_confd = { 2996 .confd = { 2997 .bLength = sizeof(struct usb_config_descriptor), 2998 .bDescriptorType = UDESC_CONFIG, 2999 .wTotalLength[0] = sizeof(ehci_confd), 3000 .bNumInterface = 1, 3001 .bConfigurationValue = 1, 3002 .iConfiguration = 0, 3003 .bmAttributes = UC_SELF_POWERED, 3004 .bMaxPower = 0 /* max power */ 3005 }, 3006 .ifcd = { 3007 .bLength = sizeof(struct usb_interface_descriptor), 3008 .bDescriptorType = UDESC_INTERFACE, 3009 .bNumEndpoints = 1, 3010 .bInterfaceClass = UICLASS_HUB, 3011 .bInterfaceSubClass = UISUBCLASS_HUB, 3012 .bInterfaceProtocol = 0, 3013 }, 3014 .endpd = { 3015 .bLength = sizeof(struct usb_endpoint_descriptor), 3016 .bDescriptorType = UDESC_ENDPOINT, 3017 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3018 .bmAttributes = UE_INTERRUPT, 3019 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3020 .bInterval = 255, 3021 }, 3022 }; 3023 3024 static const 3025 struct usb_hub_descriptor ehci_hubd = 3026 { 3027 .bDescLength = 0, /* dynamic length */ 3028 .bDescriptorType = UDESC_HUB, 3029 }; 3030 3031 static void 3032 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3033 { 3034 uint32_t port; 3035 uint32_t v; 3036 3037 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3038 3039 port = EHCI_PORTSC(index); 3040 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3041 EOWRITE4(sc, port, v | EHCI_PS_PO); 3042 } 3043 3044 static usb_error_t 3045 ehci_roothub_exec(struct usb_device *udev, 3046 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3047 { 3048 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3049 const char *str_ptr; 3050 const void *ptr; 3051 uint32_t port; 3052 uint32_t v; 3053 uint16_t len; 3054 uint16_t i; 3055 uint16_t value; 3056 uint16_t index; 3057 usb_error_t err; 3058 3059 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3060 3061 /* buffer reset */ 3062 ptr = (const void *)&sc->sc_hub_desc; 3063 len = 0; 3064 err = 0; 3065 3066 value = UGETW(req->wValue); 3067 index = UGETW(req->wIndex); 3068 3069 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3070 "wValue=0x%04x wIndex=0x%04x\n", 3071 req->bmRequestType, req->bRequest, 3072 UGETW(req->wLength), value, index); 3073 3074 #define C(x,y) ((x) | ((y) << 8)) 3075 switch (C(req->bRequest, req->bmRequestType)) { 3076 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3077 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3078 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3079 /* 3080 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3081 * for the integrated root hub. 3082 */ 3083 break; 3084 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3085 len = 1; 3086 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3087 break; 3088 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3089 switch (value >> 8) { 3090 case UDESC_DEVICE: 3091 if ((value & 0xff) != 0) { 3092 err = USB_ERR_IOERROR; 3093 goto done; 3094 } 3095 len = sizeof(ehci_devd); 3096 ptr = (const void *)&ehci_devd; 3097 break; 3098 /* 3099 * We can't really operate at another speed, 3100 * but the specification says we need this 3101 * descriptor: 3102 */ 3103 case UDESC_DEVICE_QUALIFIER: 3104 if ((value & 0xff) != 0) { 3105 err = USB_ERR_IOERROR; 3106 goto done; 3107 } 3108 len = sizeof(ehci_odevd); 3109 ptr = (const void *)&ehci_odevd; 3110 break; 3111 3112 case UDESC_CONFIG: 3113 if ((value & 0xff) != 0) { 3114 err = USB_ERR_IOERROR; 3115 goto done; 3116 } 3117 len = sizeof(ehci_confd); 3118 ptr = (const void *)&ehci_confd; 3119 break; 3120 3121 case UDESC_STRING: 3122 switch (value & 0xff) { 3123 case 0: /* Language table */ 3124 str_ptr = "\001"; 3125 break; 3126 3127 case 1: /* Vendor */ 3128 str_ptr = sc->sc_vendor; 3129 break; 3130 3131 case 2: /* Product */ 3132 str_ptr = "EHCI root HUB"; 3133 break; 3134 3135 default: 3136 str_ptr = ""; 3137 break; 3138 } 3139 3140 len = usb_make_str_desc( 3141 sc->sc_hub_desc.temp, 3142 sizeof(sc->sc_hub_desc.temp), 3143 str_ptr); 3144 break; 3145 default: 3146 err = USB_ERR_IOERROR; 3147 goto done; 3148 } 3149 break; 3150 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3151 len = 1; 3152 sc->sc_hub_desc.temp[0] = 0; 3153 break; 3154 case C(UR_GET_STATUS, UT_READ_DEVICE): 3155 len = 2; 3156 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3157 break; 3158 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3159 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3160 len = 2; 3161 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3162 break; 3163 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3164 if (value >= EHCI_MAX_DEVICES) { 3165 err = USB_ERR_IOERROR; 3166 goto done; 3167 } 3168 sc->sc_addr = value; 3169 break; 3170 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3171 if ((value != 0) && (value != 1)) { 3172 err = USB_ERR_IOERROR; 3173 goto done; 3174 } 3175 sc->sc_conf = value; 3176 break; 3177 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3178 break; 3179 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3180 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3181 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3182 err = USB_ERR_IOERROR; 3183 goto done; 3184 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3185 break; 3186 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3187 break; 3188 /* Hub requests */ 3189 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3190 break; 3191 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3192 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3193 3194 if ((index < 1) || 3195 (index > sc->sc_noport)) { 3196 err = USB_ERR_IOERROR; 3197 goto done; 3198 } 3199 port = EHCI_PORTSC(index); 3200 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3201 switch (value) { 3202 case UHF_PORT_ENABLE: 3203 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3204 break; 3205 case UHF_PORT_SUSPEND: 3206 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3207 3208 /* 3209 * waking up a High Speed device is rather 3210 * complicated if 3211 */ 3212 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3213 } 3214 /* wait 20ms for resume sequence to complete */ 3215 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3216 3217 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3218 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3219 3220 /* 4ms settle time */ 3221 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3222 break; 3223 case UHF_PORT_POWER: 3224 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3225 break; 3226 case UHF_PORT_TEST: 3227 DPRINTFN(3, "clear port test " 3228 "%d\n", index); 3229 break; 3230 case UHF_PORT_INDICATOR: 3231 DPRINTFN(3, "clear port ind " 3232 "%d\n", index); 3233 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3234 break; 3235 case UHF_C_PORT_CONNECTION: 3236 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3237 break; 3238 case UHF_C_PORT_ENABLE: 3239 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3240 break; 3241 case UHF_C_PORT_SUSPEND: 3242 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3243 break; 3244 case UHF_C_PORT_OVER_CURRENT: 3245 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3246 break; 3247 case UHF_C_PORT_RESET: 3248 sc->sc_isreset = 0; 3249 break; 3250 default: 3251 err = USB_ERR_IOERROR; 3252 goto done; 3253 } 3254 break; 3255 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3256 if ((value & 0xff) != 0) { 3257 err = USB_ERR_IOERROR; 3258 goto done; 3259 } 3260 v = EREAD4(sc, EHCI_HCSPARAMS); 3261 3262 sc->sc_hub_desc.hubd = ehci_hubd; 3263 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3264 3265 if (EHCI_HCS_PPC(v)) 3266 i = UHD_PWR_INDIVIDUAL; 3267 else 3268 i = UHD_PWR_NO_SWITCH; 3269 3270 if (EHCI_HCS_P_INDICATOR(v)) 3271 i |= UHD_PORT_IND; 3272 3273 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3274 /* XXX can't find out? */ 3275 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3276 /* XXX don't know if ports are removable or not */ 3277 sc->sc_hub_desc.hubd.bDescLength = 3278 8 + ((sc->sc_noport + 7) / 8); 3279 len = sc->sc_hub_desc.hubd.bDescLength; 3280 break; 3281 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3282 len = 16; 3283 memset(sc->sc_hub_desc.temp, 0, 16); 3284 break; 3285 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3286 DPRINTFN(9, "get port status i=%d\n", 3287 index); 3288 if ((index < 1) || 3289 (index > sc->sc_noport)) { 3290 err = USB_ERR_IOERROR; 3291 goto done; 3292 } 3293 v = EOREAD4(sc, EHCI_PORTSC(index)); 3294 DPRINTFN(9, "port status=0x%04x\n", v); 3295 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3296 if ((v & 0xc000000) == 0x8000000) 3297 i = UPS_HIGH_SPEED; 3298 else if ((v & 0xc000000) == 0x4000000) 3299 i = UPS_LOW_SPEED; 3300 else 3301 i = 0; 3302 } else { 3303 i = UPS_HIGH_SPEED; 3304 } 3305 if (v & EHCI_PS_CS) 3306 i |= UPS_CURRENT_CONNECT_STATUS; 3307 if (v & EHCI_PS_PE) 3308 i |= UPS_PORT_ENABLED; 3309 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3310 i |= UPS_SUSPEND; 3311 if (v & EHCI_PS_OCA) 3312 i |= UPS_OVERCURRENT_INDICATOR; 3313 if (v & EHCI_PS_PR) 3314 i |= UPS_RESET; 3315 if (v & EHCI_PS_PP) 3316 i |= UPS_PORT_POWER; 3317 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3318 i = 0; 3319 if (v & EHCI_PS_CSC) 3320 i |= UPS_C_CONNECT_STATUS; 3321 if (v & EHCI_PS_PEC) 3322 i |= UPS_C_PORT_ENABLED; 3323 if (v & EHCI_PS_OCC) 3324 i |= UPS_C_OVERCURRENT_INDICATOR; 3325 if (v & EHCI_PS_FPR) 3326 i |= UPS_C_SUSPEND; 3327 if (sc->sc_isreset) 3328 i |= UPS_C_PORT_RESET; 3329 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3330 len = sizeof(sc->sc_hub_desc.ps); 3331 break; 3332 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3333 err = USB_ERR_IOERROR; 3334 goto done; 3335 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3336 break; 3337 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3338 if ((index < 1) || 3339 (index > sc->sc_noport)) { 3340 err = USB_ERR_IOERROR; 3341 goto done; 3342 } 3343 port = EHCI_PORTSC(index); 3344 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3345 switch (value) { 3346 case UHF_PORT_ENABLE: 3347 EOWRITE4(sc, port, v | EHCI_PS_PE); 3348 break; 3349 case UHF_PORT_SUSPEND: 3350 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3351 break; 3352 case UHF_PORT_RESET: 3353 DPRINTFN(6, "reset port %d\n", index); 3354 #ifdef USB_DEBUG 3355 if (ehcinohighspeed) { 3356 /* 3357 * Connect USB device to companion 3358 * controller. 3359 */ 3360 ehci_disown(sc, index, 1); 3361 break; 3362 } 3363 #endif 3364 if (EHCI_PS_IS_LOWSPEED(v) && 3365 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3366 /* Low speed device, give up ownership. */ 3367 ehci_disown(sc, index, 1); 3368 break; 3369 } 3370 /* Start reset sequence. */ 3371 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3372 EOWRITE4(sc, port, v | EHCI_PS_PR); 3373 3374 /* Wait for reset to complete. */ 3375 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3376 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3377 3378 /* Terminate reset sequence. */ 3379 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3380 EOWRITE4(sc, port, v); 3381 3382 /* Wait for HC to complete reset. */ 3383 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3384 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3385 3386 v = EOREAD4(sc, port); 3387 DPRINTF("ehci after reset, status=0x%08x\n", v); 3388 if (v & EHCI_PS_PR) { 3389 device_printf(sc->sc_bus.bdev, 3390 "port reset timeout\n"); 3391 err = USB_ERR_TIMEOUT; 3392 goto done; 3393 } 3394 if (!(v & EHCI_PS_PE) && 3395 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3396 /* Not a high speed device, give up ownership.*/ 3397 ehci_disown(sc, index, 0); 3398 break; 3399 } 3400 sc->sc_isreset = 1; 3401 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3402 index, v); 3403 break; 3404 3405 case UHF_PORT_POWER: 3406 DPRINTFN(3, "set port power %d\n", index); 3407 EOWRITE4(sc, port, v | EHCI_PS_PP); 3408 break; 3409 3410 case UHF_PORT_TEST: 3411 DPRINTFN(3, "set port test %d\n", index); 3412 break; 3413 3414 case UHF_PORT_INDICATOR: 3415 DPRINTFN(3, "set port ind %d\n", index); 3416 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3417 break; 3418 3419 default: 3420 err = USB_ERR_IOERROR; 3421 goto done; 3422 } 3423 break; 3424 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3425 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3426 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3427 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3428 break; 3429 default: 3430 err = USB_ERR_IOERROR; 3431 goto done; 3432 } 3433 done: 3434 *plength = len; 3435 *pptr = ptr; 3436 return (err); 3437 } 3438 3439 static void 3440 ehci_xfer_setup(struct usb_setup_params *parm) 3441 { 3442 struct usb_page_search page_info; 3443 struct usb_page_cache *pc; 3444 ehci_softc_t *sc; 3445 struct usb_xfer *xfer; 3446 void *last_obj; 3447 uint32_t nqtd; 3448 uint32_t nqh; 3449 uint32_t nsitd; 3450 uint32_t nitd; 3451 uint32_t n; 3452 3453 sc = EHCI_BUS2SC(parm->udev->bus); 3454 xfer = parm->curr_xfer; 3455 3456 nqtd = 0; 3457 nqh = 0; 3458 nsitd = 0; 3459 nitd = 0; 3460 3461 /* 3462 * compute maximum number of some structures 3463 */ 3464 if (parm->methods == &ehci_device_ctrl_methods) { 3465 3466 /* 3467 * The proof for the "nqtd" formula is illustrated like 3468 * this: 3469 * 3470 * +------------------------------------+ 3471 * | | 3472 * | |remainder -> | 3473 * | +-----+---+ | 3474 * | | xxx | x | frm 0 | 3475 * | +-----+---++ | 3476 * | | xxx | xx | frm 1 | 3477 * | +-----+----+ | 3478 * | ... | 3479 * +------------------------------------+ 3480 * 3481 * "xxx" means a completely full USB transfer descriptor 3482 * 3483 * "x" and "xx" means a short USB packet 3484 * 3485 * For the remainder of an USB transfer modulo 3486 * "max_data_length" we need two USB transfer descriptors. 3487 * One to transfer the remaining data and one to finalise 3488 * with a zero length packet in case the "force_short_xfer" 3489 * flag is set. We only need two USB transfer descriptors in 3490 * the case where the transfer length of the first one is a 3491 * factor of "max_frame_size". The rest of the needed USB 3492 * transfer descriptors is given by the buffer size divided 3493 * by the maximum data payload. 3494 */ 3495 parm->hc_max_packet_size = 0x400; 3496 parm->hc_max_packet_count = 1; 3497 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3498 xfer->flags_int.bdma_enable = 1; 3499 3500 usbd_transfer_setup_sub(parm); 3501 3502 nqh = 1; 3503 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3504 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3505 3506 } else if (parm->methods == &ehci_device_bulk_methods) { 3507 3508 parm->hc_max_packet_size = 0x400; 3509 parm->hc_max_packet_count = 1; 3510 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3511 xfer->flags_int.bdma_enable = 1; 3512 3513 usbd_transfer_setup_sub(parm); 3514 3515 nqh = 1; 3516 nqtd = ((2 * xfer->nframes) 3517 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3518 3519 } else if (parm->methods == &ehci_device_intr_methods) { 3520 3521 if (parm->speed == USB_SPEED_HIGH) { 3522 parm->hc_max_packet_size = 0x400; 3523 parm->hc_max_packet_count = 3; 3524 } else if (parm->speed == USB_SPEED_FULL) { 3525 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3526 parm->hc_max_packet_count = 1; 3527 } else { 3528 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3529 parm->hc_max_packet_count = 1; 3530 } 3531 3532 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3533 xfer->flags_int.bdma_enable = 1; 3534 3535 usbd_transfer_setup_sub(parm); 3536 3537 nqh = 1; 3538 nqtd = ((2 * xfer->nframes) 3539 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3540 3541 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3542 3543 parm->hc_max_packet_size = 0x3FF; 3544 parm->hc_max_packet_count = 1; 3545 parm->hc_max_frame_size = 0x3FF; 3546 xfer->flags_int.bdma_enable = 1; 3547 3548 usbd_transfer_setup_sub(parm); 3549 3550 nsitd = xfer->nframes; 3551 3552 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3553 3554 parm->hc_max_packet_size = 0x400; 3555 parm->hc_max_packet_count = 3; 3556 parm->hc_max_frame_size = 0xC00; 3557 xfer->flags_int.bdma_enable = 1; 3558 3559 usbd_transfer_setup_sub(parm); 3560 3561 nitd = ((xfer->nframes + 7) / 8) << 3562 usbd_xfer_get_fps_shift(xfer); 3563 3564 } else { 3565 3566 parm->hc_max_packet_size = 0x400; 3567 parm->hc_max_packet_count = 1; 3568 parm->hc_max_frame_size = 0x400; 3569 3570 usbd_transfer_setup_sub(parm); 3571 } 3572 3573 alloc_dma_set: 3574 3575 if (parm->err) { 3576 return; 3577 } 3578 /* 3579 * Allocate queue heads and transfer descriptors 3580 */ 3581 last_obj = NULL; 3582 3583 if (usbd_transfer_setup_sub_malloc( 3584 parm, &pc, sizeof(ehci_itd_t), 3585 EHCI_ITD_ALIGN, nitd)) { 3586 parm->err = USB_ERR_NOMEM; 3587 return; 3588 } 3589 if (parm->buf) { 3590 for (n = 0; n != nitd; n++) { 3591 ehci_itd_t *td; 3592 3593 usbd_get_page(pc + n, 0, &page_info); 3594 3595 td = page_info.buffer; 3596 3597 /* init TD */ 3598 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3599 td->obj_next = last_obj; 3600 td->page_cache = pc + n; 3601 3602 last_obj = td; 3603 3604 usb_pc_cpu_flush(pc + n); 3605 } 3606 } 3607 if (usbd_transfer_setup_sub_malloc( 3608 parm, &pc, sizeof(ehci_sitd_t), 3609 EHCI_SITD_ALIGN, nsitd)) { 3610 parm->err = USB_ERR_NOMEM; 3611 return; 3612 } 3613 if (parm->buf) { 3614 for (n = 0; n != nsitd; n++) { 3615 ehci_sitd_t *td; 3616 3617 usbd_get_page(pc + n, 0, &page_info); 3618 3619 td = page_info.buffer; 3620 3621 /* init TD */ 3622 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3623 td->obj_next = last_obj; 3624 td->page_cache = pc + n; 3625 3626 last_obj = td; 3627 3628 usb_pc_cpu_flush(pc + n); 3629 } 3630 } 3631 if (usbd_transfer_setup_sub_malloc( 3632 parm, &pc, sizeof(ehci_qtd_t), 3633 EHCI_QTD_ALIGN, nqtd)) { 3634 parm->err = USB_ERR_NOMEM; 3635 return; 3636 } 3637 if (parm->buf) { 3638 for (n = 0; n != nqtd; n++) { 3639 ehci_qtd_t *qtd; 3640 3641 usbd_get_page(pc + n, 0, &page_info); 3642 3643 qtd = page_info.buffer; 3644 3645 /* init TD */ 3646 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3647 qtd->obj_next = last_obj; 3648 qtd->page_cache = pc + n; 3649 3650 last_obj = qtd; 3651 3652 usb_pc_cpu_flush(pc + n); 3653 } 3654 } 3655 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3656 3657 last_obj = NULL; 3658 3659 if (usbd_transfer_setup_sub_malloc( 3660 parm, &pc, sizeof(ehci_qh_t), 3661 EHCI_QH_ALIGN, nqh)) { 3662 parm->err = USB_ERR_NOMEM; 3663 return; 3664 } 3665 if (parm->buf) { 3666 for (n = 0; n != nqh; n++) { 3667 ehci_qh_t *qh; 3668 3669 usbd_get_page(pc + n, 0, &page_info); 3670 3671 qh = page_info.buffer; 3672 3673 /* init QH */ 3674 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3675 qh->obj_next = last_obj; 3676 qh->page_cache = pc + n; 3677 3678 last_obj = qh; 3679 3680 usb_pc_cpu_flush(pc + n); 3681 } 3682 } 3683 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3684 3685 if (!xfer->flags_int.curr_dma_set) { 3686 xfer->flags_int.curr_dma_set = 1; 3687 goto alloc_dma_set; 3688 } 3689 } 3690 3691 static void 3692 ehci_xfer_unsetup(struct usb_xfer *xfer) 3693 { 3694 return; 3695 } 3696 3697 static void 3698 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3699 struct usb_endpoint *ep) 3700 { 3701 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3702 3703 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3704 ep, udev->address, 3705 edesc->bEndpointAddress, udev->flags.usb_mode, 3706 sc->sc_addr); 3707 3708 if (udev->device_index != sc->sc_addr) { 3709 3710 if ((udev->speed != USB_SPEED_HIGH) && 3711 ((udev->hs_hub_addr == 0) || 3712 (udev->hs_port_no == 0) || 3713 (udev->parent_hs_hub == NULL) || 3714 (udev->parent_hs_hub->hub == NULL))) { 3715 /* We need a transaction translator */ 3716 goto done; 3717 } 3718 switch (edesc->bmAttributes & UE_XFERTYPE) { 3719 case UE_CONTROL: 3720 ep->methods = &ehci_device_ctrl_methods; 3721 break; 3722 case UE_INTERRUPT: 3723 ep->methods = &ehci_device_intr_methods; 3724 break; 3725 case UE_ISOCHRONOUS: 3726 if (udev->speed == USB_SPEED_HIGH) { 3727 ep->methods = &ehci_device_isoc_hs_methods; 3728 } else if (udev->speed == USB_SPEED_FULL) { 3729 ep->methods = &ehci_device_isoc_fs_methods; 3730 } 3731 break; 3732 case UE_BULK: 3733 ep->methods = &ehci_device_bulk_methods; 3734 break; 3735 default: 3736 /* do nothing */ 3737 break; 3738 } 3739 } 3740 done: 3741 return; 3742 } 3743 3744 static void 3745 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3746 { 3747 /* 3748 * Wait until the hardware has finished any possible use of 3749 * the transfer descriptor(s) and QH 3750 */ 3751 *pus = (188); /* microseconds */ 3752 } 3753 3754 static void 3755 ehci_device_resume(struct usb_device *udev) 3756 { 3757 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3758 struct usb_xfer *xfer; 3759 struct usb_pipe_methods *methods; 3760 3761 DPRINTF("\n"); 3762 3763 USB_BUS_LOCK(udev->bus); 3764 3765 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3766 3767 if (xfer->xroot->udev == udev) { 3768 3769 methods = xfer->endpoint->methods; 3770 3771 if ((methods == &ehci_device_bulk_methods) || 3772 (methods == &ehci_device_ctrl_methods)) { 3773 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3774 sc->sc_async_p_last); 3775 } 3776 if (methods == &ehci_device_intr_methods) { 3777 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3778 sc->sc_intr_p_last[xfer->qh_pos]); 3779 } 3780 } 3781 } 3782 3783 USB_BUS_UNLOCK(udev->bus); 3784 3785 return; 3786 } 3787 3788 static void 3789 ehci_device_suspend(struct usb_device *udev) 3790 { 3791 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3792 struct usb_xfer *xfer; 3793 struct usb_pipe_methods *methods; 3794 3795 DPRINTF("\n"); 3796 3797 USB_BUS_LOCK(udev->bus); 3798 3799 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3800 3801 if (xfer->xroot->udev == udev) { 3802 3803 methods = xfer->endpoint->methods; 3804 3805 if ((methods == &ehci_device_bulk_methods) || 3806 (methods == &ehci_device_ctrl_methods)) { 3807 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3808 sc->sc_async_p_last); 3809 } 3810 if (methods == &ehci_device_intr_methods) { 3811 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3812 sc->sc_intr_p_last[xfer->qh_pos]); 3813 } 3814 } 3815 } 3816 3817 USB_BUS_UNLOCK(udev->bus); 3818 } 3819 3820 static void 3821 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3822 { 3823 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3824 3825 switch (state) { 3826 case USB_HW_POWER_SUSPEND: 3827 case USB_HW_POWER_SHUTDOWN: 3828 ehci_suspend(sc); 3829 break; 3830 case USB_HW_POWER_RESUME: 3831 ehci_resume(sc); 3832 break; 3833 default: 3834 break; 3835 } 3836 } 3837 3838 static void 3839 ehci_set_hw_power(struct usb_bus *bus) 3840 { 3841 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3842 uint32_t temp; 3843 uint32_t flags; 3844 3845 DPRINTF("\n"); 3846 3847 USB_BUS_LOCK(bus); 3848 3849 flags = bus->hw_power_state; 3850 3851 temp = EOREAD4(sc, EHCI_USBCMD); 3852 3853 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3854 3855 if (flags & (USB_HW_POWER_CONTROL | 3856 USB_HW_POWER_BULK)) { 3857 DPRINTF("Async is active\n"); 3858 temp |= EHCI_CMD_ASE; 3859 } 3860 if (flags & (USB_HW_POWER_INTERRUPT | 3861 USB_HW_POWER_ISOC)) { 3862 DPRINTF("Periodic is active\n"); 3863 temp |= EHCI_CMD_PSE; 3864 } 3865 EOWRITE4(sc, EHCI_USBCMD, temp); 3866 3867 USB_BUS_UNLOCK(bus); 3868 3869 return; 3870 } 3871 3872 struct usb_bus_methods ehci_bus_methods = 3873 { 3874 .endpoint_init = ehci_ep_init, 3875 .xfer_setup = ehci_xfer_setup, 3876 .xfer_unsetup = ehci_xfer_unsetup, 3877 .get_dma_delay = ehci_get_dma_delay, 3878 .device_resume = ehci_device_resume, 3879 .device_suspend = ehci_device_suspend, 3880 .set_hw_power = ehci_set_hw_power, 3881 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3882 .roothub_exec = ehci_roothub_exec, 3883 .xfer_poll = ehci_do_poll, 3884 }; 3885