1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 6 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 7 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 8 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 /* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 0.96 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 37 * The EHCI 1.0 spec can be found at 38 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/usb_20.zip 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) command failures are not recovered correctly 47 */ 48 49 #ifdef USB_GLOBAL_INCLUDE_FILE 50 #include USB_GLOBAL_INCLUDE_FILE 51 #else 52 #include <sys/stdint.h> 53 #include <sys/stddef.h> 54 #include <sys/param.h> 55 #include <sys/queue.h> 56 #include <sys/types.h> 57 #include <sys/systm.h> 58 #include <sys/kernel.h> 59 #include <sys/bus.h> 60 #include <sys/module.h> 61 #include <sys/lock.h> 62 #include <sys/mutex.h> 63 #include <sys/condvar.h> 64 #include <sys/sysctl.h> 65 #include <sys/sx.h> 66 #include <sys/unistd.h> 67 #include <sys/callout.h> 68 #include <sys/malloc.h> 69 #include <sys/priv.h> 70 71 #include <dev/usb/usb.h> 72 #include <dev/usb/usbdi.h> 73 74 #define USB_DEBUG_VAR ehcidebug 75 76 #include <dev/usb/usb_core.h> 77 #include <dev/usb/usb_debug.h> 78 #include <dev/usb/usb_busdma.h> 79 #include <dev/usb/usb_process.h> 80 #include <dev/usb/usb_transfer.h> 81 #include <dev/usb/usb_device.h> 82 #include <dev/usb/usb_hub.h> 83 #include <dev/usb/usb_util.h> 84 85 #include <dev/usb/usb_controller.h> 86 #include <dev/usb/usb_bus.h> 87 #endif /* USB_GLOBAL_INCLUDE_FILE */ 88 89 #include <dev/usb/controller/ehci.h> 90 #include <dev/usb/controller/ehcireg.h> 91 92 #define EHCI_BUS2SC(bus) \ 93 __containerof(bus, ehci_softc_t, sc_bus) 94 95 #ifdef USB_DEBUG 96 static int ehcidebug = 0; 97 static int ehcinohighspeed = 0; 98 static int ehciiaadbug = 0; 99 static int ehcilostintrbug = 0; 100 101 static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 102 "USB ehci"); 103 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 104 &ehcidebug, 0, "Debug level"); 105 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 106 &ehcinohighspeed, 0, "Disable High Speed USB"); 107 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 108 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 109 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 110 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 111 112 static void ehci_dump_regs(ehci_softc_t *sc); 113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115 #endif 116 117 #define EHCI_INTR_ENDPT 1 118 119 static const struct usb_bus_methods ehci_bus_methods; 120 static const struct usb_pipe_methods ehci_device_bulk_methods; 121 static const struct usb_pipe_methods ehci_device_ctrl_methods; 122 static const struct usb_pipe_methods ehci_device_intr_methods; 123 static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 124 static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126 static void ehci_do_poll(struct usb_bus *); 127 static void ehci_device_done(struct usb_xfer *, usb_error_t); 128 static uint8_t ehci_check_transfer(struct usb_xfer *); 129 static void ehci_timeout(void *); 130 static void ehci_poll_timeout(void *); 131 132 static void ehci_root_intr(ehci_softc_t *sc); 133 134 struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147 }; 148 149 void 150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151 { 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181 } 182 183 usb_error_t 184 ehci_reset(ehci_softc_t *sc) 185 { 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 128); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_vendor_post_reset != NULL) 195 sc->sc_vendor_post_reset(sc); 196 return (0); 197 } 198 } 199 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 200 return (USB_ERR_IOERROR); 201 } 202 203 static usb_error_t 204 ehci_hcreset(ehci_softc_t *sc) 205 { 206 uint32_t hcr; 207 int i; 208 209 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 210 for (i = 0; i < 100; i++) { 211 usb_pause_mtx(NULL, hz / 128); 212 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 213 if (hcr) 214 break; 215 } 216 if (!hcr) 217 /* 218 * Fall through and try reset anyway even though 219 * Table 2-9 in the EHCI spec says this will result 220 * in undefined behavior. 221 */ 222 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 223 224 return (ehci_reset(sc)); 225 } 226 227 static int 228 ehci_init_sub(struct ehci_softc *sc) 229 { 230 struct usb_page_search buf_res; 231 uint32_t cparams; 232 uint32_t hcr; 233 uint8_t i; 234 235 cparams = EREAD4(sc, EHCI_HCCPARAMS); 236 237 DPRINTF("cparams=0x%x\n", cparams); 238 239 if (EHCI_HCC_64BIT(cparams)) { 240 DPRINTF("HCC uses 64-bit structures\n"); 241 242 /* MUST clear segment register if 64 bit capable */ 243 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 244 } 245 246 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 247 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 248 249 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 250 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 251 252 /* enable interrupts */ 253 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 254 255 /* turn on controller */ 256 EOWRITE4(sc, EHCI_USBCMD, 257 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 258 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 259 EHCI_CMD_ASE | 260 EHCI_CMD_PSE | 261 EHCI_CMD_RS); 262 263 /* Take over port ownership */ 264 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 265 266 for (i = 0; i < 100; i++) { 267 usb_pause_mtx(NULL, hz / 128); 268 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 269 if (!hcr) { 270 break; 271 } 272 } 273 if (hcr) { 274 device_printf(sc->sc_bus.bdev, "run timeout\n"); 275 return (USB_ERR_IOERROR); 276 } 277 return (USB_ERR_NORMAL_COMPLETION); 278 } 279 280 usb_error_t 281 ehci_init(ehci_softc_t *sc) 282 { 283 struct usb_page_search buf_res; 284 uint32_t version; 285 uint32_t sparams; 286 uint16_t i; 287 uint16_t x; 288 uint16_t y; 289 uint16_t bit; 290 usb_error_t err = 0; 291 292 DPRINTF("start\n"); 293 294 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 295 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 296 297 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 298 299 #ifdef USB_DEBUG 300 if (ehciiaadbug) 301 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 302 if (ehcilostintrbug) 303 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 304 if (ehcidebug > 2) { 305 ehci_dump_regs(sc); 306 } 307 #endif 308 309 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 310 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 311 version >> 8, version & 0xff); 312 313 sparams = EREAD4(sc, EHCI_HCSPARAMS); 314 DPRINTF("sparams=0x%x\n", sparams); 315 316 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 317 sc->sc_bus.usbrev = USB_REV_2_0; 318 319 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 320 /* Reset the controller */ 321 DPRINTF("%s: resetting\n", 322 device_get_nameunit(sc->sc_bus.bdev)); 323 324 err = ehci_hcreset(sc); 325 if (err) { 326 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 327 return (err); 328 } 329 } 330 331 /* 332 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 333 * bytes 2: 256*4 bytes 3: unknown 334 */ 335 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 336 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 337 return (USB_ERR_IOERROR); 338 } 339 /* set up the bus struct */ 340 sc->sc_bus.methods = &ehci_bus_methods; 341 342 sc->sc_eintrs = EHCI_NORMAL_INTRS; 343 344 if (1) { 345 struct ehci_qh_sub *qh; 346 347 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 348 349 qh = buf_res.buffer; 350 351 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 352 353 /* init terminate TD */ 354 qh->qtd_next = 355 htohc32(sc, EHCI_LINK_TERMINATE); 356 qh->qtd_altnext = 357 htohc32(sc, EHCI_LINK_TERMINATE); 358 qh->qtd_status = 359 htohc32(sc, EHCI_QTD_HALTED); 360 } 361 362 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 363 ehci_qh_t *qh; 364 365 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 366 367 qh = buf_res.buffer; 368 369 /* initialize page cache pointer */ 370 371 qh->page_cache = sc->sc_hw.intr_start_pc + i; 372 373 /* store a pointer to queue head */ 374 375 sc->sc_intr_p_last[i] = qh; 376 377 qh->qh_self = 378 htohc32(sc, buf_res.physaddr) | 379 htohc32(sc, EHCI_LINK_QH); 380 381 qh->qh_endp = 382 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 383 qh->qh_endphub = 384 htohc32(sc, EHCI_QH_SET_MULT(1)); 385 qh->qh_curqtd = 0; 386 387 qh->qh_qtd.qtd_next = 388 htohc32(sc, EHCI_LINK_TERMINATE); 389 qh->qh_qtd.qtd_altnext = 390 htohc32(sc, EHCI_LINK_TERMINATE); 391 qh->qh_qtd.qtd_status = 392 htohc32(sc, EHCI_QTD_HALTED); 393 } 394 395 /* 396 * the QHs are arranged to give poll intervals that are 397 * powers of 2 times 1ms 398 */ 399 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 400 while (bit) { 401 x = bit; 402 while (x & bit) { 403 ehci_qh_t *qh_x; 404 ehci_qh_t *qh_y; 405 406 y = (x ^ bit) | (bit / 2); 407 408 qh_x = sc->sc_intr_p_last[x]; 409 qh_y = sc->sc_intr_p_last[y]; 410 411 /* 412 * the next QH has half the poll interval 413 */ 414 qh_x->qh_link = qh_y->qh_self; 415 416 x++; 417 } 418 bit >>= 1; 419 } 420 421 if (1) { 422 ehci_qh_t *qh; 423 424 qh = sc->sc_intr_p_last[0]; 425 426 /* the last (1ms) QH terminates */ 427 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 428 } 429 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 430 ehci_sitd_t *sitd; 431 ehci_itd_t *itd; 432 433 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 434 435 sitd = buf_res.buffer; 436 437 /* initialize page cache pointer */ 438 439 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 440 441 /* store a pointer to the transfer descriptor */ 442 443 sc->sc_isoc_fs_p_last[i] = sitd; 444 445 /* initialize full speed isochronous */ 446 447 sitd->sitd_self = 448 htohc32(sc, buf_res.physaddr) | 449 htohc32(sc, EHCI_LINK_SITD); 450 451 sitd->sitd_back = 452 htohc32(sc, EHCI_LINK_TERMINATE); 453 454 sitd->sitd_next = 455 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 456 457 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 458 459 itd = buf_res.buffer; 460 461 /* initialize page cache pointer */ 462 463 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 464 465 /* store a pointer to the transfer descriptor */ 466 467 sc->sc_isoc_hs_p_last[i] = itd; 468 469 /* initialize high speed isochronous */ 470 471 itd->itd_self = 472 htohc32(sc, buf_res.physaddr) | 473 htohc32(sc, EHCI_LINK_ITD); 474 475 itd->itd_next = 476 sitd->sitd_self; 477 } 478 479 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 480 481 if (1) { 482 uint32_t *pframes; 483 484 pframes = buf_res.buffer; 485 486 /* 487 * execution order: 488 * pframes -> high speed isochronous -> 489 * full speed isochronous -> interrupt QH's 490 */ 491 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 492 pframes[i] = sc->sc_isoc_hs_p_last 493 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 494 } 495 } 496 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 497 498 if (1) { 499 ehci_qh_t *qh; 500 501 qh = buf_res.buffer; 502 503 /* initialize page cache pointer */ 504 505 qh->page_cache = &sc->sc_hw.async_start_pc; 506 507 /* store a pointer to the queue head */ 508 509 sc->sc_async_p_last = qh; 510 511 /* init dummy QH that starts the async list */ 512 513 qh->qh_self = 514 htohc32(sc, buf_res.physaddr) | 515 htohc32(sc, EHCI_LINK_QH); 516 517 /* fill the QH */ 518 qh->qh_endp = 519 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 520 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 521 qh->qh_link = qh->qh_self; 522 qh->qh_curqtd = 0; 523 524 /* fill the overlay qTD */ 525 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 526 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 527 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 528 } 529 /* flush all cache into memory */ 530 531 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 532 533 #ifdef USB_DEBUG 534 if (ehcidebug) { 535 ehci_dump_sqh(sc, sc->sc_async_p_last); 536 } 537 #endif 538 539 /* finial setup */ 540 err = ehci_init_sub(sc); 541 542 if (!err) { 543 /* catch any lost interrupts */ 544 ehci_do_poll(&sc->sc_bus); 545 } 546 return (err); 547 } 548 549 /* 550 * shut down the controller when the system is going down 551 */ 552 void 553 ehci_detach(ehci_softc_t *sc) 554 { 555 USB_BUS_LOCK(&sc->sc_bus); 556 557 usb_callout_stop(&sc->sc_tmo_pcd); 558 usb_callout_stop(&sc->sc_tmo_poll); 559 560 EOWRITE4(sc, EHCI_USBINTR, 0); 561 USB_BUS_UNLOCK(&sc->sc_bus); 562 563 if (ehci_hcreset(sc)) { 564 DPRINTF("reset failed!\n"); 565 } 566 567 /* XXX let stray task complete */ 568 usb_pause_mtx(NULL, hz / 20); 569 570 usb_callout_drain(&sc->sc_tmo_pcd); 571 usb_callout_drain(&sc->sc_tmo_poll); 572 } 573 574 static void 575 ehci_suspend(ehci_softc_t *sc) 576 { 577 DPRINTF("stopping the HC\n"); 578 579 /* reset HC */ 580 ehci_hcreset(sc); 581 } 582 583 static void 584 ehci_resume(ehci_softc_t *sc) 585 { 586 /* reset HC */ 587 ehci_hcreset(sc); 588 589 /* setup HC */ 590 ehci_init_sub(sc); 591 592 /* catch any lost interrupts */ 593 ehci_do_poll(&sc->sc_bus); 594 } 595 596 #ifdef USB_DEBUG 597 static void 598 ehci_dump_regs(ehci_softc_t *sc) 599 { 600 uint32_t i; 601 602 i = EOREAD4(sc, EHCI_USBCMD); 603 printf("cmd=0x%08x\n", i); 604 605 if (i & EHCI_CMD_ITC_1) 606 printf(" EHCI_CMD_ITC_1\n"); 607 if (i & EHCI_CMD_ITC_2) 608 printf(" EHCI_CMD_ITC_2\n"); 609 if (i & EHCI_CMD_ITC_4) 610 printf(" EHCI_CMD_ITC_4\n"); 611 if (i & EHCI_CMD_ITC_8) 612 printf(" EHCI_CMD_ITC_8\n"); 613 if (i & EHCI_CMD_ITC_16) 614 printf(" EHCI_CMD_ITC_16\n"); 615 if (i & EHCI_CMD_ITC_32) 616 printf(" EHCI_CMD_ITC_32\n"); 617 if (i & EHCI_CMD_ITC_64) 618 printf(" EHCI_CMD_ITC_64\n"); 619 if (i & EHCI_CMD_ASPME) 620 printf(" EHCI_CMD_ASPME\n"); 621 if (i & EHCI_CMD_ASPMC) 622 printf(" EHCI_CMD_ASPMC\n"); 623 if (i & EHCI_CMD_LHCR) 624 printf(" EHCI_CMD_LHCR\n"); 625 if (i & EHCI_CMD_IAAD) 626 printf(" EHCI_CMD_IAAD\n"); 627 if (i & EHCI_CMD_ASE) 628 printf(" EHCI_CMD_ASE\n"); 629 if (i & EHCI_CMD_PSE) 630 printf(" EHCI_CMD_PSE\n"); 631 if (i & EHCI_CMD_FLS_M) 632 printf(" EHCI_CMD_FLS_M\n"); 633 if (i & EHCI_CMD_HCRESET) 634 printf(" EHCI_CMD_HCRESET\n"); 635 if (i & EHCI_CMD_RS) 636 printf(" EHCI_CMD_RS\n"); 637 638 i = EOREAD4(sc, EHCI_USBSTS); 639 640 printf("sts=0x%08x\n", i); 641 642 if (i & EHCI_STS_ASS) 643 printf(" EHCI_STS_ASS\n"); 644 if (i & EHCI_STS_PSS) 645 printf(" EHCI_STS_PSS\n"); 646 if (i & EHCI_STS_REC) 647 printf(" EHCI_STS_REC\n"); 648 if (i & EHCI_STS_HCH) 649 printf(" EHCI_STS_HCH\n"); 650 if (i & EHCI_STS_IAA) 651 printf(" EHCI_STS_IAA\n"); 652 if (i & EHCI_STS_HSE) 653 printf(" EHCI_STS_HSE\n"); 654 if (i & EHCI_STS_FLR) 655 printf(" EHCI_STS_FLR\n"); 656 if (i & EHCI_STS_PCD) 657 printf(" EHCI_STS_PCD\n"); 658 if (i & EHCI_STS_ERRINT) 659 printf(" EHCI_STS_ERRINT\n"); 660 if (i & EHCI_STS_INT) 661 printf(" EHCI_STS_INT\n"); 662 663 printf("ien=0x%08x\n", 664 EOREAD4(sc, EHCI_USBINTR)); 665 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 666 EOREAD4(sc, EHCI_FRINDEX), 667 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 668 EOREAD4(sc, EHCI_PERIODICLISTBASE), 669 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 670 for (i = 1; i <= sc->sc_noport; i++) { 671 printf("port %d status=0x%08x\n", i, 672 EOREAD4(sc, EHCI_PORTSC(i))); 673 } 674 } 675 676 static void 677 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 678 { 679 link = hc32toh(sc, link); 680 printf("0x%08x", link); 681 if (link & EHCI_LINK_TERMINATE) 682 printf("<T>"); 683 else { 684 printf("<"); 685 if (type) { 686 switch (EHCI_LINK_TYPE(link)) { 687 case EHCI_LINK_ITD: 688 printf("ITD"); 689 break; 690 case EHCI_LINK_QH: 691 printf("QH"); 692 break; 693 case EHCI_LINK_SITD: 694 printf("SITD"); 695 break; 696 case EHCI_LINK_FSTN: 697 printf("FSTN"); 698 break; 699 } 700 } 701 printf(">"); 702 } 703 } 704 705 static void 706 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 707 { 708 uint32_t s; 709 710 printf(" next="); 711 ehci_dump_link(sc, qtd->qtd_next, 0); 712 printf(" altnext="); 713 ehci_dump_link(sc, qtd->qtd_altnext, 0); 714 printf("\n"); 715 s = hc32toh(sc, qtd->qtd_status); 716 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 717 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 718 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 719 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 720 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 721 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 722 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 723 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 724 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 725 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 726 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 727 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 728 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 729 730 for (s = 0; s < 5; s++) { 731 printf(" buffer[%d]=0x%08x\n", s, 732 hc32toh(sc, qtd->qtd_buffer[s])); 733 } 734 for (s = 0; s < 5; s++) { 735 printf(" buffer_hi[%d]=0x%08x\n", s, 736 hc32toh(sc, qtd->qtd_buffer_hi[s])); 737 } 738 } 739 740 static uint8_t 741 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 742 { 743 uint8_t temp; 744 745 usb_pc_cpu_invalidate(sqtd->page_cache); 746 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 747 ehci_dump_qtd(sc, sqtd); 748 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 749 return (temp); 750 } 751 752 static void 753 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 754 { 755 uint16_t i; 756 uint8_t stop; 757 758 stop = 0; 759 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 760 stop = ehci_dump_sqtd(sc, sqtd); 761 } 762 if (sqtd) { 763 printf("dump aborted, too many TDs\n"); 764 } 765 } 766 767 static void 768 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 769 { 770 uint32_t endp; 771 uint32_t endphub; 772 773 usb_pc_cpu_invalidate(qh->page_cache); 774 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 775 printf(" link="); 776 ehci_dump_link(sc, qh->qh_link, 1); 777 printf("\n"); 778 endp = hc32toh(sc, qh->qh_endp); 779 printf(" endp=0x%08x\n", endp); 780 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 781 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 782 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 783 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 784 printf(" mpl=0x%x ctl=%d nrl=%d\n", 785 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 786 EHCI_QH_GET_NRL(endp)); 787 endphub = hc32toh(sc, qh->qh_endphub); 788 printf(" endphub=0x%08x\n", endphub); 789 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 790 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 791 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 792 EHCI_QH_GET_MULT(endphub)); 793 printf(" curqtd="); 794 ehci_dump_link(sc, qh->qh_curqtd, 0); 795 printf("\n"); 796 printf("Overlay qTD:\n"); 797 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 798 } 799 800 static void 801 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 802 { 803 usb_pc_cpu_invalidate(sitd->page_cache); 804 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 805 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 806 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 807 hc32toh(sc, sitd->sitd_portaddr), 808 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 809 ? "in" : "out", 810 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 811 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 812 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 813 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 814 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 815 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 816 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 817 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 818 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 819 hc32toh(sc, sitd->sitd_back), 820 hc32toh(sc, sitd->sitd_bp[0]), 821 hc32toh(sc, sitd->sitd_bp[1]), 822 hc32toh(sc, sitd->sitd_bp_hi[0]), 823 hc32toh(sc, sitd->sitd_bp_hi[1])); 824 } 825 826 static void 827 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 828 { 829 usb_pc_cpu_invalidate(itd->page_cache); 830 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 831 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 832 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 833 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 834 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 835 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 836 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 837 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 838 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 839 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 840 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 841 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 842 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 843 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 844 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 845 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 846 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 847 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 848 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 849 printf(" addr=0x%02x; endpt=0x%01x\n", 850 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 851 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 852 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 853 printf(" dir=%s; mpl=0x%02x\n", 854 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 855 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 856 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 857 hc32toh(sc, itd->itd_bp[2]), 858 hc32toh(sc, itd->itd_bp[3]), 859 hc32toh(sc, itd->itd_bp[4]), 860 hc32toh(sc, itd->itd_bp[5]), 861 hc32toh(sc, itd->itd_bp[6])); 862 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 863 " 0x%08x,0x%08x,0x%08x\n", 864 hc32toh(sc, itd->itd_bp_hi[0]), 865 hc32toh(sc, itd->itd_bp_hi[1]), 866 hc32toh(sc, itd->itd_bp_hi[2]), 867 hc32toh(sc, itd->itd_bp_hi[3]), 868 hc32toh(sc, itd->itd_bp_hi[4]), 869 hc32toh(sc, itd->itd_bp_hi[5]), 870 hc32toh(sc, itd->itd_bp_hi[6])); 871 } 872 873 static void 874 ehci_dump_isoc(ehci_softc_t *sc) 875 { 876 ehci_itd_t *itd; 877 ehci_sitd_t *sitd; 878 uint16_t max = 1000; 879 uint16_t pos; 880 881 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 882 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 883 884 printf("%s: isochronous dump from frame 0x%03x:\n", 885 __FUNCTION__, pos); 886 887 itd = sc->sc_isoc_hs_p_last[pos]; 888 sitd = sc->sc_isoc_fs_p_last[pos]; 889 890 while (itd && max && max--) { 891 ehci_dump_itd(sc, itd); 892 itd = itd->prev; 893 } 894 895 while (sitd && max && max--) { 896 ehci_dump_sitd(sc, sitd); 897 sitd = sitd->prev; 898 } 899 } 900 901 #endif 902 903 static void 904 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 905 { 906 /* check for early completion */ 907 if (ehci_check_transfer(xfer)) { 908 return; 909 } 910 /* put transfer on interrupt queue */ 911 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 912 913 /* start timeout, if any */ 914 if (xfer->timeout != 0) { 915 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 916 } 917 } 918 919 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 920 static ehci_sitd_t * 921 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 922 { 923 DPRINTFN(11, "%p to %p\n", std, last); 924 925 /* (sc->sc_bus.mtx) must be locked */ 926 927 std->next = last->next; 928 std->sitd_next = last->sitd_next; 929 930 std->prev = last; 931 932 usb_pc_cpu_flush(std->page_cache); 933 934 /* 935 * the last->next->prev is never followed: std->next->prev = std; 936 */ 937 last->next = std; 938 last->sitd_next = std->sitd_self; 939 940 usb_pc_cpu_flush(last->page_cache); 941 942 return (std); 943 } 944 945 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 946 static ehci_itd_t * 947 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 948 { 949 DPRINTFN(11, "%p to %p\n", std, last); 950 951 /* (sc->sc_bus.mtx) must be locked */ 952 953 std->next = last->next; 954 std->itd_next = last->itd_next; 955 956 std->prev = last; 957 958 usb_pc_cpu_flush(std->page_cache); 959 960 /* 961 * the last->next->prev is never followed: std->next->prev = std; 962 */ 963 last->next = std; 964 last->itd_next = std->itd_self; 965 966 usb_pc_cpu_flush(last->page_cache); 967 968 return (std); 969 } 970 971 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 972 static ehci_qh_t * 973 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 974 { 975 DPRINTFN(11, "%p to %p\n", sqh, last); 976 977 if (sqh->prev != NULL) { 978 /* should not happen */ 979 DPRINTFN(0, "QH already linked!\n"); 980 return (last); 981 } 982 /* (sc->sc_bus.mtx) must be locked */ 983 984 sqh->next = last->next; 985 sqh->qh_link = last->qh_link; 986 987 sqh->prev = last; 988 989 usb_pc_cpu_flush(sqh->page_cache); 990 991 /* 992 * the last->next->prev is never followed: sqh->next->prev = sqh; 993 */ 994 995 last->next = sqh; 996 last->qh_link = sqh->qh_self; 997 998 usb_pc_cpu_flush(last->page_cache); 999 1000 return (sqh); 1001 } 1002 1003 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1004 static ehci_sitd_t * 1005 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1006 { 1007 DPRINTFN(11, "%p from %p\n", std, last); 1008 1009 /* (sc->sc_bus.mtx) must be locked */ 1010 1011 std->prev->next = std->next; 1012 std->prev->sitd_next = std->sitd_next; 1013 1014 usb_pc_cpu_flush(std->prev->page_cache); 1015 1016 if (std->next) { 1017 std->next->prev = std->prev; 1018 usb_pc_cpu_flush(std->next->page_cache); 1019 } 1020 return ((last == std) ? std->prev : last); 1021 } 1022 1023 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1024 static ehci_itd_t * 1025 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1026 { 1027 DPRINTFN(11, "%p from %p\n", std, last); 1028 1029 /* (sc->sc_bus.mtx) must be locked */ 1030 1031 std->prev->next = std->next; 1032 std->prev->itd_next = std->itd_next; 1033 1034 usb_pc_cpu_flush(std->prev->page_cache); 1035 1036 if (std->next) { 1037 std->next->prev = std->prev; 1038 usb_pc_cpu_flush(std->next->page_cache); 1039 } 1040 return ((last == std) ? std->prev : last); 1041 } 1042 1043 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1044 static ehci_qh_t * 1045 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1046 { 1047 DPRINTFN(11, "%p from %p\n", sqh, last); 1048 1049 /* (sc->sc_bus.mtx) must be locked */ 1050 1051 /* only remove if not removed from a queue */ 1052 if (sqh->prev) { 1053 sqh->prev->next = sqh->next; 1054 sqh->prev->qh_link = sqh->qh_link; 1055 1056 usb_pc_cpu_flush(sqh->prev->page_cache); 1057 1058 if (sqh->next) { 1059 sqh->next->prev = sqh->prev; 1060 usb_pc_cpu_flush(sqh->next->page_cache); 1061 } 1062 last = ((last == sqh) ? sqh->prev : last); 1063 1064 sqh->prev = 0; 1065 1066 usb_pc_cpu_flush(sqh->page_cache); 1067 } 1068 return (last); 1069 } 1070 1071 static void 1072 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1073 { 1074 uint16_t rem; 1075 uint8_t dt; 1076 1077 /* count number of full packets */ 1078 dt = (actlen / xfer->max_packet_size) & 1; 1079 1080 /* compute remainder */ 1081 rem = actlen % xfer->max_packet_size; 1082 1083 if (rem > 0) 1084 dt ^= 1; /* short packet at the end */ 1085 else if (actlen != xlen) 1086 dt ^= 1; /* zero length packet at the end */ 1087 else if (xlen == 0) 1088 dt ^= 1; /* zero length transfer */ 1089 1090 xfer->endpoint->toggle_next ^= dt; 1091 } 1092 1093 static usb_error_t 1094 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1095 { 1096 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1097 ehci_qtd_t *td; 1098 ehci_qtd_t *td_alt_next; 1099 uint32_t status; 1100 uint16_t len; 1101 1102 td = xfer->td_transfer_cache; 1103 td_alt_next = td->alt_next; 1104 1105 if (xfer->aframes != xfer->nframes) { 1106 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1107 } 1108 while (1) { 1109 usb_pc_cpu_invalidate(td->page_cache); 1110 status = hc32toh(sc, td->qtd_status); 1111 1112 len = EHCI_QTD_GET_BYTES(status); 1113 1114 /* 1115 * Verify the status length and 1116 * add the length to "frlengths[]": 1117 */ 1118 if (len > td->len) { 1119 /* should not happen */ 1120 DPRINTF("Invalid status length, " 1121 "0x%04x/0x%04x bytes\n", len, td->len); 1122 status |= EHCI_QTD_HALTED; 1123 } else if (xfer->aframes != xfer->nframes) { 1124 xfer->frlengths[xfer->aframes] += td->len - len; 1125 /* manually update data toggle */ 1126 ehci_data_toggle_update(xfer, td->len - len, td->len); 1127 } 1128 1129 /* Check for last transfer */ 1130 if (((void *)td) == xfer->td_transfer_last) { 1131 td = NULL; 1132 break; 1133 } 1134 /* Check for transfer error */ 1135 if (status & EHCI_QTD_HALTED) { 1136 /* the transfer is finished */ 1137 td = NULL; 1138 break; 1139 } 1140 /* Check for short transfer */ 1141 if (len > 0) { 1142 if (xfer->flags_int.short_frames_ok) { 1143 /* follow alt next */ 1144 td = td->alt_next; 1145 } else { 1146 /* the transfer is finished */ 1147 td = NULL; 1148 } 1149 break; 1150 } 1151 td = td->obj_next; 1152 1153 if (td->alt_next != td_alt_next) { 1154 /* this USB frame is complete */ 1155 break; 1156 } 1157 } 1158 1159 /* update transfer cache */ 1160 1161 xfer->td_transfer_cache = td; 1162 1163 #ifdef USB_DEBUG 1164 if (status & EHCI_QTD_STATERRS) { 1165 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1166 "status=%s%s%s%s%s%s%s%s\n", 1167 xfer->address, xfer->endpointno, xfer->aframes, 1168 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1169 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1170 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1171 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1172 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1173 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1174 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1175 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1176 } 1177 #endif 1178 if (status & EHCI_QTD_HALTED) { 1179 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1180 (xfer->xroot->udev->address != 0)) { 1181 /* try to separate I/O errors from STALL */ 1182 if (EHCI_QTD_GET_CERR(status) == 0) 1183 return (USB_ERR_IOERROR); 1184 } 1185 return (USB_ERR_STALLED); 1186 } 1187 return (USB_ERR_NORMAL_COMPLETION); 1188 } 1189 1190 static void 1191 ehci_non_isoc_done(struct usb_xfer *xfer) 1192 { 1193 ehci_qh_t *qh; 1194 usb_error_t err = 0; 1195 1196 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1197 xfer, xfer->endpoint); 1198 1199 #ifdef USB_DEBUG 1200 if (ehcidebug > 10) { 1201 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1202 1203 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1204 } 1205 #endif 1206 1207 /* extract data toggle directly from the QH's overlay area */ 1208 1209 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1210 1211 usb_pc_cpu_invalidate(qh->page_cache); 1212 1213 /* reset scanner */ 1214 1215 xfer->td_transfer_cache = xfer->td_transfer_first; 1216 1217 if (xfer->flags_int.control_xfr) { 1218 if (xfer->flags_int.control_hdr) { 1219 err = ehci_non_isoc_done_sub(xfer); 1220 } 1221 xfer->aframes = 1; 1222 1223 if (xfer->td_transfer_cache == NULL) { 1224 goto done; 1225 } 1226 } 1227 while (xfer->aframes != xfer->nframes) { 1228 err = ehci_non_isoc_done_sub(xfer); 1229 xfer->aframes++; 1230 1231 if (xfer->td_transfer_cache == NULL) { 1232 goto done; 1233 } 1234 } 1235 1236 if (xfer->flags_int.control_xfr && 1237 !xfer->flags_int.control_act) { 1238 err = ehci_non_isoc_done_sub(xfer); 1239 } 1240 done: 1241 ehci_device_done(xfer, err); 1242 } 1243 1244 /*------------------------------------------------------------------------* 1245 * ehci_check_transfer 1246 * 1247 * Return values: 1248 * 0: USB transfer is not finished 1249 * Else: USB transfer is finished 1250 *------------------------------------------------------------------------*/ 1251 static uint8_t 1252 ehci_check_transfer(struct usb_xfer *xfer) 1253 { 1254 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1255 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1256 1257 uint32_t status; 1258 1259 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1260 1261 if (methods == &ehci_device_isoc_fs_methods) { 1262 ehci_sitd_t *td; 1263 1264 /* isochronous full speed transfer */ 1265 1266 td = xfer->td_transfer_last; 1267 usb_pc_cpu_invalidate(td->page_cache); 1268 status = hc32toh(sc, td->sitd_status); 1269 1270 /* also check if first is complete */ 1271 1272 td = xfer->td_transfer_first; 1273 usb_pc_cpu_invalidate(td->page_cache); 1274 status |= hc32toh(sc, td->sitd_status); 1275 1276 if (!(status & EHCI_SITD_ACTIVE)) { 1277 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1278 goto transferred; 1279 } 1280 } else if (methods == &ehci_device_isoc_hs_methods) { 1281 ehci_itd_t *td; 1282 1283 /* isochronous high speed transfer */ 1284 1285 /* check last transfer */ 1286 td = xfer->td_transfer_last; 1287 usb_pc_cpu_invalidate(td->page_cache); 1288 status = td->itd_status[0]; 1289 status |= td->itd_status[1]; 1290 status |= td->itd_status[2]; 1291 status |= td->itd_status[3]; 1292 status |= td->itd_status[4]; 1293 status |= td->itd_status[5]; 1294 status |= td->itd_status[6]; 1295 status |= td->itd_status[7]; 1296 1297 /* also check first transfer */ 1298 td = xfer->td_transfer_first; 1299 usb_pc_cpu_invalidate(td->page_cache); 1300 status |= td->itd_status[0]; 1301 status |= td->itd_status[1]; 1302 status |= td->itd_status[2]; 1303 status |= td->itd_status[3]; 1304 status |= td->itd_status[4]; 1305 status |= td->itd_status[5]; 1306 status |= td->itd_status[6]; 1307 status |= td->itd_status[7]; 1308 1309 /* if no transactions are active we continue */ 1310 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1311 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1312 goto transferred; 1313 } 1314 } else { 1315 ehci_qtd_t *td; 1316 ehci_qh_t *qh; 1317 1318 /* non-isochronous transfer */ 1319 1320 /* 1321 * check whether there is an error somewhere in the middle, 1322 * or whether there was a short packet (SPD and not ACTIVE) 1323 */ 1324 td = xfer->td_transfer_cache; 1325 1326 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1327 1328 usb_pc_cpu_invalidate(qh->page_cache); 1329 1330 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1331 if (status & EHCI_QTD_ACTIVE) { 1332 /* transfer is pending */ 1333 goto done; 1334 } 1335 1336 while (1) { 1337 usb_pc_cpu_invalidate(td->page_cache); 1338 status = hc32toh(sc, td->qtd_status); 1339 1340 /* 1341 * Check if there is an active TD which 1342 * indicates that the transfer isn't done. 1343 */ 1344 if (status & EHCI_QTD_ACTIVE) { 1345 /* update cache */ 1346 xfer->td_transfer_cache = td; 1347 goto done; 1348 } 1349 /* 1350 * last transfer descriptor makes the transfer done 1351 */ 1352 if (((void *)td) == xfer->td_transfer_last) { 1353 break; 1354 } 1355 /* 1356 * any kind of error makes the transfer done 1357 */ 1358 if (status & EHCI_QTD_HALTED) { 1359 break; 1360 } 1361 /* 1362 * if there is no alternate next transfer, a short 1363 * packet also makes the transfer done 1364 */ 1365 if (EHCI_QTD_GET_BYTES(status)) { 1366 if (xfer->flags_int.short_frames_ok) { 1367 /* follow alt next */ 1368 if (td->alt_next) { 1369 td = td->alt_next; 1370 continue; 1371 } 1372 } 1373 /* transfer is done */ 1374 break; 1375 } 1376 td = td->obj_next; 1377 } 1378 ehci_non_isoc_done(xfer); 1379 goto transferred; 1380 } 1381 1382 done: 1383 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1384 return (0); 1385 1386 transferred: 1387 return (1); 1388 } 1389 1390 static void 1391 ehci_pcd_enable(ehci_softc_t *sc) 1392 { 1393 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1394 1395 sc->sc_eintrs |= EHCI_STS_PCD; 1396 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1397 1398 /* acknowledge any PCD interrupt */ 1399 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1400 1401 ehci_root_intr(sc); 1402 } 1403 1404 static void 1405 ehci_interrupt_poll(ehci_softc_t *sc) 1406 { 1407 struct usb_xfer *xfer; 1408 1409 repeat: 1410 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1411 /* 1412 * check if transfer is transferred 1413 */ 1414 if (ehci_check_transfer(xfer)) { 1415 /* queue has been modified */ 1416 goto repeat; 1417 } 1418 } 1419 } 1420 1421 /* 1422 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1423 * writing back the qTD status, or miss signalling occasionally under 1424 * heavy load. If the host machine is too fast, we can miss 1425 * transaction completion - when we scan the active list the 1426 * transaction still seems to be active. This generally exhibits 1427 * itself as a umass stall that never recovers. 1428 * 1429 * We work around this behaviour by setting up this callback after any 1430 * softintr that completes with transactions still pending, giving us 1431 * another chance to check for completion after the writeback has 1432 * taken place. 1433 */ 1434 static void 1435 ehci_poll_timeout(void *arg) 1436 { 1437 ehci_softc_t *sc = arg; 1438 1439 DPRINTFN(3, "\n"); 1440 ehci_interrupt_poll(sc); 1441 } 1442 1443 /*------------------------------------------------------------------------* 1444 * ehci_interrupt - EHCI interrupt handler 1445 * 1446 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1447 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1448 * is present ! 1449 *------------------------------------------------------------------------*/ 1450 void 1451 ehci_interrupt(ehci_softc_t *sc) 1452 { 1453 uint32_t status; 1454 1455 USB_BUS_LOCK(&sc->sc_bus); 1456 1457 DPRINTFN(16, "real interrupt\n"); 1458 1459 #ifdef USB_DEBUG 1460 if (ehcidebug > 15) { 1461 ehci_dump_regs(sc); 1462 } 1463 #endif 1464 1465 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1466 if (status == 0) { 1467 /* the interrupt was not for us */ 1468 goto done; 1469 } 1470 if (!(status & sc->sc_eintrs)) { 1471 goto done; 1472 } 1473 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1474 1475 status &= sc->sc_eintrs; 1476 1477 if (status & EHCI_STS_HSE) { 1478 printf("%s: unrecoverable error, " 1479 "controller halted\n", __FUNCTION__); 1480 #ifdef USB_DEBUG 1481 ehci_dump_regs(sc); 1482 ehci_dump_isoc(sc); 1483 #endif 1484 } 1485 if (status & EHCI_STS_PCD) { 1486 /* 1487 * Disable PCD interrupt for now, because it will be 1488 * on until the port has been reset. 1489 */ 1490 sc->sc_eintrs &= ~EHCI_STS_PCD; 1491 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1492 1493 ehci_root_intr(sc); 1494 1495 /* do not allow RHSC interrupts > 1 per second */ 1496 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1497 (void *)&ehci_pcd_enable, sc); 1498 } 1499 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1500 1501 if (status != 0) { 1502 /* block unprocessed interrupts */ 1503 sc->sc_eintrs &= ~status; 1504 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1505 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1506 } 1507 /* poll all the USB transfers */ 1508 ehci_interrupt_poll(sc); 1509 1510 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1511 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1512 (void *)&ehci_poll_timeout, sc); 1513 } 1514 1515 done: 1516 USB_BUS_UNLOCK(&sc->sc_bus); 1517 } 1518 1519 /* 1520 * called when a request does not complete 1521 */ 1522 static void 1523 ehci_timeout(void *arg) 1524 { 1525 struct usb_xfer *xfer = arg; 1526 1527 DPRINTF("xfer=%p\n", xfer); 1528 1529 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1530 1531 /* transfer is transferred */ 1532 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1533 } 1534 1535 static void 1536 ehci_do_poll(struct usb_bus *bus) 1537 { 1538 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1539 1540 USB_BUS_LOCK(&sc->sc_bus); 1541 ehci_interrupt_poll(sc); 1542 USB_BUS_UNLOCK(&sc->sc_bus); 1543 } 1544 1545 static void 1546 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1547 { 1548 struct usb_page_search buf_res; 1549 ehci_qtd_t *td; 1550 ehci_qtd_t *td_next; 1551 ehci_qtd_t *td_alt_next; 1552 uint32_t buf_offset; 1553 uint32_t average; 1554 uint32_t len_old; 1555 uint32_t terminate; 1556 uint32_t qtd_altnext; 1557 uint8_t shortpkt_old; 1558 uint8_t precompute; 1559 1560 terminate = temp->sc->sc_terminate_self; 1561 qtd_altnext = temp->sc->sc_terminate_self; 1562 td_alt_next = NULL; 1563 buf_offset = 0; 1564 shortpkt_old = temp->shortpkt; 1565 len_old = temp->len; 1566 precompute = 1; 1567 1568 restart: 1569 1570 td = temp->td; 1571 td_next = temp->td_next; 1572 1573 while (1) { 1574 if (temp->len == 0) { 1575 if (temp->shortpkt) { 1576 break; 1577 } 1578 /* send a Zero Length Packet, ZLP, last */ 1579 1580 temp->shortpkt = 1; 1581 average = 0; 1582 1583 } else { 1584 average = temp->average; 1585 1586 if (temp->len < average) { 1587 if (temp->len % temp->max_frame_size) { 1588 temp->shortpkt = 1; 1589 } 1590 average = temp->len; 1591 } 1592 } 1593 1594 if (td_next == NULL) { 1595 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1596 } 1597 /* get next TD */ 1598 1599 td = td_next; 1600 td_next = td->obj_next; 1601 1602 /* check if we are pre-computing */ 1603 1604 if (precompute) { 1605 /* update remaining length */ 1606 1607 temp->len -= average; 1608 1609 continue; 1610 } 1611 /* fill out current TD */ 1612 1613 td->qtd_status = 1614 temp->qtd_status | 1615 htohc32(temp->sc, EHCI_QTD_IOC | 1616 EHCI_QTD_SET_BYTES(average)); 1617 1618 if (average == 0) { 1619 if (temp->auto_data_toggle == 0) { 1620 /* update data toggle, ZLP case */ 1621 1622 temp->qtd_status ^= 1623 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1624 } 1625 td->len = 0; 1626 1627 /* properly reset reserved fields */ 1628 td->qtd_buffer[0] = 0; 1629 td->qtd_buffer[1] = 0; 1630 td->qtd_buffer[2] = 0; 1631 td->qtd_buffer[3] = 0; 1632 td->qtd_buffer[4] = 0; 1633 td->qtd_buffer_hi[0] = 0; 1634 td->qtd_buffer_hi[1] = 0; 1635 td->qtd_buffer_hi[2] = 0; 1636 td->qtd_buffer_hi[3] = 0; 1637 td->qtd_buffer_hi[4] = 0; 1638 } else { 1639 uint8_t x; 1640 1641 if (temp->auto_data_toggle == 0) { 1642 /* update data toggle */ 1643 1644 if (howmany(average, temp->max_frame_size) & 1) { 1645 temp->qtd_status ^= 1646 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1647 } 1648 } 1649 td->len = average; 1650 1651 /* update remaining length */ 1652 1653 temp->len -= average; 1654 1655 /* fill out buffer pointers */ 1656 1657 usbd_get_page(temp->pc, buf_offset, &buf_res); 1658 td->qtd_buffer[0] = 1659 htohc32(temp->sc, buf_res.physaddr); 1660 td->qtd_buffer_hi[0] = 0; 1661 1662 x = 1; 1663 1664 while (average > EHCI_PAGE_SIZE) { 1665 average -= EHCI_PAGE_SIZE; 1666 buf_offset += EHCI_PAGE_SIZE; 1667 usbd_get_page(temp->pc, buf_offset, &buf_res); 1668 td->qtd_buffer[x] = 1669 htohc32(temp->sc, 1670 buf_res.physaddr & (~0xFFF)); 1671 td->qtd_buffer_hi[x] = 0; 1672 x++; 1673 } 1674 1675 /* 1676 * NOTE: The "average" variable is never zero after 1677 * exiting the loop above ! 1678 * 1679 * NOTE: We have to subtract one from the offset to 1680 * ensure that we are computing the physical address 1681 * of a valid page ! 1682 */ 1683 buf_offset += average; 1684 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1685 td->qtd_buffer[x] = 1686 htohc32(temp->sc, 1687 buf_res.physaddr & (~0xFFF)); 1688 td->qtd_buffer_hi[x] = 0; 1689 1690 /* properly reset reserved fields */ 1691 while (++x < EHCI_QTD_NBUFFERS) { 1692 td->qtd_buffer[x] = 0; 1693 td->qtd_buffer_hi[x] = 0; 1694 } 1695 } 1696 1697 if (td_next) { 1698 /* link the current TD with the next one */ 1699 td->qtd_next = td_next->qtd_self; 1700 } 1701 td->qtd_altnext = qtd_altnext; 1702 td->alt_next = td_alt_next; 1703 1704 usb_pc_cpu_flush(td->page_cache); 1705 } 1706 1707 if (precompute) { 1708 precompute = 0; 1709 1710 /* setup alt next pointer, if any */ 1711 if (temp->last_frame) { 1712 td_alt_next = NULL; 1713 qtd_altnext = terminate; 1714 } else { 1715 /* we use this field internally */ 1716 td_alt_next = td_next; 1717 if (temp->setup_alt_next) { 1718 qtd_altnext = td_next->qtd_self; 1719 } else { 1720 qtd_altnext = terminate; 1721 } 1722 } 1723 1724 /* restore */ 1725 temp->shortpkt = shortpkt_old; 1726 temp->len = len_old; 1727 goto restart; 1728 } 1729 temp->td = td; 1730 temp->td_next = td_next; 1731 } 1732 1733 static void 1734 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1735 { 1736 struct ehci_std_temp temp; 1737 const struct usb_pipe_methods *methods; 1738 ehci_qh_t *qh; 1739 ehci_qtd_t *td; 1740 uint32_t qh_endp; 1741 uint32_t qh_endphub; 1742 uint32_t x; 1743 1744 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1745 xfer->address, UE_GET_ADDR(xfer->endpointno), 1746 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1747 1748 temp.average = xfer->max_hc_frame_size; 1749 temp.max_frame_size = xfer->max_frame_size; 1750 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1751 1752 /* toggle the DMA set we are using */ 1753 xfer->flags_int.curr_dma_set ^= 1; 1754 1755 /* get next DMA set */ 1756 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1757 1758 xfer->td_transfer_first = td; 1759 xfer->td_transfer_cache = td; 1760 1761 temp.td = NULL; 1762 temp.td_next = td; 1763 temp.qtd_status = 0; 1764 temp.last_frame = 0; 1765 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1766 1767 if (xfer->flags_int.control_xfr) { 1768 if (xfer->endpoint->toggle_next) { 1769 /* DATA1 is next */ 1770 temp.qtd_status |= 1771 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1772 } 1773 temp.auto_data_toggle = 0; 1774 } else { 1775 temp.auto_data_toggle = 1; 1776 } 1777 1778 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1779 (xfer->xroot->udev->address != 0)) { 1780 /* max 3 retries */ 1781 temp.qtd_status |= 1782 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1783 } 1784 /* check if we should prepend a setup message */ 1785 1786 if (xfer->flags_int.control_xfr) { 1787 if (xfer->flags_int.control_hdr) { 1788 xfer->endpoint->toggle_next = 0; 1789 1790 temp.qtd_status &= 1791 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1792 temp.qtd_status |= htohc32(temp.sc, 1793 EHCI_QTD_ACTIVE | 1794 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1795 EHCI_QTD_SET_TOGGLE(0)); 1796 1797 temp.len = xfer->frlengths[0]; 1798 temp.pc = xfer->frbuffers + 0; 1799 temp.shortpkt = temp.len ? 1 : 0; 1800 /* check for last frame */ 1801 if (xfer->nframes == 1) { 1802 /* no STATUS stage yet, SETUP is last */ 1803 if (xfer->flags_int.control_act) { 1804 temp.last_frame = 1; 1805 temp.setup_alt_next = 0; 1806 } 1807 } 1808 ehci_setup_standard_chain_sub(&temp); 1809 } 1810 x = 1; 1811 } else { 1812 x = 0; 1813 } 1814 1815 while (x != xfer->nframes) { 1816 /* DATA0 / DATA1 message */ 1817 1818 temp.len = xfer->frlengths[x]; 1819 temp.pc = xfer->frbuffers + x; 1820 1821 x++; 1822 1823 if (x == xfer->nframes) { 1824 if (xfer->flags_int.control_xfr) { 1825 /* no STATUS stage yet, DATA is last */ 1826 if (xfer->flags_int.control_act) { 1827 temp.last_frame = 1; 1828 temp.setup_alt_next = 0; 1829 } 1830 } else { 1831 temp.last_frame = 1; 1832 temp.setup_alt_next = 0; 1833 } 1834 } 1835 /* keep previous data toggle and error count */ 1836 1837 temp.qtd_status &= 1838 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1839 EHCI_QTD_SET_TOGGLE(1)); 1840 1841 if (temp.len == 0) { 1842 /* make sure that we send an USB packet */ 1843 1844 temp.shortpkt = 0; 1845 1846 } else { 1847 /* regular data transfer */ 1848 1849 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1850 } 1851 1852 /* set endpoint direction */ 1853 1854 temp.qtd_status |= 1855 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1856 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1857 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1858 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1859 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1860 1861 ehci_setup_standard_chain_sub(&temp); 1862 } 1863 1864 /* check if we should append a status stage */ 1865 1866 if (xfer->flags_int.control_xfr && 1867 !xfer->flags_int.control_act) { 1868 /* 1869 * Send a DATA1 message and invert the current endpoint 1870 * direction. 1871 */ 1872 1873 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1874 EHCI_QTD_SET_TOGGLE(1)); 1875 temp.qtd_status |= 1876 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1877 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1878 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1879 EHCI_QTD_SET_TOGGLE(1)) : 1880 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1881 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1882 EHCI_QTD_SET_TOGGLE(1)); 1883 1884 temp.len = 0; 1885 temp.pc = NULL; 1886 temp.shortpkt = 0; 1887 temp.last_frame = 1; 1888 temp.setup_alt_next = 0; 1889 1890 ehci_setup_standard_chain_sub(&temp); 1891 } 1892 td = temp.td; 1893 1894 /* the last TD terminates the transfer: */ 1895 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1896 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1897 1898 usb_pc_cpu_flush(td->page_cache); 1899 1900 /* must have at least one frame! */ 1901 1902 xfer->td_transfer_last = td; 1903 1904 #ifdef USB_DEBUG 1905 if (ehcidebug > 8) { 1906 DPRINTF("nexttog=%d; data before transfer:\n", 1907 xfer->endpoint->toggle_next); 1908 ehci_dump_sqtds(temp.sc, 1909 xfer->td_transfer_first); 1910 } 1911 #endif 1912 1913 methods = xfer->endpoint->methods; 1914 1915 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1916 1917 /* the "qh_link" field is filled when the QH is added */ 1918 1919 qh_endp = 1920 (EHCI_QH_SET_ADDR(xfer->address) | 1921 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1922 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1923 1924 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1925 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1926 if (methods != &ehci_device_intr_methods) 1927 qh_endp |= EHCI_QH_SET_NRL(8); 1928 } else { 1929 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1930 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1931 } else { 1932 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1933 } 1934 1935 if (methods == &ehci_device_ctrl_methods) { 1936 qh_endp |= EHCI_QH_CTL; 1937 } 1938 if (methods != &ehci_device_intr_methods) { 1939 /* Only try one time per microframe! */ 1940 qh_endp |= EHCI_QH_SET_NRL(1); 1941 } 1942 } 1943 1944 if (temp.auto_data_toggle == 0) { 1945 /* software computes the data toggle */ 1946 qh_endp |= EHCI_QH_DTC; 1947 } 1948 1949 qh->qh_endp = htohc32(temp.sc, qh_endp); 1950 1951 qh_endphub = 1952 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1953 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1954 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1955 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1956 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1957 1958 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1959 qh->qh_curqtd = 0; 1960 1961 /* fill the overlay qTD */ 1962 1963 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1964 /* DATA1 is next */ 1965 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1966 } else { 1967 qh->qh_qtd.qtd_status = 0; 1968 } 1969 1970 td = xfer->td_transfer_first; 1971 1972 qh->qh_qtd.qtd_next = td->qtd_self; 1973 qh->qh_qtd.qtd_altnext = 1974 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1975 1976 /* properly reset reserved fields */ 1977 qh->qh_qtd.qtd_buffer[0] = 0; 1978 qh->qh_qtd.qtd_buffer[1] = 0; 1979 qh->qh_qtd.qtd_buffer[2] = 0; 1980 qh->qh_qtd.qtd_buffer[3] = 0; 1981 qh->qh_qtd.qtd_buffer[4] = 0; 1982 qh->qh_qtd.qtd_buffer_hi[0] = 0; 1983 qh->qh_qtd.qtd_buffer_hi[1] = 0; 1984 qh->qh_qtd.qtd_buffer_hi[2] = 0; 1985 qh->qh_qtd.qtd_buffer_hi[3] = 0; 1986 qh->qh_qtd.qtd_buffer_hi[4] = 0; 1987 1988 usb_pc_cpu_flush(qh->page_cache); 1989 1990 if (xfer->xroot->udev->flags.self_suspended == 0) { 1991 EHCI_APPEND_QH(qh, *qh_last); 1992 } 1993 } 1994 1995 static void 1996 ehci_root_intr(ehci_softc_t *sc) 1997 { 1998 uint16_t i; 1999 uint16_t m; 2000 2001 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2002 2003 /* clear any old interrupt data */ 2004 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2005 2006 /* set bits */ 2007 m = (sc->sc_noport + 1); 2008 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2009 m = (8 * sizeof(sc->sc_hub_idata)); 2010 } 2011 for (i = 1; i < m; i++) { 2012 /* pick out CHANGE bits from the status register */ 2013 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2014 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2015 DPRINTF("port %d changed\n", i); 2016 } 2017 } 2018 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2019 sizeof(sc->sc_hub_idata)); 2020 } 2021 2022 static void 2023 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2024 { 2025 uint32_t nframes = xfer->nframes; 2026 uint32_t status; 2027 uint32_t *plen = xfer->frlengths; 2028 uint16_t len = 0; 2029 ehci_sitd_t *td = xfer->td_transfer_first; 2030 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2031 2032 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2033 xfer, xfer->endpoint); 2034 2035 while (nframes--) { 2036 if (td == NULL) { 2037 panic("%s:%d: out of TD's\n", 2038 __FUNCTION__, __LINE__); 2039 } 2040 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2041 pp_last = &sc->sc_isoc_fs_p_last[0]; 2042 } 2043 #ifdef USB_DEBUG 2044 if (ehcidebug > 15) { 2045 DPRINTF("isoc FS-TD\n"); 2046 ehci_dump_sitd(sc, td); 2047 } 2048 #endif 2049 usb_pc_cpu_invalidate(td->page_cache); 2050 status = hc32toh(sc, td->sitd_status); 2051 2052 len = EHCI_SITD_GET_LEN(status); 2053 2054 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2055 2056 if (*plen >= len) { 2057 len = *plen - len; 2058 } else { 2059 len = 0; 2060 } 2061 2062 *plen = len; 2063 2064 /* remove FS-TD from schedule */ 2065 EHCI_REMOVE_FS_TD(td, *pp_last); 2066 2067 pp_last++; 2068 plen++; 2069 td = td->obj_next; 2070 } 2071 2072 xfer->aframes = xfer->nframes; 2073 } 2074 2075 static void 2076 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2077 { 2078 uint32_t nframes = xfer->nframes; 2079 uint32_t status; 2080 uint32_t *plen = xfer->frlengths; 2081 uint16_t len = 0; 2082 uint8_t td_no = 0; 2083 ehci_itd_t *td = xfer->td_transfer_first; 2084 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2085 2086 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2087 xfer, xfer->endpoint); 2088 2089 while (nframes) { 2090 if (td == NULL) { 2091 panic("%s:%d: out of TD's\n", 2092 __FUNCTION__, __LINE__); 2093 } 2094 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2095 pp_last = &sc->sc_isoc_hs_p_last[0]; 2096 } 2097 #ifdef USB_DEBUG 2098 if (ehcidebug > 15) { 2099 DPRINTF("isoc HS-TD\n"); 2100 ehci_dump_itd(sc, td); 2101 } 2102 #endif 2103 2104 usb_pc_cpu_invalidate(td->page_cache); 2105 status = hc32toh(sc, td->itd_status[td_no]); 2106 2107 len = EHCI_ITD_GET_LEN(status); 2108 2109 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2110 2111 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2112 if (*plen >= len) { 2113 /* 2114 * The length is valid. NOTE: The 2115 * complete length is written back 2116 * into the status field, and not the 2117 * remainder like with other transfer 2118 * descriptor types. 2119 */ 2120 } else { 2121 /* Invalid length - truncate */ 2122 len = 0; 2123 } 2124 2125 *plen = len; 2126 plen++; 2127 nframes--; 2128 } 2129 2130 td_no++; 2131 2132 if ((td_no == 8) || (nframes == 0)) { 2133 /* remove HS-TD from schedule */ 2134 EHCI_REMOVE_HS_TD(td, *pp_last); 2135 pp_last++; 2136 2137 td_no = 0; 2138 td = td->obj_next; 2139 } 2140 } 2141 xfer->aframes = xfer->nframes; 2142 } 2143 2144 /* NOTE: "done" can be run two times in a row, 2145 * from close and from interrupt 2146 */ 2147 static void 2148 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2149 { 2150 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2151 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2152 2153 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2154 2155 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2156 xfer, xfer->endpoint, error); 2157 2158 if ((methods == &ehci_device_bulk_methods) || 2159 (methods == &ehci_device_ctrl_methods)) { 2160 #ifdef USB_DEBUG 2161 if (ehcidebug > 8) { 2162 DPRINTF("nexttog=%d; data after transfer:\n", 2163 xfer->endpoint->toggle_next); 2164 ehci_dump_sqtds(sc, 2165 xfer->td_transfer_first); 2166 } 2167 #endif 2168 2169 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2170 sc->sc_async_p_last); 2171 } 2172 if (methods == &ehci_device_intr_methods) { 2173 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2174 sc->sc_intr_p_last[xfer->qh_pos]); 2175 } 2176 /* 2177 * Only finish isochronous transfers once which will update 2178 * "xfer->frlengths". 2179 */ 2180 if (xfer->td_transfer_first && 2181 xfer->td_transfer_last) { 2182 if (methods == &ehci_device_isoc_fs_methods) { 2183 ehci_isoc_fs_done(sc, xfer); 2184 } 2185 if (methods == &ehci_device_isoc_hs_methods) { 2186 ehci_isoc_hs_done(sc, xfer); 2187 } 2188 xfer->td_transfer_first = NULL; 2189 xfer->td_transfer_last = NULL; 2190 } 2191 /* dequeue transfer and start next transfer */ 2192 usbd_transfer_done(xfer, error); 2193 } 2194 2195 /*------------------------------------------------------------------------* 2196 * ehci bulk support 2197 *------------------------------------------------------------------------*/ 2198 static void 2199 ehci_device_bulk_open(struct usb_xfer *xfer) 2200 { 2201 return; 2202 } 2203 2204 static void 2205 ehci_device_bulk_close(struct usb_xfer *xfer) 2206 { 2207 ehci_device_done(xfer, USB_ERR_CANCELLED); 2208 } 2209 2210 static void 2211 ehci_device_bulk_enter(struct usb_xfer *xfer) 2212 { 2213 return; 2214 } 2215 2216 static void 2217 ehci_doorbell_async(struct ehci_softc *sc) 2218 { 2219 uint32_t temp; 2220 2221 /* 2222 * XXX Performance quirk: Some Host Controllers have a too low 2223 * interrupt rate. Issue an IAAD to stimulate the Host 2224 * Controller after queueing the BULK transfer. 2225 * 2226 * XXX Force the host controller to refresh any QH caches. 2227 */ 2228 temp = EOREAD4(sc, EHCI_USBCMD); 2229 if (!(temp & EHCI_CMD_IAAD)) 2230 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2231 } 2232 2233 static void 2234 ehci_device_bulk_start(struct usb_xfer *xfer) 2235 { 2236 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2237 2238 /* setup TD's and QH */ 2239 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2240 2241 /* put transfer on interrupt queue */ 2242 ehci_transfer_intr_enqueue(xfer); 2243 2244 /* 2245 * XXX Certain nVidia chipsets choke when using the IAAD 2246 * feature too frequently. 2247 */ 2248 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2249 return; 2250 2251 ehci_doorbell_async(sc); 2252 } 2253 2254 static const struct usb_pipe_methods ehci_device_bulk_methods = 2255 { 2256 .open = ehci_device_bulk_open, 2257 .close = ehci_device_bulk_close, 2258 .enter = ehci_device_bulk_enter, 2259 .start = ehci_device_bulk_start, 2260 }; 2261 2262 /*------------------------------------------------------------------------* 2263 * ehci control support 2264 *------------------------------------------------------------------------*/ 2265 static void 2266 ehci_device_ctrl_open(struct usb_xfer *xfer) 2267 { 2268 return; 2269 } 2270 2271 static void 2272 ehci_device_ctrl_close(struct usb_xfer *xfer) 2273 { 2274 ehci_device_done(xfer, USB_ERR_CANCELLED); 2275 } 2276 2277 static void 2278 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2279 { 2280 return; 2281 } 2282 2283 static void 2284 ehci_device_ctrl_start(struct usb_xfer *xfer) 2285 { 2286 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2287 2288 /* setup TD's and QH */ 2289 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2290 2291 /* put transfer on interrupt queue */ 2292 ehci_transfer_intr_enqueue(xfer); 2293 } 2294 2295 static const struct usb_pipe_methods ehci_device_ctrl_methods = 2296 { 2297 .open = ehci_device_ctrl_open, 2298 .close = ehci_device_ctrl_close, 2299 .enter = ehci_device_ctrl_enter, 2300 .start = ehci_device_ctrl_start, 2301 }; 2302 2303 /*------------------------------------------------------------------------* 2304 * ehci interrupt support 2305 *------------------------------------------------------------------------*/ 2306 static void 2307 ehci_device_intr_open(struct usb_xfer *xfer) 2308 { 2309 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2310 uint16_t best; 2311 uint16_t bit; 2312 uint16_t x; 2313 2314 usb_hs_bandwidth_alloc(xfer); 2315 2316 /* 2317 * Find the best QH position corresponding to the given interval: 2318 */ 2319 2320 best = 0; 2321 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2322 while (bit) { 2323 if (xfer->interval >= bit) { 2324 x = bit; 2325 best = bit; 2326 while (x & bit) { 2327 if (sc->sc_intr_stat[x] < 2328 sc->sc_intr_stat[best]) { 2329 best = x; 2330 } 2331 x++; 2332 } 2333 break; 2334 } 2335 bit >>= 1; 2336 } 2337 2338 sc->sc_intr_stat[best]++; 2339 xfer->qh_pos = best; 2340 2341 DPRINTFN(3, "best=%d interval=%d\n", 2342 best, xfer->interval); 2343 } 2344 2345 static void 2346 ehci_device_intr_close(struct usb_xfer *xfer) 2347 { 2348 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2349 2350 sc->sc_intr_stat[xfer->qh_pos]--; 2351 2352 ehci_device_done(xfer, USB_ERR_CANCELLED); 2353 2354 /* bandwidth must be freed after device done */ 2355 usb_hs_bandwidth_free(xfer); 2356 } 2357 2358 static void 2359 ehci_device_intr_enter(struct usb_xfer *xfer) 2360 { 2361 return; 2362 } 2363 2364 static void 2365 ehci_device_intr_start(struct usb_xfer *xfer) 2366 { 2367 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2368 2369 /* setup TD's and QH */ 2370 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2371 2372 /* put transfer on interrupt queue */ 2373 ehci_transfer_intr_enqueue(xfer); 2374 } 2375 2376 static const struct usb_pipe_methods ehci_device_intr_methods = 2377 { 2378 .open = ehci_device_intr_open, 2379 .close = ehci_device_intr_close, 2380 .enter = ehci_device_intr_enter, 2381 .start = ehci_device_intr_start, 2382 }; 2383 2384 /*------------------------------------------------------------------------* 2385 * ehci full speed isochronous support 2386 *------------------------------------------------------------------------*/ 2387 static void 2388 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2389 { 2390 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2391 ehci_sitd_t *td; 2392 uint32_t sitd_portaddr; 2393 uint8_t ds; 2394 2395 sitd_portaddr = 2396 EHCI_SITD_SET_ADDR(xfer->address) | 2397 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2398 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2399 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2400 2401 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2402 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2403 2404 sitd_portaddr = htohc32(sc, sitd_portaddr); 2405 2406 /* initialize all TD's */ 2407 2408 for (ds = 0; ds != 2; ds++) { 2409 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2410 td->sitd_portaddr = sitd_portaddr; 2411 2412 /* 2413 * TODO: make some kind of automatic 2414 * SMASK/CMASK selection based on micro-frame 2415 * usage 2416 * 2417 * micro-frame usage (8 microframes per 1ms) 2418 */ 2419 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2420 2421 usb_pc_cpu_flush(td->page_cache); 2422 } 2423 } 2424 } 2425 2426 static void 2427 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2428 { 2429 ehci_device_done(xfer, USB_ERR_CANCELLED); 2430 } 2431 2432 static void 2433 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2434 { 2435 struct usb_page_search buf_res; 2436 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2437 ehci_sitd_t *td; 2438 ehci_sitd_t *td_last = NULL; 2439 ehci_sitd_t **pp_last; 2440 uint32_t *plen; 2441 uint32_t buf_offset; 2442 uint32_t nframes; 2443 uint32_t temp; 2444 uint32_t sitd_mask; 2445 uint16_t tlen; 2446 uint8_t sa; 2447 uint8_t sb; 2448 2449 #ifdef USB_DEBUG 2450 uint8_t once = 1; 2451 2452 #endif 2453 2454 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2455 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2456 2457 /* get the current frame index */ 2458 2459 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2460 2461 /* 2462 * check if the frame index is within the window where the frames 2463 * will be inserted 2464 */ 2465 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2466 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2467 2468 if ((xfer->endpoint->is_synced == 0) || 2469 (buf_offset < xfer->nframes)) { 2470 /* 2471 * If there is data underflow or the pipe queue is empty we 2472 * schedule the transfer a few frames ahead of the current 2473 * frame position. Else two isochronous transfers might 2474 * overlap. 2475 */ 2476 xfer->endpoint->isoc_next = (nframes + 3) & 2477 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2478 xfer->endpoint->is_synced = 1; 2479 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2480 } 2481 /* 2482 * compute how many milliseconds the insertion is ahead of the 2483 * current frame position: 2484 */ 2485 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2486 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2487 2488 /* 2489 * pre-compute when the isochronous transfer will be finished: 2490 */ 2491 xfer->isoc_time_complete = 2492 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2493 buf_offset + xfer->nframes; 2494 2495 /* get the real number of frames */ 2496 2497 nframes = xfer->nframes; 2498 2499 buf_offset = 0; 2500 2501 plen = xfer->frlengths; 2502 2503 /* toggle the DMA set we are using */ 2504 xfer->flags_int.curr_dma_set ^= 1; 2505 2506 /* get next DMA set */ 2507 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2508 xfer->td_transfer_first = td; 2509 2510 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2511 2512 /* store starting position */ 2513 2514 xfer->qh_pos = xfer->endpoint->isoc_next; 2515 2516 while (nframes--) { 2517 if (td == NULL) { 2518 panic("%s:%d: out of TD's\n", 2519 __FUNCTION__, __LINE__); 2520 } 2521 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2522 pp_last = &sc->sc_isoc_fs_p_last[0]; 2523 2524 /* reuse sitd_portaddr and sitd_back from last transfer */ 2525 2526 if (*plen > xfer->max_frame_size) { 2527 #ifdef USB_DEBUG 2528 if (once) { 2529 once = 0; 2530 printf("%s: frame length(%d) exceeds %d " 2531 "bytes (frame truncated)\n", 2532 __FUNCTION__, *plen, 2533 xfer->max_frame_size); 2534 } 2535 #endif 2536 *plen = xfer->max_frame_size; 2537 } 2538 2539 /* allocate a slot */ 2540 2541 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2542 xfer->isoc_time_complete - nframes - 1); 2543 2544 if (sa == 255) { 2545 /* 2546 * Schedule is FULL, set length to zero: 2547 */ 2548 2549 *plen = 0; 2550 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2551 } 2552 if (*plen) { 2553 /* 2554 * only call "usbd_get_page()" when we have a 2555 * non-zero length 2556 */ 2557 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2558 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2559 buf_offset += *plen; 2560 /* 2561 * NOTE: We need to subtract one from the offset so 2562 * that we are on a valid page! 2563 */ 2564 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2565 &buf_res); 2566 temp = buf_res.physaddr & ~0xFFF; 2567 } else { 2568 td->sitd_bp[0] = 0; 2569 temp = 0; 2570 } 2571 2572 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2573 tlen = *plen; 2574 if (tlen <= 188) { 2575 temp |= 1; /* T-count = 1, TP = ALL */ 2576 tlen = 1; 2577 } else { 2578 tlen += 187; 2579 tlen /= 188; 2580 temp |= tlen; /* T-count = [1..6] */ 2581 temp |= 8; /* TP = Begin */ 2582 } 2583 2584 tlen += sa; 2585 2586 if (tlen >= 8) { 2587 sb = 0; 2588 } else { 2589 sb = (1 << tlen); 2590 } 2591 2592 sa = (1 << sa); 2593 sa = (sb - sa) & 0x3F; 2594 sb = 0; 2595 } else { 2596 sb = (-(4 << sa)) & 0xFE; 2597 sa = (1 << sa) & 0x3F; 2598 } 2599 2600 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2601 EHCI_SITD_SET_CMASK(sb)); 2602 2603 td->sitd_bp[1] = htohc32(sc, temp); 2604 2605 td->sitd_mask = htohc32(sc, sitd_mask); 2606 2607 if (nframes == 0) { 2608 td->sitd_status = htohc32(sc, 2609 EHCI_SITD_IOC | 2610 EHCI_SITD_ACTIVE | 2611 EHCI_SITD_SET_LEN(*plen)); 2612 } else { 2613 td->sitd_status = htohc32(sc, 2614 EHCI_SITD_ACTIVE | 2615 EHCI_SITD_SET_LEN(*plen)); 2616 } 2617 usb_pc_cpu_flush(td->page_cache); 2618 2619 #ifdef USB_DEBUG 2620 if (ehcidebug > 15) { 2621 DPRINTF("FS-TD %d\n", nframes); 2622 ehci_dump_sitd(sc, td); 2623 } 2624 #endif 2625 /* insert TD into schedule */ 2626 EHCI_APPEND_FS_TD(td, *pp_last); 2627 pp_last++; 2628 2629 plen++; 2630 td_last = td; 2631 td = td->obj_next; 2632 } 2633 2634 xfer->td_transfer_last = td_last; 2635 2636 /* update isoc_next */ 2637 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2638 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2639 2640 /* 2641 * We don't allow cancelling of the SPLIT transaction USB FULL 2642 * speed transfer, because it disturbs the bandwidth 2643 * computation algorithm. 2644 */ 2645 xfer->flags_int.can_cancel_immed = 0; 2646 } 2647 2648 static void 2649 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2650 { 2651 /* 2652 * We don't allow cancelling of the SPLIT transaction USB FULL 2653 * speed transfer, because it disturbs the bandwidth 2654 * computation algorithm. 2655 */ 2656 xfer->flags_int.can_cancel_immed = 0; 2657 2658 /* set a default timeout */ 2659 if (xfer->timeout == 0) 2660 xfer->timeout = 500; /* ms */ 2661 2662 /* put transfer on interrupt queue */ 2663 ehci_transfer_intr_enqueue(xfer); 2664 } 2665 2666 static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2667 { 2668 .open = ehci_device_isoc_fs_open, 2669 .close = ehci_device_isoc_fs_close, 2670 .enter = ehci_device_isoc_fs_enter, 2671 .start = ehci_device_isoc_fs_start, 2672 }; 2673 2674 /*------------------------------------------------------------------------* 2675 * ehci high speed isochronous support 2676 *------------------------------------------------------------------------*/ 2677 static void 2678 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2679 { 2680 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2681 ehci_itd_t *td; 2682 uint32_t temp; 2683 uint8_t ds; 2684 2685 usb_hs_bandwidth_alloc(xfer); 2686 2687 /* initialize all TD's */ 2688 2689 for (ds = 0; ds != 2; ds++) { 2690 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2691 /* set TD inactive */ 2692 td->itd_status[0] = 0; 2693 td->itd_status[1] = 0; 2694 td->itd_status[2] = 0; 2695 td->itd_status[3] = 0; 2696 td->itd_status[4] = 0; 2697 td->itd_status[5] = 0; 2698 td->itd_status[6] = 0; 2699 td->itd_status[7] = 0; 2700 2701 /* set endpoint and address */ 2702 td->itd_bp[0] = htohc32(sc, 2703 EHCI_ITD_SET_ADDR(xfer->address) | 2704 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2705 2706 temp = 2707 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2708 2709 /* set direction */ 2710 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2711 temp |= EHCI_ITD_SET_DIR_IN; 2712 } 2713 /* set maximum packet size */ 2714 td->itd_bp[1] = htohc32(sc, temp); 2715 2716 /* set transfer multiplier */ 2717 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2718 2719 usb_pc_cpu_flush(td->page_cache); 2720 } 2721 } 2722 } 2723 2724 static void 2725 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2726 { 2727 ehci_device_done(xfer, USB_ERR_CANCELLED); 2728 2729 /* bandwidth must be freed after device done */ 2730 usb_hs_bandwidth_free(xfer); 2731 } 2732 2733 static void 2734 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2735 { 2736 struct usb_page_search buf_res; 2737 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2738 ehci_itd_t *td; 2739 ehci_itd_t *td_last = NULL; 2740 ehci_itd_t **pp_last; 2741 bus_size_t page_addr; 2742 uint32_t *plen; 2743 uint32_t status; 2744 uint32_t buf_offset; 2745 uint32_t nframes; 2746 uint32_t itd_offset[8 + 1]; 2747 uint8_t x; 2748 uint8_t td_no; 2749 uint8_t page_no; 2750 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2751 2752 #ifdef USB_DEBUG 2753 uint8_t once = 1; 2754 2755 #endif 2756 2757 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2758 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2759 2760 /* get the current frame index */ 2761 2762 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2763 2764 /* 2765 * check if the frame index is within the window where the frames 2766 * will be inserted 2767 */ 2768 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2769 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2770 2771 if ((xfer->endpoint->is_synced == 0) || 2772 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2773 /* 2774 * If there is data underflow or the pipe queue is empty we 2775 * schedule the transfer a few frames ahead of the current 2776 * frame position. Else two isochronous transfers might 2777 * overlap. 2778 */ 2779 xfer->endpoint->isoc_next = (nframes + 3) & 2780 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2781 xfer->endpoint->is_synced = 1; 2782 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2783 } 2784 /* 2785 * compute how many milliseconds the insertion is ahead of the 2786 * current frame position: 2787 */ 2788 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2789 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2790 2791 /* 2792 * pre-compute when the isochronous transfer will be finished: 2793 */ 2794 xfer->isoc_time_complete = 2795 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2796 (((xfer->nframes << shift) + 7) / 8); 2797 2798 /* get the real number of frames */ 2799 2800 nframes = xfer->nframes; 2801 2802 buf_offset = 0; 2803 td_no = 0; 2804 2805 plen = xfer->frlengths; 2806 2807 /* toggle the DMA set we are using */ 2808 xfer->flags_int.curr_dma_set ^= 1; 2809 2810 /* get next DMA set */ 2811 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2812 xfer->td_transfer_first = td; 2813 2814 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2815 2816 /* store starting position */ 2817 2818 xfer->qh_pos = xfer->endpoint->isoc_next; 2819 2820 while (nframes) { 2821 if (td == NULL) { 2822 panic("%s:%d: out of TD's\n", 2823 __FUNCTION__, __LINE__); 2824 } 2825 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2826 pp_last = &sc->sc_isoc_hs_p_last[0]; 2827 } 2828 /* range check */ 2829 if (*plen > xfer->max_frame_size) { 2830 #ifdef USB_DEBUG 2831 if (once) { 2832 once = 0; 2833 printf("%s: frame length(%d) exceeds %d bytes " 2834 "(frame truncated)\n", 2835 __FUNCTION__, *plen, xfer->max_frame_size); 2836 } 2837 #endif 2838 *plen = xfer->max_frame_size; 2839 } 2840 2841 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2842 status = (EHCI_ITD_SET_LEN(*plen) | 2843 EHCI_ITD_ACTIVE | 2844 EHCI_ITD_SET_PG(0)); 2845 td->itd_status[td_no] = htohc32(sc, status); 2846 itd_offset[td_no] = buf_offset; 2847 buf_offset += *plen; 2848 plen++; 2849 nframes --; 2850 } else { 2851 td->itd_status[td_no] = 0; /* not active */ 2852 itd_offset[td_no] = buf_offset; 2853 } 2854 2855 td_no++; 2856 2857 if ((td_no == 8) || (nframes == 0)) { 2858 /* the rest of the transfers are not active, if any */ 2859 for (x = td_no; x != 8; x++) { 2860 td->itd_status[x] = 0; /* not active */ 2861 } 2862 2863 /* check if there is any data to be transferred */ 2864 if (itd_offset[0] != buf_offset) { 2865 page_no = 0; 2866 itd_offset[td_no] = buf_offset; 2867 2868 /* get first page offset */ 2869 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2870 /* get page address */ 2871 page_addr = buf_res.physaddr & ~0xFFF; 2872 /* update page address */ 2873 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2874 td->itd_bp[0] |= htohc32(sc, page_addr); 2875 2876 for (x = 0; x != td_no; x++) { 2877 /* set page number and page offset */ 2878 status = (EHCI_ITD_SET_PG(page_no) | 2879 (buf_res.physaddr & 0xFFF)); 2880 td->itd_status[x] |= htohc32(sc, status); 2881 2882 /* get next page offset */ 2883 if (itd_offset[x + 1] == buf_offset) { 2884 /* 2885 * We subtract one so that 2886 * we don't go off the last 2887 * page! 2888 */ 2889 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2890 } else { 2891 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2892 } 2893 2894 /* check if we need a new page */ 2895 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2896 /* new page needed */ 2897 page_addr = buf_res.physaddr & ~0xFFF; 2898 if (page_no == 6) { 2899 panic("%s: too many pages\n", __FUNCTION__); 2900 } 2901 page_no++; 2902 /* update page address */ 2903 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2904 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2905 } 2906 } 2907 } 2908 /* set IOC bit if we are complete */ 2909 if (nframes == 0) { 2910 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2911 } 2912 usb_pc_cpu_flush(td->page_cache); 2913 #ifdef USB_DEBUG 2914 if (ehcidebug > 15) { 2915 DPRINTF("HS-TD %d\n", nframes); 2916 ehci_dump_itd(sc, td); 2917 } 2918 #endif 2919 /* insert TD into schedule */ 2920 EHCI_APPEND_HS_TD(td, *pp_last); 2921 pp_last++; 2922 2923 td_no = 0; 2924 td_last = td; 2925 td = td->obj_next; 2926 } 2927 } 2928 2929 xfer->td_transfer_last = td_last; 2930 2931 /* update isoc_next */ 2932 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2933 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2934 } 2935 2936 static void 2937 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2938 { 2939 /* put transfer on interrupt queue */ 2940 ehci_transfer_intr_enqueue(xfer); 2941 } 2942 2943 static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2944 { 2945 .open = ehci_device_isoc_hs_open, 2946 .close = ehci_device_isoc_hs_close, 2947 .enter = ehci_device_isoc_hs_enter, 2948 .start = ehci_device_isoc_hs_start, 2949 }; 2950 2951 /*------------------------------------------------------------------------* 2952 * ehci root control support 2953 *------------------------------------------------------------------------* 2954 * Simulate a hardware hub by handling all the necessary requests. 2955 *------------------------------------------------------------------------*/ 2956 2957 static const 2958 struct usb_device_descriptor ehci_devd = 2959 { 2960 sizeof(struct usb_device_descriptor), 2961 UDESC_DEVICE, /* type */ 2962 {0x00, 0x02}, /* USB version */ 2963 UDCLASS_HUB, /* class */ 2964 UDSUBCLASS_HUB, /* subclass */ 2965 UDPROTO_HSHUBSTT, /* protocol */ 2966 64, /* max packet */ 2967 {0}, {0}, {0x00, 0x01}, /* device id */ 2968 1, 2, 0, /* string indexes */ 2969 1 /* # of configurations */ 2970 }; 2971 2972 static const 2973 struct usb_device_qualifier ehci_odevd = 2974 { 2975 sizeof(struct usb_device_qualifier), 2976 UDESC_DEVICE_QUALIFIER, /* type */ 2977 {0x00, 0x02}, /* USB version */ 2978 UDCLASS_HUB, /* class */ 2979 UDSUBCLASS_HUB, /* subclass */ 2980 UDPROTO_FSHUB, /* protocol */ 2981 0, /* max packet */ 2982 0, /* # of configurations */ 2983 0 2984 }; 2985 2986 static const struct ehci_config_desc ehci_confd = { 2987 .confd = { 2988 .bLength = sizeof(struct usb_config_descriptor), 2989 .bDescriptorType = UDESC_CONFIG, 2990 .wTotalLength[0] = sizeof(ehci_confd), 2991 .bNumInterface = 1, 2992 .bConfigurationValue = 1, 2993 .iConfiguration = 0, 2994 .bmAttributes = UC_SELF_POWERED, 2995 .bMaxPower = 0 /* max power */ 2996 }, 2997 .ifcd = { 2998 .bLength = sizeof(struct usb_interface_descriptor), 2999 .bDescriptorType = UDESC_INTERFACE, 3000 .bNumEndpoints = 1, 3001 .bInterfaceClass = UICLASS_HUB, 3002 .bInterfaceSubClass = UISUBCLASS_HUB, 3003 .bInterfaceProtocol = 0, 3004 }, 3005 .endpd = { 3006 .bLength = sizeof(struct usb_endpoint_descriptor), 3007 .bDescriptorType = UDESC_ENDPOINT, 3008 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3009 .bmAttributes = UE_INTERRUPT, 3010 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3011 .bInterval = 255, 3012 }, 3013 }; 3014 3015 static const 3016 struct usb_hub_descriptor ehci_hubd = 3017 { 3018 .bDescLength = 0, /* dynamic length */ 3019 .bDescriptorType = UDESC_HUB, 3020 }; 3021 3022 uint16_t 3023 ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3024 { 3025 uint32_t v; 3026 3027 v = EOREAD4(sc, EHCI_PORTSC(index)); 3028 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3029 3030 if (v == EHCI_PORT_SPEED_HIGH) 3031 return (UPS_HIGH_SPEED); 3032 if (v == EHCI_PORT_SPEED_LOW) 3033 return (UPS_LOW_SPEED); 3034 return (0); 3035 } 3036 3037 uint16_t 3038 ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3039 { 3040 uint32_t v; 3041 3042 v = EOREAD4(sc, EHCI_HOSTC(index)); 3043 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3044 3045 if (v == EHCI_PORT_SPEED_HIGH) 3046 return (UPS_HIGH_SPEED); 3047 if (v == EHCI_PORT_SPEED_LOW) 3048 return (UPS_LOW_SPEED); 3049 return (0); 3050 } 3051 3052 static void 3053 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3054 { 3055 uint32_t port; 3056 uint32_t v; 3057 3058 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3059 3060 port = EHCI_PORTSC(index); 3061 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3062 EOWRITE4(sc, port, v | EHCI_PS_PO); 3063 } 3064 3065 static usb_error_t 3066 ehci_roothub_exec(struct usb_device *udev, 3067 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3068 { 3069 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3070 const char *str_ptr; 3071 const void *ptr; 3072 uint32_t port; 3073 uint32_t v; 3074 uint16_t len; 3075 uint16_t i; 3076 uint16_t value; 3077 uint16_t index; 3078 usb_error_t err; 3079 3080 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3081 3082 /* buffer reset */ 3083 ptr = (const void *)&sc->sc_hub_desc; 3084 len = 0; 3085 err = 0; 3086 3087 value = UGETW(req->wValue); 3088 index = UGETW(req->wIndex); 3089 3090 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3091 "wValue=0x%04x wIndex=0x%04x\n", 3092 req->bmRequestType, req->bRequest, 3093 UGETW(req->wLength), value, index); 3094 3095 #define C(x,y) ((x) | ((y) << 8)) 3096 switch (C(req->bRequest, req->bmRequestType)) { 3097 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3098 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3099 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3100 /* 3101 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3102 * for the integrated root hub. 3103 */ 3104 break; 3105 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3106 len = 1; 3107 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3108 break; 3109 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3110 switch (value >> 8) { 3111 case UDESC_DEVICE: 3112 if ((value & 0xff) != 0) { 3113 err = USB_ERR_IOERROR; 3114 goto done; 3115 } 3116 len = sizeof(ehci_devd); 3117 ptr = (const void *)&ehci_devd; 3118 break; 3119 /* 3120 * We can't really operate at another speed, 3121 * but the specification says we need this 3122 * descriptor: 3123 */ 3124 case UDESC_DEVICE_QUALIFIER: 3125 if ((value & 0xff) != 0) { 3126 err = USB_ERR_IOERROR; 3127 goto done; 3128 } 3129 len = sizeof(ehci_odevd); 3130 ptr = (const void *)&ehci_odevd; 3131 break; 3132 3133 case UDESC_CONFIG: 3134 if ((value & 0xff) != 0) { 3135 err = USB_ERR_IOERROR; 3136 goto done; 3137 } 3138 len = sizeof(ehci_confd); 3139 ptr = (const void *)&ehci_confd; 3140 break; 3141 3142 case UDESC_STRING: 3143 switch (value & 0xff) { 3144 case 0: /* Language table */ 3145 str_ptr = "\001"; 3146 break; 3147 3148 case 1: /* Vendor */ 3149 str_ptr = sc->sc_vendor; 3150 break; 3151 3152 case 2: /* Product */ 3153 str_ptr = "EHCI root HUB"; 3154 break; 3155 3156 default: 3157 str_ptr = ""; 3158 break; 3159 } 3160 3161 len = usb_make_str_desc( 3162 sc->sc_hub_desc.temp, 3163 sizeof(sc->sc_hub_desc.temp), 3164 str_ptr); 3165 break; 3166 default: 3167 err = USB_ERR_IOERROR; 3168 goto done; 3169 } 3170 break; 3171 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3172 len = 1; 3173 sc->sc_hub_desc.temp[0] = 0; 3174 break; 3175 case C(UR_GET_STATUS, UT_READ_DEVICE): 3176 len = 2; 3177 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3178 break; 3179 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3180 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3181 len = 2; 3182 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3183 break; 3184 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3185 if (value >= EHCI_MAX_DEVICES) { 3186 err = USB_ERR_IOERROR; 3187 goto done; 3188 } 3189 sc->sc_addr = value; 3190 break; 3191 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3192 if ((value != 0) && (value != 1)) { 3193 err = USB_ERR_IOERROR; 3194 goto done; 3195 } 3196 sc->sc_conf = value; 3197 break; 3198 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3199 break; 3200 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3201 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3202 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3203 err = USB_ERR_IOERROR; 3204 goto done; 3205 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3206 break; 3207 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3208 break; 3209 /* Hub requests */ 3210 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3211 break; 3212 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3213 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3214 3215 if ((index < 1) || 3216 (index > sc->sc_noport)) { 3217 err = USB_ERR_IOERROR; 3218 goto done; 3219 } 3220 port = EHCI_PORTSC(index); 3221 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3222 switch (value) { 3223 case UHF_PORT_ENABLE: 3224 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3225 break; 3226 case UHF_PORT_SUSPEND: 3227 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3228 /* 3229 * waking up a High Speed device is rather 3230 * complicated if 3231 */ 3232 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3233 } 3234 /* wait 20ms for resume sequence to complete */ 3235 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3236 3237 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3238 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3239 3240 /* 4ms settle time */ 3241 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3242 break; 3243 case UHF_PORT_POWER: 3244 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3245 break; 3246 case UHF_PORT_TEST: 3247 DPRINTFN(3, "clear port test " 3248 "%d\n", index); 3249 break; 3250 case UHF_PORT_INDICATOR: 3251 DPRINTFN(3, "clear port ind " 3252 "%d\n", index); 3253 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3254 break; 3255 case UHF_C_PORT_CONNECTION: 3256 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3257 break; 3258 case UHF_C_PORT_ENABLE: 3259 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3260 break; 3261 case UHF_C_PORT_SUSPEND: 3262 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3263 break; 3264 case UHF_C_PORT_OVER_CURRENT: 3265 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3266 break; 3267 case UHF_C_PORT_RESET: 3268 sc->sc_isreset = 0; 3269 break; 3270 default: 3271 err = USB_ERR_IOERROR; 3272 goto done; 3273 } 3274 break; 3275 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3276 if ((value & 0xff) != 0) { 3277 err = USB_ERR_IOERROR; 3278 goto done; 3279 } 3280 v = EREAD4(sc, EHCI_HCSPARAMS); 3281 3282 sc->sc_hub_desc.hubd = ehci_hubd; 3283 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3284 3285 if (EHCI_HCS_PPC(v)) 3286 i = UHD_PWR_INDIVIDUAL; 3287 else 3288 i = UHD_PWR_NO_SWITCH; 3289 3290 if (EHCI_HCS_P_INDICATOR(v)) 3291 i |= UHD_PORT_IND; 3292 3293 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3294 /* XXX can't find out? */ 3295 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3296 /* XXX don't know if ports are removable or not */ 3297 sc->sc_hub_desc.hubd.bDescLength = 3298 8 + ((sc->sc_noport + 7) / 8); 3299 len = sc->sc_hub_desc.hubd.bDescLength; 3300 break; 3301 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3302 len = 16; 3303 memset(sc->sc_hub_desc.temp, 0, 16); 3304 break; 3305 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3306 DPRINTFN(9, "get port status i=%d\n", 3307 index); 3308 if ((index < 1) || 3309 (index > sc->sc_noport)) { 3310 err = USB_ERR_IOERROR; 3311 goto done; 3312 } 3313 v = EOREAD4(sc, EHCI_PORTSC(index)); 3314 DPRINTFN(9, "port status=0x%04x\n", v); 3315 if (sc->sc_flags & EHCI_SCFLG_TT) { 3316 if (sc->sc_vendor_get_port_speed != NULL) { 3317 i = sc->sc_vendor_get_port_speed(sc, index); 3318 } else { 3319 device_printf(sc->sc_bus.bdev, 3320 "EHCI_SCFLG_TT quirk is set but " 3321 "sc_vendor_get_hub_speed() is NULL\n"); 3322 i = UPS_HIGH_SPEED; 3323 } 3324 } else { 3325 i = UPS_HIGH_SPEED; 3326 } 3327 if (v & EHCI_PS_CS) 3328 i |= UPS_CURRENT_CONNECT_STATUS; 3329 if (v & EHCI_PS_PE) 3330 i |= UPS_PORT_ENABLED; 3331 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3332 i |= UPS_SUSPEND; 3333 if (v & EHCI_PS_OCA) 3334 i |= UPS_OVERCURRENT_INDICATOR; 3335 if (v & EHCI_PS_PR) 3336 i |= UPS_RESET; 3337 if (v & EHCI_PS_PP) 3338 i |= UPS_PORT_POWER; 3339 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3340 i = 0; 3341 if (v & EHCI_PS_CSC) 3342 i |= UPS_C_CONNECT_STATUS; 3343 if (v & EHCI_PS_PEC) 3344 i |= UPS_C_PORT_ENABLED; 3345 if (v & EHCI_PS_OCC) 3346 i |= UPS_C_OVERCURRENT_INDICATOR; 3347 if (v & EHCI_PS_FPR) 3348 i |= UPS_C_SUSPEND; 3349 if (sc->sc_isreset) 3350 i |= UPS_C_PORT_RESET; 3351 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3352 len = sizeof(sc->sc_hub_desc.ps); 3353 break; 3354 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3355 err = USB_ERR_IOERROR; 3356 goto done; 3357 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3358 break; 3359 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3360 if ((index < 1) || 3361 (index > sc->sc_noport)) { 3362 err = USB_ERR_IOERROR; 3363 goto done; 3364 } 3365 port = EHCI_PORTSC(index); 3366 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3367 switch (value) { 3368 case UHF_PORT_ENABLE: 3369 EOWRITE4(sc, port, v | EHCI_PS_PE); 3370 break; 3371 case UHF_PORT_SUSPEND: 3372 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3373 break; 3374 case UHF_PORT_RESET: 3375 DPRINTFN(6, "reset port %d\n", index); 3376 #ifdef USB_DEBUG 3377 if (ehcinohighspeed) { 3378 /* 3379 * Connect USB device to companion 3380 * controller. 3381 */ 3382 ehci_disown(sc, index, 1); 3383 break; 3384 } 3385 #endif 3386 if (EHCI_PS_IS_LOWSPEED(v) && 3387 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3388 /* Low speed device, give up ownership. */ 3389 ehci_disown(sc, index, 1); 3390 break; 3391 } 3392 /* Start reset sequence. */ 3393 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3394 EOWRITE4(sc, port, v | EHCI_PS_PR); 3395 3396 /* Wait for reset to complete. */ 3397 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3398 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3399 3400 /* Terminate reset sequence. */ 3401 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3402 EOWRITE4(sc, port, v); 3403 3404 /* Wait for HC to complete reset. */ 3405 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3406 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3407 3408 v = EOREAD4(sc, port); 3409 DPRINTF("ehci after reset, status=0x%08x\n", v); 3410 if (v & EHCI_PS_PR) { 3411 device_printf(sc->sc_bus.bdev, 3412 "port reset timeout\n"); 3413 err = USB_ERR_TIMEOUT; 3414 goto done; 3415 } 3416 if (!(v & EHCI_PS_PE) && 3417 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3418 /* Not a high speed device, give up ownership.*/ 3419 ehci_disown(sc, index, 0); 3420 break; 3421 } 3422 sc->sc_isreset = 1; 3423 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3424 index, v); 3425 break; 3426 3427 case UHF_PORT_POWER: 3428 DPRINTFN(3, "set port power %d\n", index); 3429 EOWRITE4(sc, port, v | EHCI_PS_PP); 3430 break; 3431 3432 case UHF_PORT_TEST: 3433 DPRINTFN(3, "set port test %d\n", index); 3434 break; 3435 3436 case UHF_PORT_INDICATOR: 3437 DPRINTFN(3, "set port ind %d\n", index); 3438 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3439 break; 3440 3441 default: 3442 err = USB_ERR_IOERROR; 3443 goto done; 3444 } 3445 break; 3446 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3447 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3448 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3449 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3450 break; 3451 default: 3452 err = USB_ERR_IOERROR; 3453 goto done; 3454 } 3455 done: 3456 *plength = len; 3457 *pptr = ptr; 3458 return (err); 3459 } 3460 3461 static void 3462 ehci_xfer_setup(struct usb_setup_params *parm) 3463 { 3464 struct usb_page_search page_info; 3465 struct usb_page_cache *pc; 3466 ehci_softc_t *sc; 3467 struct usb_xfer *xfer; 3468 void *last_obj; 3469 uint32_t nqtd; 3470 uint32_t nqh; 3471 uint32_t nsitd; 3472 uint32_t nitd; 3473 uint32_t n; 3474 3475 sc = EHCI_BUS2SC(parm->udev->bus); 3476 xfer = parm->curr_xfer; 3477 3478 nqtd = 0; 3479 nqh = 0; 3480 nsitd = 0; 3481 nitd = 0; 3482 3483 /* 3484 * compute maximum number of some structures 3485 */ 3486 if (parm->methods == &ehci_device_ctrl_methods) { 3487 /* 3488 * The proof for the "nqtd" formula is illustrated like 3489 * this: 3490 * 3491 * +------------------------------------+ 3492 * | | 3493 * | |remainder -> | 3494 * | +-----+---+ | 3495 * | | xxx | x | frm 0 | 3496 * | +-----+---++ | 3497 * | | xxx | xx | frm 1 | 3498 * | +-----+----+ | 3499 * | ... | 3500 * +------------------------------------+ 3501 * 3502 * "xxx" means a completely full USB transfer descriptor 3503 * 3504 * "x" and "xx" means a short USB packet 3505 * 3506 * For the remainder of an USB transfer modulo 3507 * "max_data_length" we need two USB transfer descriptors. 3508 * One to transfer the remaining data and one to finalise 3509 * with a zero length packet in case the "force_short_xfer" 3510 * flag is set. We only need two USB transfer descriptors in 3511 * the case where the transfer length of the first one is a 3512 * factor of "max_frame_size". The rest of the needed USB 3513 * transfer descriptors is given by the buffer size divided 3514 * by the maximum data payload. 3515 */ 3516 parm->hc_max_packet_size = 0x400; 3517 parm->hc_max_packet_count = 1; 3518 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3519 xfer->flags_int.bdma_enable = 1; 3520 3521 usbd_transfer_setup_sub(parm); 3522 3523 nqh = 1; 3524 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3525 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3526 3527 } else if (parm->methods == &ehci_device_bulk_methods) { 3528 parm->hc_max_packet_size = 0x400; 3529 parm->hc_max_packet_count = 1; 3530 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3531 xfer->flags_int.bdma_enable = 1; 3532 3533 usbd_transfer_setup_sub(parm); 3534 3535 nqh = 1; 3536 nqtd = ((2 * xfer->nframes) 3537 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3538 3539 } else if (parm->methods == &ehci_device_intr_methods) { 3540 if (parm->speed == USB_SPEED_HIGH) { 3541 parm->hc_max_packet_size = 0x400; 3542 parm->hc_max_packet_count = 3; 3543 } else if (parm->speed == USB_SPEED_FULL) { 3544 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3545 parm->hc_max_packet_count = 1; 3546 } else { 3547 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3548 parm->hc_max_packet_count = 1; 3549 } 3550 3551 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3552 xfer->flags_int.bdma_enable = 1; 3553 3554 usbd_transfer_setup_sub(parm); 3555 3556 nqh = 1; 3557 nqtd = ((2 * xfer->nframes) 3558 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3559 3560 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3561 parm->hc_max_packet_size = 0x3FF; 3562 parm->hc_max_packet_count = 1; 3563 parm->hc_max_frame_size = 0x3FF; 3564 xfer->flags_int.bdma_enable = 1; 3565 3566 usbd_transfer_setup_sub(parm); 3567 3568 nsitd = xfer->nframes; 3569 3570 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3571 parm->hc_max_packet_size = 0x400; 3572 parm->hc_max_packet_count = 3; 3573 parm->hc_max_frame_size = 0xC00; 3574 xfer->flags_int.bdma_enable = 1; 3575 3576 usbd_transfer_setup_sub(parm); 3577 3578 nitd = ((xfer->nframes + 7) / 8) << 3579 usbd_xfer_get_fps_shift(xfer); 3580 3581 } else { 3582 parm->hc_max_packet_size = 0x400; 3583 parm->hc_max_packet_count = 1; 3584 parm->hc_max_frame_size = 0x400; 3585 3586 usbd_transfer_setup_sub(parm); 3587 } 3588 3589 alloc_dma_set: 3590 3591 if (parm->err) { 3592 return; 3593 } 3594 /* 3595 * Allocate queue heads and transfer descriptors 3596 */ 3597 last_obj = NULL; 3598 3599 if (usbd_transfer_setup_sub_malloc( 3600 parm, &pc, sizeof(ehci_itd_t), 3601 EHCI_ITD_ALIGN, nitd)) { 3602 parm->err = USB_ERR_NOMEM; 3603 return; 3604 } 3605 if (parm->buf) { 3606 for (n = 0; n != nitd; n++) { 3607 ehci_itd_t *td; 3608 3609 usbd_get_page(pc + n, 0, &page_info); 3610 3611 td = page_info.buffer; 3612 3613 /* init TD */ 3614 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3615 td->obj_next = last_obj; 3616 td->page_cache = pc + n; 3617 3618 last_obj = td; 3619 3620 usb_pc_cpu_flush(pc + n); 3621 } 3622 } 3623 if (usbd_transfer_setup_sub_malloc( 3624 parm, &pc, sizeof(ehci_sitd_t), 3625 EHCI_SITD_ALIGN, nsitd)) { 3626 parm->err = USB_ERR_NOMEM; 3627 return; 3628 } 3629 if (parm->buf) { 3630 for (n = 0; n != nsitd; n++) { 3631 ehci_sitd_t *td; 3632 3633 usbd_get_page(pc + n, 0, &page_info); 3634 3635 td = page_info.buffer; 3636 3637 /* init TD */ 3638 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3639 td->obj_next = last_obj; 3640 td->page_cache = pc + n; 3641 3642 last_obj = td; 3643 3644 usb_pc_cpu_flush(pc + n); 3645 } 3646 } 3647 if (usbd_transfer_setup_sub_malloc( 3648 parm, &pc, sizeof(ehci_qtd_t), 3649 EHCI_QTD_ALIGN, nqtd)) { 3650 parm->err = USB_ERR_NOMEM; 3651 return; 3652 } 3653 if (parm->buf) { 3654 for (n = 0; n != nqtd; n++) { 3655 ehci_qtd_t *qtd; 3656 3657 usbd_get_page(pc + n, 0, &page_info); 3658 3659 qtd = page_info.buffer; 3660 3661 /* init TD */ 3662 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3663 qtd->obj_next = last_obj; 3664 qtd->page_cache = pc + n; 3665 3666 last_obj = qtd; 3667 3668 usb_pc_cpu_flush(pc + n); 3669 } 3670 } 3671 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3672 3673 last_obj = NULL; 3674 3675 if (usbd_transfer_setup_sub_malloc( 3676 parm, &pc, sizeof(ehci_qh_t), 3677 EHCI_QH_ALIGN, nqh)) { 3678 parm->err = USB_ERR_NOMEM; 3679 return; 3680 } 3681 if (parm->buf) { 3682 for (n = 0; n != nqh; n++) { 3683 ehci_qh_t *qh; 3684 3685 usbd_get_page(pc + n, 0, &page_info); 3686 3687 qh = page_info.buffer; 3688 3689 /* init QH */ 3690 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3691 qh->obj_next = last_obj; 3692 qh->page_cache = pc + n; 3693 3694 last_obj = qh; 3695 3696 usb_pc_cpu_flush(pc + n); 3697 } 3698 } 3699 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3700 3701 if (!xfer->flags_int.curr_dma_set) { 3702 xfer->flags_int.curr_dma_set = 1; 3703 goto alloc_dma_set; 3704 } 3705 } 3706 3707 static void 3708 ehci_xfer_unsetup(struct usb_xfer *xfer) 3709 { 3710 return; 3711 } 3712 3713 static void 3714 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3715 struct usb_endpoint *ep) 3716 { 3717 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3718 3719 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3720 ep, udev->address, 3721 edesc->bEndpointAddress, udev->flags.usb_mode, 3722 sc->sc_addr); 3723 3724 if (udev->device_index != sc->sc_addr) { 3725 if ((udev->speed != USB_SPEED_HIGH) && 3726 ((udev->hs_hub_addr == 0) || 3727 (udev->hs_port_no == 0) || 3728 (udev->parent_hs_hub == NULL) || 3729 (udev->parent_hs_hub->hub == NULL))) { 3730 /* We need a transaction translator */ 3731 goto done; 3732 } 3733 switch (edesc->bmAttributes & UE_XFERTYPE) { 3734 case UE_CONTROL: 3735 ep->methods = &ehci_device_ctrl_methods; 3736 break; 3737 case UE_INTERRUPT: 3738 ep->methods = &ehci_device_intr_methods; 3739 break; 3740 case UE_ISOCHRONOUS: 3741 if (udev->speed == USB_SPEED_HIGH) { 3742 ep->methods = &ehci_device_isoc_hs_methods; 3743 } else if (udev->speed == USB_SPEED_FULL) { 3744 ep->methods = &ehci_device_isoc_fs_methods; 3745 } 3746 break; 3747 case UE_BULK: 3748 ep->methods = &ehci_device_bulk_methods; 3749 break; 3750 default: 3751 /* do nothing */ 3752 break; 3753 } 3754 } 3755 done: 3756 return; 3757 } 3758 3759 static void 3760 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3761 { 3762 /* 3763 * Wait until the hardware has finished any possible use of 3764 * the transfer descriptor(s) and QH 3765 */ 3766 *pus = (1125); /* microseconds */ 3767 } 3768 3769 static void 3770 ehci_device_resume(struct usb_device *udev) 3771 { 3772 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3773 struct usb_xfer *xfer; 3774 const struct usb_pipe_methods *methods; 3775 3776 DPRINTF("\n"); 3777 3778 USB_BUS_LOCK(udev->bus); 3779 3780 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3781 if (xfer->xroot->udev == udev) { 3782 methods = xfer->endpoint->methods; 3783 3784 if ((methods == &ehci_device_bulk_methods) || 3785 (methods == &ehci_device_ctrl_methods)) { 3786 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3787 sc->sc_async_p_last); 3788 } 3789 if (methods == &ehci_device_intr_methods) { 3790 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3791 sc->sc_intr_p_last[xfer->qh_pos]); 3792 } 3793 } 3794 } 3795 3796 USB_BUS_UNLOCK(udev->bus); 3797 3798 return; 3799 } 3800 3801 static void 3802 ehci_device_suspend(struct usb_device *udev) 3803 { 3804 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3805 struct usb_xfer *xfer; 3806 const struct usb_pipe_methods *methods; 3807 3808 DPRINTF("\n"); 3809 3810 USB_BUS_LOCK(udev->bus); 3811 3812 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3813 if (xfer->xroot->udev == udev) { 3814 methods = xfer->endpoint->methods; 3815 3816 if ((methods == &ehci_device_bulk_methods) || 3817 (methods == &ehci_device_ctrl_methods)) { 3818 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3819 sc->sc_async_p_last); 3820 } 3821 if (methods == &ehci_device_intr_methods) { 3822 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3823 sc->sc_intr_p_last[xfer->qh_pos]); 3824 } 3825 } 3826 } 3827 3828 USB_BUS_UNLOCK(udev->bus); 3829 } 3830 3831 static void 3832 ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3833 { 3834 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3835 3836 switch (state) { 3837 case USB_HW_POWER_SUSPEND: 3838 case USB_HW_POWER_SHUTDOWN: 3839 ehci_suspend(sc); 3840 break; 3841 case USB_HW_POWER_RESUME: 3842 ehci_resume(sc); 3843 break; 3844 default: 3845 break; 3846 } 3847 } 3848 3849 static void 3850 ehci_set_hw_power(struct usb_bus *bus) 3851 { 3852 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3853 uint32_t temp; 3854 uint32_t flags; 3855 3856 DPRINTF("\n"); 3857 3858 USB_BUS_LOCK(bus); 3859 3860 flags = bus->hw_power_state; 3861 3862 temp = EOREAD4(sc, EHCI_USBCMD); 3863 3864 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3865 3866 if (flags & (USB_HW_POWER_CONTROL | 3867 USB_HW_POWER_BULK)) { 3868 DPRINTF("Async is active\n"); 3869 temp |= EHCI_CMD_ASE; 3870 } 3871 if (flags & (USB_HW_POWER_INTERRUPT | 3872 USB_HW_POWER_ISOC)) { 3873 DPRINTF("Periodic is active\n"); 3874 temp |= EHCI_CMD_PSE; 3875 } 3876 EOWRITE4(sc, EHCI_USBCMD, temp); 3877 3878 USB_BUS_UNLOCK(bus); 3879 3880 return; 3881 } 3882 3883 static void 3884 ehci_start_dma_delay_second(struct usb_xfer *xfer) 3885 { 3886 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3887 3888 DPRINTF("\n"); 3889 3890 /* trigger doorbell */ 3891 ehci_doorbell_async(sc); 3892 3893 /* give the doorbell 4ms */ 3894 usbd_transfer_timeout_ms(xfer, 3895 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3896 } 3897 3898 /* 3899 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3900 * controllers apparently cache the QH descriptors and need a message 3901 * that the cache needs to be discarded. 3902 */ 3903 static void 3904 ehci_start_dma_delay(struct usb_xfer *xfer) 3905 { 3906 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3907 3908 DPRINTF("\n"); 3909 3910 /* trigger doorbell */ 3911 ehci_doorbell_async(sc); 3912 3913 /* give the doorbell 4ms */ 3914 usbd_transfer_timeout_ms(xfer, 3915 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3916 } 3917 3918 static const struct usb_bus_methods ehci_bus_methods = 3919 { 3920 .endpoint_init = ehci_ep_init, 3921 .xfer_setup = ehci_xfer_setup, 3922 .xfer_unsetup = ehci_xfer_unsetup, 3923 .get_dma_delay = ehci_get_dma_delay, 3924 .device_resume = ehci_device_resume, 3925 .device_suspend = ehci_device_suspend, 3926 .set_hw_power = ehci_set_hw_power, 3927 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3928 .roothub_exec = ehci_roothub_exec, 3929 .xfer_poll = ehci_do_poll, 3930 .start_dma_delay = ehci_start_dma_delay, 3931 }; 3932