1 /*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41 /* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46 #include <sys/cdefs.h> 47 __FBSDID("$FreeBSD$"); 48 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR ehcidebug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #include <dev/usb/controller/ehci.h> 85 #include <dev/usb/controller/ehcireg.h> 86 87 #define EHCI_BUS2SC(bus) \ 88 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 89 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 90 91 #ifdef USB_DEBUG 92 static int ehcidebug = 0; 93 static int ehcinohighspeed = 0; 94 static int ehciiaadbug = 0; 95 static int ehcilostintrbug = 0; 96 97 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 98 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 99 &ehcidebug, 0, "Debug level"); 100 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 101 &ehcinohighspeed, 0, "Disable High Speed USB"); 102 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW, 103 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 104 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW, 105 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 106 107 TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 108 TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 109 TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug); 110 TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug); 111 112 static void ehci_dump_regs(ehci_softc_t *sc); 113 static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 114 115 #endif 116 117 #define EHCI_INTR_ENDPT 1 118 119 extern struct usb_bus_methods ehci_bus_methods; 120 extern struct usb_pipe_methods ehci_device_bulk_methods; 121 extern struct usb_pipe_methods ehci_device_ctrl_methods; 122 extern struct usb_pipe_methods ehci_device_intr_methods; 123 extern struct usb_pipe_methods ehci_device_isoc_fs_methods; 124 extern struct usb_pipe_methods ehci_device_isoc_hs_methods; 125 126 static void ehci_do_poll(struct usb_bus *); 127 static void ehci_device_done(struct usb_xfer *, usb_error_t); 128 static uint8_t ehci_check_transfer(struct usb_xfer *); 129 static void ehci_timeout(void *); 130 static void ehci_poll_timeout(void *); 131 132 static void ehci_root_intr(ehci_softc_t *sc); 133 134 struct ehci_std_temp { 135 ehci_softc_t *sc; 136 struct usb_page_cache *pc; 137 ehci_qtd_t *td; 138 ehci_qtd_t *td_next; 139 uint32_t average; 140 uint32_t qtd_status; 141 uint32_t len; 142 uint16_t max_frame_size; 143 uint8_t shortpkt; 144 uint8_t auto_data_toggle; 145 uint8_t setup_alt_next; 146 uint8_t last_frame; 147 }; 148 149 void 150 ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 151 { 152 ehci_softc_t *sc = EHCI_BUS2SC(bus); 153 uint32_t i; 154 155 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 156 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 157 158 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 159 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 160 161 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 162 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.intr_start_pc + i, 166 sc->sc_hw.intr_start_pg + i, 167 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 168 } 169 170 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 171 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 172 sc->sc_hw.isoc_hs_start_pg + i, 173 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 174 } 175 176 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 177 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 178 sc->sc_hw.isoc_fs_start_pg + i, 179 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 180 } 181 } 182 183 usb_error_t 184 ehci_reset(ehci_softc_t *sc) 185 { 186 uint32_t hcr; 187 int i; 188 189 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 190 for (i = 0; i < 100; i++) { 191 usb_pause_mtx(NULL, hz / 1000); 192 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 193 if (!hcr) { 194 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 195 /* 196 * Force USBMODE as requested. Controllers 197 * may have multiple operating modes. 198 */ 199 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 200 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 201 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 202 device_printf(sc->sc_bus.bdev, 203 "set host controller mode\n"); 204 } 205 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 206 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 207 device_printf(sc->sc_bus.bdev, 208 "set big-endian mode\n"); 209 } 210 EOWRITE4(sc, EHCI_USBMODE, usbmode); 211 } 212 return (0); 213 } 214 } 215 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 216 return (USB_ERR_IOERROR); 217 } 218 219 static usb_error_t 220 ehci_hcreset(ehci_softc_t *sc) 221 { 222 uint32_t hcr; 223 int i; 224 225 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 226 for (i = 0; i < 100; i++) { 227 usb_pause_mtx(NULL, hz / 1000); 228 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 229 if (hcr) 230 break; 231 } 232 if (!hcr) 233 /* 234 * Fall through and try reset anyway even though 235 * Table 2-9 in the EHCI spec says this will result 236 * in undefined behavior. 237 */ 238 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 239 240 return ehci_reset(sc); 241 } 242 243 usb_error_t 244 ehci_init(ehci_softc_t *sc) 245 { 246 struct usb_page_search buf_res; 247 uint32_t version; 248 uint32_t sparams; 249 uint32_t cparams; 250 uint32_t hcr; 251 uint16_t i; 252 uint16_t x; 253 uint16_t y; 254 uint16_t bit; 255 usb_error_t err = 0; 256 257 DPRINTF("start\n"); 258 259 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 260 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 261 262 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 263 264 #ifdef USB_DEBUG 265 if (ehciiaadbug) 266 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 267 if (ehcilostintrbug) 268 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 269 if (ehcidebug > 2) { 270 ehci_dump_regs(sc); 271 } 272 #endif 273 274 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 275 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 276 version >> 8, version & 0xff); 277 278 sparams = EREAD4(sc, EHCI_HCSPARAMS); 279 DPRINTF("sparams=0x%x\n", sparams); 280 281 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 282 cparams = EREAD4(sc, EHCI_HCCPARAMS); 283 DPRINTF("cparams=0x%x\n", cparams); 284 285 if (EHCI_HCC_64BIT(cparams)) { 286 DPRINTF("HCC uses 64-bit structures\n"); 287 288 /* MUST clear segment register if 64 bit capable */ 289 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 290 } 291 sc->sc_bus.usbrev = USB_REV_2_0; 292 293 /* Reset the controller */ 294 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 295 296 err = ehci_hcreset(sc); 297 if (err) { 298 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 299 return (err); 300 } 301 /* 302 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 303 * bytes 2: 256*4 bytes 3: unknown 304 */ 305 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 306 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 307 return (USB_ERR_IOERROR); 308 } 309 /* set up the bus struct */ 310 sc->sc_bus.methods = &ehci_bus_methods; 311 312 sc->sc_eintrs = EHCI_NORMAL_INTRS; 313 314 if (1) { 315 struct ehci_qh_sub *qh; 316 317 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 318 319 qh = buf_res.buffer; 320 321 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 322 323 /* init terminate TD */ 324 qh->qtd_next = 325 htohc32(sc, EHCI_LINK_TERMINATE); 326 qh->qtd_altnext = 327 htohc32(sc, EHCI_LINK_TERMINATE); 328 qh->qtd_status = 329 htohc32(sc, EHCI_QTD_HALTED); 330 } 331 332 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 333 ehci_qh_t *qh; 334 335 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 336 337 qh = buf_res.buffer; 338 339 /* initialize page cache pointer */ 340 341 qh->page_cache = sc->sc_hw.intr_start_pc + i; 342 343 /* store a pointer to queue head */ 344 345 sc->sc_intr_p_last[i] = qh; 346 347 qh->qh_self = 348 htohc32(sc, buf_res.physaddr) | 349 htohc32(sc, EHCI_LINK_QH); 350 351 qh->qh_endp = 352 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 353 qh->qh_endphub = 354 htohc32(sc, EHCI_QH_SET_MULT(1)); 355 qh->qh_curqtd = 0; 356 357 qh->qh_qtd.qtd_next = 358 htohc32(sc, EHCI_LINK_TERMINATE); 359 qh->qh_qtd.qtd_altnext = 360 htohc32(sc, EHCI_LINK_TERMINATE); 361 qh->qh_qtd.qtd_status = 362 htohc32(sc, EHCI_QTD_HALTED); 363 } 364 365 /* 366 * the QHs are arranged to give poll intervals that are 367 * powers of 2 times 1ms 368 */ 369 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 370 while (bit) { 371 x = bit; 372 while (x & bit) { 373 ehci_qh_t *qh_x; 374 ehci_qh_t *qh_y; 375 376 y = (x ^ bit) | (bit / 2); 377 378 qh_x = sc->sc_intr_p_last[x]; 379 qh_y = sc->sc_intr_p_last[y]; 380 381 /* 382 * the next QH has half the poll interval 383 */ 384 qh_x->qh_link = qh_y->qh_self; 385 386 x++; 387 } 388 bit >>= 1; 389 } 390 391 if (1) { 392 ehci_qh_t *qh; 393 394 qh = sc->sc_intr_p_last[0]; 395 396 /* the last (1ms) QH terminates */ 397 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 398 } 399 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 400 ehci_sitd_t *sitd; 401 ehci_itd_t *itd; 402 403 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 404 405 sitd = buf_res.buffer; 406 407 /* initialize page cache pointer */ 408 409 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 410 411 /* store a pointer to the transfer descriptor */ 412 413 sc->sc_isoc_fs_p_last[i] = sitd; 414 415 /* initialize full speed isochronous */ 416 417 sitd->sitd_self = 418 htohc32(sc, buf_res.physaddr) | 419 htohc32(sc, EHCI_LINK_SITD); 420 421 sitd->sitd_back = 422 htohc32(sc, EHCI_LINK_TERMINATE); 423 424 sitd->sitd_next = 425 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 426 427 428 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 429 430 itd = buf_res.buffer; 431 432 /* initialize page cache pointer */ 433 434 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 435 436 /* store a pointer to the transfer descriptor */ 437 438 sc->sc_isoc_hs_p_last[i] = itd; 439 440 /* initialize high speed isochronous */ 441 442 itd->itd_self = 443 htohc32(sc, buf_res.physaddr) | 444 htohc32(sc, EHCI_LINK_ITD); 445 446 itd->itd_next = 447 sitd->sitd_self; 448 } 449 450 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 451 452 if (1) { 453 uint32_t *pframes; 454 455 pframes = buf_res.buffer; 456 457 /* 458 * execution order: 459 * pframes -> high speed isochronous -> 460 * full speed isochronous -> interrupt QH's 461 */ 462 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 463 pframes[i] = sc->sc_isoc_hs_p_last 464 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 465 } 466 } 467 /* setup sync list pointer */ 468 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 469 470 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 471 472 if (1) { 473 474 ehci_qh_t *qh; 475 476 qh = buf_res.buffer; 477 478 /* initialize page cache pointer */ 479 480 qh->page_cache = &sc->sc_hw.async_start_pc; 481 482 /* store a pointer to the queue head */ 483 484 sc->sc_async_p_last = qh; 485 486 /* init dummy QH that starts the async list */ 487 488 qh->qh_self = 489 htohc32(sc, buf_res.physaddr) | 490 htohc32(sc, EHCI_LINK_QH); 491 492 /* fill the QH */ 493 qh->qh_endp = 494 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 495 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 496 qh->qh_link = qh->qh_self; 497 qh->qh_curqtd = 0; 498 499 /* fill the overlay qTD */ 500 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 501 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 502 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 503 } 504 /* flush all cache into memory */ 505 506 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 507 508 #ifdef USB_DEBUG 509 if (ehcidebug) { 510 ehci_dump_sqh(sc, sc->sc_async_p_last); 511 } 512 #endif 513 514 /* setup async list pointer */ 515 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 516 517 518 /* enable interrupts */ 519 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 520 521 /* turn on controller */ 522 EOWRITE4(sc, EHCI_USBCMD, 523 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 524 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 525 EHCI_CMD_ASE | 526 EHCI_CMD_PSE | 527 EHCI_CMD_RS); 528 529 /* Take over port ownership */ 530 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 531 532 for (i = 0; i < 100; i++) { 533 usb_pause_mtx(NULL, hz / 1000); 534 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 535 if (!hcr) { 536 break; 537 } 538 } 539 if (hcr) { 540 device_printf(sc->sc_bus.bdev, "run timeout\n"); 541 return (USB_ERR_IOERROR); 542 } 543 544 if (!err) { 545 /* catch any lost interrupts */ 546 ehci_do_poll(&sc->sc_bus); 547 } 548 return (err); 549 } 550 551 /* 552 * shut down the controller when the system is going down 553 */ 554 void 555 ehci_detach(ehci_softc_t *sc) 556 { 557 USB_BUS_LOCK(&sc->sc_bus); 558 559 usb_callout_stop(&sc->sc_tmo_pcd); 560 usb_callout_stop(&sc->sc_tmo_poll); 561 562 EOWRITE4(sc, EHCI_USBINTR, 0); 563 USB_BUS_UNLOCK(&sc->sc_bus); 564 565 if (ehci_hcreset(sc)) { 566 DPRINTF("reset failed!\n"); 567 } 568 569 /* XXX let stray task complete */ 570 usb_pause_mtx(NULL, hz / 20); 571 572 usb_callout_drain(&sc->sc_tmo_pcd); 573 usb_callout_drain(&sc->sc_tmo_poll); 574 } 575 576 void 577 ehci_suspend(ehci_softc_t *sc) 578 { 579 uint32_t cmd; 580 uint32_t hcr; 581 uint8_t i; 582 583 USB_BUS_LOCK(&sc->sc_bus); 584 585 for (i = 1; i <= sc->sc_noport; i++) { 586 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 587 if (((cmd & EHCI_PS_PO) == 0) && 588 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 589 EOWRITE4(sc, EHCI_PORTSC(i), 590 cmd | EHCI_PS_SUSP); 591 } 592 } 593 594 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 595 596 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 597 EOWRITE4(sc, EHCI_USBCMD, cmd); 598 599 for (i = 0; i < 100; i++) { 600 hcr = EOREAD4(sc, EHCI_USBSTS) & 601 (EHCI_STS_ASS | EHCI_STS_PSS); 602 603 if (hcr == 0) { 604 break; 605 } 606 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 607 } 608 609 if (hcr != 0) { 610 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 611 } 612 cmd &= ~EHCI_CMD_RS; 613 EOWRITE4(sc, EHCI_USBCMD, cmd); 614 615 for (i = 0; i < 100; i++) { 616 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 617 if (hcr == EHCI_STS_HCH) { 618 break; 619 } 620 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 621 } 622 623 if (hcr != EHCI_STS_HCH) { 624 device_printf(sc->sc_bus.bdev, 625 "config timeout\n"); 626 } 627 USB_BUS_UNLOCK(&sc->sc_bus); 628 } 629 630 void 631 ehci_resume(ehci_softc_t *sc) 632 { 633 struct usb_page_search buf_res; 634 uint32_t cmd; 635 uint32_t hcr; 636 uint8_t i; 637 638 USB_BUS_LOCK(&sc->sc_bus); 639 640 /* restore things in case the bios doesn't */ 641 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 642 643 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 644 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 645 646 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 647 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 648 649 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 650 651 hcr = 0; 652 for (i = 1; i <= sc->sc_noport; i++) { 653 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 654 if (((cmd & EHCI_PS_PO) == 0) && 655 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 656 EOWRITE4(sc, EHCI_PORTSC(i), 657 cmd | EHCI_PS_FPR); 658 hcr = 1; 659 } 660 } 661 662 if (hcr) { 663 usb_pause_mtx(&sc->sc_bus.bus_mtx, 664 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 665 666 for (i = 1; i <= sc->sc_noport; i++) { 667 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 668 if (((cmd & EHCI_PS_PO) == 0) && 669 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 670 EOWRITE4(sc, EHCI_PORTSC(i), 671 cmd & ~EHCI_PS_FPR); 672 } 673 } 674 } 675 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 676 677 for (i = 0; i < 100; i++) { 678 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 679 if (hcr != EHCI_STS_HCH) { 680 break; 681 } 682 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 683 } 684 if (hcr == EHCI_STS_HCH) { 685 device_printf(sc->sc_bus.bdev, "config timeout\n"); 686 } 687 688 USB_BUS_UNLOCK(&sc->sc_bus); 689 690 usb_pause_mtx(NULL, 691 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 692 693 /* catch any lost interrupts */ 694 ehci_do_poll(&sc->sc_bus); 695 } 696 697 void 698 ehci_shutdown(ehci_softc_t *sc) 699 { 700 DPRINTF("stopping the HC\n"); 701 702 if (ehci_hcreset(sc)) { 703 DPRINTF("reset failed!\n"); 704 } 705 } 706 707 #ifdef USB_DEBUG 708 static void 709 ehci_dump_regs(ehci_softc_t *sc) 710 { 711 uint32_t i; 712 713 i = EOREAD4(sc, EHCI_USBCMD); 714 printf("cmd=0x%08x\n", i); 715 716 if (i & EHCI_CMD_ITC_1) 717 printf(" EHCI_CMD_ITC_1\n"); 718 if (i & EHCI_CMD_ITC_2) 719 printf(" EHCI_CMD_ITC_2\n"); 720 if (i & EHCI_CMD_ITC_4) 721 printf(" EHCI_CMD_ITC_4\n"); 722 if (i & EHCI_CMD_ITC_8) 723 printf(" EHCI_CMD_ITC_8\n"); 724 if (i & EHCI_CMD_ITC_16) 725 printf(" EHCI_CMD_ITC_16\n"); 726 if (i & EHCI_CMD_ITC_32) 727 printf(" EHCI_CMD_ITC_32\n"); 728 if (i & EHCI_CMD_ITC_64) 729 printf(" EHCI_CMD_ITC_64\n"); 730 if (i & EHCI_CMD_ASPME) 731 printf(" EHCI_CMD_ASPME\n"); 732 if (i & EHCI_CMD_ASPMC) 733 printf(" EHCI_CMD_ASPMC\n"); 734 if (i & EHCI_CMD_LHCR) 735 printf(" EHCI_CMD_LHCR\n"); 736 if (i & EHCI_CMD_IAAD) 737 printf(" EHCI_CMD_IAAD\n"); 738 if (i & EHCI_CMD_ASE) 739 printf(" EHCI_CMD_ASE\n"); 740 if (i & EHCI_CMD_PSE) 741 printf(" EHCI_CMD_PSE\n"); 742 if (i & EHCI_CMD_FLS_M) 743 printf(" EHCI_CMD_FLS_M\n"); 744 if (i & EHCI_CMD_HCRESET) 745 printf(" EHCI_CMD_HCRESET\n"); 746 if (i & EHCI_CMD_RS) 747 printf(" EHCI_CMD_RS\n"); 748 749 i = EOREAD4(sc, EHCI_USBSTS); 750 751 printf("sts=0x%08x\n", i); 752 753 if (i & EHCI_STS_ASS) 754 printf(" EHCI_STS_ASS\n"); 755 if (i & EHCI_STS_PSS) 756 printf(" EHCI_STS_PSS\n"); 757 if (i & EHCI_STS_REC) 758 printf(" EHCI_STS_REC\n"); 759 if (i & EHCI_STS_HCH) 760 printf(" EHCI_STS_HCH\n"); 761 if (i & EHCI_STS_IAA) 762 printf(" EHCI_STS_IAA\n"); 763 if (i & EHCI_STS_HSE) 764 printf(" EHCI_STS_HSE\n"); 765 if (i & EHCI_STS_FLR) 766 printf(" EHCI_STS_FLR\n"); 767 if (i & EHCI_STS_PCD) 768 printf(" EHCI_STS_PCD\n"); 769 if (i & EHCI_STS_ERRINT) 770 printf(" EHCI_STS_ERRINT\n"); 771 if (i & EHCI_STS_INT) 772 printf(" EHCI_STS_INT\n"); 773 774 printf("ien=0x%08x\n", 775 EOREAD4(sc, EHCI_USBINTR)); 776 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 777 EOREAD4(sc, EHCI_FRINDEX), 778 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 779 EOREAD4(sc, EHCI_PERIODICLISTBASE), 780 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 781 for (i = 1; i <= sc->sc_noport; i++) { 782 printf("port %d status=0x%08x\n", i, 783 EOREAD4(sc, EHCI_PORTSC(i))); 784 } 785 } 786 787 static void 788 ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 789 { 790 link = hc32toh(sc, link); 791 printf("0x%08x", link); 792 if (link & EHCI_LINK_TERMINATE) 793 printf("<T>"); 794 else { 795 printf("<"); 796 if (type) { 797 switch (EHCI_LINK_TYPE(link)) { 798 case EHCI_LINK_ITD: 799 printf("ITD"); 800 break; 801 case EHCI_LINK_QH: 802 printf("QH"); 803 break; 804 case EHCI_LINK_SITD: 805 printf("SITD"); 806 break; 807 case EHCI_LINK_FSTN: 808 printf("FSTN"); 809 break; 810 } 811 } 812 printf(">"); 813 } 814 } 815 816 static void 817 ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 818 { 819 uint32_t s; 820 821 printf(" next="); 822 ehci_dump_link(sc, qtd->qtd_next, 0); 823 printf(" altnext="); 824 ehci_dump_link(sc, qtd->qtd_altnext, 0); 825 printf("\n"); 826 s = hc32toh(sc, qtd->qtd_status); 827 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 828 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 829 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 830 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 831 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 832 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 833 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 834 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 835 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 836 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 837 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 838 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 839 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 840 841 for (s = 0; s < 5; s++) { 842 printf(" buffer[%d]=0x%08x\n", s, 843 hc32toh(sc, qtd->qtd_buffer[s])); 844 } 845 for (s = 0; s < 5; s++) { 846 printf(" buffer_hi[%d]=0x%08x\n", s, 847 hc32toh(sc, qtd->qtd_buffer_hi[s])); 848 } 849 } 850 851 static uint8_t 852 ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 853 { 854 uint8_t temp; 855 856 usb_pc_cpu_invalidate(sqtd->page_cache); 857 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 858 ehci_dump_qtd(sc, sqtd); 859 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 860 return (temp); 861 } 862 863 static void 864 ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 865 { 866 uint16_t i; 867 uint8_t stop; 868 869 stop = 0; 870 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 871 stop = ehci_dump_sqtd(sc, sqtd); 872 } 873 if (sqtd) { 874 printf("dump aborted, too many TDs\n"); 875 } 876 } 877 878 static void 879 ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 880 { 881 uint32_t endp; 882 uint32_t endphub; 883 884 usb_pc_cpu_invalidate(qh->page_cache); 885 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 886 printf(" link="); 887 ehci_dump_link(sc, qh->qh_link, 1); 888 printf("\n"); 889 endp = hc32toh(sc, qh->qh_endp); 890 printf(" endp=0x%08x\n", endp); 891 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 892 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 893 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 894 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 895 printf(" mpl=0x%x ctl=%d nrl=%d\n", 896 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 897 EHCI_QH_GET_NRL(endp)); 898 endphub = hc32toh(sc, qh->qh_endphub); 899 printf(" endphub=0x%08x\n", endphub); 900 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 901 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 902 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 903 EHCI_QH_GET_MULT(endphub)); 904 printf(" curqtd="); 905 ehci_dump_link(sc, qh->qh_curqtd, 0); 906 printf("\n"); 907 printf("Overlay qTD:\n"); 908 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 909 } 910 911 static void 912 ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 913 { 914 usb_pc_cpu_invalidate(sitd->page_cache); 915 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 916 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 917 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 918 hc32toh(sc, sitd->sitd_portaddr), 919 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 920 ? "in" : "out", 921 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 922 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 923 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 924 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 925 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 926 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 927 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 928 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 929 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 930 hc32toh(sc, sitd->sitd_back), 931 hc32toh(sc, sitd->sitd_bp[0]), 932 hc32toh(sc, sitd->sitd_bp[1]), 933 hc32toh(sc, sitd->sitd_bp_hi[0]), 934 hc32toh(sc, sitd->sitd_bp_hi[1])); 935 } 936 937 static void 938 ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 939 { 940 usb_pc_cpu_invalidate(itd->page_cache); 941 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 942 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 943 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 944 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 945 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 946 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 947 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 948 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 949 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 950 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 951 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 952 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 953 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 954 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 955 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 956 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 957 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 958 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 959 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 960 printf(" addr=0x%02x; endpt=0x%01x\n", 961 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 962 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 963 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 964 printf(" dir=%s; mpl=0x%02x\n", 965 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 966 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 967 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 968 hc32toh(sc, itd->itd_bp[2]), 969 hc32toh(sc, itd->itd_bp[3]), 970 hc32toh(sc, itd->itd_bp[4]), 971 hc32toh(sc, itd->itd_bp[5]), 972 hc32toh(sc, itd->itd_bp[6])); 973 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 974 " 0x%08x,0x%08x,0x%08x\n", 975 hc32toh(sc, itd->itd_bp_hi[0]), 976 hc32toh(sc, itd->itd_bp_hi[1]), 977 hc32toh(sc, itd->itd_bp_hi[2]), 978 hc32toh(sc, itd->itd_bp_hi[3]), 979 hc32toh(sc, itd->itd_bp_hi[4]), 980 hc32toh(sc, itd->itd_bp_hi[5]), 981 hc32toh(sc, itd->itd_bp_hi[6])); 982 } 983 984 static void 985 ehci_dump_isoc(ehci_softc_t *sc) 986 { 987 ehci_itd_t *itd; 988 ehci_sitd_t *sitd; 989 uint16_t max = 1000; 990 uint16_t pos; 991 992 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 993 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 994 995 printf("%s: isochronous dump from frame 0x%03x:\n", 996 __FUNCTION__, pos); 997 998 itd = sc->sc_isoc_hs_p_last[pos]; 999 sitd = sc->sc_isoc_fs_p_last[pos]; 1000 1001 while (itd && max && max--) { 1002 ehci_dump_itd(sc, itd); 1003 itd = itd->prev; 1004 } 1005 1006 while (sitd && max && max--) { 1007 ehci_dump_sitd(sc, sitd); 1008 sitd = sitd->prev; 1009 } 1010 } 1011 1012 #endif 1013 1014 static void 1015 ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 1016 { 1017 /* check for early completion */ 1018 if (ehci_check_transfer(xfer)) { 1019 return; 1020 } 1021 /* put transfer on interrupt queue */ 1022 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1023 1024 /* start timeout, if any */ 1025 if (xfer->timeout != 0) { 1026 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 1027 } 1028 } 1029 1030 #define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 1031 static ehci_sitd_t * 1032 _ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1033 { 1034 DPRINTFN(11, "%p to %p\n", std, last); 1035 1036 /* (sc->sc_bus.mtx) must be locked */ 1037 1038 std->next = last->next; 1039 std->sitd_next = last->sitd_next; 1040 1041 std->prev = last; 1042 1043 usb_pc_cpu_flush(std->page_cache); 1044 1045 /* 1046 * the last->next->prev is never followed: std->next->prev = std; 1047 */ 1048 last->next = std; 1049 last->sitd_next = std->sitd_self; 1050 1051 usb_pc_cpu_flush(last->page_cache); 1052 1053 return (std); 1054 } 1055 1056 #define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1057 static ehci_itd_t * 1058 _ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1059 { 1060 DPRINTFN(11, "%p to %p\n", std, last); 1061 1062 /* (sc->sc_bus.mtx) must be locked */ 1063 1064 std->next = last->next; 1065 std->itd_next = last->itd_next; 1066 1067 std->prev = last; 1068 1069 usb_pc_cpu_flush(std->page_cache); 1070 1071 /* 1072 * the last->next->prev is never followed: std->next->prev = std; 1073 */ 1074 last->next = std; 1075 last->itd_next = std->itd_self; 1076 1077 usb_pc_cpu_flush(last->page_cache); 1078 1079 return (std); 1080 } 1081 1082 #define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1083 static ehci_qh_t * 1084 _ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1085 { 1086 DPRINTFN(11, "%p to %p\n", sqh, last); 1087 1088 if (sqh->prev != NULL) { 1089 /* should not happen */ 1090 DPRINTFN(0, "QH already linked!\n"); 1091 return (last); 1092 } 1093 /* (sc->sc_bus.mtx) must be locked */ 1094 1095 sqh->next = last->next; 1096 sqh->qh_link = last->qh_link; 1097 1098 sqh->prev = last; 1099 1100 usb_pc_cpu_flush(sqh->page_cache); 1101 1102 /* 1103 * the last->next->prev is never followed: sqh->next->prev = sqh; 1104 */ 1105 1106 last->next = sqh; 1107 last->qh_link = sqh->qh_self; 1108 1109 usb_pc_cpu_flush(last->page_cache); 1110 1111 return (sqh); 1112 } 1113 1114 #define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1115 static ehci_sitd_t * 1116 _ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1117 { 1118 DPRINTFN(11, "%p from %p\n", std, last); 1119 1120 /* (sc->sc_bus.mtx) must be locked */ 1121 1122 std->prev->next = std->next; 1123 std->prev->sitd_next = std->sitd_next; 1124 1125 usb_pc_cpu_flush(std->prev->page_cache); 1126 1127 if (std->next) { 1128 std->next->prev = std->prev; 1129 usb_pc_cpu_flush(std->next->page_cache); 1130 } 1131 return ((last == std) ? std->prev : last); 1132 } 1133 1134 #define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1135 static ehci_itd_t * 1136 _ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1137 { 1138 DPRINTFN(11, "%p from %p\n", std, last); 1139 1140 /* (sc->sc_bus.mtx) must be locked */ 1141 1142 std->prev->next = std->next; 1143 std->prev->itd_next = std->itd_next; 1144 1145 usb_pc_cpu_flush(std->prev->page_cache); 1146 1147 if (std->next) { 1148 std->next->prev = std->prev; 1149 usb_pc_cpu_flush(std->next->page_cache); 1150 } 1151 return ((last == std) ? std->prev : last); 1152 } 1153 1154 #define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1155 static ehci_qh_t * 1156 _ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1157 { 1158 DPRINTFN(11, "%p from %p\n", sqh, last); 1159 1160 /* (sc->sc_bus.mtx) must be locked */ 1161 1162 /* only remove if not removed from a queue */ 1163 if (sqh->prev) { 1164 1165 sqh->prev->next = sqh->next; 1166 sqh->prev->qh_link = sqh->qh_link; 1167 1168 usb_pc_cpu_flush(sqh->prev->page_cache); 1169 1170 if (sqh->next) { 1171 sqh->next->prev = sqh->prev; 1172 usb_pc_cpu_flush(sqh->next->page_cache); 1173 } 1174 last = ((last == sqh) ? sqh->prev : last); 1175 1176 sqh->prev = 0; 1177 1178 usb_pc_cpu_flush(sqh->page_cache); 1179 } 1180 return (last); 1181 } 1182 1183 static void 1184 ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1185 { 1186 uint16_t rem; 1187 uint8_t dt; 1188 1189 /* count number of full packets */ 1190 dt = (actlen / xfer->max_packet_size) & 1; 1191 1192 /* compute remainder */ 1193 rem = actlen % xfer->max_packet_size; 1194 1195 if (rem > 0) 1196 dt ^= 1; /* short packet at the end */ 1197 else if (actlen != xlen) 1198 dt ^= 1; /* zero length packet at the end */ 1199 1200 xfer->endpoint->toggle_next ^= dt; 1201 } 1202 1203 static usb_error_t 1204 ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1205 { 1206 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1207 ehci_qtd_t *td; 1208 ehci_qtd_t *td_alt_next; 1209 uint32_t status; 1210 uint16_t len; 1211 1212 td = xfer->td_transfer_cache; 1213 td_alt_next = td->alt_next; 1214 1215 if (xfer->aframes != xfer->nframes) { 1216 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1217 } 1218 while (1) { 1219 1220 usb_pc_cpu_invalidate(td->page_cache); 1221 status = hc32toh(sc, td->qtd_status); 1222 1223 len = EHCI_QTD_GET_BYTES(status); 1224 1225 /* 1226 * Verify the status length and 1227 * add the length to "frlengths[]": 1228 */ 1229 if (len > td->len) { 1230 /* should not happen */ 1231 DPRINTF("Invalid status length, " 1232 "0x%04x/0x%04x bytes\n", len, td->len); 1233 status |= EHCI_QTD_HALTED; 1234 } else if (xfer->aframes != xfer->nframes) { 1235 xfer->frlengths[xfer->aframes] += td->len - len; 1236 /* manually update data toggle */ 1237 ehci_data_toggle_update(xfer, td->len - len, td->len); 1238 } 1239 1240 /* Check for last transfer */ 1241 if (((void *)td) == xfer->td_transfer_last) { 1242 td = NULL; 1243 break; 1244 } 1245 /* Check for transfer error */ 1246 if (status & EHCI_QTD_HALTED) { 1247 /* the transfer is finished */ 1248 td = NULL; 1249 break; 1250 } 1251 /* Check for short transfer */ 1252 if (len > 0) { 1253 if (xfer->flags_int.short_frames_ok) { 1254 /* follow alt next */ 1255 td = td->alt_next; 1256 } else { 1257 /* the transfer is finished */ 1258 td = NULL; 1259 } 1260 break; 1261 } 1262 td = td->obj_next; 1263 1264 if (td->alt_next != td_alt_next) { 1265 /* this USB frame is complete */ 1266 break; 1267 } 1268 } 1269 1270 /* update transfer cache */ 1271 1272 xfer->td_transfer_cache = td; 1273 1274 #ifdef USB_DEBUG 1275 if (status & EHCI_QTD_STATERRS) { 1276 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1277 "status=%s%s%s%s%s%s%s%s\n", 1278 xfer->address, xfer->endpointno, xfer->aframes, 1279 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1280 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1281 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1282 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1283 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1284 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1285 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1286 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1287 } 1288 #endif 1289 1290 return ((status & EHCI_QTD_HALTED) ? 1291 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1292 } 1293 1294 static void 1295 ehci_non_isoc_done(struct usb_xfer *xfer) 1296 { 1297 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1298 ehci_qh_t *qh; 1299 uint32_t status; 1300 usb_error_t err = 0; 1301 1302 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1303 xfer, xfer->endpoint); 1304 1305 #ifdef USB_DEBUG 1306 if (ehcidebug > 10) { 1307 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1308 1309 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1310 } 1311 #endif 1312 1313 /* extract data toggle directly from the QH's overlay area */ 1314 1315 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1316 1317 usb_pc_cpu_invalidate(qh->page_cache); 1318 1319 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1320 1321 /* reset scanner */ 1322 1323 xfer->td_transfer_cache = xfer->td_transfer_first; 1324 1325 if (xfer->flags_int.control_xfr) { 1326 1327 if (xfer->flags_int.control_hdr) { 1328 1329 err = ehci_non_isoc_done_sub(xfer); 1330 } 1331 xfer->aframes = 1; 1332 1333 if (xfer->td_transfer_cache == NULL) { 1334 goto done; 1335 } 1336 } 1337 while (xfer->aframes != xfer->nframes) { 1338 1339 err = ehci_non_isoc_done_sub(xfer); 1340 xfer->aframes++; 1341 1342 if (xfer->td_transfer_cache == NULL) { 1343 goto done; 1344 } 1345 } 1346 1347 if (xfer->flags_int.control_xfr && 1348 !xfer->flags_int.control_act) { 1349 1350 err = ehci_non_isoc_done_sub(xfer); 1351 } 1352 done: 1353 ehci_device_done(xfer, err); 1354 } 1355 1356 /*------------------------------------------------------------------------* 1357 * ehci_check_transfer 1358 * 1359 * Return values: 1360 * 0: USB transfer is not finished 1361 * Else: USB transfer is finished 1362 *------------------------------------------------------------------------*/ 1363 static uint8_t 1364 ehci_check_transfer(struct usb_xfer *xfer) 1365 { 1366 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1367 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1368 1369 uint32_t status; 1370 1371 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1372 1373 if (methods == &ehci_device_isoc_fs_methods) { 1374 ehci_sitd_t *td; 1375 1376 /* isochronous full speed transfer */ 1377 1378 td = xfer->td_transfer_last; 1379 usb_pc_cpu_invalidate(td->page_cache); 1380 status = hc32toh(sc, td->sitd_status); 1381 1382 /* also check if first is complete */ 1383 1384 td = xfer->td_transfer_first; 1385 usb_pc_cpu_invalidate(td->page_cache); 1386 status |= hc32toh(sc, td->sitd_status); 1387 1388 if (!(status & EHCI_SITD_ACTIVE)) { 1389 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1390 goto transferred; 1391 } 1392 } else if (methods == &ehci_device_isoc_hs_methods) { 1393 ehci_itd_t *td; 1394 1395 /* isochronous high speed transfer */ 1396 1397 /* check last transfer */ 1398 td = xfer->td_transfer_last; 1399 usb_pc_cpu_invalidate(td->page_cache); 1400 status = td->itd_status[0]; 1401 status |= td->itd_status[1]; 1402 status |= td->itd_status[2]; 1403 status |= td->itd_status[3]; 1404 status |= td->itd_status[4]; 1405 status |= td->itd_status[5]; 1406 status |= td->itd_status[6]; 1407 status |= td->itd_status[7]; 1408 1409 /* also check first transfer */ 1410 td = xfer->td_transfer_first; 1411 usb_pc_cpu_invalidate(td->page_cache); 1412 status |= td->itd_status[0]; 1413 status |= td->itd_status[1]; 1414 status |= td->itd_status[2]; 1415 status |= td->itd_status[3]; 1416 status |= td->itd_status[4]; 1417 status |= td->itd_status[5]; 1418 status |= td->itd_status[6]; 1419 status |= td->itd_status[7]; 1420 1421 /* if no transactions are active we continue */ 1422 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1423 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1424 goto transferred; 1425 } 1426 } else { 1427 ehci_qtd_t *td; 1428 ehci_qh_t *qh; 1429 1430 /* non-isochronous transfer */ 1431 1432 /* 1433 * check whether there is an error somewhere in the middle, 1434 * or whether there was a short packet (SPD and not ACTIVE) 1435 */ 1436 td = xfer->td_transfer_cache; 1437 1438 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1439 1440 usb_pc_cpu_invalidate(qh->page_cache); 1441 1442 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1443 if (status & EHCI_QTD_ACTIVE) { 1444 /* transfer is pending */ 1445 goto done; 1446 } 1447 1448 while (1) { 1449 usb_pc_cpu_invalidate(td->page_cache); 1450 status = hc32toh(sc, td->qtd_status); 1451 1452 /* 1453 * Check if there is an active TD which 1454 * indicates that the transfer isn't done. 1455 */ 1456 if (status & EHCI_QTD_ACTIVE) { 1457 /* update cache */ 1458 xfer->td_transfer_cache = td; 1459 goto done; 1460 } 1461 /* 1462 * last transfer descriptor makes the transfer done 1463 */ 1464 if (((void *)td) == xfer->td_transfer_last) { 1465 break; 1466 } 1467 /* 1468 * any kind of error makes the transfer done 1469 */ 1470 if (status & EHCI_QTD_HALTED) { 1471 break; 1472 } 1473 /* 1474 * if there is no alternate next transfer, a short 1475 * packet also makes the transfer done 1476 */ 1477 if (EHCI_QTD_GET_BYTES(status)) { 1478 if (xfer->flags_int.short_frames_ok) { 1479 /* follow alt next */ 1480 if (td->alt_next) { 1481 td = td->alt_next; 1482 continue; 1483 } 1484 } 1485 /* transfer is done */ 1486 break; 1487 } 1488 td = td->obj_next; 1489 } 1490 ehci_non_isoc_done(xfer); 1491 goto transferred; 1492 } 1493 1494 done: 1495 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1496 return (0); 1497 1498 transferred: 1499 return (1); 1500 } 1501 1502 static void 1503 ehci_pcd_enable(ehci_softc_t *sc) 1504 { 1505 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1506 1507 sc->sc_eintrs |= EHCI_STS_PCD; 1508 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1509 1510 /* acknowledge any PCD interrupt */ 1511 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1512 1513 ehci_root_intr(sc); 1514 } 1515 1516 static void 1517 ehci_interrupt_poll(ehci_softc_t *sc) 1518 { 1519 struct usb_xfer *xfer; 1520 1521 repeat: 1522 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1523 /* 1524 * check if transfer is transferred 1525 */ 1526 if (ehci_check_transfer(xfer)) { 1527 /* queue has been modified */ 1528 goto repeat; 1529 } 1530 } 1531 } 1532 1533 /* 1534 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1535 * writing back the qTD status, or miss signalling occasionally under 1536 * heavy load. If the host machine is too fast, we can miss 1537 * transaction completion - when we scan the active list the 1538 * transaction still seems to be active. This generally exhibits 1539 * itself as a umass stall that never recovers. 1540 * 1541 * We work around this behaviour by setting up this callback after any 1542 * softintr that completes with transactions still pending, giving us 1543 * another chance to check for completion after the writeback has 1544 * taken place. 1545 */ 1546 static void 1547 ehci_poll_timeout(void *arg) 1548 { 1549 ehci_softc_t *sc = arg; 1550 1551 DPRINTFN(3, "\n"); 1552 ehci_interrupt_poll(sc); 1553 } 1554 1555 /*------------------------------------------------------------------------* 1556 * ehci_interrupt - EHCI interrupt handler 1557 * 1558 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1559 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1560 * is present ! 1561 *------------------------------------------------------------------------*/ 1562 void 1563 ehci_interrupt(ehci_softc_t *sc) 1564 { 1565 uint32_t status; 1566 1567 USB_BUS_LOCK(&sc->sc_bus); 1568 1569 DPRINTFN(16, "real interrupt\n"); 1570 1571 #ifdef USB_DEBUG 1572 if (ehcidebug > 15) { 1573 ehci_dump_regs(sc); 1574 } 1575 #endif 1576 1577 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1578 if (status == 0) { 1579 /* the interrupt was not for us */ 1580 goto done; 1581 } 1582 if (!(status & sc->sc_eintrs)) { 1583 goto done; 1584 } 1585 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1586 1587 status &= sc->sc_eintrs; 1588 1589 if (status & EHCI_STS_HSE) { 1590 printf("%s: unrecoverable error, " 1591 "controller halted\n", __FUNCTION__); 1592 #ifdef USB_DEBUG 1593 ehci_dump_regs(sc); 1594 ehci_dump_isoc(sc); 1595 #endif 1596 } 1597 if (status & EHCI_STS_PCD) { 1598 /* 1599 * Disable PCD interrupt for now, because it will be 1600 * on until the port has been reset. 1601 */ 1602 sc->sc_eintrs &= ~EHCI_STS_PCD; 1603 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1604 1605 ehci_root_intr(sc); 1606 1607 /* do not allow RHSC interrupts > 1 per second */ 1608 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1609 (void *)&ehci_pcd_enable, sc); 1610 } 1611 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1612 1613 if (status != 0) { 1614 /* block unprocessed interrupts */ 1615 sc->sc_eintrs &= ~status; 1616 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1617 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1618 } 1619 /* poll all the USB transfers */ 1620 ehci_interrupt_poll(sc); 1621 1622 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1623 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1624 (void *)&ehci_poll_timeout, sc); 1625 } 1626 1627 done: 1628 USB_BUS_UNLOCK(&sc->sc_bus); 1629 } 1630 1631 /* 1632 * called when a request does not complete 1633 */ 1634 static void 1635 ehci_timeout(void *arg) 1636 { 1637 struct usb_xfer *xfer = arg; 1638 1639 DPRINTF("xfer=%p\n", xfer); 1640 1641 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1642 1643 /* transfer is transferred */ 1644 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1645 } 1646 1647 static void 1648 ehci_do_poll(struct usb_bus *bus) 1649 { 1650 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1651 1652 USB_BUS_LOCK(&sc->sc_bus); 1653 ehci_interrupt_poll(sc); 1654 USB_BUS_UNLOCK(&sc->sc_bus); 1655 } 1656 1657 static void 1658 ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1659 { 1660 struct usb_page_search buf_res; 1661 ehci_qtd_t *td; 1662 ehci_qtd_t *td_next; 1663 ehci_qtd_t *td_alt_next; 1664 uint32_t buf_offset; 1665 uint32_t average; 1666 uint32_t len_old; 1667 uint32_t terminate; 1668 uint32_t qtd_altnext; 1669 uint8_t shortpkt_old; 1670 uint8_t precompute; 1671 1672 terminate = temp->sc->sc_terminate_self; 1673 qtd_altnext = temp->sc->sc_terminate_self; 1674 td_alt_next = NULL; 1675 buf_offset = 0; 1676 shortpkt_old = temp->shortpkt; 1677 len_old = temp->len; 1678 precompute = 1; 1679 1680 restart: 1681 1682 td = temp->td; 1683 td_next = temp->td_next; 1684 1685 while (1) { 1686 1687 if (temp->len == 0) { 1688 1689 if (temp->shortpkt) { 1690 break; 1691 } 1692 /* send a Zero Length Packet, ZLP, last */ 1693 1694 temp->shortpkt = 1; 1695 average = 0; 1696 1697 } else { 1698 1699 average = temp->average; 1700 1701 if (temp->len < average) { 1702 if (temp->len % temp->max_frame_size) { 1703 temp->shortpkt = 1; 1704 } 1705 average = temp->len; 1706 } 1707 } 1708 1709 if (td_next == NULL) { 1710 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1711 } 1712 /* get next TD */ 1713 1714 td = td_next; 1715 td_next = td->obj_next; 1716 1717 /* check if we are pre-computing */ 1718 1719 if (precompute) { 1720 1721 /* update remaining length */ 1722 1723 temp->len -= average; 1724 1725 continue; 1726 } 1727 /* fill out current TD */ 1728 1729 td->qtd_status = 1730 temp->qtd_status | 1731 htohc32(temp->sc, EHCI_QTD_IOC | 1732 EHCI_QTD_SET_BYTES(average)); 1733 1734 if (average == 0) { 1735 1736 if (temp->auto_data_toggle == 0) { 1737 1738 /* update data toggle, ZLP case */ 1739 1740 temp->qtd_status ^= 1741 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1742 } 1743 td->len = 0; 1744 1745 td->qtd_buffer[0] = 0; 1746 td->qtd_buffer_hi[0] = 0; 1747 1748 td->qtd_buffer[1] = 0; 1749 td->qtd_buffer_hi[1] = 0; 1750 1751 } else { 1752 1753 uint8_t x; 1754 1755 if (temp->auto_data_toggle == 0) { 1756 1757 /* update data toggle */ 1758 1759 if (((average + temp->max_frame_size - 1) / 1760 temp->max_frame_size) & 1) { 1761 temp->qtd_status ^= 1762 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1763 } 1764 } 1765 td->len = average; 1766 1767 /* update remaining length */ 1768 1769 temp->len -= average; 1770 1771 /* fill out buffer pointers */ 1772 1773 usbd_get_page(temp->pc, buf_offset, &buf_res); 1774 td->qtd_buffer[0] = 1775 htohc32(temp->sc, buf_res.physaddr); 1776 td->qtd_buffer_hi[0] = 0; 1777 1778 x = 1; 1779 1780 while (average > EHCI_PAGE_SIZE) { 1781 average -= EHCI_PAGE_SIZE; 1782 buf_offset += EHCI_PAGE_SIZE; 1783 usbd_get_page(temp->pc, buf_offset, &buf_res); 1784 td->qtd_buffer[x] = 1785 htohc32(temp->sc, 1786 buf_res.physaddr & (~0xFFF)); 1787 td->qtd_buffer_hi[x] = 0; 1788 x++; 1789 } 1790 1791 /* 1792 * NOTE: The "average" variable is never zero after 1793 * exiting the loop above ! 1794 * 1795 * NOTE: We have to subtract one from the offset to 1796 * ensure that we are computing the physical address 1797 * of a valid page ! 1798 */ 1799 buf_offset += average; 1800 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1801 td->qtd_buffer[x] = 1802 htohc32(temp->sc, 1803 buf_res.physaddr & (~0xFFF)); 1804 td->qtd_buffer_hi[x] = 0; 1805 } 1806 1807 if (td_next) { 1808 /* link the current TD with the next one */ 1809 td->qtd_next = td_next->qtd_self; 1810 } 1811 td->qtd_altnext = qtd_altnext; 1812 td->alt_next = td_alt_next; 1813 1814 usb_pc_cpu_flush(td->page_cache); 1815 } 1816 1817 if (precompute) { 1818 precompute = 0; 1819 1820 /* setup alt next pointer, if any */ 1821 if (temp->last_frame) { 1822 td_alt_next = NULL; 1823 qtd_altnext = terminate; 1824 } else { 1825 /* we use this field internally */ 1826 td_alt_next = td_next; 1827 if (temp->setup_alt_next) { 1828 qtd_altnext = td_next->qtd_self; 1829 } else { 1830 qtd_altnext = terminate; 1831 } 1832 } 1833 1834 /* restore */ 1835 temp->shortpkt = shortpkt_old; 1836 temp->len = len_old; 1837 goto restart; 1838 } 1839 temp->td = td; 1840 temp->td_next = td_next; 1841 } 1842 1843 static void 1844 ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1845 { 1846 struct ehci_std_temp temp; 1847 struct usb_pipe_methods *methods; 1848 ehci_qh_t *qh; 1849 ehci_qtd_t *td; 1850 uint32_t qh_endp; 1851 uint32_t qh_endphub; 1852 uint32_t x; 1853 1854 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1855 xfer->address, UE_GET_ADDR(xfer->endpointno), 1856 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1857 1858 temp.average = xfer->max_hc_frame_size; 1859 temp.max_frame_size = xfer->max_frame_size; 1860 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1861 1862 /* toggle the DMA set we are using */ 1863 xfer->flags_int.curr_dma_set ^= 1; 1864 1865 /* get next DMA set */ 1866 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1867 1868 xfer->td_transfer_first = td; 1869 xfer->td_transfer_cache = td; 1870 1871 temp.td = NULL; 1872 temp.td_next = td; 1873 temp.qtd_status = 0; 1874 temp.last_frame = 0; 1875 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1876 1877 if (xfer->flags_int.control_xfr) { 1878 if (xfer->endpoint->toggle_next) { 1879 /* DATA1 is next */ 1880 temp.qtd_status |= 1881 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1882 } 1883 temp.auto_data_toggle = 0; 1884 } else { 1885 temp.auto_data_toggle = 1; 1886 } 1887 1888 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1889 (xfer->xroot->udev->address != 0)) { 1890 /* max 3 retries */ 1891 temp.qtd_status |= 1892 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1893 } 1894 /* check if we should prepend a setup message */ 1895 1896 if (xfer->flags_int.control_xfr) { 1897 if (xfer->flags_int.control_hdr) { 1898 1899 xfer->endpoint->toggle_next = 0; 1900 1901 temp.qtd_status &= 1902 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1903 temp.qtd_status |= htohc32(temp.sc, 1904 EHCI_QTD_ACTIVE | 1905 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1906 EHCI_QTD_SET_TOGGLE(0)); 1907 1908 temp.len = xfer->frlengths[0]; 1909 temp.pc = xfer->frbuffers + 0; 1910 temp.shortpkt = temp.len ? 1 : 0; 1911 /* check for last frame */ 1912 if (xfer->nframes == 1) { 1913 /* no STATUS stage yet, SETUP is last */ 1914 if (xfer->flags_int.control_act) { 1915 temp.last_frame = 1; 1916 temp.setup_alt_next = 0; 1917 } 1918 } 1919 ehci_setup_standard_chain_sub(&temp); 1920 } 1921 x = 1; 1922 } else { 1923 x = 0; 1924 } 1925 1926 while (x != xfer->nframes) { 1927 1928 /* DATA0 / DATA1 message */ 1929 1930 temp.len = xfer->frlengths[x]; 1931 temp.pc = xfer->frbuffers + x; 1932 1933 x++; 1934 1935 if (x == xfer->nframes) { 1936 if (xfer->flags_int.control_xfr) { 1937 /* no STATUS stage yet, DATA is last */ 1938 if (xfer->flags_int.control_act) { 1939 temp.last_frame = 1; 1940 temp.setup_alt_next = 0; 1941 } 1942 } else { 1943 temp.last_frame = 1; 1944 temp.setup_alt_next = 0; 1945 } 1946 } 1947 /* keep previous data toggle and error count */ 1948 1949 temp.qtd_status &= 1950 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1951 EHCI_QTD_SET_TOGGLE(1)); 1952 1953 if (temp.len == 0) { 1954 1955 /* make sure that we send an USB packet */ 1956 1957 temp.shortpkt = 0; 1958 1959 } else { 1960 1961 /* regular data transfer */ 1962 1963 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1964 } 1965 1966 /* set endpoint direction */ 1967 1968 temp.qtd_status |= 1969 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1970 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1971 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1972 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1973 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1974 1975 ehci_setup_standard_chain_sub(&temp); 1976 } 1977 1978 /* check if we should append a status stage */ 1979 1980 if (xfer->flags_int.control_xfr && 1981 !xfer->flags_int.control_act) { 1982 1983 /* 1984 * Send a DATA1 message and invert the current endpoint 1985 * direction. 1986 */ 1987 1988 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1989 EHCI_QTD_SET_TOGGLE(1)); 1990 temp.qtd_status |= 1991 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1992 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1993 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1994 EHCI_QTD_SET_TOGGLE(1)) : 1995 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1996 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1997 EHCI_QTD_SET_TOGGLE(1)); 1998 1999 temp.len = 0; 2000 temp.pc = NULL; 2001 temp.shortpkt = 0; 2002 temp.last_frame = 1; 2003 temp.setup_alt_next = 0; 2004 2005 ehci_setup_standard_chain_sub(&temp); 2006 } 2007 td = temp.td; 2008 2009 /* the last TD terminates the transfer: */ 2010 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 2011 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 2012 2013 usb_pc_cpu_flush(td->page_cache); 2014 2015 /* must have at least one frame! */ 2016 2017 xfer->td_transfer_last = td; 2018 2019 #ifdef USB_DEBUG 2020 if (ehcidebug > 8) { 2021 DPRINTF("nexttog=%d; data before transfer:\n", 2022 xfer->endpoint->toggle_next); 2023 ehci_dump_sqtds(temp.sc, 2024 xfer->td_transfer_first); 2025 } 2026 #endif 2027 2028 methods = xfer->endpoint->methods; 2029 2030 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 2031 2032 /* the "qh_link" field is filled when the QH is added */ 2033 2034 qh_endp = 2035 (EHCI_QH_SET_ADDR(xfer->address) | 2036 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2037 EHCI_QH_SET_MPL(xfer->max_packet_size)); 2038 2039 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2040 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 2041 if (methods != &ehci_device_intr_methods) 2042 qh_endp |= EHCI_QH_SET_NRL(8); 2043 } else { 2044 2045 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 2046 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 2047 } else { 2048 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 2049 } 2050 2051 if (methods == &ehci_device_ctrl_methods) { 2052 qh_endp |= EHCI_QH_CTL; 2053 } 2054 if (methods != &ehci_device_intr_methods) { 2055 /* Only try one time per microframe! */ 2056 qh_endp |= EHCI_QH_SET_NRL(1); 2057 } 2058 } 2059 2060 if (temp.auto_data_toggle == 0) { 2061 /* software computes the data toggle */ 2062 qh_endp |= EHCI_QH_DTC; 2063 } 2064 2065 qh->qh_endp = htohc32(temp.sc, qh_endp); 2066 2067 qh_endphub = 2068 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 2069 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 2070 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 2071 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2072 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 2073 2074 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2075 qh->qh_curqtd = 0; 2076 2077 /* fill the overlay qTD */ 2078 2079 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2080 /* DATA1 is next */ 2081 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2082 } else { 2083 qh->qh_qtd.qtd_status = 0; 2084 } 2085 2086 td = xfer->td_transfer_first; 2087 2088 qh->qh_qtd.qtd_next = td->qtd_self; 2089 qh->qh_qtd.qtd_altnext = 2090 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2091 2092 usb_pc_cpu_flush(qh->page_cache); 2093 2094 if (xfer->xroot->udev->flags.self_suspended == 0) { 2095 EHCI_APPEND_QH(qh, *qh_last); 2096 } 2097 } 2098 2099 static void 2100 ehci_root_intr(ehci_softc_t *sc) 2101 { 2102 uint16_t i; 2103 uint16_t m; 2104 2105 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2106 2107 /* clear any old interrupt data */ 2108 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2109 2110 /* set bits */ 2111 m = (sc->sc_noport + 1); 2112 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2113 m = (8 * sizeof(sc->sc_hub_idata)); 2114 } 2115 for (i = 1; i < m; i++) { 2116 /* pick out CHANGE bits from the status register */ 2117 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2118 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2119 DPRINTF("port %d changed\n", i); 2120 } 2121 } 2122 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2123 sizeof(sc->sc_hub_idata)); 2124 } 2125 2126 static void 2127 ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2128 { 2129 uint32_t nframes = xfer->nframes; 2130 uint32_t status; 2131 uint32_t *plen = xfer->frlengths; 2132 uint16_t len = 0; 2133 ehci_sitd_t *td = xfer->td_transfer_first; 2134 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2135 2136 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2137 xfer, xfer->endpoint); 2138 2139 while (nframes--) { 2140 if (td == NULL) { 2141 panic("%s:%d: out of TD's\n", 2142 __FUNCTION__, __LINE__); 2143 } 2144 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2145 pp_last = &sc->sc_isoc_fs_p_last[0]; 2146 } 2147 #ifdef USB_DEBUG 2148 if (ehcidebug > 15) { 2149 DPRINTF("isoc FS-TD\n"); 2150 ehci_dump_sitd(sc, td); 2151 } 2152 #endif 2153 usb_pc_cpu_invalidate(td->page_cache); 2154 status = hc32toh(sc, td->sitd_status); 2155 2156 len = EHCI_SITD_GET_LEN(status); 2157 2158 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2159 2160 if (*plen >= len) { 2161 len = *plen - len; 2162 } else { 2163 len = 0; 2164 } 2165 2166 *plen = len; 2167 2168 /* remove FS-TD from schedule */ 2169 EHCI_REMOVE_FS_TD(td, *pp_last); 2170 2171 pp_last++; 2172 plen++; 2173 td = td->obj_next; 2174 } 2175 2176 xfer->aframes = xfer->nframes; 2177 } 2178 2179 static void 2180 ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2181 { 2182 uint32_t nframes = xfer->nframes; 2183 uint32_t status; 2184 uint32_t *plen = xfer->frlengths; 2185 uint16_t len = 0; 2186 uint8_t td_no = 0; 2187 ehci_itd_t *td = xfer->td_transfer_first; 2188 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2189 2190 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2191 xfer, xfer->endpoint); 2192 2193 while (nframes) { 2194 if (td == NULL) { 2195 panic("%s:%d: out of TD's\n", 2196 __FUNCTION__, __LINE__); 2197 } 2198 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2199 pp_last = &sc->sc_isoc_hs_p_last[0]; 2200 } 2201 #ifdef USB_DEBUG 2202 if (ehcidebug > 15) { 2203 DPRINTF("isoc HS-TD\n"); 2204 ehci_dump_itd(sc, td); 2205 } 2206 #endif 2207 2208 usb_pc_cpu_invalidate(td->page_cache); 2209 status = hc32toh(sc, td->itd_status[td_no]); 2210 2211 len = EHCI_ITD_GET_LEN(status); 2212 2213 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2214 2215 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2216 2217 if (*plen >= len) { 2218 /* 2219 * The length is valid. NOTE: The 2220 * complete length is written back 2221 * into the status field, and not the 2222 * remainder like with other transfer 2223 * descriptor types. 2224 */ 2225 } else { 2226 /* Invalid length - truncate */ 2227 len = 0; 2228 } 2229 2230 *plen = len; 2231 plen++; 2232 nframes--; 2233 } 2234 2235 td_no++; 2236 2237 if ((td_no == 8) || (nframes == 0)) { 2238 /* remove HS-TD from schedule */ 2239 EHCI_REMOVE_HS_TD(td, *pp_last); 2240 pp_last++; 2241 2242 td_no = 0; 2243 td = td->obj_next; 2244 } 2245 } 2246 xfer->aframes = xfer->nframes; 2247 } 2248 2249 /* NOTE: "done" can be run two times in a row, 2250 * from close and from interrupt 2251 */ 2252 static void 2253 ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2254 { 2255 struct usb_pipe_methods *methods = xfer->endpoint->methods; 2256 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2257 2258 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2259 2260 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2261 xfer, xfer->endpoint, error); 2262 2263 if ((methods == &ehci_device_bulk_methods) || 2264 (methods == &ehci_device_ctrl_methods)) { 2265 #ifdef USB_DEBUG 2266 if (ehcidebug > 8) { 2267 DPRINTF("nexttog=%d; data after transfer:\n", 2268 xfer->endpoint->toggle_next); 2269 ehci_dump_sqtds(sc, 2270 xfer->td_transfer_first); 2271 } 2272 #endif 2273 2274 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2275 sc->sc_async_p_last); 2276 } 2277 if (methods == &ehci_device_intr_methods) { 2278 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2279 sc->sc_intr_p_last[xfer->qh_pos]); 2280 } 2281 /* 2282 * Only finish isochronous transfers once which will update 2283 * "xfer->frlengths". 2284 */ 2285 if (xfer->td_transfer_first && 2286 xfer->td_transfer_last) { 2287 if (methods == &ehci_device_isoc_fs_methods) { 2288 ehci_isoc_fs_done(sc, xfer); 2289 } 2290 if (methods == &ehci_device_isoc_hs_methods) { 2291 ehci_isoc_hs_done(sc, xfer); 2292 } 2293 xfer->td_transfer_first = NULL; 2294 xfer->td_transfer_last = NULL; 2295 } 2296 /* dequeue transfer and start next transfer */ 2297 usbd_transfer_done(xfer, error); 2298 } 2299 2300 /*------------------------------------------------------------------------* 2301 * ehci bulk support 2302 *------------------------------------------------------------------------*/ 2303 static void 2304 ehci_device_bulk_open(struct usb_xfer *xfer) 2305 { 2306 return; 2307 } 2308 2309 static void 2310 ehci_device_bulk_close(struct usb_xfer *xfer) 2311 { 2312 ehci_device_done(xfer, USB_ERR_CANCELLED); 2313 } 2314 2315 static void 2316 ehci_device_bulk_enter(struct usb_xfer *xfer) 2317 { 2318 return; 2319 } 2320 2321 static void 2322 ehci_device_bulk_start(struct usb_xfer *xfer) 2323 { 2324 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2325 uint32_t temp; 2326 2327 /* setup TD's and QH */ 2328 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2329 2330 /* put transfer on interrupt queue */ 2331 ehci_transfer_intr_enqueue(xfer); 2332 2333 /* 2334 * XXX Certain nVidia chipsets choke when using the IAAD 2335 * feature too frequently. 2336 */ 2337 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2338 return; 2339 2340 /* XXX Performance quirk: Some Host Controllers have a too low 2341 * interrupt rate. Issue an IAAD to stimulate the Host 2342 * Controller after queueing the BULK transfer. 2343 */ 2344 temp = EOREAD4(sc, EHCI_USBCMD); 2345 if (!(temp & EHCI_CMD_IAAD)) 2346 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2347 } 2348 2349 struct usb_pipe_methods ehci_device_bulk_methods = 2350 { 2351 .open = ehci_device_bulk_open, 2352 .close = ehci_device_bulk_close, 2353 .enter = ehci_device_bulk_enter, 2354 .start = ehci_device_bulk_start, 2355 }; 2356 2357 /*------------------------------------------------------------------------* 2358 * ehci control support 2359 *------------------------------------------------------------------------*/ 2360 static void 2361 ehci_device_ctrl_open(struct usb_xfer *xfer) 2362 { 2363 return; 2364 } 2365 2366 static void 2367 ehci_device_ctrl_close(struct usb_xfer *xfer) 2368 { 2369 ehci_device_done(xfer, USB_ERR_CANCELLED); 2370 } 2371 2372 static void 2373 ehci_device_ctrl_enter(struct usb_xfer *xfer) 2374 { 2375 return; 2376 } 2377 2378 static void 2379 ehci_device_ctrl_start(struct usb_xfer *xfer) 2380 { 2381 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2382 2383 /* setup TD's and QH */ 2384 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2385 2386 /* put transfer on interrupt queue */ 2387 ehci_transfer_intr_enqueue(xfer); 2388 } 2389 2390 struct usb_pipe_methods ehci_device_ctrl_methods = 2391 { 2392 .open = ehci_device_ctrl_open, 2393 .close = ehci_device_ctrl_close, 2394 .enter = ehci_device_ctrl_enter, 2395 .start = ehci_device_ctrl_start, 2396 }; 2397 2398 /*------------------------------------------------------------------------* 2399 * ehci interrupt support 2400 *------------------------------------------------------------------------*/ 2401 static void 2402 ehci_device_intr_open(struct usb_xfer *xfer) 2403 { 2404 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2405 uint16_t best; 2406 uint16_t bit; 2407 uint16_t x; 2408 2409 usb_hs_bandwidth_alloc(xfer); 2410 2411 /* 2412 * Find the best QH position corresponding to the given interval: 2413 */ 2414 2415 best = 0; 2416 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2417 while (bit) { 2418 if (xfer->interval >= bit) { 2419 x = bit; 2420 best = bit; 2421 while (x & bit) { 2422 if (sc->sc_intr_stat[x] < 2423 sc->sc_intr_stat[best]) { 2424 best = x; 2425 } 2426 x++; 2427 } 2428 break; 2429 } 2430 bit >>= 1; 2431 } 2432 2433 sc->sc_intr_stat[best]++; 2434 xfer->qh_pos = best; 2435 2436 DPRINTFN(3, "best=%d interval=%d\n", 2437 best, xfer->interval); 2438 } 2439 2440 static void 2441 ehci_device_intr_close(struct usb_xfer *xfer) 2442 { 2443 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2444 2445 sc->sc_intr_stat[xfer->qh_pos]--; 2446 2447 ehci_device_done(xfer, USB_ERR_CANCELLED); 2448 2449 /* bandwidth must be freed after device done */ 2450 usb_hs_bandwidth_free(xfer); 2451 } 2452 2453 static void 2454 ehci_device_intr_enter(struct usb_xfer *xfer) 2455 { 2456 return; 2457 } 2458 2459 static void 2460 ehci_device_intr_start(struct usb_xfer *xfer) 2461 { 2462 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2463 2464 /* setup TD's and QH */ 2465 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2466 2467 /* put transfer on interrupt queue */ 2468 ehci_transfer_intr_enqueue(xfer); 2469 } 2470 2471 struct usb_pipe_methods ehci_device_intr_methods = 2472 { 2473 .open = ehci_device_intr_open, 2474 .close = ehci_device_intr_close, 2475 .enter = ehci_device_intr_enter, 2476 .start = ehci_device_intr_start, 2477 }; 2478 2479 /*------------------------------------------------------------------------* 2480 * ehci full speed isochronous support 2481 *------------------------------------------------------------------------*/ 2482 static void 2483 ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2484 { 2485 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2486 ehci_sitd_t *td; 2487 uint32_t sitd_portaddr; 2488 uint8_t ds; 2489 2490 sitd_portaddr = 2491 EHCI_SITD_SET_ADDR(xfer->address) | 2492 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2493 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2494 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2495 2496 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2497 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2498 } 2499 sitd_portaddr = htohc32(sc, sitd_portaddr); 2500 2501 /* initialize all TD's */ 2502 2503 for (ds = 0; ds != 2; ds++) { 2504 2505 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2506 2507 td->sitd_portaddr = sitd_portaddr; 2508 2509 /* 2510 * TODO: make some kind of automatic 2511 * SMASK/CMASK selection based on micro-frame 2512 * usage 2513 * 2514 * micro-frame usage (8 microframes per 1ms) 2515 */ 2516 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2517 2518 usb_pc_cpu_flush(td->page_cache); 2519 } 2520 } 2521 } 2522 2523 static void 2524 ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2525 { 2526 ehci_device_done(xfer, USB_ERR_CANCELLED); 2527 } 2528 2529 static void 2530 ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2531 { 2532 struct usb_page_search buf_res; 2533 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2534 struct usb_fs_isoc_schedule *fss_start; 2535 struct usb_fs_isoc_schedule *fss_end; 2536 struct usb_fs_isoc_schedule *fss; 2537 ehci_sitd_t *td; 2538 ehci_sitd_t *td_last = NULL; 2539 ehci_sitd_t **pp_last; 2540 uint32_t *plen; 2541 uint32_t buf_offset; 2542 uint32_t nframes; 2543 uint32_t temp; 2544 uint32_t sitd_mask; 2545 uint16_t tlen; 2546 uint8_t sa; 2547 uint8_t sb; 2548 uint8_t error; 2549 2550 #ifdef USB_DEBUG 2551 uint8_t once = 1; 2552 2553 #endif 2554 2555 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2556 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2557 2558 /* get the current frame index */ 2559 2560 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2561 2562 /* 2563 * check if the frame index is within the window where the frames 2564 * will be inserted 2565 */ 2566 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2567 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2568 2569 if ((xfer->endpoint->is_synced == 0) || 2570 (buf_offset < xfer->nframes)) { 2571 /* 2572 * If there is data underflow or the pipe queue is empty we 2573 * schedule the transfer a few frames ahead of the current 2574 * frame position. Else two isochronous transfers might 2575 * overlap. 2576 */ 2577 xfer->endpoint->isoc_next = (nframes + 3) & 2578 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2579 xfer->endpoint->is_synced = 1; 2580 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2581 } 2582 /* 2583 * compute how many milliseconds the insertion is ahead of the 2584 * current frame position: 2585 */ 2586 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2587 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2588 2589 /* 2590 * pre-compute when the isochronous transfer will be finished: 2591 */ 2592 xfer->isoc_time_complete = 2593 usbd_fs_isoc_schedule_isoc_time_expand 2594 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2595 xfer->nframes; 2596 2597 /* get the real number of frames */ 2598 2599 nframes = xfer->nframes; 2600 2601 buf_offset = 0; 2602 2603 plen = xfer->frlengths; 2604 2605 /* toggle the DMA set we are using */ 2606 xfer->flags_int.curr_dma_set ^= 1; 2607 2608 /* get next DMA set */ 2609 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2610 xfer->td_transfer_first = td; 2611 2612 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2613 2614 /* store starting position */ 2615 2616 xfer->qh_pos = xfer->endpoint->isoc_next; 2617 2618 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2619 2620 while (nframes--) { 2621 if (td == NULL) { 2622 panic("%s:%d: out of TD's\n", 2623 __FUNCTION__, __LINE__); 2624 } 2625 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2626 pp_last = &sc->sc_isoc_fs_p_last[0]; 2627 } 2628 if (fss >= fss_end) { 2629 fss = fss_start; 2630 } 2631 /* reuse sitd_portaddr and sitd_back from last transfer */ 2632 2633 if (*plen > xfer->max_frame_size) { 2634 #ifdef USB_DEBUG 2635 if (once) { 2636 once = 0; 2637 printf("%s: frame length(%d) exceeds %d " 2638 "bytes (frame truncated)\n", 2639 __FUNCTION__, *plen, 2640 xfer->max_frame_size); 2641 } 2642 #endif 2643 *plen = xfer->max_frame_size; 2644 } 2645 /* 2646 * We currently don't care if the ISOCHRONOUS schedule is 2647 * full! 2648 */ 2649 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen); 2650 if (error) { 2651 /* 2652 * The FULL speed schedule is FULL! Set length 2653 * to zero. 2654 */ 2655 *plen = 0; 2656 } 2657 if (*plen) { 2658 /* 2659 * only call "usbd_get_page()" when we have a 2660 * non-zero length 2661 */ 2662 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2663 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2664 buf_offset += *plen; 2665 /* 2666 * NOTE: We need to subtract one from the offset so 2667 * that we are on a valid page! 2668 */ 2669 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2670 &buf_res); 2671 temp = buf_res.physaddr & ~0xFFF; 2672 } else { 2673 td->sitd_bp[0] = 0; 2674 temp = 0; 2675 } 2676 2677 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2678 tlen = *plen; 2679 if (tlen <= 188) { 2680 temp |= 1; /* T-count = 1, TP = ALL */ 2681 tlen = 1; 2682 } else { 2683 tlen += 187; 2684 tlen /= 188; 2685 temp |= tlen; /* T-count = [1..6] */ 2686 temp |= 8; /* TP = Begin */ 2687 } 2688 2689 tlen += sa; 2690 2691 if (tlen >= 8) { 2692 sb = 0; 2693 } else { 2694 sb = (1 << tlen); 2695 } 2696 2697 sa = (1 << sa); 2698 sa = (sb - sa) & 0x3F; 2699 sb = 0; 2700 } else { 2701 sb = (-(4 << sa)) & 0xFE; 2702 sa = (1 << sa) & 0x3F; 2703 } 2704 2705 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2706 EHCI_SITD_SET_CMASK(sb)); 2707 2708 td->sitd_bp[1] = htohc32(sc, temp); 2709 2710 td->sitd_mask = htohc32(sc, sitd_mask); 2711 2712 if (nframes == 0) { 2713 td->sitd_status = htohc32(sc, 2714 EHCI_SITD_IOC | 2715 EHCI_SITD_ACTIVE | 2716 EHCI_SITD_SET_LEN(*plen)); 2717 } else { 2718 td->sitd_status = htohc32(sc, 2719 EHCI_SITD_ACTIVE | 2720 EHCI_SITD_SET_LEN(*plen)); 2721 } 2722 usb_pc_cpu_flush(td->page_cache); 2723 2724 #ifdef USB_DEBUG 2725 if (ehcidebug > 15) { 2726 DPRINTF("FS-TD %d\n", nframes); 2727 ehci_dump_sitd(sc, td); 2728 } 2729 #endif 2730 /* insert TD into schedule */ 2731 EHCI_APPEND_FS_TD(td, *pp_last); 2732 pp_last++; 2733 2734 plen++; 2735 fss++; 2736 td_last = td; 2737 td = td->obj_next; 2738 } 2739 2740 xfer->td_transfer_last = td_last; 2741 2742 /* update isoc_next */ 2743 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2744 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2745 } 2746 2747 static void 2748 ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2749 { 2750 /* put transfer on interrupt queue */ 2751 ehci_transfer_intr_enqueue(xfer); 2752 } 2753 2754 struct usb_pipe_methods ehci_device_isoc_fs_methods = 2755 { 2756 .open = ehci_device_isoc_fs_open, 2757 .close = ehci_device_isoc_fs_close, 2758 .enter = ehci_device_isoc_fs_enter, 2759 .start = ehci_device_isoc_fs_start, 2760 }; 2761 2762 /*------------------------------------------------------------------------* 2763 * ehci high speed isochronous support 2764 *------------------------------------------------------------------------*/ 2765 static void 2766 ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2767 { 2768 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2769 ehci_itd_t *td; 2770 uint32_t temp; 2771 uint8_t ds; 2772 2773 usb_hs_bandwidth_alloc(xfer); 2774 2775 /* initialize all TD's */ 2776 2777 for (ds = 0; ds != 2; ds++) { 2778 2779 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2780 2781 /* set TD inactive */ 2782 td->itd_status[0] = 0; 2783 td->itd_status[1] = 0; 2784 td->itd_status[2] = 0; 2785 td->itd_status[3] = 0; 2786 td->itd_status[4] = 0; 2787 td->itd_status[5] = 0; 2788 td->itd_status[6] = 0; 2789 td->itd_status[7] = 0; 2790 2791 /* set endpoint and address */ 2792 td->itd_bp[0] = htohc32(sc, 2793 EHCI_ITD_SET_ADDR(xfer->address) | 2794 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2795 2796 temp = 2797 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2798 2799 /* set direction */ 2800 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2801 temp |= EHCI_ITD_SET_DIR_IN; 2802 } 2803 /* set maximum packet size */ 2804 td->itd_bp[1] = htohc32(sc, temp); 2805 2806 /* set transfer multiplier */ 2807 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2808 2809 usb_pc_cpu_flush(td->page_cache); 2810 } 2811 } 2812 } 2813 2814 static void 2815 ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2816 { 2817 ehci_device_done(xfer, USB_ERR_CANCELLED); 2818 2819 /* bandwidth must be freed after device done */ 2820 usb_hs_bandwidth_free(xfer); 2821 } 2822 2823 static void 2824 ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2825 { 2826 struct usb_page_search buf_res; 2827 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2828 ehci_itd_t *td; 2829 ehci_itd_t *td_last = NULL; 2830 ehci_itd_t **pp_last; 2831 bus_size_t page_addr; 2832 uint32_t *plen; 2833 uint32_t status; 2834 uint32_t buf_offset; 2835 uint32_t nframes; 2836 uint32_t itd_offset[8 + 1]; 2837 uint8_t x; 2838 uint8_t td_no; 2839 uint8_t page_no; 2840 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2841 2842 #ifdef USB_DEBUG 2843 uint8_t once = 1; 2844 2845 #endif 2846 2847 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2848 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2849 2850 /* get the current frame index */ 2851 2852 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2853 2854 /* 2855 * check if the frame index is within the window where the frames 2856 * will be inserted 2857 */ 2858 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2859 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2860 2861 if ((xfer->endpoint->is_synced == 0) || 2862 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2863 /* 2864 * If there is data underflow or the pipe queue is empty we 2865 * schedule the transfer a few frames ahead of the current 2866 * frame position. Else two isochronous transfers might 2867 * overlap. 2868 */ 2869 xfer->endpoint->isoc_next = (nframes + 3) & 2870 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2871 xfer->endpoint->is_synced = 1; 2872 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2873 } 2874 /* 2875 * compute how many milliseconds the insertion is ahead of the 2876 * current frame position: 2877 */ 2878 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2879 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2880 2881 /* 2882 * pre-compute when the isochronous transfer will be finished: 2883 */ 2884 xfer->isoc_time_complete = 2885 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2886 (((xfer->nframes << shift) + 7) / 8); 2887 2888 /* get the real number of frames */ 2889 2890 nframes = xfer->nframes; 2891 2892 buf_offset = 0; 2893 td_no = 0; 2894 2895 plen = xfer->frlengths; 2896 2897 /* toggle the DMA set we are using */ 2898 xfer->flags_int.curr_dma_set ^= 1; 2899 2900 /* get next DMA set */ 2901 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2902 xfer->td_transfer_first = td; 2903 2904 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2905 2906 /* store starting position */ 2907 2908 xfer->qh_pos = xfer->endpoint->isoc_next; 2909 2910 while (nframes) { 2911 if (td == NULL) { 2912 panic("%s:%d: out of TD's\n", 2913 __FUNCTION__, __LINE__); 2914 } 2915 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2916 pp_last = &sc->sc_isoc_hs_p_last[0]; 2917 } 2918 /* range check */ 2919 if (*plen > xfer->max_frame_size) { 2920 #ifdef USB_DEBUG 2921 if (once) { 2922 once = 0; 2923 printf("%s: frame length(%d) exceeds %d bytes " 2924 "(frame truncated)\n", 2925 __FUNCTION__, *plen, xfer->max_frame_size); 2926 } 2927 #endif 2928 *plen = xfer->max_frame_size; 2929 } 2930 2931 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2932 status = (EHCI_ITD_SET_LEN(*plen) | 2933 EHCI_ITD_ACTIVE | 2934 EHCI_ITD_SET_PG(0)); 2935 td->itd_status[td_no] = htohc32(sc, status); 2936 itd_offset[td_no] = buf_offset; 2937 buf_offset += *plen; 2938 plen++; 2939 nframes --; 2940 } else { 2941 td->itd_status[td_no] = 0; /* not active */ 2942 itd_offset[td_no] = buf_offset; 2943 } 2944 2945 td_no++; 2946 2947 if ((td_no == 8) || (nframes == 0)) { 2948 2949 /* the rest of the transfers are not active, if any */ 2950 for (x = td_no; x != 8; x++) { 2951 td->itd_status[x] = 0; /* not active */ 2952 } 2953 2954 /* check if there is any data to be transferred */ 2955 if (itd_offset[0] != buf_offset) { 2956 page_no = 0; 2957 itd_offset[td_no] = buf_offset; 2958 2959 /* get first page offset */ 2960 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2961 /* get page address */ 2962 page_addr = buf_res.physaddr & ~0xFFF; 2963 /* update page address */ 2964 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2965 td->itd_bp[0] |= htohc32(sc, page_addr); 2966 2967 for (x = 0; x != td_no; x++) { 2968 /* set page number and page offset */ 2969 status = (EHCI_ITD_SET_PG(page_no) | 2970 (buf_res.physaddr & 0xFFF)); 2971 td->itd_status[x] |= htohc32(sc, status); 2972 2973 /* get next page offset */ 2974 if (itd_offset[x + 1] == buf_offset) { 2975 /* 2976 * We subtract one so that 2977 * we don't go off the last 2978 * page! 2979 */ 2980 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2981 } else { 2982 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2983 } 2984 2985 /* check if we need a new page */ 2986 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2987 /* new page needed */ 2988 page_addr = buf_res.physaddr & ~0xFFF; 2989 if (page_no == 6) { 2990 panic("%s: too many pages\n", __FUNCTION__); 2991 } 2992 page_no++; 2993 /* update page address */ 2994 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2995 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2996 } 2997 } 2998 } 2999 /* set IOC bit if we are complete */ 3000 if (nframes == 0) { 3001 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 3002 } 3003 usb_pc_cpu_flush(td->page_cache); 3004 #ifdef USB_DEBUG 3005 if (ehcidebug > 15) { 3006 DPRINTF("HS-TD %d\n", nframes); 3007 ehci_dump_itd(sc, td); 3008 } 3009 #endif 3010 /* insert TD into schedule */ 3011 EHCI_APPEND_HS_TD(td, *pp_last); 3012 pp_last++; 3013 3014 td_no = 0; 3015 td_last = td; 3016 td = td->obj_next; 3017 } 3018 } 3019 3020 xfer->td_transfer_last = td_last; 3021 3022 /* update isoc_next */ 3023 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 3024 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 3025 } 3026 3027 static void 3028 ehci_device_isoc_hs_start(struct usb_xfer *xfer) 3029 { 3030 /* put transfer on interrupt queue */ 3031 ehci_transfer_intr_enqueue(xfer); 3032 } 3033 3034 struct usb_pipe_methods ehci_device_isoc_hs_methods = 3035 { 3036 .open = ehci_device_isoc_hs_open, 3037 .close = ehci_device_isoc_hs_close, 3038 .enter = ehci_device_isoc_hs_enter, 3039 .start = ehci_device_isoc_hs_start, 3040 }; 3041 3042 /*------------------------------------------------------------------------* 3043 * ehci root control support 3044 *------------------------------------------------------------------------* 3045 * Simulate a hardware hub by handling all the necessary requests. 3046 *------------------------------------------------------------------------*/ 3047 3048 static const 3049 struct usb_device_descriptor ehci_devd = 3050 { 3051 sizeof(struct usb_device_descriptor), 3052 UDESC_DEVICE, /* type */ 3053 {0x00, 0x02}, /* USB version */ 3054 UDCLASS_HUB, /* class */ 3055 UDSUBCLASS_HUB, /* subclass */ 3056 UDPROTO_HSHUBSTT, /* protocol */ 3057 64, /* max packet */ 3058 {0}, {0}, {0x00, 0x01}, /* device id */ 3059 1, 2, 0, /* string indicies */ 3060 1 /* # of configurations */ 3061 }; 3062 3063 static const 3064 struct usb_device_qualifier ehci_odevd = 3065 { 3066 sizeof(struct usb_device_qualifier), 3067 UDESC_DEVICE_QUALIFIER, /* type */ 3068 {0x00, 0x02}, /* USB version */ 3069 UDCLASS_HUB, /* class */ 3070 UDSUBCLASS_HUB, /* subclass */ 3071 UDPROTO_FSHUB, /* protocol */ 3072 0, /* max packet */ 3073 0, /* # of configurations */ 3074 0 3075 }; 3076 3077 static const struct ehci_config_desc ehci_confd = { 3078 .confd = { 3079 .bLength = sizeof(struct usb_config_descriptor), 3080 .bDescriptorType = UDESC_CONFIG, 3081 .wTotalLength[0] = sizeof(ehci_confd), 3082 .bNumInterface = 1, 3083 .bConfigurationValue = 1, 3084 .iConfiguration = 0, 3085 .bmAttributes = UC_SELF_POWERED, 3086 .bMaxPower = 0 /* max power */ 3087 }, 3088 .ifcd = { 3089 .bLength = sizeof(struct usb_interface_descriptor), 3090 .bDescriptorType = UDESC_INTERFACE, 3091 .bNumEndpoints = 1, 3092 .bInterfaceClass = UICLASS_HUB, 3093 .bInterfaceSubClass = UISUBCLASS_HUB, 3094 .bInterfaceProtocol = 0, 3095 }, 3096 .endpd = { 3097 .bLength = sizeof(struct usb_endpoint_descriptor), 3098 .bDescriptorType = UDESC_ENDPOINT, 3099 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3100 .bmAttributes = UE_INTERRUPT, 3101 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3102 .bInterval = 255, 3103 }, 3104 }; 3105 3106 static const 3107 struct usb_hub_descriptor ehci_hubd = 3108 { 3109 0, /* dynamic length */ 3110 UDESC_HUB, 3111 0, 3112 {0, 0}, 3113 0, 3114 0, 3115 {0}, 3116 }; 3117 3118 static void 3119 ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3120 { 3121 uint32_t port; 3122 uint32_t v; 3123 3124 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3125 3126 port = EHCI_PORTSC(index); 3127 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3128 EOWRITE4(sc, port, v | EHCI_PS_PO); 3129 } 3130 3131 static usb_error_t 3132 ehci_roothub_exec(struct usb_device *udev, 3133 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3134 { 3135 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3136 const char *str_ptr; 3137 const void *ptr; 3138 uint32_t port; 3139 uint32_t v; 3140 uint16_t len; 3141 uint16_t i; 3142 uint16_t value; 3143 uint16_t index; 3144 usb_error_t err; 3145 3146 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3147 3148 /* buffer reset */ 3149 ptr = (const void *)&sc->sc_hub_desc; 3150 len = 0; 3151 err = 0; 3152 3153 value = UGETW(req->wValue); 3154 index = UGETW(req->wIndex); 3155 3156 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3157 "wValue=0x%04x wIndex=0x%04x\n", 3158 req->bmRequestType, req->bRequest, 3159 UGETW(req->wLength), value, index); 3160 3161 #define C(x,y) ((x) | ((y) << 8)) 3162 switch (C(req->bRequest, req->bmRequestType)) { 3163 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3164 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3165 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3166 /* 3167 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3168 * for the integrated root hub. 3169 */ 3170 break; 3171 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3172 len = 1; 3173 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3174 break; 3175 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3176 switch (value >> 8) { 3177 case UDESC_DEVICE: 3178 if ((value & 0xff) != 0) { 3179 err = USB_ERR_IOERROR; 3180 goto done; 3181 } 3182 len = sizeof(ehci_devd); 3183 ptr = (const void *)&ehci_devd; 3184 break; 3185 /* 3186 * We can't really operate at another speed, 3187 * but the specification says we need this 3188 * descriptor: 3189 */ 3190 case UDESC_DEVICE_QUALIFIER: 3191 if ((value & 0xff) != 0) { 3192 err = USB_ERR_IOERROR; 3193 goto done; 3194 } 3195 len = sizeof(ehci_odevd); 3196 ptr = (const void *)&ehci_odevd; 3197 break; 3198 3199 case UDESC_CONFIG: 3200 if ((value & 0xff) != 0) { 3201 err = USB_ERR_IOERROR; 3202 goto done; 3203 } 3204 len = sizeof(ehci_confd); 3205 ptr = (const void *)&ehci_confd; 3206 break; 3207 3208 case UDESC_STRING: 3209 switch (value & 0xff) { 3210 case 0: /* Language table */ 3211 str_ptr = "\001"; 3212 break; 3213 3214 case 1: /* Vendor */ 3215 str_ptr = sc->sc_vendor; 3216 break; 3217 3218 case 2: /* Product */ 3219 str_ptr = "EHCI root HUB"; 3220 break; 3221 3222 default: 3223 str_ptr = ""; 3224 break; 3225 } 3226 3227 len = usb_make_str_desc( 3228 sc->sc_hub_desc.temp, 3229 sizeof(sc->sc_hub_desc.temp), 3230 str_ptr); 3231 break; 3232 default: 3233 err = USB_ERR_IOERROR; 3234 goto done; 3235 } 3236 break; 3237 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3238 len = 1; 3239 sc->sc_hub_desc.temp[0] = 0; 3240 break; 3241 case C(UR_GET_STATUS, UT_READ_DEVICE): 3242 len = 2; 3243 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3244 break; 3245 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3246 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3247 len = 2; 3248 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3249 break; 3250 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3251 if (value >= EHCI_MAX_DEVICES) { 3252 err = USB_ERR_IOERROR; 3253 goto done; 3254 } 3255 sc->sc_addr = value; 3256 break; 3257 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3258 if ((value != 0) && (value != 1)) { 3259 err = USB_ERR_IOERROR; 3260 goto done; 3261 } 3262 sc->sc_conf = value; 3263 break; 3264 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3265 break; 3266 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3267 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3268 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3269 err = USB_ERR_IOERROR; 3270 goto done; 3271 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3272 break; 3273 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3274 break; 3275 /* Hub requests */ 3276 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3277 break; 3278 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3279 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3280 3281 if ((index < 1) || 3282 (index > sc->sc_noport)) { 3283 err = USB_ERR_IOERROR; 3284 goto done; 3285 } 3286 port = EHCI_PORTSC(index); 3287 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3288 switch (value) { 3289 case UHF_PORT_ENABLE: 3290 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3291 break; 3292 case UHF_PORT_SUSPEND: 3293 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3294 3295 /* 3296 * waking up a High Speed device is rather 3297 * complicated if 3298 */ 3299 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3300 } 3301 /* wait 20ms for resume sequence to complete */ 3302 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3303 3304 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3305 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3306 3307 /* 4ms settle time */ 3308 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3309 break; 3310 case UHF_PORT_POWER: 3311 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3312 break; 3313 case UHF_PORT_TEST: 3314 DPRINTFN(3, "clear port test " 3315 "%d\n", index); 3316 break; 3317 case UHF_PORT_INDICATOR: 3318 DPRINTFN(3, "clear port ind " 3319 "%d\n", index); 3320 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3321 break; 3322 case UHF_C_PORT_CONNECTION: 3323 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3324 break; 3325 case UHF_C_PORT_ENABLE: 3326 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3327 break; 3328 case UHF_C_PORT_SUSPEND: 3329 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3330 break; 3331 case UHF_C_PORT_OVER_CURRENT: 3332 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3333 break; 3334 case UHF_C_PORT_RESET: 3335 sc->sc_isreset = 0; 3336 break; 3337 default: 3338 err = USB_ERR_IOERROR; 3339 goto done; 3340 } 3341 break; 3342 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3343 if ((value & 0xff) != 0) { 3344 err = USB_ERR_IOERROR; 3345 goto done; 3346 } 3347 v = EREAD4(sc, EHCI_HCSPARAMS); 3348 3349 sc->sc_hub_desc.hubd = ehci_hubd; 3350 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3351 3352 if (EHCI_HCS_PPC(v)) 3353 i = UHD_PWR_INDIVIDUAL; 3354 else 3355 i = UHD_PWR_NO_SWITCH; 3356 3357 if (EHCI_HCS_P_INDICATOR(v)) 3358 i |= UHD_PORT_IND; 3359 3360 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3361 /* XXX can't find out? */ 3362 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3363 /* XXX don't know if ports are removable or not */ 3364 sc->sc_hub_desc.hubd.bDescLength = 3365 8 + ((sc->sc_noport + 7) / 8); 3366 len = sc->sc_hub_desc.hubd.bDescLength; 3367 break; 3368 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3369 len = 16; 3370 bzero(sc->sc_hub_desc.temp, 16); 3371 break; 3372 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3373 DPRINTFN(9, "get port status i=%d\n", 3374 index); 3375 if ((index < 1) || 3376 (index > sc->sc_noport)) { 3377 err = USB_ERR_IOERROR; 3378 goto done; 3379 } 3380 v = EOREAD4(sc, EHCI_PORTSC(index)); 3381 DPRINTFN(9, "port status=0x%04x\n", v); 3382 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3383 if ((v & 0xc000000) == 0x8000000) 3384 i = UPS_HIGH_SPEED; 3385 else if ((v & 0xc000000) == 0x4000000) 3386 i = UPS_LOW_SPEED; 3387 else 3388 i = 0; 3389 } else { 3390 i = UPS_HIGH_SPEED; 3391 } 3392 if (v & EHCI_PS_CS) 3393 i |= UPS_CURRENT_CONNECT_STATUS; 3394 if (v & EHCI_PS_PE) 3395 i |= UPS_PORT_ENABLED; 3396 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3397 i |= UPS_SUSPEND; 3398 if (v & EHCI_PS_OCA) 3399 i |= UPS_OVERCURRENT_INDICATOR; 3400 if (v & EHCI_PS_PR) 3401 i |= UPS_RESET; 3402 if (v & EHCI_PS_PP) 3403 i |= UPS_PORT_POWER; 3404 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3405 i = 0; 3406 if (v & EHCI_PS_CSC) 3407 i |= UPS_C_CONNECT_STATUS; 3408 if (v & EHCI_PS_PEC) 3409 i |= UPS_C_PORT_ENABLED; 3410 if (v & EHCI_PS_OCC) 3411 i |= UPS_C_OVERCURRENT_INDICATOR; 3412 if (v & EHCI_PS_FPR) 3413 i |= UPS_C_SUSPEND; 3414 if (sc->sc_isreset) 3415 i |= UPS_C_PORT_RESET; 3416 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3417 len = sizeof(sc->sc_hub_desc.ps); 3418 break; 3419 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3420 err = USB_ERR_IOERROR; 3421 goto done; 3422 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3423 break; 3424 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3425 if ((index < 1) || 3426 (index > sc->sc_noport)) { 3427 err = USB_ERR_IOERROR; 3428 goto done; 3429 } 3430 port = EHCI_PORTSC(index); 3431 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3432 switch (value) { 3433 case UHF_PORT_ENABLE: 3434 EOWRITE4(sc, port, v | EHCI_PS_PE); 3435 break; 3436 case UHF_PORT_SUSPEND: 3437 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3438 break; 3439 case UHF_PORT_RESET: 3440 DPRINTFN(6, "reset port %d\n", index); 3441 #ifdef USB_DEBUG 3442 if (ehcinohighspeed) { 3443 /* 3444 * Connect USB device to companion 3445 * controller. 3446 */ 3447 ehci_disown(sc, index, 1); 3448 break; 3449 } 3450 #endif 3451 if (EHCI_PS_IS_LOWSPEED(v) && 3452 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3453 /* Low speed device, give up ownership. */ 3454 ehci_disown(sc, index, 1); 3455 break; 3456 } 3457 /* Start reset sequence. */ 3458 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3459 EOWRITE4(sc, port, v | EHCI_PS_PR); 3460 3461 /* Wait for reset to complete. */ 3462 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3463 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3464 3465 /* Terminate reset sequence. */ 3466 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3467 EOWRITE4(sc, port, v); 3468 3469 /* Wait for HC to complete reset. */ 3470 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3471 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3472 3473 v = EOREAD4(sc, port); 3474 DPRINTF("ehci after reset, status=0x%08x\n", v); 3475 if (v & EHCI_PS_PR) { 3476 device_printf(sc->sc_bus.bdev, 3477 "port reset timeout\n"); 3478 err = USB_ERR_TIMEOUT; 3479 goto done; 3480 } 3481 if (!(v & EHCI_PS_PE) && 3482 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3483 /* Not a high speed device, give up ownership.*/ 3484 ehci_disown(sc, index, 0); 3485 break; 3486 } 3487 sc->sc_isreset = 1; 3488 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3489 index, v); 3490 break; 3491 3492 case UHF_PORT_POWER: 3493 DPRINTFN(3, "set port power %d\n", index); 3494 EOWRITE4(sc, port, v | EHCI_PS_PP); 3495 break; 3496 3497 case UHF_PORT_TEST: 3498 DPRINTFN(3, "set port test %d\n", index); 3499 break; 3500 3501 case UHF_PORT_INDICATOR: 3502 DPRINTFN(3, "set port ind %d\n", index); 3503 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3504 break; 3505 3506 default: 3507 err = USB_ERR_IOERROR; 3508 goto done; 3509 } 3510 break; 3511 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3512 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3513 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3514 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3515 break; 3516 default: 3517 err = USB_ERR_IOERROR; 3518 goto done; 3519 } 3520 done: 3521 *plength = len; 3522 *pptr = ptr; 3523 return (err); 3524 } 3525 3526 static void 3527 ehci_xfer_setup(struct usb_setup_params *parm) 3528 { 3529 struct usb_page_search page_info; 3530 struct usb_page_cache *pc; 3531 ehci_softc_t *sc; 3532 struct usb_xfer *xfer; 3533 void *last_obj; 3534 uint32_t nqtd; 3535 uint32_t nqh; 3536 uint32_t nsitd; 3537 uint32_t nitd; 3538 uint32_t n; 3539 3540 sc = EHCI_BUS2SC(parm->udev->bus); 3541 xfer = parm->curr_xfer; 3542 3543 nqtd = 0; 3544 nqh = 0; 3545 nsitd = 0; 3546 nitd = 0; 3547 3548 /* 3549 * compute maximum number of some structures 3550 */ 3551 if (parm->methods == &ehci_device_ctrl_methods) { 3552 3553 /* 3554 * The proof for the "nqtd" formula is illustrated like 3555 * this: 3556 * 3557 * +------------------------------------+ 3558 * | | 3559 * | |remainder -> | 3560 * | +-----+---+ | 3561 * | | xxx | x | frm 0 | 3562 * | +-----+---++ | 3563 * | | xxx | xx | frm 1 | 3564 * | +-----+----+ | 3565 * | ... | 3566 * +------------------------------------+ 3567 * 3568 * "xxx" means a completely full USB transfer descriptor 3569 * 3570 * "x" and "xx" means a short USB packet 3571 * 3572 * For the remainder of an USB transfer modulo 3573 * "max_data_length" we need two USB transfer descriptors. 3574 * One to transfer the remaining data and one to finalise 3575 * with a zero length packet in case the "force_short_xfer" 3576 * flag is set. We only need two USB transfer descriptors in 3577 * the case where the transfer length of the first one is a 3578 * factor of "max_frame_size". The rest of the needed USB 3579 * transfer descriptors is given by the buffer size divided 3580 * by the maximum data payload. 3581 */ 3582 parm->hc_max_packet_size = 0x400; 3583 parm->hc_max_packet_count = 1; 3584 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3585 xfer->flags_int.bdma_enable = 1; 3586 3587 usbd_transfer_setup_sub(parm); 3588 3589 nqh = 1; 3590 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3591 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3592 3593 } else if (parm->methods == &ehci_device_bulk_methods) { 3594 3595 parm->hc_max_packet_size = 0x400; 3596 parm->hc_max_packet_count = 1; 3597 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3598 xfer->flags_int.bdma_enable = 1; 3599 3600 usbd_transfer_setup_sub(parm); 3601 3602 nqh = 1; 3603 nqtd = ((2 * xfer->nframes) 3604 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3605 3606 } else if (parm->methods == &ehci_device_intr_methods) { 3607 3608 if (parm->speed == USB_SPEED_HIGH) { 3609 parm->hc_max_packet_size = 0x400; 3610 parm->hc_max_packet_count = 3; 3611 } else if (parm->speed == USB_SPEED_FULL) { 3612 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3613 parm->hc_max_packet_count = 1; 3614 } else { 3615 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3616 parm->hc_max_packet_count = 1; 3617 } 3618 3619 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3620 xfer->flags_int.bdma_enable = 1; 3621 3622 usbd_transfer_setup_sub(parm); 3623 3624 nqh = 1; 3625 nqtd = ((2 * xfer->nframes) 3626 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3627 3628 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3629 3630 parm->hc_max_packet_size = 0x3FF; 3631 parm->hc_max_packet_count = 1; 3632 parm->hc_max_frame_size = 0x3FF; 3633 xfer->flags_int.bdma_enable = 1; 3634 3635 usbd_transfer_setup_sub(parm); 3636 3637 nsitd = xfer->nframes; 3638 3639 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3640 3641 parm->hc_max_packet_size = 0x400; 3642 parm->hc_max_packet_count = 3; 3643 parm->hc_max_frame_size = 0xC00; 3644 xfer->flags_int.bdma_enable = 1; 3645 3646 usbd_transfer_setup_sub(parm); 3647 3648 nitd = ((xfer->nframes + 7) / 8) << 3649 usbd_xfer_get_fps_shift(xfer); 3650 3651 } else { 3652 3653 parm->hc_max_packet_size = 0x400; 3654 parm->hc_max_packet_count = 1; 3655 parm->hc_max_frame_size = 0x400; 3656 3657 usbd_transfer_setup_sub(parm); 3658 } 3659 3660 alloc_dma_set: 3661 3662 if (parm->err) { 3663 return; 3664 } 3665 /* 3666 * Allocate queue heads and transfer descriptors 3667 */ 3668 last_obj = NULL; 3669 3670 if (usbd_transfer_setup_sub_malloc( 3671 parm, &pc, sizeof(ehci_itd_t), 3672 EHCI_ITD_ALIGN, nitd)) { 3673 parm->err = USB_ERR_NOMEM; 3674 return; 3675 } 3676 if (parm->buf) { 3677 for (n = 0; n != nitd; n++) { 3678 ehci_itd_t *td; 3679 3680 usbd_get_page(pc + n, 0, &page_info); 3681 3682 td = page_info.buffer; 3683 3684 /* init TD */ 3685 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3686 td->obj_next = last_obj; 3687 td->page_cache = pc + n; 3688 3689 last_obj = td; 3690 3691 usb_pc_cpu_flush(pc + n); 3692 } 3693 } 3694 if (usbd_transfer_setup_sub_malloc( 3695 parm, &pc, sizeof(ehci_sitd_t), 3696 EHCI_SITD_ALIGN, nsitd)) { 3697 parm->err = USB_ERR_NOMEM; 3698 return; 3699 } 3700 if (parm->buf) { 3701 for (n = 0; n != nsitd; n++) { 3702 ehci_sitd_t *td; 3703 3704 usbd_get_page(pc + n, 0, &page_info); 3705 3706 td = page_info.buffer; 3707 3708 /* init TD */ 3709 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3710 td->obj_next = last_obj; 3711 td->page_cache = pc + n; 3712 3713 last_obj = td; 3714 3715 usb_pc_cpu_flush(pc + n); 3716 } 3717 } 3718 if (usbd_transfer_setup_sub_malloc( 3719 parm, &pc, sizeof(ehci_qtd_t), 3720 EHCI_QTD_ALIGN, nqtd)) { 3721 parm->err = USB_ERR_NOMEM; 3722 return; 3723 } 3724 if (parm->buf) { 3725 for (n = 0; n != nqtd; n++) { 3726 ehci_qtd_t *qtd; 3727 3728 usbd_get_page(pc + n, 0, &page_info); 3729 3730 qtd = page_info.buffer; 3731 3732 /* init TD */ 3733 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3734 qtd->obj_next = last_obj; 3735 qtd->page_cache = pc + n; 3736 3737 last_obj = qtd; 3738 3739 usb_pc_cpu_flush(pc + n); 3740 } 3741 } 3742 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3743 3744 last_obj = NULL; 3745 3746 if (usbd_transfer_setup_sub_malloc( 3747 parm, &pc, sizeof(ehci_qh_t), 3748 EHCI_QH_ALIGN, nqh)) { 3749 parm->err = USB_ERR_NOMEM; 3750 return; 3751 } 3752 if (parm->buf) { 3753 for (n = 0; n != nqh; n++) { 3754 ehci_qh_t *qh; 3755 3756 usbd_get_page(pc + n, 0, &page_info); 3757 3758 qh = page_info.buffer; 3759 3760 /* init QH */ 3761 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3762 qh->obj_next = last_obj; 3763 qh->page_cache = pc + n; 3764 3765 last_obj = qh; 3766 3767 usb_pc_cpu_flush(pc + n); 3768 } 3769 } 3770 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3771 3772 if (!xfer->flags_int.curr_dma_set) { 3773 xfer->flags_int.curr_dma_set = 1; 3774 goto alloc_dma_set; 3775 } 3776 } 3777 3778 static void 3779 ehci_xfer_unsetup(struct usb_xfer *xfer) 3780 { 3781 return; 3782 } 3783 3784 static void 3785 ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3786 struct usb_endpoint *ep) 3787 { 3788 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3789 3790 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3791 ep, udev->address, 3792 edesc->bEndpointAddress, udev->flags.usb_mode, 3793 sc->sc_addr); 3794 3795 if (udev->flags.usb_mode != USB_MODE_HOST) { 3796 /* not supported */ 3797 return; 3798 } 3799 if (udev->device_index != sc->sc_addr) { 3800 3801 if ((udev->speed != USB_SPEED_HIGH) && 3802 ((udev->hs_hub_addr == 0) || 3803 (udev->hs_port_no == 0) || 3804 (udev->parent_hs_hub == NULL) || 3805 (udev->parent_hs_hub->hub == NULL))) { 3806 /* We need a transaction translator */ 3807 goto done; 3808 } 3809 switch (edesc->bmAttributes & UE_XFERTYPE) { 3810 case UE_CONTROL: 3811 ep->methods = &ehci_device_ctrl_methods; 3812 break; 3813 case UE_INTERRUPT: 3814 ep->methods = &ehci_device_intr_methods; 3815 break; 3816 case UE_ISOCHRONOUS: 3817 if (udev->speed == USB_SPEED_HIGH) { 3818 ep->methods = &ehci_device_isoc_hs_methods; 3819 } else if (udev->speed == USB_SPEED_FULL) { 3820 ep->methods = &ehci_device_isoc_fs_methods; 3821 } 3822 break; 3823 case UE_BULK: 3824 ep->methods = &ehci_device_bulk_methods; 3825 break; 3826 default: 3827 /* do nothing */ 3828 break; 3829 } 3830 } 3831 done: 3832 return; 3833 } 3834 3835 static void 3836 ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3837 { 3838 /* 3839 * Wait until the hardware has finished any possible use of 3840 * the transfer descriptor(s) and QH 3841 */ 3842 *pus = (188); /* microseconds */ 3843 } 3844 3845 static void 3846 ehci_device_resume(struct usb_device *udev) 3847 { 3848 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3849 struct usb_xfer *xfer; 3850 struct usb_pipe_methods *methods; 3851 3852 DPRINTF("\n"); 3853 3854 USB_BUS_LOCK(udev->bus); 3855 3856 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3857 3858 if (xfer->xroot->udev == udev) { 3859 3860 methods = xfer->endpoint->methods; 3861 3862 if ((methods == &ehci_device_bulk_methods) || 3863 (methods == &ehci_device_ctrl_methods)) { 3864 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3865 sc->sc_async_p_last); 3866 } 3867 if (methods == &ehci_device_intr_methods) { 3868 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3869 sc->sc_intr_p_last[xfer->qh_pos]); 3870 } 3871 } 3872 } 3873 3874 USB_BUS_UNLOCK(udev->bus); 3875 3876 return; 3877 } 3878 3879 static void 3880 ehci_device_suspend(struct usb_device *udev) 3881 { 3882 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3883 struct usb_xfer *xfer; 3884 struct usb_pipe_methods *methods; 3885 3886 DPRINTF("\n"); 3887 3888 USB_BUS_LOCK(udev->bus); 3889 3890 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3891 3892 if (xfer->xroot->udev == udev) { 3893 3894 methods = xfer->endpoint->methods; 3895 3896 if ((methods == &ehci_device_bulk_methods) || 3897 (methods == &ehci_device_ctrl_methods)) { 3898 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3899 sc->sc_async_p_last); 3900 } 3901 if (methods == &ehci_device_intr_methods) { 3902 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3903 sc->sc_intr_p_last[xfer->qh_pos]); 3904 } 3905 } 3906 } 3907 3908 USB_BUS_UNLOCK(udev->bus); 3909 3910 return; 3911 } 3912 3913 static void 3914 ehci_set_hw_power(struct usb_bus *bus) 3915 { 3916 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3917 uint32_t temp; 3918 uint32_t flags; 3919 3920 DPRINTF("\n"); 3921 3922 USB_BUS_LOCK(bus); 3923 3924 flags = bus->hw_power_state; 3925 3926 temp = EOREAD4(sc, EHCI_USBCMD); 3927 3928 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3929 3930 if (flags & (USB_HW_POWER_CONTROL | 3931 USB_HW_POWER_BULK)) { 3932 DPRINTF("Async is active\n"); 3933 temp |= EHCI_CMD_ASE; 3934 } 3935 if (flags & (USB_HW_POWER_INTERRUPT | 3936 USB_HW_POWER_ISOC)) { 3937 DPRINTF("Periodic is active\n"); 3938 temp |= EHCI_CMD_PSE; 3939 } 3940 EOWRITE4(sc, EHCI_USBCMD, temp); 3941 3942 USB_BUS_UNLOCK(bus); 3943 3944 return; 3945 } 3946 3947 struct usb_bus_methods ehci_bus_methods = 3948 { 3949 .endpoint_init = ehci_ep_init, 3950 .xfer_setup = ehci_xfer_setup, 3951 .xfer_unsetup = ehci_xfer_unsetup, 3952 .get_dma_delay = ehci_get_dma_delay, 3953 .device_resume = ehci_device_resume, 3954 .device_suspend = ehci_device_suspend, 3955 .set_hw_power = ehci_set_hw_power, 3956 .roothub_exec = ehci_roothub_exec, 3957 .xfer_poll = ehci_do_poll, 3958 }; 3959