1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _DWC_OTG_H_ 28 #define _DWC_OTG_H_ 29 30 #define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 31 #define DWC_OTG_FRAME_MASK 0x7FF 32 #define DWC_OTG_MAX_TXP 4 33 #define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 34 #define DWC_OTG_MAX_CHANNELS 16 35 #define DWC_OTG_MAX_ENDPOINTS 16 36 #define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 37 38 #define DWC_OTG_READ_4(sc, reg) \ 39 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 40 41 #define DWC_OTG_WRITE_4(sc, reg, data) \ 42 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 43 44 struct dwc_otg_td; 45 struct dwc_otg_softc; 46 47 typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_td *td); 48 49 struct dwc_otg_td { 50 struct dwc_otg_td *obj_next; 51 dwc_otg_cmd_t *func; 52 struct usb_page_cache *pc; 53 uint32_t tx_bytes; 54 uint32_t offset; 55 uint32_t remainder; 56 uint32_t hcchar; /* HOST CFG */ 57 uint32_t hcsplt; /* HOST CFG */ 58 uint16_t max_packet_size; /* packet_size */ 59 uint16_t npkt; 60 uint8_t errcnt; 61 uint8_t tmr_res; 62 uint8_t tmr_val; 63 uint8_t curr_frame; 64 uint8_t ep_no; 65 uint8_t channel; 66 uint8_t state; 67 #define DWC_CHAN_ST_START 0 68 #define DWC_CHAN_ST_WAIT_ANE 1 69 #define DWC_CHAN_ST_WAIT_S_ANE 2 70 #define DWC_CHAN_ST_WAIT_C_ANE 3 71 #define DWC_CHAN_ST_RX_PKT 4 72 #define DWC_CHAN_ST_RX_SPKT 5 73 #define DWC_CHAN_ST_RX_SPKT_SYNC 6 74 #define DWC_CHAN_ST_TX_PKT 4 75 #define DWC_CHAN_ST_TX_CPKT 5 76 #define DWC_CHAN_ST_TX_PKT_SYNC 6 77 uint8_t error:1; 78 uint8_t error_any:1; 79 uint8_t error_stall:1; 80 uint8_t alt_next:1; 81 uint8_t short_pkt:1; 82 uint8_t did_stall:1; 83 uint8_t toggle:1; 84 uint8_t set_toggle:1; 85 uint8_t got_short:1; 86 uint8_t did_nak:1; 87 }; 88 89 struct dwc_otg_std_temp { 90 dwc_otg_cmd_t *func; 91 struct usb_page_cache *pc; 92 struct dwc_otg_td *td; 93 struct dwc_otg_td *td_next; 94 uint32_t len; 95 uint32_t offset; 96 uint16_t max_frame_size; 97 uint8_t short_pkt; 98 99 /* 100 * short_pkt = 0: transfer should be short terminated 101 * short_pkt = 1: transfer should not be short terminated 102 */ 103 uint8_t setup_alt_next; 104 uint8_t did_stall; 105 uint8_t bulk_or_control; 106 }; 107 108 struct dwc_otg_config_desc { 109 struct usb_config_descriptor confd; 110 struct usb_interface_descriptor ifcd; 111 struct usb_endpoint_descriptor endpd; 112 } __packed; 113 114 union dwc_otg_hub_temp { 115 uWord wValue; 116 struct usb_port_status ps; 117 }; 118 119 struct dwc_otg_flags { 120 uint8_t change_connect:1; 121 uint8_t change_suspend:1; 122 uint8_t change_reset:1; 123 uint8_t change_enabled:1; 124 uint8_t change_over_current:1; 125 uint8_t status_suspend:1; /* set if suspended */ 126 uint8_t status_vbus:1; /* set if present */ 127 uint8_t status_bus_reset:1; /* set if reset complete */ 128 uint8_t status_high_speed:1; /* set if High Speed is selected */ 129 uint8_t status_low_speed:1; /* set if Low Speed is selected */ 130 uint8_t status_device_mode:1; /* set if device mode */ 131 uint8_t self_powered:1; 132 uint8_t clocks_off:1; 133 uint8_t port_powered:1; 134 uint8_t port_enabled:1; 135 uint8_t port_over_current:1; 136 uint8_t d_pulled_up:1; 137 }; 138 139 struct dwc_otg_profile { 140 struct usb_hw_ep_profile usb; 141 uint16_t max_buffer; 142 }; 143 144 struct dwc_otg_chan_state { 145 uint32_t hcint; 146 uint8_t wait_sof; 147 uint8_t allocated; 148 uint8_t suspended; 149 }; 150 151 struct dwc_otg_softc { 152 struct usb_bus sc_bus; 153 union dwc_otg_hub_temp sc_hub_temp; 154 struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 155 struct usb_callout sc_timer; 156 157 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 158 struct resource *sc_io_res; 159 struct resource *sc_irq_res; 160 void *sc_intr_hdl; 161 bus_size_t sc_io_size; 162 bus_space_tag_t sc_io_tag; 163 bus_space_handle_t sc_io_hdl; 164 165 uint32_t sc_rx_bounce_buffer[1024 / 4]; 166 uint32_t sc_tx_bounce_buffer[(512 * DWC_OTG_MAX_TXP) / 4]; 167 168 uint32_t sc_fifo_size; 169 uint32_t sc_irq_mask; 170 uint32_t sc_last_rx_status; 171 uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 172 uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 173 struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 174 uint32_t sc_tmr_val; 175 uint32_t sc_hprt_val; 176 177 uint16_t sc_active_rx_ep; 178 179 uint8_t sc_timer_active; 180 uint8_t sc_dev_ep_max; 181 uint8_t sc_dev_in_ep_max; 182 uint8_t sc_host_ch_max; 183 uint8_t sc_rt_addr; /* root HUB address */ 184 uint8_t sc_conf; /* root HUB config */ 185 uint8_t sc_mode; /* mode of operation */ 186 #define DWC_MODE_OTG 0 /* both modes */ 187 #define DWC_MODE_DEVICE 1 /* device only */ 188 #define DWC_MODE_HOST 2 /* host only */ 189 190 uint8_t sc_hub_idata[1]; 191 192 struct dwc_otg_flags sc_flags; 193 }; 194 195 /* prototypes */ 196 197 void dwc_otg_interrupt(struct dwc_otg_softc *); 198 int dwc_otg_init(struct dwc_otg_softc *); 199 void dwc_otg_uninit(struct dwc_otg_softc *); 200 201 #endif /* _DWC_OTG_H_ */ 202