1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DWC_OTG_H_ 29 #define _DWC_OTG_H_ 30 31 #define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 32 #define DWC_OTG_FRAME_MASK 0x7FF 33 #define DWC_OTG_MAX_TXP 4 34 #define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 35 #define DWC_OTG_MAX_CHANNELS 16 36 #define DWC_OTG_MAX_ENDPOINTS 16 37 #define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 38 #define DWC_OTG_TT_SLOT_MAX 8 39 #define DWC_OTG_SLOT_IDLE_MAX 3 40 #define DWC_OTG_SLOT_IDLE_MIN 2 41 #ifndef DWC_OTG_TX_MAX_FIFO_SIZE 42 #define DWC_OTG_TX_MAX_FIFO_SIZE DWC_OTG_MAX_TXN 43 #endif 44 45 #define DWC_OTG_READ_4(sc, reg) \ 46 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 47 48 #define DWC_OTG_WRITE_4(sc, reg, data) \ 49 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 50 51 struct dwc_otg_td; 52 struct dwc_otg_softc; 53 54 typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_softc *sc, struct dwc_otg_td *td); 55 56 struct dwc_otg_td { 57 struct dwc_otg_td *obj_next; 58 dwc_otg_cmd_t *func; 59 struct usb_page_cache *pc; 60 uint32_t tx_bytes; 61 uint32_t offset; 62 uint32_t remainder; 63 uint32_t hcchar; /* HOST CFG */ 64 uint32_t hcsplt; /* HOST CFG */ 65 uint16_t max_packet_size; /* packet_size */ 66 uint16_t npkt; 67 uint8_t max_packet_count; /* packet_count */ 68 uint8_t errcnt; 69 uint8_t tmr_res; 70 uint8_t tmr_val; 71 uint8_t ep_no; 72 uint8_t ep_type; 73 uint8_t channel[3]; 74 uint8_t tt_index; /* TT data */ 75 uint8_t tt_start_slot; /* TT data */ 76 uint8_t tt_complete_slot; /* TT data */ 77 uint8_t tt_xactpos; /* TT data */ 78 uint8_t state; 79 #define DWC_CHAN_ST_START 0 80 #define DWC_CHAN_ST_WAIT_ANE 1 81 #define DWC_CHAN_ST_WAIT_S_ANE 2 82 #define DWC_CHAN_ST_WAIT_C_ANE 3 83 #define DWC_CHAN_ST_WAIT_C_PKT 4 84 #define DWC_CHAN_ST_TX_WAIT_ISOC 5 85 uint8_t error_any:1; 86 uint8_t error_stall:1; 87 uint8_t alt_next:1; 88 uint8_t short_pkt:1; 89 uint8_t did_stall:1; 90 uint8_t toggle:1; 91 uint8_t set_toggle:1; 92 uint8_t got_short:1; 93 uint8_t tt_scheduled:1; 94 uint8_t did_nak:1; 95 }; 96 97 struct dwc_otg_tt_info { 98 uint8_t slot_index; 99 }; 100 101 struct dwc_otg_std_temp { 102 dwc_otg_cmd_t *func; 103 struct usb_page_cache *pc; 104 struct dwc_otg_td *td; 105 struct dwc_otg_td *td_next; 106 uint32_t len; 107 uint32_t offset; 108 uint16_t max_frame_size; 109 uint8_t short_pkt; 110 111 /* 112 * short_pkt = 0: transfer should be short terminated 113 * short_pkt = 1: transfer should not be short terminated 114 */ 115 uint8_t setup_alt_next; 116 uint8_t did_stall; 117 uint8_t bulk_or_control; 118 }; 119 120 struct dwc_otg_config_desc { 121 struct usb_config_descriptor confd; 122 struct usb_interface_descriptor ifcd; 123 struct usb_endpoint_descriptor endpd; 124 } __packed; 125 126 union dwc_otg_hub_temp { 127 uWord wValue; 128 struct usb_port_status ps; 129 }; 130 131 struct dwc_otg_flags { 132 uint8_t change_connect:1; 133 uint8_t change_suspend:1; 134 uint8_t change_reset:1; 135 uint8_t change_enabled:1; 136 uint8_t change_over_current:1; 137 uint8_t status_suspend:1; /* set if suspended */ 138 uint8_t status_vbus:1; /* set if present */ 139 uint8_t status_bus_reset:1; /* set if reset complete */ 140 uint8_t status_high_speed:1; /* set if High Speed is selected */ 141 uint8_t status_low_speed:1; /* set if Low Speed is selected */ 142 uint8_t status_device_mode:1; /* set if device mode */ 143 uint8_t self_powered:1; 144 uint8_t clocks_off:1; 145 uint8_t port_powered:1; 146 uint8_t port_enabled:1; 147 uint8_t port_over_current:1; 148 uint8_t d_pulled_up:1; 149 }; 150 151 struct dwc_otg_profile { 152 struct usb_hw_ep_profile usb; 153 uint16_t max_buffer; 154 }; 155 156 struct dwc_otg_chan_state { 157 uint16_t allocated; 158 uint16_t wait_halted; 159 uint32_t hcint; 160 }; 161 162 struct dwc_otg_softc { 163 struct usb_bus sc_bus; 164 union dwc_otg_hub_temp sc_hub_temp; 165 struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 166 struct dwc_otg_tt_info sc_tt_info[DWC_OTG_MAX_DEVICES]; 167 struct usb_callout sc_timer; 168 169 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 170 struct resource *sc_io_res; 171 struct resource *sc_irq_res; 172 void *sc_intr_hdl; 173 bus_size_t sc_io_size; 174 bus_space_tag_t sc_io_tag; 175 bus_space_handle_t sc_io_hdl; 176 177 uint32_t sc_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4]; 178 179 uint32_t sc_fifo_size; 180 uint32_t sc_irq_mask; 181 uint32_t sc_last_rx_status; 182 uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 183 uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 184 struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 185 uint32_t sc_tmr_val; 186 uint32_t sc_hprt_val; 187 uint32_t sc_xfer_complete; 188 189 uint16_t sc_current_rx_bytes; 190 uint16_t sc_current_rx_fifo; 191 192 uint16_t sc_active_rx_ep; 193 uint16_t sc_last_frame_num; 194 195 uint8_t sc_phy_type; 196 uint8_t sc_phy_bits; 197 #define DWC_OTG_PHY_ULPI 1 198 #define DWC_OTG_PHY_HSIC 2 199 #define DWC_OTG_PHY_INTERNAL 3 200 #define DWC_OTG_PHY_UTMI 4 201 202 uint8_t sc_timer_active; 203 uint8_t sc_dev_ep_max; 204 uint8_t sc_dev_in_ep_max; 205 uint8_t sc_host_ch_max; 206 uint8_t sc_needsof; 207 uint8_t sc_rt_addr; /* root HUB address */ 208 uint8_t sc_conf; /* root HUB config */ 209 uint8_t sc_mode; /* mode of operation */ 210 #define DWC_MODE_OTG 0 /* both modes */ 211 #define DWC_MODE_DEVICE 1 /* device only */ 212 #define DWC_MODE_HOST 2 /* host only */ 213 214 uint8_t sc_hub_idata[1]; 215 216 struct dwc_otg_flags sc_flags; 217 }; 218 219 /* prototypes */ 220 221 driver_filter_t dwc_otg_filter_interrupt; 222 driver_intr_t dwc_otg_interrupt; 223 int dwc_otg_init(struct dwc_otg_softc *); 224 void dwc_otg_uninit(struct dwc_otg_softc *); 225 226 #endif /* _DWC_OTG_H_ */ 227