1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #ifndef _DWC_OTG_H_ 28 #define _DWC_OTG_H_ 29 30 #define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 31 #define DWC_OTG_FRAME_MASK 0x7FF 32 #define DWC_OTG_MAX_TXP 4 33 #define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 34 #define DWC_OTG_MAX_CHANNELS 16 35 #define DWC_OTG_MAX_ENDPOINTS 16 36 #define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 37 #define DWC_OTG_TT_SLOT_MAX 8 38 #define DWC_OTG_SLOT_IDLE_MAX 3 39 #define DWC_OTG_SLOT_IDLE_MIN 2 40 #define DWC_OTG_NAK_MAX 16 /* 16 NAKs = 2 ms */ 41 #ifndef DWC_OTG_TX_MAX_FIFO_SIZE 42 #define DWC_OTG_TX_MAX_FIFO_SIZE DWC_OTG_MAX_TXN 43 #endif 44 45 #define DWC_OTG_READ_4(sc, reg) \ 46 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 47 48 #define DWC_OTG_WRITE_4(sc, reg, data) \ 49 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 50 51 struct dwc_otg_td; 52 struct dwc_otg_softc; 53 54 typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_softc *sc, struct dwc_otg_td *td); 55 56 struct dwc_otg_td { 57 struct dwc_otg_td *obj_next; 58 dwc_otg_cmd_t *func; 59 struct usb_page_cache *pc; 60 uint32_t tx_bytes; 61 uint32_t offset; 62 uint32_t remainder; 63 uint32_t hcchar; /* HOST CFG */ 64 uint32_t hcsplt; /* HOST CFG */ 65 uint16_t max_packet_size; /* packet_size */ 66 uint16_t npkt; 67 uint8_t max_packet_count; /* packet_count */ 68 uint8_t errcnt; 69 uint8_t tmr_res; 70 uint8_t tmr_val; 71 uint8_t did_nak; /* NAK counter */ 72 uint8_t ep_no; 73 uint8_t ep_type; 74 uint8_t channel; 75 uint8_t tt_index; /* TT data */ 76 uint8_t tt_start_slot; /* TT data */ 77 uint8_t tt_complete_slot; /* TT data */ 78 uint8_t tt_xactpos; /* TT data */ 79 uint8_t state; 80 #define DWC_CHAN_ST_START 0 81 #define DWC_CHAN_ST_WAIT_ANE 1 82 #define DWC_CHAN_ST_WAIT_S_ANE 2 83 #define DWC_CHAN_ST_WAIT_C_ANE 3 84 #define DWC_CHAN_ST_WAIT_C_PKT 4 85 #define DWC_CHAN_ST_TX_PKT_ISOC 5 86 #define DWC_CHAN_ST_TX_WAIT_ISOC 6 87 uint8_t error_any:1; 88 uint8_t error_stall:1; 89 uint8_t alt_next:1; 90 uint8_t short_pkt:1; 91 uint8_t did_stall:1; 92 uint8_t toggle:1; 93 uint8_t set_toggle:1; 94 uint8_t got_short:1; 95 uint8_t tt_scheduled:1; 96 }; 97 98 struct dwc_otg_tt_info { 99 uint8_t slot_index; 100 }; 101 102 struct dwc_otg_std_temp { 103 dwc_otg_cmd_t *func; 104 struct usb_page_cache *pc; 105 struct dwc_otg_td *td; 106 struct dwc_otg_td *td_next; 107 uint32_t len; 108 uint32_t offset; 109 uint16_t max_frame_size; 110 uint8_t short_pkt; 111 112 /* 113 * short_pkt = 0: transfer should be short terminated 114 * short_pkt = 1: transfer should not be short terminated 115 */ 116 uint8_t setup_alt_next; 117 uint8_t did_stall; 118 uint8_t bulk_or_control; 119 }; 120 121 struct dwc_otg_config_desc { 122 struct usb_config_descriptor confd; 123 struct usb_interface_descriptor ifcd; 124 struct usb_endpoint_descriptor endpd; 125 } __packed; 126 127 union dwc_otg_hub_temp { 128 uWord wValue; 129 struct usb_port_status ps; 130 }; 131 132 struct dwc_otg_flags { 133 uint8_t change_connect:1; 134 uint8_t change_suspend:1; 135 uint8_t change_reset:1; 136 uint8_t change_enabled:1; 137 uint8_t change_over_current:1; 138 uint8_t status_suspend:1; /* set if suspended */ 139 uint8_t status_vbus:1; /* set if present */ 140 uint8_t status_bus_reset:1; /* set if reset complete */ 141 uint8_t status_high_speed:1; /* set if High Speed is selected */ 142 uint8_t status_low_speed:1; /* set if Low Speed is selected */ 143 uint8_t status_device_mode:1; /* set if device mode */ 144 uint8_t self_powered:1; 145 uint8_t clocks_off:1; 146 uint8_t port_powered:1; 147 uint8_t port_enabled:1; 148 uint8_t port_over_current:1; 149 uint8_t d_pulled_up:1; 150 }; 151 152 struct dwc_otg_profile { 153 struct usb_hw_ep_profile usb; 154 uint16_t max_buffer; 155 }; 156 157 struct dwc_otg_chan_state { 158 uint16_t allocated; 159 uint16_t wait_halted; 160 uint32_t hcint; 161 }; 162 163 struct dwc_otg_softc { 164 struct usb_bus sc_bus; 165 union dwc_otg_hub_temp sc_hub_temp; 166 struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 167 struct dwc_otg_tt_info sc_tt_info[DWC_OTG_MAX_DEVICES]; 168 struct usb_callout sc_timer; 169 170 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 171 struct resource *sc_io_res; 172 struct resource *sc_irq_res; 173 void *sc_intr_hdl; 174 bus_size_t sc_io_size; 175 bus_space_tag_t sc_io_tag; 176 bus_space_handle_t sc_io_hdl; 177 178 uint32_t sc_rx_bounce_buffer[1024 / 4]; 179 uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4]; 180 181 uint32_t sc_fifo_size; 182 uint32_t sc_irq_mask; 183 uint32_t sc_last_rx_status; 184 uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 185 uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 186 struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 187 uint32_t sc_tmr_val; 188 uint32_t sc_hprt_val; 189 uint32_t sc_xfer_complete; 190 191 uint16_t sc_active_rx_ep; 192 uint16_t sc_last_frame_num; 193 194 uint8_t sc_timer_active; 195 uint8_t sc_dev_ep_max; 196 uint8_t sc_dev_in_ep_max; 197 uint8_t sc_host_ch_max; 198 uint8_t sc_needsof; 199 uint8_t sc_rt_addr; /* root HUB address */ 200 uint8_t sc_conf; /* root HUB config */ 201 uint8_t sc_mode; /* mode of operation */ 202 #define DWC_MODE_OTG 0 /* both modes */ 203 #define DWC_MODE_DEVICE 1 /* device only */ 204 #define DWC_MODE_HOST 2 /* host only */ 205 206 uint8_t sc_hub_idata[1]; 207 208 struct dwc_otg_flags sc_flags; 209 }; 210 211 /* prototypes */ 212 213 driver_filter_t dwc_otg_filter_interrupt; 214 driver_intr_t dwc_otg_interrupt; 215 int dwc_otg_init(struct dwc_otg_softc *); 216 void dwc_otg_uninit(struct dwc_otg_softc *); 217 218 #endif /* _DWC_OTG_H_ */ 219