1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_ENABLED \ 97 (GINTMSK_ENUMDONEMSK | \ 98 GINTMSK_USBRSTMSK | \ 99 GINTMSK_USBSUSPMSK | \ 100 GINTMSK_IEPINTMSK | \ 101 GINTMSK_SESSREQINTMSK | \ 102 GINTMSK_RXFLVLMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTMSK_OTGINTMSK | \ 105 GINTMSK_PRTINTMSK) 106 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 108 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 109 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 110 GINTSTS_SESSREQINT) 111 112 #define DWC_OTG_PHY_ULPI 0 113 #define DWC_OTG_PHY_HSIC 1 114 #define DWC_OTG_PHY_INTERNAL 2 115 116 #ifndef DWC_OTG_PHY_DEFAULT 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 118 #endif 119 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 121 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 124 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 125 126 #ifdef USB_DEBUG 127 static int dwc_otg_debug; 128 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 130 &dwc_otg_debug, 0, "DWC OTG debug level"); 131 #endif 132 133 #define DWC_OTG_INTR_ENDPT 1 134 135 /* prototypes */ 136 137 static const struct usb_bus_methods dwc_otg_bus_methods; 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 140 141 static dwc_otg_cmd_t dwc_otg_setup_rx; 142 static dwc_otg_cmd_t dwc_otg_data_rx; 143 static dwc_otg_cmd_t dwc_otg_data_tx; 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 145 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_tx; 148 static dwc_otg_cmd_t dwc_otg_host_data_rx; 149 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 151 static void dwc_otg_do_poll(struct usb_bus *); 152 static void dwc_otg_standard_done(struct usb_xfer *); 153 static void dwc_otg_root_intr(struct dwc_otg_softc *); 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static void 184 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 185 { 186 uint32_t temp; 187 188 /* reset FIFO */ 189 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 190 191 /* wait for reset to complete */ 192 for (temp = 0; temp != 16; temp++) { 193 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 194 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 195 break; 196 } 197 } 198 199 static int 200 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 201 { 202 struct dwc_otg_profile *pf; 203 uint32_t fifo_size; 204 uint32_t fifo_regs; 205 uint32_t tx_start; 206 uint8_t x; 207 208 fifo_size = sc->sc_fifo_size; 209 210 /* 211 * NOTE: Reserved fixed size area at end of RAM, which must 212 * not be allocated to the FIFOs: 213 */ 214 fifo_regs = 4 * 16; 215 216 if (fifo_size < fifo_regs) { 217 DPRINTF("Too little FIFO\n"); 218 return (EINVAL); 219 } 220 221 /* subtract FIFO regs from total once */ 222 fifo_size -= fifo_regs; 223 224 /* split equally for IN and OUT */ 225 fifo_size /= 2; 226 227 /* Align to 4 bytes boundary (refer to PGM) */ 228 fifo_size &= ~3; 229 230 /* set global receive FIFO size */ 231 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 232 233 tx_start = fifo_size; 234 235 if (fifo_size < 64) { 236 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 237 return (EINVAL); 238 } 239 240 if (mode == DWC_MODE_HOST) { 241 242 /* reset active endpoints */ 243 sc->sc_active_rx_ep = 0; 244 245 /* split equally for periodic and non-periodic */ 246 fifo_size /= 2; 247 248 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 249 250 /* align to 4 bytes boundary */ 251 fifo_size &= ~3; 252 253 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 254 ((fifo_size / 4) << 16) | 255 (tx_start / 4)); 256 257 tx_start += fifo_size; 258 259 for (x = 0; x != sc->sc_host_ch_max; x++) { 260 /* enable all host interrupts */ 261 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 262 HCINT_DEFAULT_MASK); 263 } 264 265 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 266 ((fifo_size / 4) << 16) | 267 (tx_start / 4)); 268 269 /* reset host channel state */ 270 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 271 272 /* enable all host channel interrupts */ 273 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 274 (1U << sc->sc_host_ch_max) - 1U); 275 } 276 277 if (mode == DWC_MODE_DEVICE) { 278 279 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 280 (0x10 << 16) | (tx_start / 4)); 281 fifo_size -= 0x40; 282 tx_start += 0x40; 283 284 /* setup control endpoint profile */ 285 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 286 287 /* reset active endpoints */ 288 sc->sc_active_rx_ep = 1; 289 290 for (x = 1; x != sc->sc_dev_ep_max; x++) { 291 292 pf = sc->sc_hw_ep_profile + x; 293 294 pf->usb.max_out_frame_size = 1024 * 3; 295 pf->usb.is_simplex = 0; /* assume duplex */ 296 pf->usb.support_bulk = 1; 297 pf->usb.support_interrupt = 1; 298 pf->usb.support_isochronous = 1; 299 pf->usb.support_out = 1; 300 301 if (x < sc->sc_dev_in_ep_max) { 302 uint32_t limit; 303 304 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 305 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 306 DWC_OTG_TX_MAX_FIFO_SIZE); 307 308 /* see if there is enough FIFO space */ 309 if (limit <= fifo_size) { 310 pf->max_buffer = limit; 311 pf->usb.support_in = 1; 312 } else { 313 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 314 if (limit <= fifo_size) { 315 pf->usb.support_in = 1; 316 } else { 317 pf->usb.is_simplex = 1; 318 limit = 0; 319 } 320 } 321 /* set FIFO size */ 322 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 323 ((limit / 4) << 16) | (tx_start / 4)); 324 tx_start += limit; 325 fifo_size -= limit; 326 pf->usb.max_in_frame_size = limit; 327 } else { 328 pf->usb.is_simplex = 1; 329 } 330 331 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 332 pf->usb.max_in_frame_size, 333 pf->usb.max_out_frame_size); 334 } 335 } 336 337 /* reset RX FIFO */ 338 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 339 340 if (mode != DWC_MODE_OTG) { 341 /* reset all TX FIFOs */ 342 dwc_otg_tx_fifo_reset(sc, 343 GRSTCTL_TXFIFO(0x10) | 344 GRSTCTL_TXFFLSH); 345 } else { 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* reset host channel state */ 350 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 351 } 352 return (0); 353 } 354 355 static void 356 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 357 { 358 359 /* 360 * Disabled until further. Assuming that the register is already 361 * programmed correctly by the boot loader. 362 */ 363 #if 0 364 uint32_t temp; 365 366 /* setup HOST frame interval register, based on existing value */ 367 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 368 if (temp >= 10000) 369 temp /= 1000; 370 else 371 temp /= 125; 372 373 /* figure out nearest X-tal value */ 374 if (temp >= 54) 375 temp = 60; /* MHz */ 376 else if (temp >= 39) 377 temp = 48; /* MHz */ 378 else 379 temp = 30; /* MHz */ 380 381 if (sc->sc_flags.status_high_speed) 382 temp *= 125; 383 else 384 temp *= 1000; 385 386 DPRINTF("HFIR=0x%08x\n", temp); 387 388 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 389 #endif 390 } 391 392 static void 393 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 394 { 395 if (sc->sc_flags.clocks_off && 396 sc->sc_flags.port_powered) { 397 398 DPRINTFN(5, "\n"); 399 400 /* TODO - platform specific */ 401 402 sc->sc_flags.clocks_off = 0; 403 } 404 } 405 406 static void 407 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 408 { 409 if (!sc->sc_flags.clocks_off) { 410 411 DPRINTFN(5, "\n"); 412 413 /* TODO - platform specific */ 414 415 sc->sc_flags.clocks_off = 1; 416 } 417 } 418 419 static void 420 dwc_otg_pull_up(struct dwc_otg_softc *sc) 421 { 422 uint32_t temp; 423 424 /* pullup D+, if possible */ 425 426 if (!sc->sc_flags.d_pulled_up && 427 sc->sc_flags.port_powered) { 428 sc->sc_flags.d_pulled_up = 1; 429 430 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 431 temp &= ~DCTL_SFTDISCON; 432 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 433 } 434 } 435 436 static void 437 dwc_otg_pull_down(struct dwc_otg_softc *sc) 438 { 439 uint32_t temp; 440 441 /* pulldown D+, if possible */ 442 443 if (sc->sc_flags.d_pulled_up) { 444 sc->sc_flags.d_pulled_up = 0; 445 446 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 447 temp |= DCTL_SFTDISCON; 448 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 449 } 450 } 451 452 static void 453 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 454 { 455 /* In device mode we don't use the SOF interrupt */ 456 if (sc->sc_flags.status_device_mode != 0) 457 return; 458 /* Ensure the SOF interrupt is not disabled */ 459 sc->sc_needsof = 1; 460 /* Check if the SOF interrupt is already enabled */ 461 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 462 return; 463 sc->sc_irq_mask |= GINTMSK_SOFMSK; 464 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 465 } 466 467 static void 468 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 469 { 470 if (sc->sc_flags.status_suspend) { 471 /* update status bits */ 472 sc->sc_flags.status_suspend = 0; 473 sc->sc_flags.change_suspend = 1; 474 475 if (sc->sc_flags.status_device_mode) { 476 /* 477 * Disable resume interrupt and enable suspend 478 * interrupt: 479 */ 480 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 481 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 482 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 483 } 484 485 /* complete root HUB interrupt endpoint */ 486 dwc_otg_root_intr(sc); 487 } 488 } 489 490 static void 491 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 492 { 493 if (!sc->sc_flags.status_suspend) { 494 /* update status bits */ 495 sc->sc_flags.status_suspend = 1; 496 sc->sc_flags.change_suspend = 1; 497 498 if (sc->sc_flags.status_device_mode) { 499 /* 500 * Disable suspend interrupt and enable resume 501 * interrupt: 502 */ 503 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 504 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 505 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 506 } 507 508 /* complete root HUB interrupt endpoint */ 509 dwc_otg_root_intr(sc); 510 } 511 } 512 513 static void 514 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 515 { 516 if (!sc->sc_flags.status_suspend) 517 return; 518 519 DPRINTFN(5, "Remote wakeup\n"); 520 521 if (sc->sc_flags.status_device_mode) { 522 uint32_t temp; 523 524 /* enable remote wakeup signalling */ 525 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 526 temp |= DCTL_RMTWKUPSIG; 527 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 528 529 /* Wait 8ms for remote wakeup to complete. */ 530 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 531 532 temp &= ~DCTL_RMTWKUPSIG; 533 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 534 } else { 535 /* enable USB port */ 536 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 537 538 /* wait 10ms */ 539 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 540 541 /* resume port */ 542 sc->sc_hprt_val |= HPRT_PRTRES; 543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 544 545 /* Wait 100ms for resume signalling to complete. */ 546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 547 548 /* clear suspend and resume */ 549 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 550 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 551 552 /* Wait 4ms */ 553 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 554 } 555 556 /* need to fake resume IRQ */ 557 dwc_otg_resume_irq(sc); 558 } 559 560 static void 561 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 562 { 563 uint32_t temp; 564 565 DPRINTFN(5, "addr=%d\n", addr); 566 567 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 568 temp &= ~DCFG_DEVADDR_SET(0x7F); 569 temp |= DCFG_DEVADDR_SET(addr); 570 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 571 } 572 573 static void 574 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 575 { 576 DPRINTFN(5, "RX status clear\n"); 577 578 /* enable RX FIFO level interrupt */ 579 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 580 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 581 582 /* clear cached status */ 583 sc->sc_last_rx_status = 0; 584 } 585 586 static void 587 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 588 { 589 uint32_t hcint; 590 591 /* clear all pending interrupts */ 592 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 593 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 594 595 /* clear buffered interrupts */ 596 sc->sc_chan_state[x].hcint = 0; 597 } 598 599 static uint8_t 600 dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 601 { 602 uint32_t temp; 603 604 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 605 606 if (td->ep_type == UE_INTERRUPT || 607 td->ep_type == UE_ISOCHRONOUS) { 608 if (!(temp & GINTSTS_PTXFEMP)) { 609 DPRINTF("Periodic TX FIFO is not empty\n"); 610 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 611 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 612 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 613 } 614 return (1); /* busy */ 615 } 616 } else { 617 if (!(temp & GINTSTS_NPTXFEMP)) { 618 DPRINTF("Non-periodic TX FIFO is not empty\n"); 619 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 620 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 621 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 622 } 623 return (1); /* busy */ 624 } 625 } 626 return (0); /* ready for transmit */ 627 } 628 629 static uint8_t 630 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 631 struct dwc_otg_td *td, uint8_t is_out) 632 { 633 uint8_t x; 634 635 if (td->channel < DWC_OTG_MAX_CHANNELS) 636 return (0); /* already allocated */ 637 638 /* check if device is suspended */ 639 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 640 return (1); /* busy - cannot transfer data */ 641 642 /* compute needed TX FIFO size */ 643 if (is_out != 0) { 644 if (dwc_otg_host_check_fifo_empty(sc, td) != 0) 645 return (1); /* busy - cannot transfer data */ 646 } 647 648 for (x = 0; x != sc->sc_host_ch_max; x++) { 649 /* check if channel is allocated */ 650 if (sc->sc_chan_state[x].allocated != 0) 651 continue; 652 /* check if channel is still enabled */ 653 if (sc->sc_chan_state[x].wait_halted != 0) 654 continue; 655 656 sc->sc_chan_state[x].allocated = 1; 657 658 /* clear interrupts */ 659 dwc_otg_clear_hcint(sc, x); 660 661 DPRINTF("CH=%d HCCHAR=0x%08x " 662 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 663 664 /* set active channel */ 665 sc->sc_active_rx_ep |= (1 << x); 666 667 /* set channel */ 668 td->channel = x; 669 670 return (0); /* allocated */ 671 } 672 /* wait a bit */ 673 dwc_otg_enable_sof_irq(sc); 674 return (1); /* busy */ 675 } 676 677 static void 678 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 679 { 680 uint32_t hcchar; 681 uint8_t x; 682 683 if (td->channel >= DWC_OTG_MAX_CHANNELS) 684 return; /* already freed */ 685 686 /* free channel */ 687 x = td->channel; 688 td->channel = DWC_OTG_MAX_CHANNELS; 689 690 DPRINTF("CH=%d\n", x); 691 692 /* 693 * We need to let programmed host channels run till complete 694 * else the host channel will stop functioning. 695 */ 696 sc->sc_chan_state[x].allocated = 0; 697 698 /* ack any pending messages */ 699 if (sc->sc_last_rx_status != 0 && 700 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 701 dwc_otg_common_rx_ack(sc); 702 } 703 704 /* clear active channel */ 705 sc->sc_active_rx_ep &= ~(1 << x); 706 707 /* disable host channel */ 708 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 709 if (hcchar & HCCHAR_CHENA) { 710 DPRINTF("Halting channel %d\n", x); 711 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 712 hcchar | HCCHAR_CHDIS); 713 sc->sc_chan_state[x].wait_halted = 1; 714 /* don't write HCCHAR until the channel is halted */ 715 } 716 } 717 718 static void 719 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 720 { 721 /* dump any pending messages */ 722 if (sc->sc_last_rx_status != 0) { 723 if (td->channel < DWC_OTG_MAX_CHANNELS && 724 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 725 dwc_otg_common_rx_ack(sc); 726 } 727 } 728 } 729 730 static uint8_t 731 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 732 { 733 struct usb_device_request req __aligned(4); 734 uint32_t hcint; 735 uint32_t hcchar; 736 uint8_t delta; 737 738 dwc_otg_host_dump_rx(sc, td); 739 740 if (td->channel < DWC_OTG_MAX_CHANNELS) { 741 hcint = sc->sc_chan_state[td->channel].hcint; 742 743 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 744 td->channel, td->state, hcint, 745 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 746 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 747 } else { 748 hcint = 0; 749 goto check_state; 750 } 751 752 if (hcint & (HCINT_RETRY | 753 HCINT_ACK | HCINT_NYET)) { 754 /* give success bits priority over failure bits */ 755 } else if (hcint & HCINT_STALL) { 756 DPRINTF("CH=%d STALL\n", td->channel); 757 td->error_stall = 1; 758 td->error_any = 1; 759 goto complete; 760 } else if (hcint & HCINT_ERRORS) { 761 DPRINTF("CH=%d ERROR\n", td->channel); 762 td->errcnt++; 763 if (td->hcsplt != 0 || td->errcnt >= 3) { 764 td->error_any = 1; 765 goto complete; 766 } 767 } 768 769 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 770 HCINT_ACK | HCINT_NYET)) { 771 if (!(hcint & HCINT_ERRORS)) 772 td->errcnt = 0; 773 } 774 775 check_state: 776 switch (td->state) { 777 case DWC_CHAN_ST_START: 778 goto send_pkt; 779 780 case DWC_CHAN_ST_WAIT_ANE: 781 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 782 td->did_nak = 1; 783 td->tt_scheduled = 0; 784 goto send_pkt; 785 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 786 td->offset += td->tx_bytes; 787 td->remainder -= td->tx_bytes; 788 td->toggle = 1; 789 td->tt_scheduled = 0; 790 goto complete; 791 } 792 break; 793 794 case DWC_CHAN_ST_WAIT_S_ANE: 795 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 796 td->did_nak = 1; 797 td->tt_scheduled = 0; 798 goto send_pkt; 799 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 800 goto send_cpkt; 801 } 802 break; 803 804 case DWC_CHAN_ST_WAIT_C_ANE: 805 if (hcint & HCINT_NYET) { 806 goto send_cpkt; 807 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 808 td->did_nak = 1; 809 td->tt_scheduled = 0; 810 goto send_pkt; 811 } else if (hcint & HCINT_ACK) { 812 td->offset += td->tx_bytes; 813 td->remainder -= td->tx_bytes; 814 td->toggle = 1; 815 goto complete; 816 } 817 break; 818 819 case DWC_CHAN_ST_WAIT_C_PKT: 820 goto send_cpkt; 821 822 default: 823 break; 824 } 825 goto busy; 826 827 send_pkt: 828 /* free existing channel, if any */ 829 dwc_otg_host_channel_free(sc, td); 830 831 if (sizeof(req) != td->remainder) { 832 td->error_any = 1; 833 goto complete; 834 } 835 836 if (td->hcsplt != 0) { 837 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 838 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 839 td->state = DWC_CHAN_ST_START; 840 goto busy; 841 } 842 delta = sc->sc_last_frame_num - td->tt_start_slot; 843 if (delta > 5) { 844 /* missed it */ 845 td->tt_scheduled = 0; 846 td->state = DWC_CHAN_ST_START; 847 goto busy; 848 } 849 } 850 851 /* allocate a new channel */ 852 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 853 td->state = DWC_CHAN_ST_START; 854 goto busy; 855 } 856 857 if (td->hcsplt != 0) { 858 td->hcsplt &= ~HCSPLT_COMPSPLT; 859 td->state = DWC_CHAN_ST_WAIT_S_ANE; 860 } else { 861 td->state = DWC_CHAN_ST_WAIT_ANE; 862 } 863 864 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 865 866 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 867 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 868 (1 << HCTSIZ_PKTCNT_SHIFT) | 869 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 870 871 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 872 873 hcchar = td->hcchar; 874 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 875 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 876 877 /* must enable channel before writing data to FIFO */ 878 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 879 880 /* transfer data into FIFO */ 881 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 882 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 883 884 /* wait until next slot before trying complete split */ 885 td->tt_complete_slot = sc->sc_last_frame_num + 1; 886 887 /* store number of bytes transmitted */ 888 td->tx_bytes = sizeof(req); 889 goto busy; 890 891 send_cpkt: 892 /* free existing channel, if any */ 893 dwc_otg_host_channel_free(sc, td); 894 895 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 896 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 897 td->state = DWC_CHAN_ST_WAIT_C_PKT; 898 goto busy; 899 } 900 delta = sc->sc_last_frame_num - td->tt_start_slot; 901 if (delta > DWC_OTG_TT_SLOT_MAX) { 902 /* we missed the service interval */ 903 if (td->ep_type != UE_ISOCHRONOUS) 904 td->error_any = 1; 905 goto complete; 906 } 907 /* allocate a new channel */ 908 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 909 td->state = DWC_CHAN_ST_WAIT_C_PKT; 910 goto busy; 911 } 912 913 /* wait until next slot before trying complete split */ 914 td->tt_complete_slot = sc->sc_last_frame_num + 1; 915 916 td->hcsplt |= HCSPLT_COMPSPLT; 917 td->state = DWC_CHAN_ST_WAIT_C_ANE; 918 919 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 920 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 921 922 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 923 924 hcchar = td->hcchar; 925 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 926 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 927 928 /* must enable channel before writing data to FIFO */ 929 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 930 931 busy: 932 return (1); /* busy */ 933 934 complete: 935 dwc_otg_host_channel_free(sc, td); 936 return (0); /* complete */ 937 } 938 939 static uint8_t 940 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 941 { 942 struct usb_device_request req __aligned(4); 943 uint32_t temp; 944 uint16_t count; 945 946 /* check endpoint status */ 947 948 if (sc->sc_last_rx_status == 0) 949 goto not_complete; 950 951 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 952 goto not_complete; 953 954 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 955 GRXSTSRD_STP_DATA) { 956 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 957 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 958 /* release FIFO */ 959 dwc_otg_common_rx_ack(sc); 960 goto not_complete; 961 } 962 /* release FIFO */ 963 dwc_otg_common_rx_ack(sc); 964 return (0); /* complete */ 965 } 966 967 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 968 GRXSTSRD_DPID_DATA0) { 969 /* release FIFO */ 970 dwc_otg_common_rx_ack(sc); 971 goto not_complete; 972 } 973 974 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 975 976 /* clear did stall */ 977 td->did_stall = 0; 978 979 /* get the packet byte count */ 980 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 981 982 if (count != sizeof(req)) { 983 DPRINTFN(0, "Unsupported SETUP packet " 984 "length, %d bytes\n", count); 985 /* release FIFO */ 986 dwc_otg_common_rx_ack(sc); 987 goto not_complete; 988 } 989 990 /* copy in control request */ 991 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 992 993 /* copy data into real buffer */ 994 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 995 996 td->offset = sizeof(req); 997 td->remainder = 0; 998 999 /* sneak peek the set address */ 1000 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1001 (req.bRequest == UR_SET_ADDRESS)) { 1002 /* must write address before ZLP */ 1003 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1004 } 1005 1006 /* don't send any data by default */ 1007 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1008 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1009 1010 /* reset IN endpoint buffer */ 1011 dwc_otg_tx_fifo_reset(sc, 1012 GRSTCTL_TXFIFO(0) | 1013 GRSTCTL_TXFFLSH); 1014 1015 /* acknowledge RX status */ 1016 dwc_otg_common_rx_ack(sc); 1017 td->did_stall = 1; 1018 1019 not_complete: 1020 /* abort any ongoing transfer, before enabling again */ 1021 if (!td->did_stall) { 1022 td->did_stall = 1; 1023 1024 DPRINTFN(5, "stalling IN and OUT direction\n"); 1025 1026 temp = sc->sc_out_ctl[0]; 1027 1028 /* set stall after enabling endpoint */ 1029 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1030 temp | DOEPCTL_STALL); 1031 1032 temp = sc->sc_in_ctl[0]; 1033 1034 /* set stall assuming endpoint is enabled */ 1035 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1036 temp | DIEPCTL_STALL); 1037 } 1038 return (1); /* not complete */ 1039 } 1040 1041 static uint8_t 1042 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1043 { 1044 uint8_t delta; 1045 1046 delta = sc->sc_tmr_val - td->tmr_val; 1047 if (delta >= 128) 1048 return (1); /* busy */ 1049 1050 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1051 1052 /* set toggle, if any */ 1053 if (td->set_toggle) { 1054 td->set_toggle = 0; 1055 td->toggle = 1; 1056 } 1057 return (0); 1058 } 1059 1060 static uint8_t 1061 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1062 { 1063 if (td->ep_type == UE_ISOCHRONOUS) { 1064 /* non TT isochronous traffic */ 1065 if ((td->tmr_val != 0) || 1066 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1067 goto busy; 1068 } 1069 td->tmr_val = 1; /* executed */ 1070 td->toggle = 0; 1071 1072 } else if (td->ep_type == UE_INTERRUPT) { 1073 if (!td->tt_scheduled) 1074 goto busy; 1075 td->tt_scheduled = 0; 1076 } else if (td->did_nak != 0) { 1077 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1078 /* check if we should pause sending queries for 125us */ 1079 if (td->tmr_res == frame_num) { 1080 /* wait a bit */ 1081 dwc_otg_enable_sof_irq(sc); 1082 goto busy; 1083 } 1084 /* query for data one more time */ 1085 td->tmr_res = frame_num; 1086 td->did_nak = 0; 1087 } else if (td->set_toggle) { 1088 td->set_toggle = 0; 1089 td->toggle = 1; 1090 } 1091 return (0); 1092 busy: 1093 return (1); 1094 } 1095 1096 static uint8_t 1097 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1098 { 1099 uint32_t count; 1100 uint8_t channel; 1101 1102 /* check endpoint status */ 1103 if (sc->sc_last_rx_status == 0) 1104 goto busy; 1105 1106 channel = td->channel; 1107 if (channel >= DWC_OTG_MAX_CHANNELS) 1108 goto busy; 1109 1110 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1111 goto busy; 1112 1113 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1114 case GRXSTSRH_IN_DATA: 1115 1116 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1117 (int)td->state, (int)sc->sc_last_rx_status); 1118 1119 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1120 /* 1121 * When using SPLIT transactions on interrupt 1122 * endpoints, sometimes data occurs twice. 1123 */ 1124 DPRINTF("Data already received\n"); 1125 break; 1126 } 1127 1128 /* get the packet byte count */ 1129 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1130 1131 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1132 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1133 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1134 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1135 } else { 1136 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1137 1138 /* verify the packet byte count */ 1139 if (count < td->max_packet_size) { 1140 /* we have a short packet */ 1141 td->short_pkt = 1; 1142 td->got_short = 1; 1143 } 1144 } 1145 td->toggle = 0; 1146 } else { 1147 /* verify the packet byte count */ 1148 if (count != td->max_packet_size) { 1149 if (count < td->max_packet_size) { 1150 /* we have a short packet */ 1151 td->short_pkt = 1; 1152 td->got_short = 1; 1153 } else { 1154 /* invalid USB packet */ 1155 td->error_any = 1; 1156 1157 /* release FIFO */ 1158 dwc_otg_common_rx_ack(sc); 1159 goto complete; 1160 } 1161 } 1162 td->toggle ^= 1; 1163 td->tt_scheduled = 0; 1164 } 1165 1166 /* verify the packet byte count */ 1167 if (count > td->remainder) { 1168 /* invalid USB packet */ 1169 td->error_any = 1; 1170 1171 /* release FIFO */ 1172 dwc_otg_common_rx_ack(sc); 1173 goto complete; 1174 } 1175 1176 usbd_copy_in(td->pc, td->offset, 1177 sc->sc_rx_bounce_buffer, count); 1178 1179 td->remainder -= count; 1180 td->offset += count; 1181 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1182 break; 1183 default: 1184 break; 1185 } 1186 /* release FIFO */ 1187 dwc_otg_common_rx_ack(sc); 1188 busy: 1189 return (0); 1190 complete: 1191 return (1); 1192 } 1193 1194 static uint8_t 1195 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1196 { 1197 uint32_t hcint; 1198 uint32_t hcchar; 1199 uint8_t delta; 1200 uint8_t channel; 1201 1202 channel = td->channel; 1203 1204 if (channel < DWC_OTG_MAX_CHANNELS) { 1205 hcint = sc->sc_chan_state[channel].hcint; 1206 1207 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1208 channel, td->state, hcint, 1209 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1210 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1211 1212 /* check interrupt bits */ 1213 if (hcint & (HCINT_RETRY | 1214 HCINT_ACK | HCINT_NYET)) { 1215 /* give success bits priority over failure bits */ 1216 } else if (hcint & HCINT_STALL) { 1217 DPRINTF("CH=%d STALL\n", channel); 1218 td->error_stall = 1; 1219 td->error_any = 1; 1220 goto complete; 1221 } else if (hcint & HCINT_ERRORS) { 1222 DPRINTF("CH=%d ERROR\n", channel); 1223 td->errcnt++; 1224 if (td->hcsplt != 0 || td->errcnt >= 3) { 1225 if (td->ep_type != UE_ISOCHRONOUS) { 1226 td->error_any = 1; 1227 goto complete; 1228 } 1229 } 1230 } 1231 1232 /* check channels for data, if any */ 1233 if (dwc_otg_host_data_rx_sub(sc, td)) 1234 goto complete; 1235 1236 /* refresh interrupt status */ 1237 hcint = sc->sc_chan_state[channel].hcint; 1238 1239 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1240 HCINT_ACK | HCINT_NYET)) { 1241 if (!(hcint & HCINT_ERRORS)) 1242 td->errcnt = 0; 1243 } 1244 } else { 1245 hcint = 0; 1246 } 1247 1248 switch (td->state) { 1249 case DWC_CHAN_ST_START: 1250 if (td->hcsplt != 0) 1251 goto receive_spkt; 1252 else 1253 goto receive_pkt; 1254 1255 case DWC_CHAN_ST_WAIT_ANE: 1256 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1257 if (td->ep_type == UE_INTERRUPT) { 1258 /* 1259 * The USB specification does not 1260 * mandate a particular data toggle 1261 * value for USB INTERRUPT 1262 * transfers. Switch the data toggle 1263 * value to receive the packet 1264 * correctly: 1265 */ 1266 if (hcint & HCINT_DATATGLERR) { 1267 DPRINTF("Retrying packet due to " 1268 "data toggle error\n"); 1269 td->toggle ^= 1; 1270 goto receive_pkt; 1271 } 1272 } 1273 td->did_nak = 1; 1274 td->tt_scheduled = 0; 1275 if (td->hcsplt != 0) 1276 goto receive_spkt; 1277 else 1278 goto receive_pkt; 1279 } else if (hcint & HCINT_NYET) { 1280 if (td->hcsplt != 0) { 1281 /* try again */ 1282 goto receive_pkt; 1283 } else { 1284 /* not a valid token for IN endpoints */ 1285 td->error_any = 1; 1286 goto complete; 1287 } 1288 } else if (hcint & HCINT_ACK) { 1289 /* wait for data - ACK arrived first */ 1290 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1291 goto busy; 1292 1293 if (td->ep_type == UE_ISOCHRONOUS) { 1294 /* check if we are complete */ 1295 if ((td->remainder == 0) || 1296 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1297 goto complete; 1298 } 1299 /* get another packet */ 1300 goto receive_pkt; 1301 } else { 1302 /* check if we are complete */ 1303 if ((td->remainder == 0) || (td->got_short != 0)) { 1304 if (td->short_pkt) 1305 goto complete; 1306 1307 /* 1308 * Else need to receive a zero length 1309 * packet. 1310 */ 1311 } 1312 td->tt_scheduled = 0; 1313 td->did_nak = 0; 1314 if (td->hcsplt != 0) 1315 goto receive_spkt; 1316 else 1317 goto receive_pkt; 1318 } 1319 } 1320 break; 1321 1322 case DWC_CHAN_ST_WAIT_S_ANE: 1323 /* 1324 * NOTE: The DWC OTG hardware provides a fake ACK in 1325 * case of interrupt and isochronous transfers: 1326 */ 1327 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1328 td->did_nak = 1; 1329 td->tt_scheduled = 0; 1330 goto receive_spkt; 1331 } else if (hcint & HCINT_NYET) { 1332 td->tt_scheduled = 0; 1333 goto receive_spkt; 1334 } else if (hcint & HCINT_ACK) { 1335 td->did_nak = 0; 1336 goto receive_pkt; 1337 } 1338 break; 1339 1340 case DWC_CHAN_ST_WAIT_C_PKT: 1341 goto receive_pkt; 1342 1343 default: 1344 break; 1345 } 1346 goto busy; 1347 1348 receive_pkt: 1349 /* free existing channel, if any */ 1350 dwc_otg_host_channel_free(sc, td); 1351 1352 if (td->hcsplt != 0) { 1353 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1354 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1355 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1356 goto busy; 1357 } 1358 delta = sc->sc_last_frame_num - td->tt_start_slot; 1359 if (delta > DWC_OTG_TT_SLOT_MAX) { 1360 if (td->ep_type != UE_ISOCHRONOUS) { 1361 /* we missed the service interval */ 1362 td->error_any = 1; 1363 } 1364 goto complete; 1365 } 1366 /* complete split */ 1367 td->hcsplt |= HCSPLT_COMPSPLT; 1368 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1369 dwc_otg_host_rate_check(sc, td)) { 1370 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1371 goto busy; 1372 } 1373 1374 /* allocate a new channel */ 1375 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1376 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1377 goto busy; 1378 } 1379 1380 channel = td->channel; 1381 1382 /* set toggle, if any */ 1383 if (td->set_toggle) { 1384 td->set_toggle = 0; 1385 td->toggle = 1; 1386 } 1387 1388 td->state = DWC_CHAN_ST_WAIT_ANE; 1389 1390 /* receive one packet */ 1391 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1392 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1393 (1 << HCTSIZ_PKTCNT_SHIFT) | 1394 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1395 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1396 1397 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1398 1399 hcchar = td->hcchar; 1400 hcchar |= HCCHAR_EPDIR_IN; 1401 1402 /* receive complete split ASAP */ 1403 if ((sc->sc_last_frame_num & 1) != 0 && 1404 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1405 hcchar |= HCCHAR_ODDFRM; 1406 else 1407 hcchar &= ~HCCHAR_ODDFRM; 1408 1409 /* must enable channel before data can be received */ 1410 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1411 1412 /* wait until next slot before trying complete split */ 1413 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1414 1415 goto busy; 1416 1417 receive_spkt: 1418 /* free existing channel(s), if any */ 1419 dwc_otg_host_channel_free(sc, td); 1420 1421 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1422 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1423 td->state = DWC_CHAN_ST_START; 1424 goto busy; 1425 } 1426 delta = sc->sc_last_frame_num - td->tt_start_slot; 1427 if (delta > 5) { 1428 /* missed it */ 1429 td->tt_scheduled = 0; 1430 td->state = DWC_CHAN_ST_START; 1431 goto busy; 1432 } 1433 1434 /* allocate a new channel */ 1435 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1436 td->state = DWC_CHAN_ST_START; 1437 goto busy; 1438 } 1439 1440 channel = td->channel; 1441 1442 td->hcsplt &= ~HCSPLT_COMPSPLT; 1443 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1444 1445 /* receive one packet */ 1446 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1447 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1448 1449 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1450 1451 /* send after next SOF event */ 1452 if ((sc->sc_last_frame_num & 1) == 0 && 1453 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1454 td->hcchar |= HCCHAR_ODDFRM; 1455 else 1456 td->hcchar &= ~HCCHAR_ODDFRM; 1457 1458 hcchar = td->hcchar; 1459 hcchar |= HCCHAR_EPDIR_IN; 1460 1461 /* wait until next slot before trying complete split */ 1462 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1463 1464 /* must enable channel before data can be received */ 1465 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1466 busy: 1467 return (1); /* busy */ 1468 1469 complete: 1470 dwc_otg_host_channel_free(sc, td); 1471 return (0); /* complete */ 1472 } 1473 1474 static uint8_t 1475 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1476 { 1477 uint32_t temp; 1478 uint16_t count; 1479 uint8_t got_short; 1480 1481 got_short = 0; 1482 1483 /* check endpoint status */ 1484 if (sc->sc_last_rx_status == 0) 1485 goto not_complete; 1486 1487 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1488 goto not_complete; 1489 1490 /* check for SETUP packet */ 1491 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1492 GRXSTSRD_STP_DATA || 1493 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1494 GRXSTSRD_STP_COMPLETE) { 1495 if (td->remainder == 0) { 1496 /* 1497 * We are actually complete and have 1498 * received the next SETUP 1499 */ 1500 DPRINTFN(5, "faking complete\n"); 1501 return (0); /* complete */ 1502 } 1503 /* 1504 * USB Host Aborted the transfer. 1505 */ 1506 td->error_any = 1; 1507 return (0); /* complete */ 1508 } 1509 1510 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1511 GRXSTSRD_OUT_DATA) { 1512 /* release FIFO */ 1513 dwc_otg_common_rx_ack(sc); 1514 goto not_complete; 1515 } 1516 1517 /* get the packet byte count */ 1518 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1519 1520 /* verify the packet byte count */ 1521 if (count != td->max_packet_size) { 1522 if (count < td->max_packet_size) { 1523 /* we have a short packet */ 1524 td->short_pkt = 1; 1525 got_short = 1; 1526 } else { 1527 /* invalid USB packet */ 1528 td->error_any = 1; 1529 1530 /* release FIFO */ 1531 dwc_otg_common_rx_ack(sc); 1532 return (0); /* we are complete */ 1533 } 1534 } 1535 /* verify the packet byte count */ 1536 if (count > td->remainder) { 1537 /* invalid USB packet */ 1538 td->error_any = 1; 1539 1540 /* release FIFO */ 1541 dwc_otg_common_rx_ack(sc); 1542 return (0); /* we are complete */ 1543 } 1544 1545 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1546 td->remainder -= count; 1547 td->offset += count; 1548 1549 /* release FIFO */ 1550 dwc_otg_common_rx_ack(sc); 1551 1552 temp = sc->sc_out_ctl[td->ep_no]; 1553 1554 /* check for isochronous mode */ 1555 if ((temp & DIEPCTL_EPTYPE_MASK) == 1556 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1557 /* toggle odd or even frame bit */ 1558 if (temp & DIEPCTL_SETD1PID) { 1559 temp &= ~DIEPCTL_SETD1PID; 1560 temp |= DIEPCTL_SETD0PID; 1561 } else { 1562 temp &= ~DIEPCTL_SETD0PID; 1563 temp |= DIEPCTL_SETD1PID; 1564 } 1565 sc->sc_out_ctl[td->ep_no] = temp; 1566 } 1567 1568 /* check if we are complete */ 1569 if ((td->remainder == 0) || got_short) { 1570 if (td->short_pkt) { 1571 /* we are complete */ 1572 return (0); 1573 } 1574 /* else need to receive a zero length packet */ 1575 } 1576 1577 not_complete: 1578 1579 /* enable SETUP and transfer complete interrupt */ 1580 if (td->ep_no == 0) { 1581 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1582 DXEPTSIZ_SET_MULTI(3) | 1583 DXEPTSIZ_SET_NPKT(1) | 1584 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1585 } else { 1586 /* allow reception of multiple packets */ 1587 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1588 DXEPTSIZ_SET_MULTI(1) | 1589 DXEPTSIZ_SET_NPKT(4) | 1590 DXEPTSIZ_SET_NBYTES(4 * 1591 ((td->max_packet_size + 3) & ~3))); 1592 } 1593 temp = sc->sc_out_ctl[td->ep_no]; 1594 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1595 DOEPCTL_EPENA | DOEPCTL_CNAK); 1596 1597 return (1); /* not complete */ 1598 } 1599 1600 static uint8_t 1601 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1602 { 1603 uint32_t count; 1604 uint32_t hcint; 1605 uint32_t hcchar; 1606 uint8_t delta; 1607 uint8_t channel; 1608 1609 dwc_otg_host_dump_rx(sc, td); 1610 1611 channel = td->channel; 1612 1613 if (channel < DWC_OTG_MAX_CHANNELS) { 1614 hcint = sc->sc_chan_state[channel].hcint; 1615 1616 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1617 channel, td->state, hcint, 1618 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1619 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1620 1621 if (hcint & (HCINT_RETRY | 1622 HCINT_ACK | HCINT_NYET)) { 1623 /* give success bits priority over failure bits */ 1624 } else if (hcint & HCINT_STALL) { 1625 DPRINTF("CH=%d STALL\n", channel); 1626 td->error_stall = 1; 1627 td->error_any = 1; 1628 goto complete; 1629 } else if (hcint & HCINT_ERRORS) { 1630 DPRINTF("CH=%d ERROR\n", channel); 1631 td->errcnt++; 1632 if (td->hcsplt != 0 || td->errcnt >= 3) { 1633 td->error_any = 1; 1634 goto complete; 1635 } 1636 } 1637 1638 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1639 HCINT_ACK | HCINT_NYET)) { 1640 1641 if (!(hcint & HCINT_ERRORS)) 1642 td->errcnt = 0; 1643 } 1644 } else { 1645 hcint = 0; 1646 } 1647 1648 switch (td->state) { 1649 case DWC_CHAN_ST_START: 1650 goto send_pkt; 1651 1652 case DWC_CHAN_ST_WAIT_ANE: 1653 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1654 td->did_nak = 1; 1655 td->tt_scheduled = 0; 1656 goto send_pkt; 1657 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1658 td->offset += td->tx_bytes; 1659 td->remainder -= td->tx_bytes; 1660 td->toggle ^= 1; 1661 td->did_nak = 0; 1662 td->tt_scheduled = 0; 1663 1664 /* check remainder */ 1665 if (td->remainder == 0) { 1666 if (td->short_pkt) 1667 goto complete; 1668 1669 /* 1670 * Else we need to transmit a short 1671 * packet: 1672 */ 1673 } 1674 goto send_pkt; 1675 } 1676 break; 1677 1678 case DWC_CHAN_ST_WAIT_S_ANE: 1679 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1680 td->did_nak = 1; 1681 td->tt_scheduled = 0; 1682 goto send_pkt; 1683 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1684 td->did_nak = 0; 1685 goto send_cpkt; 1686 } 1687 break; 1688 1689 case DWC_CHAN_ST_WAIT_C_ANE: 1690 if (hcint & HCINT_NYET) { 1691 goto send_cpkt; 1692 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1693 td->did_nak = 1; 1694 td->tt_scheduled = 0; 1695 goto send_pkt; 1696 } else if (hcint & HCINT_ACK) { 1697 td->offset += td->tx_bytes; 1698 td->remainder -= td->tx_bytes; 1699 td->toggle ^= 1; 1700 td->did_nak = 0; 1701 td->tt_scheduled = 0; 1702 1703 /* check remainder */ 1704 if (td->remainder == 0) { 1705 if (td->short_pkt) 1706 goto complete; 1707 1708 /* else we need to transmit a short packet */ 1709 } 1710 goto send_pkt; 1711 } 1712 break; 1713 1714 case DWC_CHAN_ST_WAIT_C_PKT: 1715 goto send_cpkt; 1716 1717 case DWC_CHAN_ST_TX_WAIT_ISOC: 1718 1719 /* Check if isochronous OUT traffic is complete */ 1720 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1721 break; 1722 1723 td->offset += td->tx_bytes; 1724 td->remainder -= td->tx_bytes; 1725 1726 if (td->hcsplt != 0 || td->remainder == 0) 1727 goto complete; 1728 1729 /* check for next packet */ 1730 if (td->max_packet_count > 1) 1731 td->tt_xactpos++; 1732 1733 /* free existing channel, if any */ 1734 dwc_otg_host_channel_free(sc, td); 1735 1736 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1737 1738 /* FALLTHROUGH */ 1739 1740 case DWC_CHAN_ST_TX_PKT_ISOC: 1741 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1742 break; 1743 channel = td->channel; 1744 goto send_isoc_pkt; 1745 default: 1746 break; 1747 } 1748 goto busy; 1749 1750 send_pkt: 1751 /* free existing channel(s), if any */ 1752 dwc_otg_host_channel_free(sc, td); 1753 1754 if (td->hcsplt != 0) { 1755 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1756 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1757 td->state = DWC_CHAN_ST_START; 1758 goto busy; 1759 } 1760 delta = sc->sc_last_frame_num - td->tt_start_slot; 1761 if (delta > 5) { 1762 /* missed it */ 1763 td->tt_scheduled = 0; 1764 td->state = DWC_CHAN_ST_START; 1765 goto busy; 1766 } 1767 } else if (dwc_otg_host_rate_check(sc, td)) { 1768 td->state = DWC_CHAN_ST_START; 1769 goto busy; 1770 } 1771 1772 /* allocate a new channel */ 1773 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1774 td->state = DWC_CHAN_ST_START; 1775 goto busy; 1776 } 1777 1778 channel = td->channel; 1779 1780 /* set toggle, if any */ 1781 if (td->set_toggle) { 1782 td->set_toggle = 0; 1783 td->toggle = 1; 1784 } 1785 1786 if (td->ep_type == UE_ISOCHRONOUS) { 1787 send_isoc_pkt: 1788 /* Isochronous OUT transfers don't have any ACKs */ 1789 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1790 td->hcsplt &= ~HCSPLT_COMPSPLT; 1791 if (td->hcsplt != 0) { 1792 /* get maximum transfer length */ 1793 count = td->remainder; 1794 if (count > HCSPLT_XACTLEN_BURST) { 1795 DPRINTF("TT overflow\n"); 1796 td->error_any = 1; 1797 goto complete; 1798 } 1799 /* Update transaction position */ 1800 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1801 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1802 } else { 1803 /* send one packet at a time */ 1804 count = td->max_packet_size; 1805 if (td->remainder < count) { 1806 /* we have a short packet */ 1807 td->short_pkt = 1; 1808 count = td->remainder; 1809 } 1810 } 1811 } else if (td->hcsplt != 0) { 1812 1813 td->hcsplt &= ~HCSPLT_COMPSPLT; 1814 1815 /* Wait for ACK/NAK/ERR from TT */ 1816 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1817 1818 /* send one packet at a time */ 1819 count = td->max_packet_size; 1820 if (td->remainder < count) { 1821 /* we have a short packet */ 1822 td->short_pkt = 1; 1823 count = td->remainder; 1824 } 1825 } else { 1826 /* Wait for ACK/NAK/STALL from device */ 1827 td->state = DWC_CHAN_ST_WAIT_ANE; 1828 1829 /* send one packet at a time */ 1830 count = td->max_packet_size; 1831 if (td->remainder < count) { 1832 /* we have a short packet */ 1833 td->short_pkt = 1; 1834 count = td->remainder; 1835 } 1836 } 1837 1838 /* check for High-Speed multi-packets */ 1839 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1840 if (td->npkt == 0) { 1841 if (td->remainder >= (3 * td->max_packet_size)) 1842 td->npkt = 3; 1843 else if (td->remainder >= (2 * td->max_packet_size)) 1844 td->npkt = 2; 1845 else 1846 td->npkt = 1; 1847 1848 if (td->npkt > td->max_packet_count) 1849 td->npkt = td->max_packet_count; 1850 1851 td->tt_xactpos = 1; /* overload */ 1852 } 1853 if (td->tt_xactpos == td->npkt) { 1854 if (td->npkt == 1) { 1855 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1856 (count << HCTSIZ_XFERSIZE_SHIFT) | 1857 (1 << HCTSIZ_PKTCNT_SHIFT) | 1858 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1859 } else if (td->npkt == 2) { 1860 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1861 (count << HCTSIZ_XFERSIZE_SHIFT) | 1862 (1 << HCTSIZ_PKTCNT_SHIFT) | 1863 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1864 } else { 1865 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1866 (count << HCTSIZ_XFERSIZE_SHIFT) | 1867 (1 << HCTSIZ_PKTCNT_SHIFT) | 1868 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1869 } 1870 td->npkt = 0; 1871 } else { 1872 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1873 (count << HCTSIZ_XFERSIZE_SHIFT) | 1874 (1 << HCTSIZ_PKTCNT_SHIFT) | 1875 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1876 } 1877 } else { 1878 /* TODO: HCTSIZ_DOPNG */ 1879 1880 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1881 (count << HCTSIZ_XFERSIZE_SHIFT) | 1882 (1 << HCTSIZ_PKTCNT_SHIFT) | 1883 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1884 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1885 } 1886 1887 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1888 1889 hcchar = td->hcchar; 1890 hcchar &= ~HCCHAR_EPDIR_IN; 1891 1892 /* send after next SOF event */ 1893 if ((sc->sc_last_frame_num & 1) == 0 && 1894 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1895 hcchar |= HCCHAR_ODDFRM; 1896 else 1897 hcchar &= ~HCCHAR_ODDFRM; 1898 1899 /* must enable before writing data to FIFO */ 1900 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1901 1902 if (count != 0) { 1903 1904 /* clear topmost word before copy */ 1905 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1906 1907 /* copy out data */ 1908 usbd_copy_out(td->pc, td->offset, 1909 sc->sc_tx_bounce_buffer, count); 1910 1911 /* transfer data into FIFO */ 1912 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1913 DOTG_DFIFO(channel), 1914 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1915 } 1916 1917 /* store number of bytes transmitted */ 1918 td->tx_bytes = count; 1919 goto busy; 1920 1921 send_cpkt: 1922 /* free existing channel, if any */ 1923 dwc_otg_host_channel_free(sc, td); 1924 1925 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1926 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1927 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1928 goto busy; 1929 } 1930 delta = sc->sc_last_frame_num - td->tt_start_slot; 1931 if (delta > DWC_OTG_TT_SLOT_MAX) { 1932 /* we missed the service interval */ 1933 if (td->ep_type != UE_ISOCHRONOUS) 1934 td->error_any = 1; 1935 goto complete; 1936 } 1937 1938 /* allocate a new channel */ 1939 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1940 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1941 goto busy; 1942 } 1943 1944 channel = td->channel; 1945 1946 td->hcsplt |= HCSPLT_COMPSPLT; 1947 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1948 1949 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1950 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1951 1952 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1953 1954 hcchar = td->hcchar; 1955 hcchar &= ~HCCHAR_EPDIR_IN; 1956 1957 /* receive complete split ASAP */ 1958 if ((sc->sc_last_frame_num & 1) != 0 && 1959 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1960 hcchar |= HCCHAR_ODDFRM; 1961 else 1962 hcchar &= ~HCCHAR_ODDFRM; 1963 1964 /* must enable channel before data can be received */ 1965 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1966 1967 /* wait until next slot before trying complete split */ 1968 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1969 busy: 1970 return (1); /* busy */ 1971 1972 complete: 1973 dwc_otg_host_channel_free(sc, td); 1974 return (0); /* complete */ 1975 } 1976 1977 static uint8_t 1978 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1979 { 1980 uint32_t max_buffer; 1981 uint32_t count; 1982 uint32_t fifo_left; 1983 uint32_t mpkt; 1984 uint32_t temp; 1985 uint8_t to; 1986 1987 to = 3; /* don't loop forever! */ 1988 1989 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1990 1991 repeat: 1992 /* check for for endpoint 0 data */ 1993 1994 temp = sc->sc_last_rx_status; 1995 1996 if ((td->ep_no == 0) && (temp != 0) && 1997 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1998 1999 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2000 GRXSTSRD_STP_DATA && 2001 (temp & GRXSTSRD_PKTSTS_MASK) != 2002 GRXSTSRD_STP_COMPLETE) { 2003 2004 /* dump data - wrong direction */ 2005 dwc_otg_common_rx_ack(sc); 2006 } else { 2007 /* 2008 * The current transfer was cancelled 2009 * by the USB Host: 2010 */ 2011 td->error_any = 1; 2012 return (0); /* complete */ 2013 } 2014 } 2015 2016 /* fill in more TX data, if possible */ 2017 if (td->tx_bytes != 0) { 2018 2019 uint16_t cpkt; 2020 2021 /* check if packets have been transferred */ 2022 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2023 2024 /* get current packet number */ 2025 cpkt = DXEPTSIZ_GET_NPKT(temp); 2026 2027 if (cpkt >= td->npkt) { 2028 fifo_left = 0; 2029 } else { 2030 if (max_buffer != 0) { 2031 fifo_left = (td->npkt - cpkt) * 2032 td->max_packet_size; 2033 2034 if (fifo_left > max_buffer) 2035 fifo_left = max_buffer; 2036 } else { 2037 fifo_left = td->max_packet_size; 2038 } 2039 } 2040 2041 count = td->tx_bytes; 2042 if (count > fifo_left) 2043 count = fifo_left; 2044 2045 if (count != 0) { 2046 2047 /* clear topmost word before copy */ 2048 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2049 2050 /* copy out data */ 2051 usbd_copy_out(td->pc, td->offset, 2052 sc->sc_tx_bounce_buffer, count); 2053 2054 /* transfer data into FIFO */ 2055 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2056 DOTG_DFIFO(td->ep_no), 2057 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2058 2059 td->tx_bytes -= count; 2060 td->remainder -= count; 2061 td->offset += count; 2062 td->npkt = cpkt; 2063 } 2064 if (td->tx_bytes != 0) 2065 goto not_complete; 2066 2067 /* check remainder */ 2068 if (td->remainder == 0) { 2069 if (td->short_pkt) 2070 return (0); /* complete */ 2071 2072 /* else we need to transmit a short packet */ 2073 } 2074 } 2075 2076 if (!to--) 2077 goto not_complete; 2078 2079 /* check if not all packets have been transferred */ 2080 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2081 2082 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2083 2084 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2085 "DIEPCTL=0x%08x\n", td->ep_no, 2086 DXEPTSIZ_GET_NPKT(temp), 2087 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2088 2089 goto not_complete; 2090 } 2091 2092 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2093 2094 /* try to optimise by sending more data */ 2095 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2096 2097 /* send multiple packets at the same time */ 2098 mpkt = max_buffer / td->max_packet_size; 2099 2100 if (mpkt > 0x3FE) 2101 mpkt = 0x3FE; 2102 2103 count = td->remainder; 2104 if (count > 0x7FFFFF) 2105 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2106 2107 td->npkt = count / td->max_packet_size; 2108 2109 /* 2110 * NOTE: We could use 0x3FE instead of "mpkt" in the 2111 * check below to get more throughput, but then we 2112 * have a dependency towards non-generic chip features 2113 * to disable the TX-FIFO-EMPTY interrupts on a per 2114 * endpoint basis. Increase the maximum buffer size of 2115 * the IN endpoint to increase the performance. 2116 */ 2117 if (td->npkt > mpkt) { 2118 td->npkt = mpkt; 2119 count = td->max_packet_size * mpkt; 2120 } else if ((count == 0) || (count % td->max_packet_size)) { 2121 /* we are transmitting a short packet */ 2122 td->npkt++; 2123 td->short_pkt = 1; 2124 } 2125 } else { 2126 /* send one packet at a time */ 2127 mpkt = 1; 2128 count = td->max_packet_size; 2129 if (td->remainder < count) { 2130 /* we have a short packet */ 2131 td->short_pkt = 1; 2132 count = td->remainder; 2133 } 2134 td->npkt = 1; 2135 } 2136 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2137 DXEPTSIZ_SET_MULTI(1) | 2138 DXEPTSIZ_SET_NPKT(td->npkt) | 2139 DXEPTSIZ_SET_NBYTES(count)); 2140 2141 /* make room for buffering */ 2142 td->npkt += mpkt; 2143 2144 temp = sc->sc_in_ctl[td->ep_no]; 2145 2146 /* check for isochronous mode */ 2147 if ((temp & DIEPCTL_EPTYPE_MASK) == 2148 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2149 /* toggle odd or even frame bit */ 2150 if (temp & DIEPCTL_SETD1PID) { 2151 temp &= ~DIEPCTL_SETD1PID; 2152 temp |= DIEPCTL_SETD0PID; 2153 } else { 2154 temp &= ~DIEPCTL_SETD0PID; 2155 temp |= DIEPCTL_SETD1PID; 2156 } 2157 sc->sc_in_ctl[td->ep_no] = temp; 2158 } 2159 2160 /* must enable before writing data to FIFO */ 2161 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2162 DIEPCTL_EPENA | DIEPCTL_CNAK); 2163 2164 td->tx_bytes = count; 2165 2166 /* check remainder */ 2167 if (td->tx_bytes == 0 && 2168 td->remainder == 0) { 2169 if (td->short_pkt) 2170 return (0); /* complete */ 2171 2172 /* else we need to transmit a short packet */ 2173 } 2174 goto repeat; 2175 2176 not_complete: 2177 return (1); /* not complete */ 2178 } 2179 2180 static uint8_t 2181 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2182 { 2183 uint32_t temp; 2184 2185 /* 2186 * If all packets are transferred we are complete: 2187 */ 2188 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2189 2190 /* check that all packets have been transferred */ 2191 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2192 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2193 goto not_complete; 2194 } 2195 return (0); 2196 2197 not_complete: 2198 2199 /* we only want to know if there is a SETUP packet or free IN packet */ 2200 2201 temp = sc->sc_last_rx_status; 2202 2203 if ((td->ep_no == 0) && (temp != 0) && 2204 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2205 2206 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2207 GRXSTSRD_STP_DATA || 2208 (temp & GRXSTSRD_PKTSTS_MASK) == 2209 GRXSTSRD_STP_COMPLETE) { 2210 DPRINTFN(5, "faking complete\n"); 2211 /* 2212 * Race condition: We are complete! 2213 */ 2214 return (0); 2215 } else { 2216 /* dump data - wrong direction */ 2217 dwc_otg_common_rx_ack(sc); 2218 } 2219 } 2220 return (1); /* not complete */ 2221 } 2222 2223 static void 2224 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2225 { 2226 struct dwc_otg_td *td; 2227 uint8_t toggle; 2228 uint8_t tmr_val; 2229 uint8_t tmr_res; 2230 2231 DPRINTFN(9, "\n"); 2232 2233 td = xfer->td_transfer_cache; 2234 if (td == NULL) 2235 return; 2236 2237 while (1) { 2238 if ((td->func) (sc, td)) { 2239 /* operation in progress */ 2240 break; 2241 } 2242 if (((void *)td) == xfer->td_transfer_last) { 2243 goto done; 2244 } 2245 if (td->error_any) { 2246 goto done; 2247 } else if (td->remainder > 0) { 2248 /* 2249 * We had a short transfer. If there is no alternate 2250 * next, stop processing ! 2251 */ 2252 if (!td->alt_next) 2253 goto done; 2254 } 2255 2256 /* 2257 * Fetch the next transfer descriptor and transfer 2258 * some flags to the next transfer descriptor 2259 */ 2260 tmr_res = td->tmr_res; 2261 tmr_val = td->tmr_val; 2262 toggle = td->toggle; 2263 td = td->obj_next; 2264 xfer->td_transfer_cache = td; 2265 td->toggle = toggle; /* transfer toggle */ 2266 td->tmr_res = tmr_res; 2267 td->tmr_val = tmr_val; 2268 } 2269 return; 2270 2271 done: 2272 xfer->td_transfer_cache = NULL; 2273 sc->sc_xfer_complete = 1; 2274 } 2275 2276 static uint8_t 2277 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2278 { 2279 struct dwc_otg_td *td; 2280 2281 DPRINTFN(9, "\n"); 2282 2283 td = xfer->td_transfer_cache; 2284 if (td == NULL) { 2285 /* compute all actual lengths */ 2286 dwc_otg_standard_done(xfer); 2287 return (1); 2288 } 2289 return (0); 2290 } 2291 2292 static void 2293 dwc_otg_timer(void *_sc) 2294 { 2295 struct dwc_otg_softc *sc = _sc; 2296 2297 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2298 2299 DPRINTF("\n"); 2300 2301 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2302 2303 /* increment timer value */ 2304 sc->sc_tmr_val++; 2305 2306 /* enable SOF interrupt, which will poll jobs */ 2307 dwc_otg_enable_sof_irq(sc); 2308 2309 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2310 2311 if (sc->sc_timer_active) { 2312 /* restart timer */ 2313 usb_callout_reset(&sc->sc_timer, 2314 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2315 &dwc_otg_timer, sc); 2316 } 2317 } 2318 2319 static void 2320 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2321 { 2322 if (sc->sc_timer_active != 0) 2323 return; 2324 2325 sc->sc_timer_active = 1; 2326 2327 /* restart timer */ 2328 usb_callout_reset(&sc->sc_timer, 2329 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2330 &dwc_otg_timer, sc); 2331 } 2332 2333 static void 2334 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2335 { 2336 if (sc->sc_timer_active == 0) 2337 return; 2338 2339 sc->sc_timer_active = 0; 2340 2341 /* stop timer */ 2342 usb_callout_stop(&sc->sc_timer); 2343 } 2344 2345 static uint16_t 2346 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2347 { 2348 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2349 pinfo->slot_index++; 2350 return (pinfo->slot_index); 2351 } 2352 2353 static uint8_t 2354 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2355 { 2356 TAILQ_HEAD(, usb_xfer) head; 2357 struct usb_xfer *xfer; 2358 struct usb_xfer *xfer_next; 2359 struct dwc_otg_td *td; 2360 uint16_t temp; 2361 uint16_t slot; 2362 2363 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2364 2365 if (sc->sc_last_frame_num == temp) 2366 return (0); 2367 2368 sc->sc_last_frame_num = temp; 2369 2370 TAILQ_INIT(&head); 2371 2372 if ((temp & 7) == 0) { 2373 2374 /* reset the schedule */ 2375 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2376 2377 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2378 td = xfer->td_transfer_cache; 2379 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2380 continue; 2381 2382 /* check for IN direction */ 2383 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2384 continue; 2385 2386 /* execute more frames */ 2387 td->tmr_val = 0; 2388 2389 sc->sc_needsof = 1; 2390 2391 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2392 continue; 2393 2394 /* compute slot */ 2395 slot = dwc_otg_compute_isoc_rx_tt_slot( 2396 sc->sc_tt_info + td->tt_index); 2397 if (slot > 3) { 2398 /* 2399 * Not enough time to get complete 2400 * split executed. 2401 */ 2402 continue; 2403 } 2404 /* Delayed start */ 2405 td->tt_start_slot = temp + slot; 2406 td->tt_scheduled = 1; 2407 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2408 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2409 } 2410 2411 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2412 td = xfer->td_transfer_cache; 2413 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2414 continue; 2415 2416 /* check for OUT direction */ 2417 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2418 continue; 2419 2420 /* execute more frames */ 2421 td->tmr_val = 0; 2422 2423 sc->sc_needsof = 1; 2424 2425 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2426 continue; 2427 2428 /* Start ASAP */ 2429 td->tt_start_slot = temp; 2430 td->tt_scheduled = 1; 2431 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2432 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2433 } 2434 2435 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2436 td = xfer->td_transfer_cache; 2437 if (td == NULL || td->ep_type != UE_INTERRUPT) 2438 continue; 2439 2440 if (td->tt_scheduled != 0) { 2441 sc->sc_needsof = 1; 2442 continue; 2443 } 2444 2445 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2446 continue; 2447 2448 if (td->hcsplt == 0) { 2449 sc->sc_needsof = 1; 2450 td->tt_scheduled = 1; 2451 continue; 2452 } 2453 2454 /* start ASAP */ 2455 td->tt_start_slot = temp; 2456 sc->sc_needsof = 1; 2457 td->tt_scheduled = 1; 2458 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2459 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2460 } 2461 2462 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2463 td = xfer->td_transfer_cache; 2464 if (td == NULL || 2465 td->ep_type != UE_CONTROL) { 2466 continue; 2467 } 2468 2469 sc->sc_needsof = 1; 2470 2471 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2472 continue; 2473 2474 /* start ASAP */ 2475 td->tt_start_slot = temp; 2476 td->tt_scheduled = 1; 2477 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2478 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2479 } 2480 } 2481 if ((temp & 7) < 6) { 2482 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2483 td = xfer->td_transfer_cache; 2484 if (td == NULL || 2485 td->ep_type != UE_BULK) { 2486 continue; 2487 } 2488 2489 sc->sc_needsof = 1; 2490 2491 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2492 continue; 2493 2494 /* start ASAP */ 2495 td->tt_start_slot = temp; 2496 td->tt_scheduled = 1; 2497 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2498 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2499 } 2500 } 2501 2502 /* Put TT transfers in execution order at the end */ 2503 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2504 2505 /* move all TT transfers in front, keeping the current order */ 2506 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2507 td = xfer->td_transfer_cache; 2508 if (td == NULL || td->hcsplt == 0) 2509 continue; 2510 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2511 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2512 } 2513 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2514 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2515 2516 /* put non-TT BULK transfers last */ 2517 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2518 td = xfer->td_transfer_cache; 2519 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2520 continue; 2521 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2522 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2523 } 2524 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2525 2526 if ((temp & 7) == 0) { 2527 2528 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2529 (int)temp, (int)sc->sc_needsof); 2530 2531 /* update SOF IRQ mask */ 2532 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2533 if (sc->sc_needsof == 0) { 2534 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2535 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2536 } 2537 } else { 2538 if (sc->sc_needsof != 0) { 2539 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2540 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2541 } 2542 } 2543 2544 /* clear need SOF flag */ 2545 sc->sc_needsof = 0; 2546 } 2547 return (1); 2548 } 2549 2550 static void 2551 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2552 { 2553 struct usb_xfer *xfer; 2554 uint32_t count = 0; 2555 uint32_t temp; 2556 uint8_t got_rx_status; 2557 uint8_t x; 2558 2559 repeat: 2560 if (++count == 16) { 2561 /* give other interrupts a chance */ 2562 DPRINTF("Yield\n"); 2563 return; 2564 } 2565 /* get all host channel interrupts */ 2566 for (x = 0; x != sc->sc_host_ch_max; x++) { 2567 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2568 if (temp != 0) { 2569 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2570 temp &= ~HCINT_SOFTWARE_ONLY; 2571 sc->sc_chan_state[x].hcint |= temp; 2572 } 2573 } 2574 2575 if (sc->sc_last_rx_status == 0) { 2576 2577 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2578 if (temp & GINTSTS_RXFLVL) { 2579 /* pop current status */ 2580 sc->sc_last_rx_status = 2581 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2582 } 2583 2584 if (sc->sc_last_rx_status != 0) { 2585 2586 uint8_t ep_no; 2587 2588 temp = sc->sc_last_rx_status & 2589 GRXSTSRD_PKTSTS_MASK; 2590 2591 /* non-data messages we simply skip */ 2592 if (temp != GRXSTSRD_STP_DATA && 2593 temp != GRXSTSRD_STP_COMPLETE && 2594 temp != GRXSTSRD_OUT_DATA) { 2595 /* check for halted channel */ 2596 if (temp == GRXSTSRH_HALTED) { 2597 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2598 sc->sc_chan_state[ep_no].wait_halted = 0; 2599 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2600 } 2601 dwc_otg_common_rx_ack(sc); 2602 goto repeat; 2603 } 2604 2605 temp = GRXSTSRD_BCNT_GET( 2606 sc->sc_last_rx_status); 2607 ep_no = GRXSTSRD_CHNUM_GET( 2608 sc->sc_last_rx_status); 2609 2610 /* receive data, if any */ 2611 if (temp != 0) { 2612 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2613 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2614 DOTG_DFIFO(ep_no), 2615 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2616 } 2617 2618 /* check if we should dump the data */ 2619 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2620 dwc_otg_common_rx_ack(sc); 2621 goto repeat; 2622 } 2623 2624 got_rx_status = 1; 2625 2626 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2627 sc->sc_last_rx_status, ep_no, 2628 (sc->sc_last_rx_status >> 15) & 3, 2629 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2630 (sc->sc_last_rx_status >> 17) & 15); 2631 } else { 2632 got_rx_status = 0; 2633 } 2634 } else { 2635 uint8_t ep_no; 2636 2637 ep_no = GRXSTSRD_CHNUM_GET( 2638 sc->sc_last_rx_status); 2639 2640 /* check if we should dump the data */ 2641 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2642 dwc_otg_common_rx_ack(sc); 2643 goto repeat; 2644 } 2645 2646 got_rx_status = 1; 2647 } 2648 2649 /* execute FIFOs */ 2650 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2651 dwc_otg_xfer_do_fifo(sc, xfer); 2652 2653 if (got_rx_status) { 2654 /* check if data was consumed */ 2655 if (sc->sc_last_rx_status == 0) 2656 goto repeat; 2657 2658 /* disable RX FIFO level interrupt */ 2659 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2660 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2661 } 2662 2663 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2664 /* update host transfer schedule, so that new transfers can be issued */ 2665 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2666 goto repeat; 2667 } 2668 } 2669 2670 static void 2671 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2672 { 2673 struct usb_xfer *xfer; 2674 repeat: 2675 /* scan for completion events */ 2676 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2677 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2678 goto repeat; 2679 } 2680 } 2681 2682 static void 2683 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2684 { 2685 DPRINTFN(5, "vbus = %u\n", is_on); 2686 2687 /* 2688 * If the USB host mode is forced, then assume VBUS is always 2689 * present else rely on the input to this function: 2690 */ 2691 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2692 2693 if (!sc->sc_flags.status_vbus) { 2694 sc->sc_flags.status_vbus = 1; 2695 2696 /* complete root HUB interrupt endpoint */ 2697 2698 dwc_otg_root_intr(sc); 2699 } 2700 } else { 2701 if (sc->sc_flags.status_vbus) { 2702 sc->sc_flags.status_vbus = 0; 2703 sc->sc_flags.status_bus_reset = 0; 2704 sc->sc_flags.status_suspend = 0; 2705 sc->sc_flags.change_suspend = 0; 2706 sc->sc_flags.change_connect = 1; 2707 2708 /* complete root HUB interrupt endpoint */ 2709 2710 dwc_otg_root_intr(sc); 2711 } 2712 } 2713 } 2714 2715 int 2716 dwc_otg_filter_interrupt(void *arg) 2717 { 2718 struct dwc_otg_softc *sc = arg; 2719 int retval = FILTER_HANDLED; 2720 uint32_t status; 2721 2722 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2723 2724 /* read and clear interrupt status */ 2725 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2726 2727 /* clear interrupts we are handling here */ 2728 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2729 2730 /* check for USB state change interrupts */ 2731 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2732 retval = FILTER_SCHEDULE_THREAD; 2733 2734 /* clear FIFO empty interrupts */ 2735 if (status & sc->sc_irq_mask & 2736 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2737 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2738 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2739 } 2740 /* clear all IN endpoint interrupts */ 2741 if (status & GINTSTS_IEPINT) { 2742 uint32_t temp; 2743 uint8_t x; 2744 2745 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2746 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2747 if (temp & DIEPMSK_XFERCOMPLMSK) { 2748 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2749 DIEPMSK_XFERCOMPLMSK); 2750 } 2751 } 2752 } 2753 2754 /* poll FIFOs, if any */ 2755 dwc_otg_interrupt_poll_locked(sc); 2756 2757 if (sc->sc_xfer_complete != 0) 2758 retval = FILTER_SCHEDULE_THREAD; 2759 2760 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2761 2762 return (retval); 2763 } 2764 2765 void 2766 dwc_otg_interrupt(void *arg) 2767 { 2768 struct dwc_otg_softc *sc = arg; 2769 uint32_t status; 2770 2771 USB_BUS_LOCK(&sc->sc_bus); 2772 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2773 2774 /* read and clear interrupt status */ 2775 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2776 2777 /* clear interrupts we are handling here */ 2778 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2779 2780 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2781 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2782 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2783 2784 if (status & GINTSTS_USBRST) { 2785 2786 /* set correct state */ 2787 sc->sc_flags.status_device_mode = 1; 2788 sc->sc_flags.status_bus_reset = 0; 2789 sc->sc_flags.status_suspend = 0; 2790 sc->sc_flags.change_suspend = 0; 2791 sc->sc_flags.change_connect = 1; 2792 2793 /* Disable SOF interrupt */ 2794 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2795 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2796 2797 /* complete root HUB interrupt endpoint */ 2798 dwc_otg_root_intr(sc); 2799 } 2800 2801 /* check for any bus state change interrupts */ 2802 if (status & GINTSTS_ENUMDONE) { 2803 2804 uint32_t temp; 2805 2806 DPRINTFN(5, "end of reset\n"); 2807 2808 /* set correct state */ 2809 sc->sc_flags.status_device_mode = 1; 2810 sc->sc_flags.status_bus_reset = 1; 2811 sc->sc_flags.status_suspend = 0; 2812 sc->sc_flags.change_suspend = 0; 2813 sc->sc_flags.change_connect = 1; 2814 sc->sc_flags.status_low_speed = 0; 2815 sc->sc_flags.port_enabled = 1; 2816 2817 /* reset FIFOs */ 2818 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2819 2820 /* reset function address */ 2821 dwc_otg_set_address(sc, 0); 2822 2823 /* figure out enumeration speed */ 2824 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2825 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2826 sc->sc_flags.status_high_speed = 1; 2827 else 2828 sc->sc_flags.status_high_speed = 0; 2829 2830 /* 2831 * Disable resume and SOF interrupt, and enable 2832 * suspend and RX frame interrupt: 2833 */ 2834 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2835 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2836 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2837 2838 /* complete root HUB interrupt endpoint */ 2839 dwc_otg_root_intr(sc); 2840 } 2841 2842 if (status & GINTSTS_PRTINT) { 2843 uint32_t hprt; 2844 2845 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2846 2847 /* clear change bits */ 2848 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2849 HPRT_PRTPWR | HPRT_PRTENCHNG | 2850 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2851 sc->sc_hprt_val); 2852 2853 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2854 2855 sc->sc_flags.status_device_mode = 0; 2856 2857 if (hprt & HPRT_PRTCONNSTS) 2858 sc->sc_flags.status_bus_reset = 1; 2859 else 2860 sc->sc_flags.status_bus_reset = 0; 2861 2862 if (hprt & HPRT_PRTENCHNG) 2863 sc->sc_flags.change_enabled = 1; 2864 2865 if (hprt & HPRT_PRTENA) 2866 sc->sc_flags.port_enabled = 1; 2867 else 2868 sc->sc_flags.port_enabled = 0; 2869 2870 if (hprt & HPRT_PRTOVRCURRCHNG) 2871 sc->sc_flags.change_over_current = 1; 2872 2873 if (hprt & HPRT_PRTOVRCURRACT) 2874 sc->sc_flags.port_over_current = 1; 2875 else 2876 sc->sc_flags.port_over_current = 0; 2877 2878 if (hprt & HPRT_PRTPWR) 2879 sc->sc_flags.port_powered = 1; 2880 else 2881 sc->sc_flags.port_powered = 0; 2882 2883 if (((hprt & HPRT_PRTSPD_MASK) 2884 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2885 sc->sc_flags.status_low_speed = 1; 2886 else 2887 sc->sc_flags.status_low_speed = 0; 2888 2889 if (((hprt & HPRT_PRTSPD_MASK) 2890 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2891 sc->sc_flags.status_high_speed = 1; 2892 else 2893 sc->sc_flags.status_high_speed = 0; 2894 2895 if (hprt & HPRT_PRTCONNDET) 2896 sc->sc_flags.change_connect = 1; 2897 2898 if (hprt & HPRT_PRTSUSP) 2899 dwc_otg_suspend_irq(sc); 2900 else 2901 dwc_otg_resume_irq(sc); 2902 2903 /* complete root HUB interrupt endpoint */ 2904 dwc_otg_root_intr(sc); 2905 2906 /* update host frame interval */ 2907 dwc_otg_update_host_frame_interval(sc); 2908 } 2909 2910 /* 2911 * If resume and suspend is set at the same time we interpret 2912 * that like RESUME. Resume is set when there is at least 3 2913 * milliseconds of inactivity on the USB BUS. 2914 */ 2915 if (status & GINTSTS_WKUPINT) { 2916 2917 DPRINTFN(5, "resume interrupt\n"); 2918 2919 dwc_otg_resume_irq(sc); 2920 2921 } else if (status & GINTSTS_USBSUSP) { 2922 2923 DPRINTFN(5, "suspend interrupt\n"); 2924 2925 dwc_otg_suspend_irq(sc); 2926 } 2927 /* check VBUS */ 2928 if (status & (GINTSTS_USBSUSP | 2929 GINTSTS_USBRST | 2930 GINTMSK_OTGINTMSK | 2931 GINTSTS_SESSREQINT)) { 2932 uint32_t temp; 2933 2934 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2935 2936 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2937 2938 dwc_otg_vbus_interrupt(sc, 2939 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2940 } 2941 2942 if (sc->sc_xfer_complete != 0) { 2943 sc->sc_xfer_complete = 0; 2944 2945 /* complete FIFOs, if any */ 2946 dwc_otg_interrupt_complete_locked(sc); 2947 2948 if (sc->sc_flags.status_device_mode == 0) { 2949 /* update host transfer schedule, so that new transfers can be issued */ 2950 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2951 dwc_otg_interrupt_poll_locked(sc); 2952 } 2953 } 2954 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2955 USB_BUS_UNLOCK(&sc->sc_bus); 2956 } 2957 2958 static void 2959 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2960 { 2961 struct dwc_otg_td *td; 2962 2963 /* get current Transfer Descriptor */ 2964 td = temp->td_next; 2965 temp->td = td; 2966 2967 /* prepare for next TD */ 2968 temp->td_next = td->obj_next; 2969 2970 /* fill out the Transfer Descriptor */ 2971 td->func = temp->func; 2972 td->pc = temp->pc; 2973 td->offset = temp->offset; 2974 td->remainder = temp->len; 2975 td->tx_bytes = 0; 2976 td->error_any = 0; 2977 td->error_stall = 0; 2978 td->npkt = 0; 2979 td->did_stall = temp->did_stall; 2980 td->short_pkt = temp->short_pkt; 2981 td->alt_next = temp->setup_alt_next; 2982 td->set_toggle = 0; 2983 td->got_short = 0; 2984 td->did_nak = 0; 2985 td->channel = DWC_OTG_MAX_CHANNELS; 2986 td->state = 0; 2987 td->errcnt = 0; 2988 td->tt_scheduled = 0; 2989 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2990 } 2991 2992 static void 2993 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2994 { 2995 struct dwc_otg_std_temp temp; 2996 struct dwc_otg_td *td; 2997 uint32_t x; 2998 uint8_t need_sync; 2999 uint8_t is_host; 3000 3001 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3002 xfer->address, UE_GET_ADDR(xfer->endpointno), 3003 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3004 3005 temp.max_frame_size = xfer->max_frame_size; 3006 3007 td = xfer->td_start[0]; 3008 xfer->td_transfer_first = td; 3009 xfer->td_transfer_cache = td; 3010 3011 /* setup temp */ 3012 3013 temp.pc = NULL; 3014 temp.td = NULL; 3015 temp.td_next = xfer->td_start[0]; 3016 temp.offset = 0; 3017 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3018 xfer->flags_int.isochronous_xfr; 3019 temp.did_stall = !xfer->flags_int.control_stall; 3020 3021 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3022 3023 /* check if we should prepend a setup message */ 3024 3025 if (xfer->flags_int.control_xfr) { 3026 if (xfer->flags_int.control_hdr) { 3027 3028 if (is_host) 3029 temp.func = &dwc_otg_host_setup_tx; 3030 else 3031 temp.func = &dwc_otg_setup_rx; 3032 3033 temp.len = xfer->frlengths[0]; 3034 temp.pc = xfer->frbuffers + 0; 3035 temp.short_pkt = temp.len ? 1 : 0; 3036 3037 /* check for last frame */ 3038 if (xfer->nframes == 1) { 3039 /* no STATUS stage yet, SETUP is last */ 3040 if (xfer->flags_int.control_act) 3041 temp.setup_alt_next = 0; 3042 } 3043 3044 dwc_otg_setup_standard_chain_sub(&temp); 3045 } 3046 x = 1; 3047 } else { 3048 x = 0; 3049 } 3050 3051 if (x != xfer->nframes) { 3052 if (xfer->endpointno & UE_DIR_IN) { 3053 if (is_host) { 3054 temp.func = &dwc_otg_host_data_rx; 3055 need_sync = 0; 3056 } else { 3057 temp.func = &dwc_otg_data_tx; 3058 need_sync = 1; 3059 } 3060 } else { 3061 if (is_host) { 3062 temp.func = &dwc_otg_host_data_tx; 3063 need_sync = 0; 3064 } else { 3065 temp.func = &dwc_otg_data_rx; 3066 need_sync = 0; 3067 } 3068 } 3069 3070 /* setup "pc" pointer */ 3071 temp.pc = xfer->frbuffers + x; 3072 } else { 3073 need_sync = 0; 3074 } 3075 while (x != xfer->nframes) { 3076 3077 /* DATA0 / DATA1 message */ 3078 3079 temp.len = xfer->frlengths[x]; 3080 3081 x++; 3082 3083 if (x == xfer->nframes) { 3084 if (xfer->flags_int.control_xfr) { 3085 if (xfer->flags_int.control_act) { 3086 temp.setup_alt_next = 0; 3087 } 3088 } else { 3089 temp.setup_alt_next = 0; 3090 } 3091 } 3092 if (temp.len == 0) { 3093 3094 /* make sure that we send an USB packet */ 3095 3096 temp.short_pkt = 0; 3097 3098 } else { 3099 3100 /* regular data transfer */ 3101 3102 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3103 } 3104 3105 dwc_otg_setup_standard_chain_sub(&temp); 3106 3107 if (xfer->flags_int.isochronous_xfr) { 3108 temp.offset += temp.len; 3109 } else { 3110 /* get next Page Cache pointer */ 3111 temp.pc = xfer->frbuffers + x; 3112 } 3113 } 3114 3115 if (xfer->flags_int.control_xfr) { 3116 3117 /* always setup a valid "pc" pointer for status and sync */ 3118 temp.pc = xfer->frbuffers + 0; 3119 temp.len = 0; 3120 temp.short_pkt = 0; 3121 temp.setup_alt_next = 0; 3122 3123 /* check if we need to sync */ 3124 if (need_sync) { 3125 /* we need a SYNC point after TX */ 3126 temp.func = &dwc_otg_data_tx_sync; 3127 dwc_otg_setup_standard_chain_sub(&temp); 3128 } 3129 3130 /* check if we should append a status stage */ 3131 if (!xfer->flags_int.control_act) { 3132 3133 /* 3134 * Send a DATA1 message and invert the current 3135 * endpoint direction. 3136 */ 3137 if (xfer->endpointno & UE_DIR_IN) { 3138 if (is_host) { 3139 temp.func = &dwc_otg_host_data_tx; 3140 need_sync = 0; 3141 } else { 3142 temp.func = &dwc_otg_data_rx; 3143 need_sync = 0; 3144 } 3145 } else { 3146 if (is_host) { 3147 temp.func = &dwc_otg_host_data_rx; 3148 need_sync = 0; 3149 } else { 3150 temp.func = &dwc_otg_data_tx; 3151 need_sync = 1; 3152 } 3153 } 3154 3155 dwc_otg_setup_standard_chain_sub(&temp); 3156 3157 /* data toggle should be DATA1 */ 3158 td = temp.td; 3159 td->set_toggle = 1; 3160 3161 if (need_sync) { 3162 /* we need a SYNC point after TX */ 3163 temp.func = &dwc_otg_data_tx_sync; 3164 dwc_otg_setup_standard_chain_sub(&temp); 3165 } 3166 } 3167 } else { 3168 /* check if we need to sync */ 3169 if (need_sync) { 3170 3171 temp.pc = xfer->frbuffers + 0; 3172 temp.len = 0; 3173 temp.short_pkt = 0; 3174 temp.setup_alt_next = 0; 3175 3176 /* we need a SYNC point after TX */ 3177 temp.func = &dwc_otg_data_tx_sync; 3178 dwc_otg_setup_standard_chain_sub(&temp); 3179 } 3180 } 3181 3182 /* must have at least one frame! */ 3183 td = temp.td; 3184 xfer->td_transfer_last = td; 3185 3186 if (is_host) { 3187 3188 struct dwc_otg_softc *sc; 3189 uint32_t hcchar; 3190 uint32_t hcsplt; 3191 3192 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3193 3194 /* get first again */ 3195 td = xfer->td_transfer_first; 3196 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3197 3198 hcchar = 3199 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3200 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3201 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3202 HCCHAR_CHENA; 3203 3204 /* 3205 * We are not always able to meet the timing 3206 * requirements of the USB interrupt endpoint's 3207 * complete split token, when doing transfers going 3208 * via a transaction translator. Use the CONTROL 3209 * transfer type instead of the INTERRUPT transfer 3210 * type in general, as a means to workaround 3211 * that. This trick should work for both FULL and LOW 3212 * speed USB traffic going through a TT. For non-TT 3213 * traffic it works aswell. The reason for using 3214 * CONTROL type instead of BULK is that some TTs might 3215 * reject LOW speed BULK traffic. 3216 */ 3217 if (td->ep_type == UE_INTERRUPT) 3218 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3219 else 3220 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3221 3222 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3223 hcchar |= HCCHAR_LSPDDEV; 3224 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3225 hcchar |= HCCHAR_EPDIR_IN; 3226 3227 switch (xfer->xroot->udev->speed) { 3228 case USB_SPEED_FULL: 3229 case USB_SPEED_LOW: 3230 /* check if root HUB port is running High Speed */ 3231 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3232 hcsplt = HCSPLT_SPLTENA | 3233 (xfer->xroot->udev->hs_port_no << 3234 HCSPLT_PRTADDR_SHIFT) | 3235 (xfer->xroot->udev->hs_hub_addr << 3236 HCSPLT_HUBADDR_SHIFT); 3237 } else { 3238 hcsplt = 0; 3239 } 3240 if (td->ep_type == UE_INTERRUPT) { 3241 uint32_t ival; 3242 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3243 if (ival == 0) 3244 ival = 1; 3245 else if (ival > 127) 3246 ival = 127; 3247 td->tmr_val = sc->sc_tmr_val + ival; 3248 td->tmr_res = ival; 3249 } else if (td->ep_type == UE_ISOCHRONOUS) { 3250 td->tmr_val = 0; 3251 td->tmr_res = 1; 3252 } else { 3253 td->tmr_val = 0; 3254 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3255 } 3256 break; 3257 case USB_SPEED_HIGH: 3258 hcsplt = 0; 3259 if (td->ep_type == UE_INTERRUPT) { 3260 uint32_t ival; 3261 #if 0 3262 hcchar |= ((xfer->max_packet_count & 3) 3263 << HCCHAR_MC_SHIFT); 3264 #endif 3265 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3266 if (ival == 0) 3267 ival = 1; 3268 else if (ival > 127) 3269 ival = 127; 3270 td->tmr_val = sc->sc_tmr_val + ival; 3271 td->tmr_res = ival; 3272 } else if (td->ep_type == UE_ISOCHRONOUS) { 3273 hcchar |= ((xfer->max_packet_count & 3) 3274 << HCCHAR_MC_SHIFT); 3275 td->tmr_val = 0; 3276 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3277 } else { 3278 td->tmr_val = 0; 3279 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3280 } 3281 break; 3282 default: 3283 hcsplt = 0; 3284 td->tmr_val = 0; 3285 td->tmr_res = 0; 3286 break; 3287 } 3288 3289 /* store configuration in all TD's */ 3290 while (1) { 3291 td->hcchar = hcchar; 3292 td->hcsplt = hcsplt; 3293 3294 if (((void *)td) == xfer->td_transfer_last) 3295 break; 3296 3297 td = td->obj_next; 3298 } 3299 } 3300 } 3301 3302 static void 3303 dwc_otg_timeout(void *arg) 3304 { 3305 struct usb_xfer *xfer = arg; 3306 3307 DPRINTF("xfer=%p\n", xfer); 3308 3309 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3310 3311 /* transfer is transferred */ 3312 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3313 } 3314 3315 static void 3316 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3317 { 3318 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3319 3320 DPRINTFN(9, "\n"); 3321 3322 /* 3323 * Poll one time in device mode, which will turn on the 3324 * endpoint interrupts. Else wait for SOF interrupt in host 3325 * mode. 3326 */ 3327 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3328 3329 if (sc->sc_flags.status_device_mode != 0) { 3330 dwc_otg_xfer_do_fifo(sc, xfer); 3331 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3332 goto done; 3333 } 3334 3335 /* put transfer on interrupt queue */ 3336 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3337 3338 /* start timeout, if any */ 3339 if (xfer->timeout != 0) { 3340 usbd_transfer_timeout_ms(xfer, 3341 &dwc_otg_timeout, xfer->timeout); 3342 } 3343 3344 if (sc->sc_flags.status_device_mode != 0) 3345 goto done; 3346 3347 /* enable SOF interrupt, if any */ 3348 dwc_otg_enable_sof_irq(sc); 3349 done: 3350 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3351 } 3352 3353 static void 3354 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3355 { 3356 DPRINTFN(9, "\n"); 3357 3358 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3359 3360 /* set port bit */ 3361 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3362 3363 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3364 sizeof(sc->sc_hub_idata)); 3365 } 3366 3367 static usb_error_t 3368 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3369 { 3370 struct dwc_otg_td *td; 3371 uint32_t len; 3372 usb_error_t error; 3373 3374 DPRINTFN(9, "\n"); 3375 3376 td = xfer->td_transfer_cache; 3377 3378 do { 3379 len = td->remainder; 3380 3381 /* store last data toggle */ 3382 xfer->endpoint->toggle_next = td->toggle; 3383 3384 if (xfer->aframes != xfer->nframes) { 3385 /* 3386 * Verify the length and subtract 3387 * the remainder from "frlengths[]": 3388 */ 3389 if (len > xfer->frlengths[xfer->aframes]) { 3390 td->error_any = 1; 3391 } else { 3392 xfer->frlengths[xfer->aframes] -= len; 3393 } 3394 } 3395 /* Check for transfer error */ 3396 if (td->error_any) { 3397 /* the transfer is finished */ 3398 error = (td->error_stall ? 3399 USB_ERR_STALLED : USB_ERR_IOERROR); 3400 td = NULL; 3401 break; 3402 } 3403 /* Check for short transfer */ 3404 if (len > 0) { 3405 if (xfer->flags_int.short_frames_ok || 3406 xfer->flags_int.isochronous_xfr) { 3407 /* follow alt next */ 3408 if (td->alt_next) { 3409 td = td->obj_next; 3410 } else { 3411 td = NULL; 3412 } 3413 } else { 3414 /* the transfer is finished */ 3415 td = NULL; 3416 } 3417 error = 0; 3418 break; 3419 } 3420 td = td->obj_next; 3421 3422 /* this USB frame is complete */ 3423 error = 0; 3424 break; 3425 3426 } while (0); 3427 3428 /* update transfer cache */ 3429 3430 xfer->td_transfer_cache = td; 3431 3432 return (error); 3433 } 3434 3435 static void 3436 dwc_otg_standard_done(struct usb_xfer *xfer) 3437 { 3438 usb_error_t err = 0; 3439 3440 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3441 xfer, xfer->endpoint); 3442 3443 /* reset scanner */ 3444 3445 xfer->td_transfer_cache = xfer->td_transfer_first; 3446 3447 if (xfer->flags_int.control_xfr) { 3448 3449 if (xfer->flags_int.control_hdr) { 3450 3451 err = dwc_otg_standard_done_sub(xfer); 3452 } 3453 xfer->aframes = 1; 3454 3455 if (xfer->td_transfer_cache == NULL) { 3456 goto done; 3457 } 3458 } 3459 while (xfer->aframes != xfer->nframes) { 3460 3461 err = dwc_otg_standard_done_sub(xfer); 3462 xfer->aframes++; 3463 3464 if (xfer->td_transfer_cache == NULL) { 3465 goto done; 3466 } 3467 } 3468 3469 if (xfer->flags_int.control_xfr && 3470 !xfer->flags_int.control_act) { 3471 3472 err = dwc_otg_standard_done_sub(xfer); 3473 } 3474 done: 3475 dwc_otg_device_done(xfer, err); 3476 } 3477 3478 /*------------------------------------------------------------------------* 3479 * dwc_otg_device_done 3480 * 3481 * NOTE: this function can be called more than one time on the 3482 * same USB transfer! 3483 *------------------------------------------------------------------------*/ 3484 static void 3485 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3486 { 3487 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3488 3489 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3490 xfer, xfer->endpoint, error); 3491 3492 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3493 3494 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3495 /* Interrupts are cleared by the interrupt handler */ 3496 } else { 3497 struct dwc_otg_td *td; 3498 3499 td = xfer->td_transfer_cache; 3500 if (td != NULL) 3501 dwc_otg_host_channel_free(sc, td); 3502 } 3503 /* dequeue transfer and start next transfer */ 3504 usbd_transfer_done(xfer, error); 3505 3506 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3507 } 3508 3509 static void 3510 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3511 { 3512 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3513 } 3514 3515 static void 3516 dwc_otg_set_stall(struct usb_device *udev, 3517 struct usb_endpoint *ep, uint8_t *did_stall) 3518 { 3519 struct dwc_otg_softc *sc; 3520 uint32_t temp; 3521 uint32_t reg; 3522 uint8_t ep_no; 3523 3524 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3525 3526 /* check mode */ 3527 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3528 /* not supported */ 3529 return; 3530 } 3531 3532 sc = DWC_OTG_BUS2SC(udev->bus); 3533 3534 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3535 3536 /* get endpoint address */ 3537 ep_no = ep->edesc->bEndpointAddress; 3538 3539 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3540 3541 if (ep_no & UE_DIR_IN) { 3542 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3543 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3544 } else { 3545 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3546 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3547 } 3548 3549 /* disable and stall endpoint */ 3550 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3551 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3552 3553 /* clear active OUT ep */ 3554 if (!(ep_no & UE_DIR_IN)) { 3555 3556 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3557 3558 if (sc->sc_last_rx_status != 0 && 3559 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3560 sc->sc_last_rx_status)) { 3561 /* dump data */ 3562 dwc_otg_common_rx_ack(sc); 3563 /* poll interrupt */ 3564 dwc_otg_interrupt_poll_locked(sc); 3565 dwc_otg_interrupt_complete_locked(sc); 3566 } 3567 } 3568 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3569 } 3570 3571 static void 3572 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3573 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3574 { 3575 uint32_t reg; 3576 uint32_t temp; 3577 3578 if (ep_type == UE_CONTROL) { 3579 /* clearing stall is not needed */ 3580 return; 3581 } 3582 3583 if (ep_dir) { 3584 reg = DOTG_DIEPCTL(ep_no); 3585 } else { 3586 reg = DOTG_DOEPCTL(ep_no); 3587 sc->sc_active_rx_ep |= (1U << ep_no); 3588 } 3589 3590 /* round up and mask away the multiplier count */ 3591 mps = (mps + 3) & 0x7FC; 3592 3593 if (ep_type == UE_BULK) { 3594 temp = DIEPCTL_EPTYPE_SET( 3595 DIEPCTL_EPTYPE_BULK) | 3596 DIEPCTL_USBACTEP; 3597 } else if (ep_type == UE_INTERRUPT) { 3598 temp = DIEPCTL_EPTYPE_SET( 3599 DIEPCTL_EPTYPE_INTERRUPT) | 3600 DIEPCTL_USBACTEP; 3601 } else { 3602 temp = DIEPCTL_EPTYPE_SET( 3603 DIEPCTL_EPTYPE_ISOC) | 3604 DIEPCTL_USBACTEP; 3605 } 3606 3607 temp |= DIEPCTL_MPS_SET(mps); 3608 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3609 3610 if (ep_dir) 3611 sc->sc_in_ctl[ep_no] = temp; 3612 else 3613 sc->sc_out_ctl[ep_no] = temp; 3614 3615 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3616 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3617 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3618 3619 /* we only reset the transmit FIFO */ 3620 if (ep_dir) { 3621 dwc_otg_tx_fifo_reset(sc, 3622 GRSTCTL_TXFIFO(ep_no) | 3623 GRSTCTL_TXFFLSH); 3624 3625 DWC_OTG_WRITE_4(sc, 3626 DOTG_DIEPTSIZ(ep_no), 0); 3627 } 3628 3629 /* poll interrupt */ 3630 dwc_otg_interrupt_poll_locked(sc); 3631 dwc_otg_interrupt_complete_locked(sc); 3632 } 3633 3634 static void 3635 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3636 { 3637 struct dwc_otg_softc *sc; 3638 struct usb_endpoint_descriptor *ed; 3639 3640 DPRINTFN(5, "endpoint=%p\n", ep); 3641 3642 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3643 3644 /* check mode */ 3645 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3646 /* not supported */ 3647 return; 3648 } 3649 /* get softc */ 3650 sc = DWC_OTG_BUS2SC(udev->bus); 3651 3652 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3653 3654 /* get endpoint descriptor */ 3655 ed = ep->edesc; 3656 3657 /* reset endpoint */ 3658 dwc_otg_clear_stall_sub_locked(sc, 3659 UGETW(ed->wMaxPacketSize), 3660 (ed->bEndpointAddress & UE_ADDR), 3661 (ed->bmAttributes & UE_XFERTYPE), 3662 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3663 3664 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3665 } 3666 3667 static void 3668 dwc_otg_device_state_change(struct usb_device *udev) 3669 { 3670 struct dwc_otg_softc *sc; 3671 uint8_t x; 3672 3673 /* check mode */ 3674 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3675 /* not supported */ 3676 return; 3677 } 3678 3679 /* get softc */ 3680 sc = DWC_OTG_BUS2SC(udev->bus); 3681 3682 /* deactivate all other endpoint but the control endpoint */ 3683 if (udev->state == USB_STATE_CONFIGURED || 3684 udev->state == USB_STATE_ADDRESSED) { 3685 3686 USB_BUS_LOCK(&sc->sc_bus); 3687 3688 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3689 3690 if (x < sc->sc_dev_in_ep_max) { 3691 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3692 DIEPCTL_EPDIS); 3693 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3694 } 3695 3696 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3697 DOEPCTL_EPDIS); 3698 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3699 } 3700 USB_BUS_UNLOCK(&sc->sc_bus); 3701 } 3702 } 3703 3704 int 3705 dwc_otg_init(struct dwc_otg_softc *sc) 3706 { 3707 uint32_t temp; 3708 3709 DPRINTF("start\n"); 3710 3711 /* set up the bus structure */ 3712 sc->sc_bus.usbrev = USB_REV_2_0; 3713 sc->sc_bus.methods = &dwc_otg_bus_methods; 3714 3715 usb_callout_init_mtx(&sc->sc_timer, 3716 &sc->sc_bus.bus_mtx, 0); 3717 3718 USB_BUS_LOCK(&sc->sc_bus); 3719 3720 /* turn on clocks */ 3721 dwc_otg_clocks_on(sc); 3722 3723 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3724 DPRINTF("Version = 0x%08x\n", temp); 3725 3726 /* disconnect */ 3727 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3728 DCTL_SFTDISCON); 3729 3730 /* wait for host to detect disconnect */ 3731 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3732 3733 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3734 GRSTCTL_CSFTRST); 3735 3736 /* wait a little bit for block to reset */ 3737 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3738 3739 switch (sc->sc_mode) { 3740 case DWC_MODE_DEVICE: 3741 temp = GUSBCFG_FORCEDEVMODE; 3742 break; 3743 case DWC_MODE_HOST: 3744 temp = GUSBCFG_FORCEHOSTMODE; 3745 break; 3746 default: 3747 temp = 0; 3748 break; 3749 } 3750 3751 /* select HSIC, ULPI or internal PHY mode */ 3752 switch (dwc_otg_phy_type) { 3753 case DWC_OTG_PHY_HSIC: 3754 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3755 GUSBCFG_PHYIF | 3756 GUSBCFG_TRD_TIM_SET(5) | temp); 3757 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3758 0x000000EC); 3759 3760 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3761 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3762 temp & ~GLPMCFG_HSIC_CONN); 3763 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3764 temp | GLPMCFG_HSIC_CONN); 3765 break; 3766 case DWC_OTG_PHY_ULPI: 3767 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3768 GUSBCFG_ULPI_UTMI_SEL | 3769 GUSBCFG_TRD_TIM_SET(5) | temp); 3770 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3771 3772 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3773 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3774 temp & ~GLPMCFG_HSIC_CONN); 3775 break; 3776 case DWC_OTG_PHY_INTERNAL: 3777 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3778 GUSBCFG_PHYSEL | 3779 GUSBCFG_TRD_TIM_SET(5) | temp); 3780 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3781 3782 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3783 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3784 temp & ~GLPMCFG_HSIC_CONN); 3785 3786 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3787 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3788 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3789 DOTG_GGPIO_PWRDWN); 3790 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3791 break; 3792 default: 3793 break; 3794 } 3795 3796 /* clear global nak */ 3797 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3798 DCTL_CGOUTNAK | 3799 DCTL_CGNPINNAK); 3800 3801 /* disable USB port */ 3802 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3803 3804 /* wait 10ms */ 3805 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3806 3807 /* enable USB port */ 3808 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3809 3810 /* wait 10ms */ 3811 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3812 3813 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3814 3815 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3816 3817 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3818 3819 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3820 3821 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3822 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3823 3824 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3825 3826 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3827 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3828 3829 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3830 3831 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3832 3833 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3834 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3835 sc->sc_host_ch_max); 3836 3837 /* setup FIFO */ 3838 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3839 USB_BUS_UNLOCK(&sc->sc_bus); 3840 return (EINVAL); 3841 } 3842 3843 /* enable interrupts */ 3844 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3845 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3846 3847 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3848 3849 /* enable all endpoint interrupts */ 3850 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3851 if (temp & GHWCFG2_MPI) { 3852 uint8_t x; 3853 3854 DPRINTF("Disable Multi Process Interrupts\n"); 3855 3856 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3857 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3858 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3859 } 3860 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 3861 } 3862 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3863 DIEPMSK_XFERCOMPLMSK); 3864 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3865 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3866 } 3867 3868 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3869 /* setup clocks */ 3870 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3871 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3872 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3873 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3874 } 3875 3876 /* only enable global IRQ */ 3877 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3878 GAHBCFG_GLBLINTRMSK); 3879 3880 /* turn off clocks */ 3881 dwc_otg_clocks_off(sc); 3882 3883 /* read initial VBUS state */ 3884 3885 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3886 3887 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3888 3889 dwc_otg_vbus_interrupt(sc, 3890 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3891 3892 USB_BUS_UNLOCK(&sc->sc_bus); 3893 3894 /* catch any lost interrupts */ 3895 3896 dwc_otg_do_poll(&sc->sc_bus); 3897 3898 return (0); /* success */ 3899 } 3900 3901 void 3902 dwc_otg_uninit(struct dwc_otg_softc *sc) 3903 { 3904 USB_BUS_LOCK(&sc->sc_bus); 3905 3906 /* stop host timer */ 3907 dwc_otg_timer_stop(sc); 3908 3909 /* set disconnect */ 3910 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3911 DCTL_SFTDISCON); 3912 3913 /* turn off global IRQ */ 3914 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3915 3916 sc->sc_flags.port_enabled = 0; 3917 sc->sc_flags.port_powered = 0; 3918 sc->sc_flags.status_vbus = 0; 3919 sc->sc_flags.status_bus_reset = 0; 3920 sc->sc_flags.status_suspend = 0; 3921 sc->sc_flags.change_suspend = 0; 3922 sc->sc_flags.change_connect = 1; 3923 3924 dwc_otg_pull_down(sc); 3925 dwc_otg_clocks_off(sc); 3926 3927 USB_BUS_UNLOCK(&sc->sc_bus); 3928 3929 usb_callout_drain(&sc->sc_timer); 3930 } 3931 3932 static void 3933 dwc_otg_suspend(struct dwc_otg_softc *sc) 3934 { 3935 return; 3936 } 3937 3938 static void 3939 dwc_otg_resume(struct dwc_otg_softc *sc) 3940 { 3941 return; 3942 } 3943 3944 static void 3945 dwc_otg_do_poll(struct usb_bus *bus) 3946 { 3947 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3948 3949 USB_BUS_LOCK(&sc->sc_bus); 3950 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3951 dwc_otg_interrupt_poll_locked(sc); 3952 dwc_otg_interrupt_complete_locked(sc); 3953 if (sc->sc_flags.status_device_mode == 0) { 3954 /* update host transfer schedule, so that new transfers can be issued */ 3955 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3956 dwc_otg_interrupt_poll_locked(sc); 3957 } 3958 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3959 USB_BUS_UNLOCK(&sc->sc_bus); 3960 } 3961 3962 /*------------------------------------------------------------------------* 3963 * DWC OTG bulk support 3964 * DWC OTG control support 3965 * DWC OTG interrupt support 3966 *------------------------------------------------------------------------*/ 3967 static void 3968 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3969 { 3970 } 3971 3972 static void 3973 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3974 { 3975 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3976 } 3977 3978 static void 3979 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3980 { 3981 } 3982 3983 static void 3984 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3985 { 3986 /* setup TDs */ 3987 dwc_otg_setup_standard_chain(xfer); 3988 dwc_otg_start_standard_chain(xfer); 3989 } 3990 3991 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3992 { 3993 .open = dwc_otg_device_non_isoc_open, 3994 .close = dwc_otg_device_non_isoc_close, 3995 .enter = dwc_otg_device_non_isoc_enter, 3996 .start = dwc_otg_device_non_isoc_start, 3997 }; 3998 3999 /*------------------------------------------------------------------------* 4000 * DWC OTG full speed isochronous support 4001 *------------------------------------------------------------------------*/ 4002 static void 4003 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4004 { 4005 } 4006 4007 static void 4008 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4009 { 4010 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4011 } 4012 4013 static void 4014 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4015 { 4016 } 4017 4018 static void 4019 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4020 { 4021 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4022 uint32_t temp; 4023 uint32_t msframes; 4024 uint32_t framenum; 4025 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4026 4027 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4028 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4029 4030 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4031 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4032 4033 /* get the current frame index */ 4034 framenum = (temp & HFNUM_FRNUM_MASK); 4035 } else { 4036 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4037 4038 /* get the current frame index */ 4039 framenum = DSTS_SOFFN_GET(temp); 4040 } 4041 4042 if (xfer->xroot->udev->parent_hs_hub != NULL) 4043 framenum /= 8; 4044 4045 framenum &= DWC_OTG_FRAME_MASK; 4046 4047 /* 4048 * Compute number of milliseconds worth of data traffic for 4049 * this USB transfer: 4050 */ 4051 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4052 msframes = ((xfer->nframes << shift) + 7) / 8; 4053 else 4054 msframes = xfer->nframes; 4055 4056 /* 4057 * check if the frame index is within the window where the frames 4058 * will be inserted 4059 */ 4060 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4061 4062 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4063 /* 4064 * If there is data underflow or the pipe queue is 4065 * empty we schedule the transfer a few frames ahead 4066 * of the current frame position. Else two isochronous 4067 * transfers might overlap. 4068 */ 4069 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4070 xfer->endpoint->is_synced = 1; 4071 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4072 } 4073 /* 4074 * compute how many milliseconds the insertion is ahead of the 4075 * current frame position: 4076 */ 4077 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4078 4079 /* 4080 * pre-compute when the isochronous transfer will be finished: 4081 */ 4082 xfer->isoc_time_complete = 4083 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4084 4085 /* setup TDs */ 4086 dwc_otg_setup_standard_chain(xfer); 4087 4088 /* compute frame number for next insertion */ 4089 xfer->endpoint->isoc_next += msframes; 4090 4091 /* start TD chain */ 4092 dwc_otg_start_standard_chain(xfer); 4093 } 4094 4095 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4096 { 4097 .open = dwc_otg_device_isoc_open, 4098 .close = dwc_otg_device_isoc_close, 4099 .enter = dwc_otg_device_isoc_enter, 4100 .start = dwc_otg_device_isoc_start, 4101 }; 4102 4103 /*------------------------------------------------------------------------* 4104 * DWC OTG root control support 4105 *------------------------------------------------------------------------* 4106 * Simulate a hardware HUB by handling all the necessary requests. 4107 *------------------------------------------------------------------------*/ 4108 4109 static const struct usb_device_descriptor dwc_otg_devd = { 4110 .bLength = sizeof(struct usb_device_descriptor), 4111 .bDescriptorType = UDESC_DEVICE, 4112 .bcdUSB = {0x00, 0x02}, 4113 .bDeviceClass = UDCLASS_HUB, 4114 .bDeviceSubClass = UDSUBCLASS_HUB, 4115 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4116 .bMaxPacketSize = 64, 4117 .bcdDevice = {0x00, 0x01}, 4118 .iManufacturer = 1, 4119 .iProduct = 2, 4120 .bNumConfigurations = 1, 4121 }; 4122 4123 static const struct dwc_otg_config_desc dwc_otg_confd = { 4124 .confd = { 4125 .bLength = sizeof(struct usb_config_descriptor), 4126 .bDescriptorType = UDESC_CONFIG, 4127 .wTotalLength[0] = sizeof(dwc_otg_confd), 4128 .bNumInterface = 1, 4129 .bConfigurationValue = 1, 4130 .iConfiguration = 0, 4131 .bmAttributes = UC_SELF_POWERED, 4132 .bMaxPower = 0, 4133 }, 4134 .ifcd = { 4135 .bLength = sizeof(struct usb_interface_descriptor), 4136 .bDescriptorType = UDESC_INTERFACE, 4137 .bNumEndpoints = 1, 4138 .bInterfaceClass = UICLASS_HUB, 4139 .bInterfaceSubClass = UISUBCLASS_HUB, 4140 .bInterfaceProtocol = 0, 4141 }, 4142 .endpd = { 4143 .bLength = sizeof(struct usb_endpoint_descriptor), 4144 .bDescriptorType = UDESC_ENDPOINT, 4145 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4146 .bmAttributes = UE_INTERRUPT, 4147 .wMaxPacketSize[0] = 8, 4148 .bInterval = 255, 4149 }, 4150 }; 4151 4152 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4153 4154 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4155 .bDescLength = sizeof(dwc_otg_hubd), 4156 .bDescriptorType = UDESC_HUB, 4157 .bNbrPorts = 1, 4158 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4159 .bPwrOn2PwrGood = 50, 4160 .bHubContrCurrent = 0, 4161 .DeviceRemovable = {0}, /* port is removable */ 4162 }; 4163 4164 #define STRING_VENDOR \ 4165 "D\0W\0C\0O\0T\0G" 4166 4167 #define STRING_PRODUCT \ 4168 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4169 4170 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4171 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4172 4173 static usb_error_t 4174 dwc_otg_roothub_exec(struct usb_device *udev, 4175 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4176 { 4177 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4178 const void *ptr; 4179 uint16_t len; 4180 uint16_t value; 4181 uint16_t index; 4182 usb_error_t err; 4183 4184 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4185 4186 /* buffer reset */ 4187 ptr = (const void *)&sc->sc_hub_temp; 4188 len = 0; 4189 err = 0; 4190 4191 value = UGETW(req->wValue); 4192 index = UGETW(req->wIndex); 4193 4194 /* demultiplex the control request */ 4195 4196 switch (req->bmRequestType) { 4197 case UT_READ_DEVICE: 4198 switch (req->bRequest) { 4199 case UR_GET_DESCRIPTOR: 4200 goto tr_handle_get_descriptor; 4201 case UR_GET_CONFIG: 4202 goto tr_handle_get_config; 4203 case UR_GET_STATUS: 4204 goto tr_handle_get_status; 4205 default: 4206 goto tr_stalled; 4207 } 4208 break; 4209 4210 case UT_WRITE_DEVICE: 4211 switch (req->bRequest) { 4212 case UR_SET_ADDRESS: 4213 goto tr_handle_set_address; 4214 case UR_SET_CONFIG: 4215 goto tr_handle_set_config; 4216 case UR_CLEAR_FEATURE: 4217 goto tr_valid; /* nop */ 4218 case UR_SET_DESCRIPTOR: 4219 goto tr_valid; /* nop */ 4220 case UR_SET_FEATURE: 4221 default: 4222 goto tr_stalled; 4223 } 4224 break; 4225 4226 case UT_WRITE_ENDPOINT: 4227 switch (req->bRequest) { 4228 case UR_CLEAR_FEATURE: 4229 switch (UGETW(req->wValue)) { 4230 case UF_ENDPOINT_HALT: 4231 goto tr_handle_clear_halt; 4232 case UF_DEVICE_REMOTE_WAKEUP: 4233 goto tr_handle_clear_wakeup; 4234 default: 4235 goto tr_stalled; 4236 } 4237 break; 4238 case UR_SET_FEATURE: 4239 switch (UGETW(req->wValue)) { 4240 case UF_ENDPOINT_HALT: 4241 goto tr_handle_set_halt; 4242 case UF_DEVICE_REMOTE_WAKEUP: 4243 goto tr_handle_set_wakeup; 4244 default: 4245 goto tr_stalled; 4246 } 4247 break; 4248 case UR_SYNCH_FRAME: 4249 goto tr_valid; /* nop */ 4250 default: 4251 goto tr_stalled; 4252 } 4253 break; 4254 4255 case UT_READ_ENDPOINT: 4256 switch (req->bRequest) { 4257 case UR_GET_STATUS: 4258 goto tr_handle_get_ep_status; 4259 default: 4260 goto tr_stalled; 4261 } 4262 break; 4263 4264 case UT_WRITE_INTERFACE: 4265 switch (req->bRequest) { 4266 case UR_SET_INTERFACE: 4267 goto tr_handle_set_interface; 4268 case UR_CLEAR_FEATURE: 4269 goto tr_valid; /* nop */ 4270 case UR_SET_FEATURE: 4271 default: 4272 goto tr_stalled; 4273 } 4274 break; 4275 4276 case UT_READ_INTERFACE: 4277 switch (req->bRequest) { 4278 case UR_GET_INTERFACE: 4279 goto tr_handle_get_interface; 4280 case UR_GET_STATUS: 4281 goto tr_handle_get_iface_status; 4282 default: 4283 goto tr_stalled; 4284 } 4285 break; 4286 4287 case UT_WRITE_CLASS_INTERFACE: 4288 case UT_WRITE_VENDOR_INTERFACE: 4289 /* XXX forward */ 4290 break; 4291 4292 case UT_READ_CLASS_INTERFACE: 4293 case UT_READ_VENDOR_INTERFACE: 4294 /* XXX forward */ 4295 break; 4296 4297 case UT_WRITE_CLASS_DEVICE: 4298 switch (req->bRequest) { 4299 case UR_CLEAR_FEATURE: 4300 goto tr_valid; 4301 case UR_SET_DESCRIPTOR: 4302 case UR_SET_FEATURE: 4303 break; 4304 default: 4305 goto tr_stalled; 4306 } 4307 break; 4308 4309 case UT_WRITE_CLASS_OTHER: 4310 switch (req->bRequest) { 4311 case UR_CLEAR_FEATURE: 4312 goto tr_handle_clear_port_feature; 4313 case UR_SET_FEATURE: 4314 goto tr_handle_set_port_feature; 4315 case UR_CLEAR_TT_BUFFER: 4316 case UR_RESET_TT: 4317 case UR_STOP_TT: 4318 goto tr_valid; 4319 4320 default: 4321 goto tr_stalled; 4322 } 4323 break; 4324 4325 case UT_READ_CLASS_OTHER: 4326 switch (req->bRequest) { 4327 case UR_GET_TT_STATE: 4328 goto tr_handle_get_tt_state; 4329 case UR_GET_STATUS: 4330 goto tr_handle_get_port_status; 4331 default: 4332 goto tr_stalled; 4333 } 4334 break; 4335 4336 case UT_READ_CLASS_DEVICE: 4337 switch (req->bRequest) { 4338 case UR_GET_DESCRIPTOR: 4339 goto tr_handle_get_class_descriptor; 4340 case UR_GET_STATUS: 4341 goto tr_handle_get_class_status; 4342 4343 default: 4344 goto tr_stalled; 4345 } 4346 break; 4347 default: 4348 goto tr_stalled; 4349 } 4350 goto tr_valid; 4351 4352 tr_handle_get_descriptor: 4353 switch (value >> 8) { 4354 case UDESC_DEVICE: 4355 if (value & 0xff) { 4356 goto tr_stalled; 4357 } 4358 len = sizeof(dwc_otg_devd); 4359 ptr = (const void *)&dwc_otg_devd; 4360 goto tr_valid; 4361 case UDESC_CONFIG: 4362 if (value & 0xff) { 4363 goto tr_stalled; 4364 } 4365 len = sizeof(dwc_otg_confd); 4366 ptr = (const void *)&dwc_otg_confd; 4367 goto tr_valid; 4368 case UDESC_STRING: 4369 switch (value & 0xff) { 4370 case 0: /* Language table */ 4371 len = sizeof(usb_string_lang_en); 4372 ptr = (const void *)&usb_string_lang_en; 4373 goto tr_valid; 4374 4375 case 1: /* Vendor */ 4376 len = sizeof(dwc_otg_vendor); 4377 ptr = (const void *)&dwc_otg_vendor; 4378 goto tr_valid; 4379 4380 case 2: /* Product */ 4381 len = sizeof(dwc_otg_product); 4382 ptr = (const void *)&dwc_otg_product; 4383 goto tr_valid; 4384 default: 4385 break; 4386 } 4387 break; 4388 default: 4389 goto tr_stalled; 4390 } 4391 goto tr_stalled; 4392 4393 tr_handle_get_config: 4394 len = 1; 4395 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4396 goto tr_valid; 4397 4398 tr_handle_get_status: 4399 len = 2; 4400 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4401 goto tr_valid; 4402 4403 tr_handle_set_address: 4404 if (value & 0xFF00) { 4405 goto tr_stalled; 4406 } 4407 sc->sc_rt_addr = value; 4408 goto tr_valid; 4409 4410 tr_handle_set_config: 4411 if (value >= 2) { 4412 goto tr_stalled; 4413 } 4414 sc->sc_conf = value; 4415 goto tr_valid; 4416 4417 tr_handle_get_interface: 4418 len = 1; 4419 sc->sc_hub_temp.wValue[0] = 0; 4420 goto tr_valid; 4421 4422 tr_handle_get_tt_state: 4423 tr_handle_get_class_status: 4424 tr_handle_get_iface_status: 4425 tr_handle_get_ep_status: 4426 len = 2; 4427 USETW(sc->sc_hub_temp.wValue, 0); 4428 goto tr_valid; 4429 4430 tr_handle_set_halt: 4431 tr_handle_set_interface: 4432 tr_handle_set_wakeup: 4433 tr_handle_clear_wakeup: 4434 tr_handle_clear_halt: 4435 goto tr_valid; 4436 4437 tr_handle_clear_port_feature: 4438 if (index != 1) 4439 goto tr_stalled; 4440 4441 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4442 4443 switch (value) { 4444 case UHF_PORT_SUSPEND: 4445 dwc_otg_wakeup_peer(sc); 4446 break; 4447 4448 case UHF_PORT_ENABLE: 4449 if (sc->sc_flags.status_device_mode == 0) { 4450 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4451 sc->sc_hprt_val | HPRT_PRTENA); 4452 } 4453 sc->sc_flags.port_enabled = 0; 4454 break; 4455 4456 case UHF_C_PORT_RESET: 4457 sc->sc_flags.change_reset = 0; 4458 break; 4459 4460 case UHF_C_PORT_ENABLE: 4461 sc->sc_flags.change_enabled = 0; 4462 break; 4463 4464 case UHF_C_PORT_OVER_CURRENT: 4465 sc->sc_flags.change_over_current = 0; 4466 break; 4467 4468 case UHF_PORT_TEST: 4469 case UHF_PORT_INDICATOR: 4470 /* nops */ 4471 break; 4472 4473 case UHF_PORT_POWER: 4474 sc->sc_flags.port_powered = 0; 4475 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4476 sc->sc_hprt_val = 0; 4477 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4478 } 4479 dwc_otg_pull_down(sc); 4480 dwc_otg_clocks_off(sc); 4481 break; 4482 4483 case UHF_C_PORT_CONNECTION: 4484 /* clear connect change flag */ 4485 sc->sc_flags.change_connect = 0; 4486 break; 4487 4488 case UHF_C_PORT_SUSPEND: 4489 sc->sc_flags.change_suspend = 0; 4490 break; 4491 4492 default: 4493 err = USB_ERR_IOERROR; 4494 goto done; 4495 } 4496 goto tr_valid; 4497 4498 tr_handle_set_port_feature: 4499 if (index != 1) { 4500 goto tr_stalled; 4501 } 4502 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4503 4504 switch (value) { 4505 case UHF_PORT_ENABLE: 4506 break; 4507 4508 case UHF_PORT_SUSPEND: 4509 if (sc->sc_flags.status_device_mode == 0) { 4510 /* set suspend BIT */ 4511 sc->sc_hprt_val |= HPRT_PRTSUSP; 4512 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4513 4514 /* generate HUB suspend event */ 4515 dwc_otg_suspend_irq(sc); 4516 } 4517 break; 4518 4519 case UHF_PORT_RESET: 4520 if (sc->sc_flags.status_device_mode == 0) { 4521 4522 DPRINTF("PORT RESET\n"); 4523 4524 /* enable PORT reset */ 4525 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4526 4527 /* Wait 62.5ms for reset to complete */ 4528 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4529 4530 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4531 4532 /* Wait 62.5ms for reset to complete */ 4533 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4534 4535 /* reset FIFOs */ 4536 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4537 4538 sc->sc_flags.change_reset = 1; 4539 } else { 4540 err = USB_ERR_IOERROR; 4541 } 4542 break; 4543 4544 case UHF_PORT_TEST: 4545 case UHF_PORT_INDICATOR: 4546 /* nops */ 4547 break; 4548 case UHF_PORT_POWER: 4549 sc->sc_flags.port_powered = 1; 4550 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4551 sc->sc_hprt_val |= HPRT_PRTPWR; 4552 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4553 } 4554 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4555 /* pull up D+, if any */ 4556 dwc_otg_pull_up(sc); 4557 } 4558 break; 4559 default: 4560 err = USB_ERR_IOERROR; 4561 goto done; 4562 } 4563 goto tr_valid; 4564 4565 tr_handle_get_port_status: 4566 4567 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4568 4569 if (index != 1) 4570 goto tr_stalled; 4571 4572 if (sc->sc_flags.status_vbus) 4573 dwc_otg_clocks_on(sc); 4574 else 4575 dwc_otg_clocks_off(sc); 4576 4577 /* Select Device Side Mode */ 4578 4579 if (sc->sc_flags.status_device_mode) { 4580 value = UPS_PORT_MODE_DEVICE; 4581 dwc_otg_timer_stop(sc); 4582 } else { 4583 value = 0; 4584 dwc_otg_timer_start(sc); 4585 } 4586 4587 if (sc->sc_flags.status_high_speed) 4588 value |= UPS_HIGH_SPEED; 4589 else if (sc->sc_flags.status_low_speed) 4590 value |= UPS_LOW_SPEED; 4591 4592 if (sc->sc_flags.port_powered) 4593 value |= UPS_PORT_POWER; 4594 4595 if (sc->sc_flags.port_enabled) 4596 value |= UPS_PORT_ENABLED; 4597 4598 if (sc->sc_flags.port_over_current) 4599 value |= UPS_OVERCURRENT_INDICATOR; 4600 4601 if (sc->sc_flags.status_vbus && 4602 sc->sc_flags.status_bus_reset) 4603 value |= UPS_CURRENT_CONNECT_STATUS; 4604 4605 if (sc->sc_flags.status_suspend) 4606 value |= UPS_SUSPEND; 4607 4608 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4609 4610 value = 0; 4611 4612 if (sc->sc_flags.change_connect) 4613 value |= UPS_C_CONNECT_STATUS; 4614 if (sc->sc_flags.change_suspend) 4615 value |= UPS_C_SUSPEND; 4616 if (sc->sc_flags.change_reset) 4617 value |= UPS_C_PORT_RESET; 4618 if (sc->sc_flags.change_over_current) 4619 value |= UPS_C_OVERCURRENT_INDICATOR; 4620 4621 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4622 len = sizeof(sc->sc_hub_temp.ps); 4623 goto tr_valid; 4624 4625 tr_handle_get_class_descriptor: 4626 if (value & 0xFF) { 4627 goto tr_stalled; 4628 } 4629 ptr = (const void *)&dwc_otg_hubd; 4630 len = sizeof(dwc_otg_hubd); 4631 goto tr_valid; 4632 4633 tr_stalled: 4634 err = USB_ERR_STALLED; 4635 tr_valid: 4636 done: 4637 *plength = len; 4638 *pptr = ptr; 4639 return (err); 4640 } 4641 4642 static void 4643 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4644 { 4645 struct usb_xfer *xfer; 4646 void *last_obj; 4647 uint32_t ntd; 4648 uint32_t n; 4649 uint8_t ep_no; 4650 uint8_t ep_type; 4651 4652 xfer = parm->curr_xfer; 4653 4654 /* 4655 * NOTE: This driver does not use any of the parameters that 4656 * are computed from the following values. Just set some 4657 * reasonable dummies: 4658 */ 4659 parm->hc_max_packet_size = 0x500; 4660 parm->hc_max_packet_count = 3; 4661 parm->hc_max_frame_size = 3 * 0x500; 4662 4663 usbd_transfer_setup_sub(parm); 4664 4665 /* 4666 * compute maximum number of TDs 4667 */ 4668 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4669 4670 if (ep_type == UE_CONTROL) { 4671 4672 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4673 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4674 } else { 4675 4676 ntd = xfer->nframes + 1 /* SYNC */ ; 4677 } 4678 4679 /* 4680 * check if "usbd_transfer_setup_sub" set an error 4681 */ 4682 if (parm->err) 4683 return; 4684 4685 /* 4686 * allocate transfer descriptors 4687 */ 4688 last_obj = NULL; 4689 4690 ep_no = xfer->endpointno & UE_ADDR; 4691 4692 /* 4693 * Check for a valid endpoint profile in USB device mode: 4694 */ 4695 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4696 const struct usb_hw_ep_profile *pf; 4697 4698 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4699 4700 if (pf == NULL) { 4701 /* should not happen */ 4702 parm->err = USB_ERR_INVAL; 4703 return; 4704 } 4705 } 4706 4707 /* align data */ 4708 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4709 4710 for (n = 0; n != ntd; n++) { 4711 4712 struct dwc_otg_td *td; 4713 4714 if (parm->buf) { 4715 4716 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4717 4718 /* compute shared bandwidth resource index for TT */ 4719 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4720 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4721 td->tt_index = parm->udev->device_index; 4722 else 4723 td->tt_index = parm->udev->parent_hs_hub->device_index; 4724 } else { 4725 td->tt_index = parm->udev->device_index; 4726 } 4727 4728 /* init TD */ 4729 td->max_packet_size = xfer->max_packet_size; 4730 td->max_packet_count = xfer->max_packet_count; 4731 td->ep_no = ep_no; 4732 td->ep_type = ep_type; 4733 td->obj_next = last_obj; 4734 4735 last_obj = td; 4736 } 4737 parm->size[0] += sizeof(*td); 4738 } 4739 4740 xfer->td_start[0] = last_obj; 4741 } 4742 4743 static void 4744 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4745 { 4746 return; 4747 } 4748 4749 static void 4750 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4751 struct usb_endpoint *ep) 4752 { 4753 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4754 4755 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4756 ep, udev->address, 4757 edesc->bEndpointAddress, udev->flags.usb_mode, 4758 sc->sc_rt_addr, udev->device_index); 4759 4760 if (udev->device_index != sc->sc_rt_addr) { 4761 4762 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4763 if (udev->speed != USB_SPEED_FULL && 4764 udev->speed != USB_SPEED_HIGH) { 4765 /* not supported */ 4766 return; 4767 } 4768 } else { 4769 if (udev->speed == USB_SPEED_HIGH) { 4770 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4771 /* high bandwidth endpoint - not tested */ 4772 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4773 return; 4774 } 4775 } 4776 } 4777 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4778 ep->methods = &dwc_otg_device_isoc_methods; 4779 else 4780 ep->methods = &dwc_otg_device_non_isoc_methods; 4781 } 4782 } 4783 4784 static void 4785 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4786 { 4787 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4788 4789 switch (state) { 4790 case USB_HW_POWER_SUSPEND: 4791 dwc_otg_suspend(sc); 4792 break; 4793 case USB_HW_POWER_SHUTDOWN: 4794 dwc_otg_uninit(sc); 4795 break; 4796 case USB_HW_POWER_RESUME: 4797 dwc_otg_resume(sc); 4798 break; 4799 default: 4800 break; 4801 } 4802 } 4803 4804 static void 4805 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4806 { 4807 /* DMA delay - wait until any use of memory is finished */ 4808 *pus = (2125); /* microseconds */ 4809 } 4810 4811 static void 4812 dwc_otg_device_resume(struct usb_device *udev) 4813 { 4814 DPRINTF("\n"); 4815 4816 /* poll all transfers again to restart resumed ones */ 4817 dwc_otg_do_poll(udev->bus); 4818 } 4819 4820 static void 4821 dwc_otg_device_suspend(struct usb_device *udev) 4822 { 4823 DPRINTF("\n"); 4824 } 4825 4826 static const struct usb_bus_methods dwc_otg_bus_methods = 4827 { 4828 .endpoint_init = &dwc_otg_ep_init, 4829 .xfer_setup = &dwc_otg_xfer_setup, 4830 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4831 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4832 .xfer_stall = &dwc_otg_xfer_stall, 4833 .set_stall = &dwc_otg_set_stall, 4834 .clear_stall = &dwc_otg_clear_stall, 4835 .roothub_exec = &dwc_otg_roothub_exec, 4836 .xfer_poll = &dwc_otg_do_poll, 4837 .device_state_change = &dwc_otg_device_state_change, 4838 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4839 .get_dma_delay = &dwc_otg_get_dma_delay, 4840 .device_resume = &dwc_otg_device_resume, 4841 .device_suspend = &dwc_otg_device_suspend, 4842 }; 4843