1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2UDEV(pc) \ 93 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_OTGINTMSK | \ 102 GINTMSK_PRTINTMSK) 103 104 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 105 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 106 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 107 GINTSTS_SESSREQINT) 108 109 static int dwc_otg_use_hsic; 110 111 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 112 113 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 114 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 115 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 116 117 #ifdef USB_DEBUG 118 static int dwc_otg_debug; 119 120 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 121 &dwc_otg_debug, 0, "DWC OTG debug level"); 122 #endif 123 124 #define DWC_OTG_INTR_ENDPT 1 125 126 /* prototypes */ 127 128 static const struct usb_bus_methods dwc_otg_bus_methods; 129 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 130 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 131 132 static dwc_otg_cmd_t dwc_otg_setup_rx; 133 static dwc_otg_cmd_t dwc_otg_data_rx; 134 static dwc_otg_cmd_t dwc_otg_data_tx; 135 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 136 137 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 138 static dwc_otg_cmd_t dwc_otg_host_data_tx; 139 static dwc_otg_cmd_t dwc_otg_host_data_rx; 140 141 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 142 static void dwc_otg_do_poll(struct usb_bus *); 143 static void dwc_otg_standard_done(struct usb_xfer *); 144 static void dwc_otg_root_intr(struct dwc_otg_softc *); 145 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 146 static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); 147 148 /* 149 * Here is a configuration that the chip supports. 150 */ 151 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 152 153 [0] = { 154 .max_in_frame_size = 64,/* fixed */ 155 .max_out_frame_size = 64, /* fixed */ 156 .is_simplex = 1, 157 .support_control = 1, 158 } 159 }; 160 161 static void 162 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 163 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 164 { 165 struct dwc_otg_softc *sc; 166 167 sc = DWC_OTG_BUS2SC(udev->bus); 168 169 if (ep_addr < sc->sc_dev_ep_max) 170 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 171 else 172 *ppf = NULL; 173 } 174 175 static int 176 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 177 { 178 struct dwc_otg_profile *pf; 179 uint32_t fifo_size; 180 uint32_t fifo_regs; 181 uint32_t tx_start; 182 uint8_t x; 183 184 fifo_size = sc->sc_fifo_size; 185 186 /* 187 * NOTE: Reserved fixed size area at end of RAM, which must 188 * not be allocated to the FIFOs: 189 */ 190 fifo_regs = 4 * 16; 191 192 if (fifo_size < fifo_regs) { 193 DPRINTF("Too little FIFO\n"); 194 return (EINVAL); 195 } 196 197 /* subtract FIFO regs from total once */ 198 fifo_size -= fifo_regs; 199 200 /* split equally for IN and OUT */ 201 fifo_size /= 2; 202 203 /* align to 4 bytes boundary */ 204 fifo_size &= ~3; 205 206 /* set global receive FIFO size */ 207 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 208 209 tx_start = fifo_size; 210 211 if (fifo_size < 64) { 212 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 213 return (EINVAL); 214 } 215 216 /* disable any leftover host channels */ 217 for (x = 0; x != sc->sc_host_ch_max; x++) { 218 if (sc->sc_chan_state[x].wait_sof == 0) 219 continue; 220 dwc_otg_host_channel_disable(sc, x); 221 } 222 223 if (mode == DWC_MODE_HOST) { 224 225 /* reset active endpoints */ 226 sc->sc_active_rx_ep = 0; 227 228 /* split equally for periodic and non-periodic */ 229 fifo_size /= 2; 230 231 /* align to 4 bytes boundary */ 232 fifo_size &= ~3; 233 234 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 235 ((fifo_size / 4) << 16) | 236 (tx_start / 4)); 237 238 tx_start += fifo_size; 239 240 for (x = 0; x != sc->sc_host_ch_max; x++) { 241 /* disable all host interrupts */ 242 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 0); 243 } 244 245 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 246 ((fifo_size / 4) << 16) | 247 (tx_start / 4)); 248 249 /* reset host channel state */ 250 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 251 252 /* reset FIFO TX levels */ 253 sc->sc_tx_cur_p_level = 0; 254 sc->sc_tx_cur_np_level = 0; 255 256 /* store maximum periodic and non-periodic FIFO TX size */ 257 sc->sc_tx_max_size = fifo_size; 258 259 /* disable all host channel interrupts */ 260 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 0); 261 } 262 263 if (mode == DWC_MODE_DEVICE) { 264 265 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 266 (0x10 << 16) | (tx_start / 4)); 267 fifo_size -= 0x40; 268 tx_start += 0x40; 269 270 /* setup control endpoint profile */ 271 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 272 273 /* reset active endpoints */ 274 sc->sc_active_rx_ep = 1; 275 276 for (x = 1; x != sc->sc_dev_ep_max; x++) { 277 278 pf = sc->sc_hw_ep_profile + x; 279 280 pf->usb.max_out_frame_size = 1024 * 3; 281 pf->usb.is_simplex = 0; /* assume duplex */ 282 pf->usb.support_bulk = 1; 283 pf->usb.support_interrupt = 1; 284 pf->usb.support_isochronous = 1; 285 pf->usb.support_out = 1; 286 287 if (x < sc->sc_dev_in_ep_max) { 288 uint32_t limit; 289 290 limit = (x == 1) ? DWC_OTG_MAX_TXN : 291 (DWC_OTG_MAX_TXN / 2); 292 293 if (fifo_size >= limit) { 294 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 295 ((limit / 4) << 16) | 296 (tx_start / 4)); 297 tx_start += limit; 298 fifo_size -= limit; 299 pf->usb.max_in_frame_size = 0x200; 300 pf->usb.support_in = 1; 301 pf->max_buffer = limit; 302 303 } else if (fifo_size >= 0x80) { 304 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 305 ((0x80 / 4) << 16) | (tx_start / 4)); 306 tx_start += 0x80; 307 fifo_size -= 0x80; 308 pf->usb.max_in_frame_size = 0x40; 309 pf->usb.support_in = 1; 310 311 } else { 312 pf->usb.is_simplex = 1; 313 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 314 (0x0 << 16) | (tx_start / 4)); 315 } 316 } else { 317 pf->usb.is_simplex = 1; 318 } 319 320 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 321 pf->usb.max_in_frame_size, 322 pf->usb.max_out_frame_size); 323 } 324 } 325 326 /* reset RX FIFO */ 327 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 328 GRSTCTL_RXFFLSH); 329 330 if (mode != DWC_MODE_OTG) { 331 /* reset all TX FIFOs */ 332 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 333 GRSTCTL_TXFIFO(0x10) | 334 GRSTCTL_TXFFLSH); 335 } else { 336 /* reset active endpoints */ 337 sc->sc_active_rx_ep = 0; 338 339 /* reset periodic and non-periodic FIFO TX size */ 340 sc->sc_tx_max_size = fifo_size; 341 342 /* reset host channel state */ 343 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 344 345 /* reset FIFO TX levels */ 346 sc->sc_tx_cur_p_level = 0; 347 sc->sc_tx_cur_np_level = 0; 348 } 349 return (0); 350 } 351 352 static void 353 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 354 { 355 356 /* 357 * Disabled until further. Assuming that the register is already 358 * programmed correctly by the boot loader. 359 */ 360 #if 0 361 uint32_t temp; 362 363 /* setup HOST frame interval register, based on existing value */ 364 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 365 if (temp >= 10000) 366 temp /= 1000; 367 else 368 temp /= 125; 369 370 /* figure out nearest X-tal value */ 371 if (temp >= 54) 372 temp = 60; /* MHz */ 373 else if (temp >= 39) 374 temp = 48; /* MHz */ 375 else 376 temp = 30; /* MHz */ 377 378 if (sc->sc_flags.status_high_speed) 379 temp *= 125; 380 else 381 temp *= 1000; 382 383 DPRINTF("HFIR=0x%08x\n", temp); 384 385 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 386 #endif 387 } 388 389 static void 390 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 391 { 392 if (sc->sc_flags.clocks_off && 393 sc->sc_flags.port_powered) { 394 395 DPRINTFN(5, "\n"); 396 397 /* TODO - platform specific */ 398 399 sc->sc_flags.clocks_off = 0; 400 } 401 } 402 403 static void 404 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 405 { 406 if (!sc->sc_flags.clocks_off) { 407 408 DPRINTFN(5, "\n"); 409 410 /* TODO - platform specific */ 411 412 sc->sc_flags.clocks_off = 1; 413 } 414 } 415 416 static void 417 dwc_otg_pull_up(struct dwc_otg_softc *sc) 418 { 419 uint32_t temp; 420 421 /* pullup D+, if possible */ 422 423 if (!sc->sc_flags.d_pulled_up && 424 sc->sc_flags.port_powered) { 425 sc->sc_flags.d_pulled_up = 1; 426 427 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 428 temp &= ~DCTL_SFTDISCON; 429 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 430 } 431 } 432 433 static void 434 dwc_otg_pull_down(struct dwc_otg_softc *sc) 435 { 436 uint32_t temp; 437 438 /* pulldown D+, if possible */ 439 440 if (sc->sc_flags.d_pulled_up) { 441 sc->sc_flags.d_pulled_up = 0; 442 443 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 444 temp |= DCTL_SFTDISCON; 445 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 446 } 447 } 448 449 static void 450 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 451 { 452 /* In device mode we don't use the SOF interrupt */ 453 if (sc->sc_flags.status_device_mode != 0 || 454 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 455 return; 456 sc->sc_irq_mask |= GINTMSK_SOFMSK; 457 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 458 } 459 460 static void 461 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 462 { 463 if (sc->sc_flags.status_suspend) { 464 /* update status bits */ 465 sc->sc_flags.status_suspend = 0; 466 sc->sc_flags.change_suspend = 1; 467 468 if (sc->sc_flags.status_device_mode) { 469 /* 470 * Disable resume interrupt and enable suspend 471 * interrupt: 472 */ 473 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 474 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 475 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 476 } 477 478 /* complete root HUB interrupt endpoint */ 479 dwc_otg_root_intr(sc); 480 } 481 } 482 483 static void 484 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 485 { 486 if (!sc->sc_flags.status_suspend) { 487 /* update status bits */ 488 sc->sc_flags.status_suspend = 1; 489 sc->sc_flags.change_suspend = 1; 490 491 if (sc->sc_flags.status_device_mode) { 492 /* 493 * Disable suspend interrupt and enable resume 494 * interrupt: 495 */ 496 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 497 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 498 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 499 } 500 501 /* complete root HUB interrupt endpoint */ 502 dwc_otg_root_intr(sc); 503 } 504 } 505 506 static void 507 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 508 { 509 if (!sc->sc_flags.status_suspend) 510 return; 511 512 DPRINTFN(5, "Remote wakeup\n"); 513 514 if (sc->sc_flags.status_device_mode) { 515 uint32_t temp; 516 517 /* enable remote wakeup signalling */ 518 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 519 temp |= DCTL_RMTWKUPSIG; 520 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 521 522 /* Wait 8ms for remote wakeup to complete. */ 523 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 524 525 temp &= ~DCTL_RMTWKUPSIG; 526 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 527 } else { 528 /* enable USB port */ 529 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 530 531 /* wait 10ms */ 532 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 533 534 /* resume port */ 535 sc->sc_hprt_val |= HPRT_PRTRES; 536 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 537 538 /* Wait 100ms for resume signalling to complete. */ 539 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 540 541 /* clear suspend and resume */ 542 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 544 545 /* Wait 4ms */ 546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 547 } 548 549 /* need to fake resume IRQ */ 550 dwc_otg_resume_irq(sc); 551 } 552 553 static void 554 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 555 { 556 uint32_t temp; 557 558 DPRINTFN(5, "addr=%d\n", addr); 559 560 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 561 temp &= ~DCFG_DEVADDR_SET(0x7F); 562 temp |= DCFG_DEVADDR_SET(addr); 563 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 564 } 565 566 static void 567 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 568 { 569 DPRINTFN(5, "RX status clear\n"); 570 571 if (sc->sc_flags.status_device_mode != 0) { 572 /* enable RX FIFO level interrupt */ 573 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 574 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 575 } 576 577 /* clear cached status */ 578 sc->sc_last_rx_status = 0; 579 } 580 581 static void 582 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 583 { 584 uint32_t hcint; 585 586 /* clear all pending interrupts */ 587 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 588 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 589 590 /* clear buffered interrupts */ 591 sc->sc_chan_state[x].hcint = 0; 592 } 593 594 static uint8_t 595 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t which, uint8_t is_out) 596 { 597 uint32_t tx_p_size; 598 uint32_t tx_np_size; 599 uint8_t x; 600 601 if (td->channel[which] < DWC_OTG_MAX_CHANNELS) 602 return (0); /* already allocated */ 603 604 /* check if device is suspended */ 605 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 606 return (1); /* busy - cannot transfer data */ 607 608 /* compute needed TX FIFO size */ 609 if (is_out != 0) { 610 if (td->ep_type == UE_INTERRUPT || 611 td->ep_type == UE_ISOCHRONOUS) { 612 tx_p_size = td->max_packet_size; 613 tx_np_size = 0; 614 if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) 615 tx_p_size = HCSPLT_XACTLEN_BURST; 616 if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { 617 DPRINTF("Too little FIFO space\n"); 618 return (1); /* too little FIFO */ 619 } 620 } else { 621 tx_p_size = 0; 622 tx_np_size = td->max_packet_size; 623 if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) 624 tx_np_size = HCSPLT_XACTLEN_BURST; 625 if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { 626 DPRINTF("Too little FIFO space\n"); 627 return (1); /* too little FIFO */ 628 } 629 } 630 } else { 631 /* not a TX transaction */ 632 tx_p_size = 0; 633 tx_np_size = 0; 634 } 635 636 for (x = 0; x != sc->sc_host_ch_max; x++) { 637 if (sc->sc_chan_state[x].allocated != 0) 638 continue; 639 /* check if channel is still enabled */ 640 if (sc->sc_chan_state[x].wait_sof != 0) 641 continue; 642 643 sc->sc_chan_state[x].allocated = 1; 644 sc->sc_chan_state[x].tx_p_size = tx_p_size; 645 sc->sc_chan_state[x].tx_np_size = tx_np_size; 646 647 /* keep track of used TX FIFO, if any */ 648 sc->sc_tx_cur_p_level += tx_p_size; 649 sc->sc_tx_cur_np_level += tx_np_size; 650 651 /* clear interrupts */ 652 dwc_otg_clear_hcint(sc, x); 653 654 DPRINTF("CH=%d HCCHAR=0x%08x " 655 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 656 657 /* set active channel */ 658 sc->sc_active_rx_ep |= (1 << x); 659 660 /* set channel */ 661 td->channel[which] = x; 662 663 return (0); /* allocated */ 664 } 665 /* wait a bit */ 666 dwc_otg_enable_sof_irq(sc); 667 return (1); /* busy */ 668 } 669 670 static void 671 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t which) 672 { 673 uint8_t x; 674 675 if (td->channel[which] >= DWC_OTG_MAX_CHANNELS) 676 return; /* already freed */ 677 678 /* free channel */ 679 x = td->channel[which]; 680 td->channel[which] = DWC_OTG_MAX_CHANNELS; 681 682 DPRINTF("CH=%d\n", x); 683 684 /* 685 * We need to let programmed host channels run till complete 686 * else the host channel will stop functioning. Assume that 687 * after a fixed given amount of time the host channel is no 688 * longer doing any USB traffic: 689 */ 690 if (td->ep_type == UE_ISOCHRONOUS || td->ep_type == UE_INTERRUPT) { 691 /* double buffered */ 692 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; 693 } else { 694 /* single buffered */ 695 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; 696 } 697 698 sc->sc_chan_state[x].allocated = 0; 699 700 /* ack any pending messages */ 701 if (sc->sc_last_rx_status != 0 && 702 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 703 dwc_otg_common_rx_ack(sc); 704 } 705 706 /* clear active channel */ 707 sc->sc_active_rx_ep &= ~(1 << x); 708 } 709 710 static uint8_t 711 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 712 { 713 struct usb_device_request req __aligned(4); 714 uint32_t hcint; 715 uint32_t hcchar; 716 uint8_t delta; 717 718 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 719 hcint = sc->sc_chan_state[td->channel[0]].hcint; 720 721 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 722 td->channel[0], td->state, hcint, 723 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 724 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 725 } else { 726 hcint = 0; 727 goto check_state; 728 } 729 730 if (hcint & (HCINT_RETRY | 731 HCINT_ACK | HCINT_NYET)) { 732 /* give success bits priority over failure bits */ 733 } else if (hcint & HCINT_STALL) { 734 DPRINTF("CH=%d STALL\n", td->channel[0]); 735 td->error_stall = 1; 736 td->error_any = 1; 737 goto complete; 738 } else if (hcint & HCINT_ERRORS) { 739 DPRINTF("CH=%d ERROR\n", td->channel[0]); 740 td->errcnt++; 741 if (td->hcsplt != 0 || td->errcnt >= 3) { 742 td->error_any = 1; 743 goto complete; 744 } 745 } 746 747 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 748 HCINT_ACK | HCINT_NYET)) { 749 if (!(hcint & HCINT_ERRORS)) 750 td->errcnt = 0; 751 } 752 753 check_state: 754 switch (td->state) { 755 case DWC_CHAN_ST_START: 756 goto send_pkt; 757 758 case DWC_CHAN_ST_WAIT_ANE: 759 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 760 td->did_nak++; 761 td->tt_scheduled = 0; 762 goto send_pkt; 763 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 764 td->offset += td->tx_bytes; 765 td->remainder -= td->tx_bytes; 766 td->toggle = 1; 767 td->tt_scheduled = 0; 768 goto complete; 769 } 770 break; 771 772 case DWC_CHAN_ST_WAIT_S_ANE: 773 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 774 td->did_nak++; 775 td->tt_scheduled = 0; 776 goto send_pkt; 777 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 778 goto send_cpkt; 779 } 780 break; 781 782 case DWC_CHAN_ST_WAIT_C_ANE: 783 if (hcint & HCINT_NYET) { 784 goto send_cpkt; 785 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 786 td->did_nak++; 787 td->tt_scheduled = 0; 788 goto send_pkt; 789 } else if (hcint & HCINT_ACK) { 790 td->offset += td->tx_bytes; 791 td->remainder -= td->tx_bytes; 792 td->toggle = 1; 793 goto complete; 794 } 795 break; 796 797 case DWC_CHAN_ST_WAIT_C_PKT: 798 goto send_cpkt; 799 800 default: 801 break; 802 } 803 goto busy; 804 805 send_pkt: 806 /* free existing channel, if any */ 807 dwc_otg_host_channel_free(sc, td, 0); 808 809 if (sizeof(req) != td->remainder) { 810 td->error_any = 1; 811 goto complete; 812 } 813 814 if (td->hcsplt != 0) { 815 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 816 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 817 td->state = DWC_CHAN_ST_START; 818 goto busy; 819 } 820 delta = sc->sc_last_frame_num - td->tt_start_slot; 821 if (delta > 5) { 822 /* missed it */ 823 td->tt_scheduled = 0; 824 td->state = DWC_CHAN_ST_START; 825 goto busy; 826 } 827 } 828 829 /* allocate a new channel */ 830 if (dwc_otg_host_channel_alloc(sc, td, 0, 1)) { 831 td->state = DWC_CHAN_ST_START; 832 goto busy; 833 } 834 835 if (td->hcsplt != 0) { 836 td->hcsplt &= ~HCSPLT_COMPSPLT; 837 td->state = DWC_CHAN_ST_WAIT_S_ANE; 838 } else { 839 td->state = DWC_CHAN_ST_WAIT_ANE; 840 } 841 842 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 843 844 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 845 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 846 (1 << HCTSIZ_PKTCNT_SHIFT) | 847 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 848 849 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 850 851 hcchar = td->hcchar; 852 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 853 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 854 855 /* must enable channel before writing data to FIFO */ 856 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 857 858 /* transfer data into FIFO */ 859 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 860 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 861 862 /* store number of bytes transmitted */ 863 td->tx_bytes = sizeof(req); 864 goto busy; 865 866 send_cpkt: 867 /* free existing channel, if any */ 868 dwc_otg_host_channel_free(sc, td, 0); 869 870 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 871 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 872 td->state = DWC_CHAN_ST_WAIT_C_PKT; 873 goto busy; 874 } 875 delta = sc->sc_last_frame_num - td->tt_start_slot; 876 if (delta > DWC_OTG_TT_SLOT_MAX) { 877 /* we missed the service interval */ 878 if (td->ep_type != UE_ISOCHRONOUS) 879 td->error_any = 1; 880 goto complete; 881 } 882 /* allocate a new channel */ 883 if (dwc_otg_host_channel_alloc(sc, td, 0, 0)) { 884 td->state = DWC_CHAN_ST_WAIT_C_PKT; 885 goto busy; 886 } 887 888 /* wait until next slot before trying again */ 889 td->tt_complete_slot++; 890 891 td->hcsplt |= HCSPLT_COMPSPLT; 892 td->state = DWC_CHAN_ST_WAIT_C_ANE; 893 894 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 895 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 896 897 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 898 899 hcchar = td->hcchar; 900 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 901 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 902 903 /* must enable channel before writing data to FIFO */ 904 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 905 906 busy: 907 return (1); /* busy */ 908 909 complete: 910 dwc_otg_host_channel_free(sc, td, 0); 911 return (0); /* complete */ 912 } 913 914 static uint8_t 915 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 916 { 917 struct usb_device_request req __aligned(4); 918 uint32_t temp; 919 uint16_t count; 920 921 /* check endpoint status */ 922 923 if (sc->sc_last_rx_status == 0) 924 goto not_complete; 925 926 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 927 goto not_complete; 928 929 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 930 GRXSTSRD_DPID_DATA0) { 931 /* release FIFO */ 932 dwc_otg_common_rx_ack(sc); 933 goto not_complete; 934 } 935 936 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 937 GRXSTSRD_STP_DATA) { 938 /* release FIFO */ 939 dwc_otg_common_rx_ack(sc); 940 goto not_complete; 941 } 942 943 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 944 945 /* clear did stall */ 946 td->did_stall = 0; 947 948 /* get the packet byte count */ 949 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 950 951 /* verify data length */ 952 if (count != td->remainder) { 953 DPRINTFN(0, "Invalid SETUP packet " 954 "length, %d bytes\n", count); 955 /* release FIFO */ 956 dwc_otg_common_rx_ack(sc); 957 goto not_complete; 958 } 959 if (count != sizeof(req)) { 960 DPRINTFN(0, "Unsupported SETUP packet " 961 "length, %d bytes\n", count); 962 /* release FIFO */ 963 dwc_otg_common_rx_ack(sc); 964 goto not_complete; 965 } 966 967 /* copy in control request */ 968 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 969 970 /* copy data into real buffer */ 971 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 972 973 td->offset = sizeof(req); 974 td->remainder = 0; 975 976 /* sneak peek the set address */ 977 if ((req.bmRequestType == UT_WRITE_DEVICE) && 978 (req.bRequest == UR_SET_ADDRESS)) { 979 /* must write address before ZLP */ 980 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 981 } 982 983 /* don't send any data by default */ 984 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 985 DXEPTSIZ_SET_NPKT(0) | 986 DXEPTSIZ_SET_NBYTES(0)); 987 988 temp = sc->sc_in_ctl[0]; 989 990 /* enable IN endpoint */ 991 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 992 temp | DIEPCTL_EPENA); 993 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 994 temp | DIEPCTL_SNAK); 995 996 /* reset IN endpoint buffer */ 997 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 998 GRSTCTL_TXFIFO(0) | 999 GRSTCTL_TXFFLSH); 1000 1001 /* acknowledge RX status */ 1002 dwc_otg_common_rx_ack(sc); 1003 return (0); /* complete */ 1004 1005 not_complete: 1006 /* abort any ongoing transfer, before enabling again */ 1007 1008 temp = sc->sc_out_ctl[0]; 1009 1010 temp |= DOEPCTL_EPENA | 1011 DOEPCTL_SNAK; 1012 1013 /* enable OUT endpoint */ 1014 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1015 1016 if (!td->did_stall) { 1017 td->did_stall = 1; 1018 1019 DPRINTFN(5, "stalling IN and OUT direction\n"); 1020 1021 /* set stall after enabling endpoint */ 1022 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1023 temp | DOEPCTL_STALL); 1024 1025 temp = sc->sc_in_ctl[0]; 1026 1027 /* set stall assuming endpoint is enabled */ 1028 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1029 temp | DIEPCTL_STALL); 1030 } 1031 1032 /* setup number of buffers to receive */ 1033 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1034 DXEPTSIZ_SET_MULTI(3) | 1035 DXEPTSIZ_SET_NPKT(1) | 1036 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1037 1038 return (1); /* not complete */ 1039 } 1040 1041 static uint8_t 1042 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1043 { 1044 uint8_t delta; 1045 1046 delta = sc->sc_tmr_val - td->tmr_val; 1047 if (delta >= 128) 1048 return (1); /* busy */ 1049 1050 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1051 1052 /* set toggle, if any */ 1053 if (td->set_toggle) { 1054 td->set_toggle = 0; 1055 td->toggle = 1; 1056 } 1057 return (0); 1058 } 1059 1060 static uint8_t 1061 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1062 { 1063 if (td->ep_type == UE_ISOCHRONOUS) { 1064 /* non TT isochronous traffic */ 1065 if ((td->tmr_val != 0) || 1066 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1067 goto busy; 1068 } 1069 td->tmr_val = 1; /* executed */ 1070 td->toggle = 0; 1071 1072 } else if (td->ep_type == UE_INTERRUPT) { 1073 if (!td->tt_scheduled) 1074 goto busy; 1075 td->tt_scheduled = 0; 1076 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1077 goto busy; 1078 } else if (td->set_toggle) { 1079 td->set_toggle = 0; 1080 td->toggle = 1; 1081 } 1082 return (0); 1083 busy: 1084 return (1); 1085 } 1086 1087 static uint8_t 1088 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1089 { 1090 uint32_t hcint; 1091 uint32_t hcchar; 1092 uint32_t count; 1093 uint8_t delta; 1094 uint8_t channel; 1095 1096 channel = td->channel[td->tt_channel_tog]; 1097 1098 if (channel < DWC_OTG_MAX_CHANNELS) { 1099 hcint = sc->sc_chan_state[channel].hcint; 1100 1101 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1102 channel, td->state, hcint, 1103 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1104 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1105 } else { 1106 hcint = 0; 1107 goto check_state; 1108 } 1109 1110 /* check interrupt bits */ 1111 1112 if (hcint & (HCINT_RETRY | 1113 HCINT_ACK | HCINT_NYET)) { 1114 /* give success bits priority over failure bits */ 1115 } else if (hcint & HCINT_STALL) { 1116 DPRINTF("CH=%d STALL\n", channel); 1117 td->error_stall = 1; 1118 td->error_any = 1; 1119 goto complete; 1120 } else if (hcint & HCINT_ERRORS) { 1121 DPRINTF("CH=%d ERROR\n", channel); 1122 td->errcnt++; 1123 if (td->hcsplt != 0 || td->errcnt >= 3) { 1124 if (td->ep_type != UE_ISOCHRONOUS) { 1125 td->error_any = 1; 1126 goto complete; 1127 } 1128 } 1129 } 1130 1131 /* check endpoint status */ 1132 if (sc->sc_last_rx_status == 0) 1133 goto check_state; 1134 1135 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1136 goto check_state; 1137 1138 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1139 case GRXSTSRH_IN_DATA: 1140 1141 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1142 (int)td->state, (int)sc->sc_last_rx_status); 1143 1144 if (hcint & HCINT_SOFTWARE_ONLY) { 1145 /* 1146 * When using SPLIT transactions on interrupt 1147 * endpoints, sometimes data occurs twice. 1148 */ 1149 DPRINTF("Data already received\n"); 1150 break; 1151 } 1152 1153 /* get the packet byte count */ 1154 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1155 1156 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1157 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1158 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1159 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1160 } else { 1161 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1162 1163 /* verify the packet byte count */ 1164 if (count < td->max_packet_size) { 1165 /* we have a short packet */ 1166 td->short_pkt = 1; 1167 td->got_short = 1; 1168 } 1169 } 1170 td->toggle = 0; 1171 } else { 1172 /* verify the packet byte count */ 1173 if (count != td->max_packet_size) { 1174 if (count < td->max_packet_size) { 1175 /* we have a short packet */ 1176 td->short_pkt = 1; 1177 td->got_short = 1; 1178 } else { 1179 /* invalid USB packet */ 1180 td->error_any = 1; 1181 1182 /* release FIFO */ 1183 dwc_otg_common_rx_ack(sc); 1184 goto complete; 1185 } 1186 } 1187 td->toggle ^= 1; 1188 td->tt_scheduled = 0; 1189 } 1190 1191 /* verify the packet byte count */ 1192 if (count > td->remainder) { 1193 /* invalid USB packet */ 1194 td->error_any = 1; 1195 1196 /* release FIFO */ 1197 dwc_otg_common_rx_ack(sc); 1198 goto complete; 1199 } 1200 1201 usbd_copy_in(td->pc, td->offset, 1202 sc->sc_rx_bounce_buffer, count); 1203 1204 td->remainder -= count; 1205 td->offset += count; 1206 hcint |= HCINT_SOFTWARE_ONLY; 1207 sc->sc_chan_state[channel].hcint = hcint; 1208 break; 1209 1210 default: 1211 break; 1212 } 1213 /* release FIFO */ 1214 dwc_otg_common_rx_ack(sc); 1215 1216 check_state: 1217 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1218 HCINT_ACK | HCINT_NYET)) { 1219 if (!(hcint & HCINT_ERRORS)) 1220 td->errcnt = 0; 1221 } 1222 1223 switch (td->state) { 1224 case DWC_CHAN_ST_START: 1225 if (td->hcsplt != 0) 1226 goto receive_spkt; 1227 else 1228 goto receive_pkt; 1229 1230 case DWC_CHAN_ST_WAIT_ANE: 1231 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1232 td->did_nak++; 1233 td->tt_scheduled = 0; 1234 if (td->hcsplt != 0) 1235 goto receive_spkt; 1236 else 1237 goto receive_pkt; 1238 } else if (hcint & HCINT_NYET) { 1239 if (td->hcsplt != 0) { 1240 /* try again */ 1241 goto receive_pkt; 1242 } else { 1243 /* not a valid token for IN endpoints */ 1244 td->error_any = 1; 1245 goto complete; 1246 } 1247 } else if (hcint & HCINT_ACK) { 1248 /* wait for data - ACK arrived first */ 1249 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1250 goto busy; 1251 1252 if (td->ep_type == UE_ISOCHRONOUS) { 1253 /* check if we are complete */ 1254 if ((td->remainder == 0) || 1255 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1256 goto complete; 1257 } 1258 /* get another packet */ 1259 goto receive_pkt; 1260 } else { 1261 /* check if we are complete */ 1262 if ((td->remainder == 0) || (td->got_short != 0)) { 1263 if (td->short_pkt) 1264 goto complete; 1265 1266 /* 1267 * Else need to receive a zero length 1268 * packet. 1269 */ 1270 } 1271 td->tt_scheduled = 0; 1272 td->did_nak = 0; 1273 if (td->hcsplt != 0) 1274 goto receive_spkt; 1275 else 1276 goto receive_pkt; 1277 } 1278 } 1279 break; 1280 1281 case DWC_CHAN_ST_WAIT_S_ANE: 1282 /* 1283 * NOTE: The DWC OTG hardware provides a fake ACK in 1284 * case of interrupt and isochronous transfers: 1285 */ 1286 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1287 td->did_nak++; 1288 td->tt_scheduled = 0; 1289 goto receive_spkt; 1290 } else if (hcint & HCINT_NYET) { 1291 td->tt_scheduled = 0; 1292 goto receive_spkt; 1293 } else if (hcint & HCINT_ACK) { 1294 td->did_nak = 0; 1295 goto receive_pkt; 1296 } 1297 break; 1298 1299 case DWC_CHAN_ST_WAIT_C_PKT: 1300 goto receive_pkt; 1301 1302 default: 1303 break; 1304 } 1305 goto busy; 1306 1307 receive_pkt: 1308 /* free existing channel, if any */ 1309 dwc_otg_host_channel_free(sc, td, td->tt_channel_tog); 1310 1311 if (td->hcsplt != 0) { 1312 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1313 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1314 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1315 goto busy; 1316 } 1317 delta = sc->sc_last_frame_num - td->tt_start_slot; 1318 if (delta > DWC_OTG_TT_SLOT_MAX) { 1319 /* we missed the service interval */ 1320 if (td->ep_type != UE_ISOCHRONOUS) 1321 td->error_any = 1; 1322 goto complete; 1323 } 1324 /* complete split */ 1325 td->hcsplt |= HCSPLT_COMPSPLT; 1326 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1327 dwc_otg_host_rate_check(sc, td)) { 1328 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1329 goto busy; 1330 } 1331 1332 /* allocate a new channel */ 1333 if (dwc_otg_host_channel_alloc(sc, td, td->tt_channel_tog, 0)) { 1334 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1335 goto busy; 1336 } 1337 1338 channel = td->channel[td->tt_channel_tog]; 1339 1340 /* set toggle, if any */ 1341 if (td->set_toggle) { 1342 td->set_toggle = 0; 1343 td->toggle = 1; 1344 } 1345 1346 td->state = DWC_CHAN_ST_WAIT_ANE; 1347 1348 /* receive one packet */ 1349 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1350 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1351 (1 << HCTSIZ_PKTCNT_SHIFT) | 1352 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1353 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1354 1355 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1356 1357 hcchar = td->hcchar; 1358 hcchar |= HCCHAR_EPDIR_IN; 1359 1360 /* check if other channel is allocated */ 1361 if (td->channel[td->tt_channel_tog ^ 1] < DWC_OTG_MAX_CHANNELS) { 1362 /* second - receive after next SOF event */ 1363 if ((sc->sc_last_frame_num & 1) != 0) 1364 hcchar |= HCCHAR_ODDFRM; 1365 else 1366 hcchar &= ~HCCHAR_ODDFRM; 1367 1368 /* other channel is next */ 1369 td->tt_channel_tog ^= 1; 1370 td->tt_complete_slot++; 1371 1372 /* must enable channel before data can be received */ 1373 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1374 } else { 1375 /* first - receive after second next SOF event */ 1376 if ((sc->sc_last_frame_num & 1) == 0) 1377 hcchar |= HCCHAR_ODDFRM; 1378 else 1379 hcchar &= ~HCCHAR_ODDFRM; 1380 1381 /* must enable channel before data can be received */ 1382 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1383 1384 if (td->hcsplt != 0) { 1385 if (td->ep_type == UE_ISOCHRONOUS || td->ep_type == UE_INTERRUPT) { 1386 /* allocate a second channel */ 1387 td->tt_channel_tog ^= 1; 1388 goto receive_pkt; 1389 } else { 1390 td->tt_complete_slot++; 1391 } 1392 } 1393 } 1394 goto busy; 1395 1396 receive_spkt: 1397 /* free existing channel(s), if any */ 1398 dwc_otg_host_channel_free(sc, td, 0); 1399 dwc_otg_host_channel_free(sc, td, 1); 1400 1401 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1402 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1403 td->state = DWC_CHAN_ST_START; 1404 goto busy; 1405 } 1406 delta = sc->sc_last_frame_num - td->tt_start_slot; 1407 if (delta > 5) { 1408 /* missed it */ 1409 td->tt_scheduled = 0; 1410 td->state = DWC_CHAN_ST_START; 1411 goto busy; 1412 } 1413 1414 /* allocate a new channel */ 1415 if (dwc_otg_host_channel_alloc(sc, td, 0, 0)) { 1416 td->state = DWC_CHAN_ST_START; 1417 goto busy; 1418 } 1419 1420 channel = td->channel[0]; 1421 1422 td->hcsplt &= ~HCSPLT_COMPSPLT; 1423 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1424 1425 /* reset channel toggle */ 1426 td->tt_channel_tog = 0; 1427 1428 /* receive one packet */ 1429 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1430 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1431 1432 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1433 1434 /* send after next SOF event */ 1435 if ((sc->sc_last_frame_num & 1) == 0) 1436 td->hcchar |= HCCHAR_ODDFRM; 1437 else 1438 td->hcchar &= ~HCCHAR_ODDFRM; 1439 1440 hcchar = td->hcchar; 1441 hcchar |= HCCHAR_EPDIR_IN; 1442 1443 /* must enable channel before data can be received */ 1444 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1445 busy: 1446 return (1); /* busy */ 1447 1448 complete: 1449 dwc_otg_host_channel_free(sc, td, 0); 1450 dwc_otg_host_channel_free(sc, td, 1); 1451 return (0); /* complete */ 1452 } 1453 1454 static uint8_t 1455 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1456 { 1457 uint32_t temp; 1458 uint16_t count; 1459 uint8_t got_short; 1460 1461 got_short = 0; 1462 1463 /* check endpoint status */ 1464 if (sc->sc_last_rx_status == 0) 1465 goto not_complete; 1466 1467 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1468 goto not_complete; 1469 1470 /* check for SETUP packet */ 1471 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1472 GRXSTSRD_STP_DATA) { 1473 if (td->remainder == 0) { 1474 /* 1475 * We are actually complete and have 1476 * received the next SETUP 1477 */ 1478 DPRINTFN(5, "faking complete\n"); 1479 return (0); /* complete */ 1480 } 1481 /* 1482 * USB Host Aborted the transfer. 1483 */ 1484 td->error_any = 1; 1485 return (0); /* complete */ 1486 } 1487 1488 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1489 GRXSTSRD_OUT_DATA) { 1490 /* release FIFO */ 1491 dwc_otg_common_rx_ack(sc); 1492 goto not_complete; 1493 } 1494 1495 /* get the packet byte count */ 1496 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1497 1498 /* verify the packet byte count */ 1499 if (count != td->max_packet_size) { 1500 if (count < td->max_packet_size) { 1501 /* we have a short packet */ 1502 td->short_pkt = 1; 1503 got_short = 1; 1504 } else { 1505 /* invalid USB packet */ 1506 td->error_any = 1; 1507 1508 /* release FIFO */ 1509 dwc_otg_common_rx_ack(sc); 1510 return (0); /* we are complete */ 1511 } 1512 } 1513 /* verify the packet byte count */ 1514 if (count > td->remainder) { 1515 /* invalid USB packet */ 1516 td->error_any = 1; 1517 1518 /* release FIFO */ 1519 dwc_otg_common_rx_ack(sc); 1520 return (0); /* we are complete */ 1521 } 1522 1523 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1524 td->remainder -= count; 1525 td->offset += count; 1526 1527 /* release FIFO */ 1528 dwc_otg_common_rx_ack(sc); 1529 1530 /* check if we are complete */ 1531 if ((td->remainder == 0) || got_short) { 1532 if (td->short_pkt) { 1533 /* we are complete */ 1534 return (0); 1535 } 1536 /* else need to receive a zero length packet */ 1537 } 1538 1539 not_complete: 1540 1541 temp = sc->sc_out_ctl[td->ep_no]; 1542 1543 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1544 1545 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1546 1547 /* enable SETUP and transfer complete interrupt */ 1548 if (td->ep_no == 0) { 1549 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1550 DXEPTSIZ_SET_NPKT(1) | 1551 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1552 } else { 1553 /* allow reception of multiple packets */ 1554 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1555 DXEPTSIZ_SET_MULTI(1) | 1556 DXEPTSIZ_SET_NPKT(4) | 1557 DXEPTSIZ_SET_NBYTES(4 * 1558 ((td->max_packet_size + 3) & ~3))); 1559 } 1560 return (1); /* not complete */ 1561 } 1562 1563 static uint8_t 1564 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1565 { 1566 uint32_t count; 1567 uint32_t hcint; 1568 uint32_t hcchar; 1569 uint8_t delta; 1570 uint8_t channel; 1571 1572 channel = td->channel[td->tt_channel_tog]; 1573 1574 if (channel < DWC_OTG_MAX_CHANNELS) { 1575 hcint = sc->sc_chan_state[channel].hcint; 1576 1577 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1578 channel, td->state, hcint, 1579 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1580 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1581 } else { 1582 hcint = 0; 1583 goto check_state; 1584 } 1585 1586 if (hcint & (HCINT_RETRY | 1587 HCINT_ACK | HCINT_NYET)) { 1588 /* give success bits priority over failure bits */ 1589 } else if (hcint & HCINT_STALL) { 1590 DPRINTF("CH=%d STALL\n", channel); 1591 td->error_stall = 1; 1592 td->error_any = 1; 1593 goto complete; 1594 } else if (hcint & HCINT_ERRORS) { 1595 DPRINTF("CH=%d ERROR\n", channel); 1596 td->errcnt++; 1597 if (td->hcsplt != 0 || td->errcnt >= 3) { 1598 td->error_any = 1; 1599 goto complete; 1600 } 1601 } 1602 1603 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1604 HCINT_ACK | HCINT_NYET)) { 1605 1606 if (!(hcint & HCINT_ERRORS)) 1607 td->errcnt = 0; 1608 } 1609 1610 check_state: 1611 switch (td->state) { 1612 case DWC_CHAN_ST_START: 1613 goto send_pkt; 1614 1615 case DWC_CHAN_ST_WAIT_ANE: 1616 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1617 td->did_nak++; 1618 td->tt_scheduled = 0; 1619 goto send_pkt; 1620 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1621 td->offset += td->tx_bytes; 1622 td->remainder -= td->tx_bytes; 1623 td->toggle ^= 1; 1624 td->did_nak = 0; 1625 td->tt_scheduled = 0; 1626 1627 /* check remainder */ 1628 if (td->remainder == 0) { 1629 if (td->short_pkt) 1630 goto complete; 1631 1632 /* 1633 * Else we need to transmit a short 1634 * packet: 1635 */ 1636 } 1637 goto send_pkt; 1638 } 1639 break; 1640 1641 case DWC_CHAN_ST_WAIT_S_ANE: 1642 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1643 td->did_nak++; 1644 td->tt_scheduled = 0; 1645 goto send_pkt; 1646 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1647 td->did_nak = 0; 1648 goto send_cpkt; 1649 } 1650 break; 1651 1652 case DWC_CHAN_ST_WAIT_C_ANE: 1653 if (hcint & HCINT_NYET) { 1654 goto send_cpkt; 1655 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1656 td->did_nak++; 1657 td->tt_scheduled = 0; 1658 goto send_pkt; 1659 } else if (hcint & HCINT_ACK) { 1660 td->offset += td->tx_bytes; 1661 td->remainder -= td->tx_bytes; 1662 td->toggle ^= 1; 1663 td->did_nak = 0; 1664 td->tt_scheduled = 0; 1665 1666 /* check remainder */ 1667 if (td->remainder == 0) { 1668 if (td->short_pkt) 1669 goto complete; 1670 1671 /* else we need to transmit a short packet */ 1672 } 1673 goto send_pkt; 1674 } 1675 break; 1676 1677 case DWC_CHAN_ST_WAIT_C_PKT: 1678 goto send_cpkt; 1679 1680 case DWC_CHAN_ST_TX_WAIT_ISOC: 1681 1682 /* Check if isochronous OUT traffic is complete */ 1683 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1684 break; 1685 1686 td->offset += td->tx_bytes; 1687 td->remainder -= td->tx_bytes; 1688 1689 if (td->hcsplt != 0 || td->remainder == 0) 1690 goto complete; 1691 1692 /* check for next packet */ 1693 if (td->max_packet_count > 1) 1694 td->tt_xactpos++; 1695 1696 /* free existing channel, if any */ 1697 dwc_otg_host_channel_free(sc, td, td->tt_channel_tog); 1698 1699 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1700 1701 /* FALLTHROUGH */ 1702 1703 case DWC_CHAN_ST_TX_PKT_ISOC: 1704 if (dwc_otg_host_channel_alloc(sc, td, 0, 1)) 1705 break; 1706 channel = td->channel[0]; 1707 goto send_isoc_pkt; 1708 default: 1709 break; 1710 } 1711 goto busy; 1712 1713 send_pkt: 1714 /* free existing channel(s), if any */ 1715 dwc_otg_host_channel_free(sc, td, 0); 1716 dwc_otg_host_channel_free(sc, td, 1); 1717 1718 if (td->hcsplt != 0) { 1719 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1720 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1721 td->state = DWC_CHAN_ST_START; 1722 goto busy; 1723 } 1724 delta = sc->sc_last_frame_num - td->tt_start_slot; 1725 if (delta > 5) { 1726 /* missed it */ 1727 td->tt_scheduled = 0; 1728 td->state = DWC_CHAN_ST_START; 1729 goto busy; 1730 } 1731 } else if (dwc_otg_host_rate_check(sc, td)) { 1732 td->state = DWC_CHAN_ST_START; 1733 goto busy; 1734 } 1735 1736 /* allocate a new channel */ 1737 if (dwc_otg_host_channel_alloc(sc, td, 0, 1)) { 1738 td->state = DWC_CHAN_ST_START; 1739 goto busy; 1740 } 1741 1742 channel = td->channel[0]; 1743 1744 /* set toggle, if any */ 1745 if (td->set_toggle) { 1746 td->set_toggle = 0; 1747 td->toggle = 1; 1748 } 1749 1750 if (td->ep_type == UE_ISOCHRONOUS) { 1751 send_isoc_pkt: 1752 /* Isochronous OUT transfers don't have any ACKs */ 1753 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1754 td->hcsplt &= ~HCSPLT_COMPSPLT; 1755 if (td->hcsplt != 0) { 1756 /* get maximum transfer length */ 1757 count = td->remainder; 1758 if (count > HCSPLT_XACTLEN_BURST) { 1759 DPRINTF("TT overflow\n"); 1760 td->error = 1; 1761 goto complete; 1762 } 1763 /* Update transaction position */ 1764 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1765 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1766 } else { 1767 /* send one packet at a time */ 1768 count = td->max_packet_size; 1769 if (td->remainder < count) { 1770 /* we have a short packet */ 1771 td->short_pkt = 1; 1772 count = td->remainder; 1773 } 1774 } 1775 } else if (td->hcsplt != 0) { 1776 1777 td->hcsplt &= ~HCSPLT_COMPSPLT; 1778 1779 /* Wait for ACK/NAK/ERR from TT */ 1780 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1781 1782 /* send one packet at a time */ 1783 count = td->max_packet_size; 1784 if (td->remainder < count) { 1785 /* we have a short packet */ 1786 td->short_pkt = 1; 1787 count = td->remainder; 1788 } 1789 } else { 1790 /* Wait for ACK/NAK/STALL from device */ 1791 td->state = DWC_CHAN_ST_WAIT_ANE; 1792 1793 /* send one packet at a time */ 1794 count = td->max_packet_size; 1795 if (td->remainder < count) { 1796 /* we have a short packet */ 1797 td->short_pkt = 1; 1798 count = td->remainder; 1799 } 1800 } 1801 1802 /* check for High-Speed multi-packets */ 1803 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1804 if (td->npkt == 0) { 1805 if (td->remainder >= (3 * td->max_packet_size)) 1806 td->npkt = 3; 1807 else if (td->remainder >= (2 * td->max_packet_size)) 1808 td->npkt = 2; 1809 else 1810 td->npkt = 1; 1811 1812 if (td->npkt > td->max_packet_count) 1813 td->npkt = td->max_packet_count; 1814 1815 td->tt_xactpos = 1; /* overload */ 1816 } 1817 if (td->tt_xactpos == td->npkt) { 1818 if (td->npkt == 1) { 1819 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1820 (count << HCTSIZ_XFERSIZE_SHIFT) | 1821 (1 << HCTSIZ_PKTCNT_SHIFT) | 1822 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1823 } else if (td->npkt == 2) { 1824 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1825 (count << HCTSIZ_XFERSIZE_SHIFT) | 1826 (1 << HCTSIZ_PKTCNT_SHIFT) | 1827 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1828 } else { 1829 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1830 (count << HCTSIZ_XFERSIZE_SHIFT) | 1831 (1 << HCTSIZ_PKTCNT_SHIFT) | 1832 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1833 } 1834 td->npkt = 0; 1835 } else { 1836 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1837 (count << HCTSIZ_XFERSIZE_SHIFT) | 1838 (1 << HCTSIZ_PKTCNT_SHIFT) | 1839 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1840 } 1841 } else { 1842 /* TODO: HCTSIZ_DOPNG */ 1843 1844 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1845 (count << HCTSIZ_XFERSIZE_SHIFT) | 1846 (1 << HCTSIZ_PKTCNT_SHIFT) | 1847 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1848 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1849 } 1850 1851 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1852 1853 hcchar = td->hcchar; 1854 hcchar &= ~HCCHAR_EPDIR_IN; 1855 1856 /* send after next SOF event */ 1857 if ((sc->sc_last_frame_num & 1) == 0) 1858 hcchar |= HCCHAR_ODDFRM; 1859 else 1860 hcchar &= ~HCCHAR_ODDFRM; 1861 1862 /* must enable before writing data to FIFO */ 1863 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1864 1865 if (count != 0) { 1866 1867 /* clear topmost word before copy */ 1868 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1869 1870 /* copy out data */ 1871 usbd_copy_out(td->pc, td->offset, 1872 sc->sc_tx_bounce_buffer, count); 1873 1874 /* transfer data into FIFO */ 1875 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1876 DOTG_DFIFO(channel), 1877 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1878 } 1879 1880 /* store number of bytes transmitted */ 1881 td->tx_bytes = count; 1882 goto busy; 1883 1884 send_cpkt: 1885 /* free existing channel, if any */ 1886 dwc_otg_host_channel_free(sc, td, td->tt_channel_tog); 1887 1888 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1889 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1890 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1891 goto busy; 1892 } 1893 delta = sc->sc_last_frame_num - td->tt_start_slot; 1894 if (delta > DWC_OTG_TT_SLOT_MAX) { 1895 /* we missed the service interval */ 1896 if (td->ep_type != UE_ISOCHRONOUS) 1897 td->error_any = 1; 1898 goto complete; 1899 } 1900 1901 /* allocate a new channel */ 1902 if (dwc_otg_host_channel_alloc(sc, td, td->tt_channel_tog, 0)) { 1903 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1904 goto busy; 1905 } 1906 1907 channel = td->channel[td->tt_channel_tog]; 1908 1909 td->hcsplt |= HCSPLT_COMPSPLT; 1910 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1911 1912 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1913 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1914 1915 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1916 1917 hcchar = td->hcchar; 1918 hcchar &= ~HCCHAR_EPDIR_IN; 1919 1920 /* check if other channel is allocated */ 1921 if (td->channel[td->tt_channel_tog ^ 1] < DWC_OTG_MAX_CHANNELS) { 1922 /* second - receive after next SOF event */ 1923 if ((sc->sc_last_frame_num & 1) != 0) 1924 hcchar |= HCCHAR_ODDFRM; 1925 else 1926 hcchar &= ~HCCHAR_ODDFRM; 1927 1928 /* other channel is next */ 1929 td->tt_channel_tog ^= 1; 1930 /* wait until next slot before trying again */ 1931 td->tt_complete_slot++; 1932 1933 /* must enable channel before data can be received */ 1934 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1935 } else { 1936 /* first - receive after second next SOF event */ 1937 if ((sc->sc_last_frame_num & 1) == 0) 1938 hcchar |= HCCHAR_ODDFRM; 1939 else 1940 hcchar &= ~HCCHAR_ODDFRM; 1941 1942 /* must enable channel before data can be received */ 1943 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1944 1945 if (td->hcsplt != 0) { 1946 if (td->ep_type == UE_ISOCHRONOUS || td->ep_type == UE_INTERRUPT) { 1947 /* allocate a second channel */ 1948 td->tt_channel_tog ^= 1; 1949 goto send_cpkt; 1950 } else { 1951 /* wait until next slot before trying again */ 1952 td->tt_complete_slot++; 1953 } 1954 } 1955 } 1956 busy: 1957 return (1); /* busy */ 1958 1959 complete: 1960 dwc_otg_host_channel_free(sc, td, 0); 1961 dwc_otg_host_channel_free(sc, td, 1); 1962 return (0); /* complete */ 1963 } 1964 1965 static uint8_t 1966 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1967 { 1968 uint32_t max_buffer; 1969 uint32_t count; 1970 uint32_t fifo_left; 1971 uint32_t mpkt; 1972 uint32_t temp; 1973 uint8_t to; 1974 1975 to = 3; /* don't loop forever! */ 1976 1977 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1978 1979 repeat: 1980 /* check for for endpoint 0 data */ 1981 1982 temp = sc->sc_last_rx_status; 1983 1984 if ((td->ep_no == 0) && (temp != 0) && 1985 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1986 1987 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1988 GRXSTSRD_STP_DATA) { 1989 1990 /* dump data - wrong direction */ 1991 dwc_otg_common_rx_ack(sc); 1992 } else { 1993 /* 1994 * The current transfer was cancelled 1995 * by the USB Host: 1996 */ 1997 td->error_any = 1; 1998 return (0); /* complete */ 1999 } 2000 } 2001 2002 /* fill in more TX data, if possible */ 2003 if (td->tx_bytes != 0) { 2004 2005 uint16_t cpkt; 2006 2007 /* check if packets have been transferred */ 2008 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2009 2010 /* get current packet number */ 2011 cpkt = DXEPTSIZ_GET_NPKT(temp); 2012 2013 if (cpkt >= td->npkt) { 2014 fifo_left = 0; 2015 } else { 2016 if (max_buffer != 0) { 2017 fifo_left = (td->npkt - cpkt) * 2018 td->max_packet_size; 2019 2020 if (fifo_left > max_buffer) 2021 fifo_left = max_buffer; 2022 } else { 2023 fifo_left = td->max_packet_size; 2024 } 2025 } 2026 2027 count = td->tx_bytes; 2028 if (count > fifo_left) 2029 count = fifo_left; 2030 2031 if (count != 0) { 2032 2033 /* clear topmost word before copy */ 2034 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2035 2036 /* copy out data */ 2037 usbd_copy_out(td->pc, td->offset, 2038 sc->sc_tx_bounce_buffer, count); 2039 2040 /* transfer data into FIFO */ 2041 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2042 DOTG_DFIFO(td->ep_no), 2043 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2044 2045 td->tx_bytes -= count; 2046 td->remainder -= count; 2047 td->offset += count; 2048 td->npkt = cpkt; 2049 } 2050 if (td->tx_bytes != 0) 2051 goto not_complete; 2052 2053 /* check remainder */ 2054 if (td->remainder == 0) { 2055 if (td->short_pkt) 2056 return (0); /* complete */ 2057 2058 /* else we need to transmit a short packet */ 2059 } 2060 } 2061 2062 if (!to--) 2063 goto not_complete; 2064 2065 /* check if not all packets have been transferred */ 2066 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2067 2068 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2069 2070 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2071 "DIEPCTL=0x%08x\n", td->ep_no, 2072 DXEPTSIZ_GET_NPKT(temp), 2073 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2074 2075 goto not_complete; 2076 } 2077 2078 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2079 2080 /* try to optimise by sending more data */ 2081 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2082 2083 /* send multiple packets at the same time */ 2084 mpkt = max_buffer / td->max_packet_size; 2085 2086 if (mpkt > 0x3FE) 2087 mpkt = 0x3FE; 2088 2089 count = td->remainder; 2090 if (count > 0x7FFFFF) 2091 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2092 2093 td->npkt = count / td->max_packet_size; 2094 2095 /* 2096 * NOTE: We could use 0x3FE instead of "mpkt" in the 2097 * check below to get more throughput, but then we 2098 * have a dependency towards non-generic chip features 2099 * to disable the TX-FIFO-EMPTY interrupts on a per 2100 * endpoint basis. Increase the maximum buffer size of 2101 * the IN endpoint to increase the performance. 2102 */ 2103 if (td->npkt > mpkt) { 2104 td->npkt = mpkt; 2105 count = td->max_packet_size * mpkt; 2106 } else if ((count == 0) || (count % td->max_packet_size)) { 2107 /* we are transmitting a short packet */ 2108 td->npkt++; 2109 td->short_pkt = 1; 2110 } 2111 } else { 2112 /* send one packet at a time */ 2113 mpkt = 1; 2114 count = td->max_packet_size; 2115 if (td->remainder < count) { 2116 /* we have a short packet */ 2117 td->short_pkt = 1; 2118 count = td->remainder; 2119 } 2120 td->npkt = 1; 2121 } 2122 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2123 DXEPTSIZ_SET_MULTI(1) | 2124 DXEPTSIZ_SET_NPKT(td->npkt) | 2125 DXEPTSIZ_SET_NBYTES(count)); 2126 2127 /* make room for buffering */ 2128 td->npkt += mpkt; 2129 2130 temp = sc->sc_in_ctl[td->ep_no]; 2131 2132 /* must enable before writing data to FIFO */ 2133 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2134 DIEPCTL_EPENA | 2135 DIEPCTL_CNAK); 2136 2137 td->tx_bytes = count; 2138 2139 /* check remainder */ 2140 if (td->tx_bytes == 0 && 2141 td->remainder == 0) { 2142 if (td->short_pkt) 2143 return (0); /* complete */ 2144 2145 /* else we need to transmit a short packet */ 2146 } 2147 goto repeat; 2148 2149 not_complete: 2150 return (1); /* not complete */ 2151 } 2152 2153 static uint8_t 2154 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2155 { 2156 uint32_t temp; 2157 2158 /* 2159 * If all packets are transferred we are complete: 2160 */ 2161 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2162 2163 /* check that all packets have been transferred */ 2164 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2165 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2166 goto not_complete; 2167 } 2168 return (0); 2169 2170 not_complete: 2171 2172 /* we only want to know if there is a SETUP packet or free IN packet */ 2173 2174 temp = sc->sc_last_rx_status; 2175 2176 if ((td->ep_no == 0) && (temp != 0) && 2177 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2178 2179 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2180 GRXSTSRD_STP_DATA) { 2181 DPRINTFN(5, "faking complete\n"); 2182 /* 2183 * Race condition: We are complete! 2184 */ 2185 return (0); 2186 } else { 2187 /* dump data - wrong direction */ 2188 dwc_otg_common_rx_ack(sc); 2189 } 2190 } 2191 return (1); /* not complete */ 2192 } 2193 2194 static void 2195 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2196 { 2197 struct dwc_otg_td *td; 2198 uint8_t toggle; 2199 uint8_t tmr_val; 2200 uint8_t tmr_res; 2201 2202 DPRINTFN(9, "\n"); 2203 2204 td = xfer->td_transfer_cache; 2205 if (td == NULL) 2206 return; 2207 2208 while (1) { 2209 if ((td->func) (sc, td)) { 2210 /* operation in progress */ 2211 break; 2212 } 2213 if (((void *)td) == xfer->td_transfer_last) { 2214 goto done; 2215 } 2216 if (td->error_any) { 2217 goto done; 2218 } else if (td->remainder > 0) { 2219 /* 2220 * We had a short transfer. If there is no alternate 2221 * next, stop processing ! 2222 */ 2223 if (!td->alt_next) 2224 goto done; 2225 } 2226 2227 /* 2228 * Fetch the next transfer descriptor and transfer 2229 * some flags to the next transfer descriptor 2230 */ 2231 tmr_res = td->tmr_res; 2232 tmr_val = td->tmr_val; 2233 toggle = td->toggle; 2234 td = td->obj_next; 2235 xfer->td_transfer_cache = td; 2236 td->toggle = toggle; /* transfer toggle */ 2237 td->tmr_res = tmr_res; 2238 td->tmr_val = tmr_val; 2239 } 2240 return; 2241 2242 done: 2243 xfer->td_transfer_cache = NULL; 2244 sc->sc_xfer_complete = 1; 2245 } 2246 2247 static uint8_t 2248 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2249 { 2250 struct dwc_otg_td *td; 2251 2252 DPRINTFN(9, "\n"); 2253 2254 td = xfer->td_transfer_cache; 2255 if (td == NULL) { 2256 /* compute all actual lengths */ 2257 dwc_otg_standard_done(xfer); 2258 return (1); 2259 } 2260 return (0); 2261 } 2262 2263 static void 2264 dwc_otg_timer(void *_sc) 2265 { 2266 struct dwc_otg_softc *sc = _sc; 2267 struct usb_xfer *xfer; 2268 struct dwc_otg_td *td; 2269 2270 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2271 2272 DPRINTF("\n"); 2273 2274 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2275 2276 /* increment timer value */ 2277 sc->sc_tmr_val++; 2278 2279 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2280 td = xfer->td_transfer_cache; 2281 if (td != NULL) { 2282 /* reset NAK counter */ 2283 td->did_nak = 0; 2284 } 2285 } 2286 2287 /* enable SOF interrupt, which will poll jobs */ 2288 dwc_otg_enable_sof_irq(sc); 2289 2290 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2291 2292 if (sc->sc_timer_active) { 2293 /* restart timer */ 2294 usb_callout_reset(&sc->sc_timer, 2295 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2296 &dwc_otg_timer, sc); 2297 } 2298 } 2299 2300 static void 2301 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2302 { 2303 if (sc->sc_timer_active != 0) 2304 return; 2305 2306 sc->sc_timer_active = 1; 2307 2308 /* restart timer */ 2309 usb_callout_reset(&sc->sc_timer, 2310 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2311 &dwc_otg_timer, sc); 2312 } 2313 2314 static void 2315 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2316 { 2317 if (sc->sc_timer_active == 0) 2318 return; 2319 2320 sc->sc_timer_active = 0; 2321 2322 /* stop timer */ 2323 usb_callout_stop(&sc->sc_timer); 2324 } 2325 2326 static void 2327 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 2328 { 2329 uint32_t hcchar; 2330 2331 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 2332 2333 /* disable host channel, if any */ 2334 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 2335 /* disable channel */ 2336 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2337 HCCHAR_CHENA | HCCHAR_CHDIS); 2338 /* wait for chip to get its brains in order */ 2339 sc->sc_chan_state[x].wait_sof = 2; 2340 } 2341 2342 /* release TX FIFO usage, if any */ 2343 sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; 2344 sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; 2345 2346 /* don't release TX FIFO usage twice */ 2347 sc->sc_chan_state[x].tx_p_size = 0; 2348 sc->sc_chan_state[x].tx_np_size = 0; 2349 } 2350 2351 static uint8_t 2352 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2353 { 2354 TAILQ_HEAD(, usb_xfer) head; 2355 struct usb_xfer *xfer; 2356 struct usb_xfer *xfer_next; 2357 struct dwc_otg_td *td; 2358 uint16_t temp; 2359 uint8_t x; 2360 2361 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2362 2363 if (sc->sc_last_frame_num == temp) 2364 return (0); 2365 2366 sc->sc_last_frame_num = temp; 2367 2368 TAILQ_INIT(&head); 2369 2370 for (x = 0; x != sc->sc_host_ch_max; x++) { 2371 if (sc->sc_chan_state[x].wait_sof == 0) 2372 continue; 2373 2374 sc->sc_needsof = 1; 2375 if (--(sc->sc_chan_state[x].wait_sof) == 0) 2376 dwc_otg_host_channel_disable(sc, x); 2377 } 2378 2379 if ((temp & 7) == 0) { 2380 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2381 td = xfer->td_transfer_cache; 2382 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2383 continue; 2384 2385 /* execute more frames */ 2386 td->tmr_val = 0; 2387 2388 sc->sc_needsof = 1; 2389 2390 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2391 continue; 2392 2393 /* Start ASAP */ 2394 td->tt_start_slot = temp + 0; 2395 td->tt_complete_slot = temp + 2; 2396 td->tt_scheduled = 1; 2397 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2398 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2399 } 2400 2401 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2402 td = xfer->td_transfer_cache; 2403 if (td == NULL || td->ep_type != UE_INTERRUPT) 2404 continue; 2405 2406 if (td->tt_scheduled != 0) { 2407 sc->sc_needsof = 1; 2408 continue; 2409 } 2410 2411 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2412 continue; 2413 2414 if (td->hcsplt == 0) { 2415 sc->sc_needsof = 1; 2416 td->tt_scheduled = 1; 2417 continue; 2418 } 2419 2420 /* start ASAP */ 2421 td->tt_start_slot = temp + 0; 2422 td->tt_complete_slot = temp + 2; 2423 sc->sc_needsof = 1; 2424 td->tt_scheduled = 1; 2425 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2426 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2427 } 2428 2429 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2430 td = xfer->td_transfer_cache; 2431 if (td == NULL || 2432 td->ep_type != UE_CONTROL || 2433 td->did_nak >= DWC_OTG_NAK_MAX) { 2434 continue; 2435 } 2436 2437 sc->sc_needsof = 1; 2438 2439 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2440 continue; 2441 2442 /* start ASAP */ 2443 td->tt_start_slot = temp + 0; 2444 td->tt_complete_slot = temp + 1; 2445 td->tt_scheduled = 1; 2446 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2447 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2448 } 2449 } 2450 if ((temp & 7) < 6) { 2451 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2452 td = xfer->td_transfer_cache; 2453 if (td == NULL || 2454 td->ep_type != UE_BULK || 2455 td->did_nak >= DWC_OTG_NAK_MAX) { 2456 continue; 2457 } 2458 2459 sc->sc_needsof = 1; 2460 2461 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2462 continue; 2463 2464 /* start ASAP */ 2465 td->tt_start_slot = temp + 0; 2466 td->tt_complete_slot = temp + 1; 2467 td->tt_scheduled = 1; 2468 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2469 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2470 } 2471 } 2472 2473 /* Put TT transfers in execution order at the end */ 2474 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2475 2476 /* move all TT transfers in front, keeping the current order */ 2477 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2478 td = xfer->td_transfer_cache; 2479 if (td == NULL || td->hcsplt == 0) 2480 continue; 2481 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2482 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2483 } 2484 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2485 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2486 2487 /* put non-TT BULK transfers last */ 2488 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2489 td = xfer->td_transfer_cache; 2490 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2491 continue; 2492 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2493 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2494 } 2495 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2496 2497 if ((temp & 7) == 0) { 2498 2499 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2500 (int)temp, (int)sc->sc_needsof); 2501 2502 /* update SOF IRQ mask */ 2503 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2504 if (sc->sc_needsof == 0) { 2505 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2506 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2507 } 2508 } else { 2509 if (sc->sc_needsof != 0) { 2510 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2511 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2512 } 2513 } 2514 2515 /* clear need SOF flag */ 2516 sc->sc_needsof = 0; 2517 } 2518 return (1); 2519 } 2520 2521 static void 2522 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2523 { 2524 struct usb_xfer *xfer; 2525 uint32_t temp; 2526 uint8_t got_rx_status; 2527 uint8_t x; 2528 2529 repeat: 2530 /* get all channel interrupts */ 2531 for (x = 0; x != sc->sc_host_ch_max; x++) { 2532 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2533 if (temp != 0) { 2534 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2535 temp &= ~HCINT_SOFTWARE_ONLY; 2536 sc->sc_chan_state[x].hcint |= temp; 2537 } 2538 } 2539 2540 if (sc->sc_last_rx_status == 0) { 2541 2542 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2543 if (temp & GINTSTS_RXFLVL) { 2544 /* pop current status */ 2545 sc->sc_last_rx_status = 2546 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2547 } 2548 2549 if (sc->sc_last_rx_status != 0) { 2550 2551 uint8_t ep_no; 2552 2553 temp = sc->sc_last_rx_status & 2554 GRXSTSRD_PKTSTS_MASK; 2555 2556 /* non-data messages we simply skip */ 2557 if (temp != GRXSTSRD_STP_DATA && 2558 temp != GRXSTSRD_OUT_DATA) { 2559 dwc_otg_common_rx_ack(sc); 2560 goto repeat; 2561 } 2562 2563 temp = GRXSTSRD_BCNT_GET( 2564 sc->sc_last_rx_status); 2565 ep_no = GRXSTSRD_CHNUM_GET( 2566 sc->sc_last_rx_status); 2567 2568 /* receive data, if any */ 2569 if (temp != 0) { 2570 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2571 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2572 DOTG_DFIFO(ep_no), 2573 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2574 } 2575 2576 /* check if we should dump the data */ 2577 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2578 dwc_otg_common_rx_ack(sc); 2579 goto repeat; 2580 } 2581 2582 got_rx_status = 1; 2583 2584 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2585 sc->sc_last_rx_status, ep_no, 2586 (sc->sc_last_rx_status >> 15) & 3, 2587 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2588 (sc->sc_last_rx_status >> 17) & 15); 2589 } else { 2590 got_rx_status = 0; 2591 } 2592 } else { 2593 uint8_t ep_no; 2594 2595 ep_no = GRXSTSRD_CHNUM_GET( 2596 sc->sc_last_rx_status); 2597 2598 /* check if we should dump the data */ 2599 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2600 dwc_otg_common_rx_ack(sc); 2601 goto repeat; 2602 } 2603 2604 got_rx_status = 1; 2605 } 2606 2607 /* execute FIFOs */ 2608 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2609 dwc_otg_xfer_do_fifo(sc, xfer); 2610 2611 if (got_rx_status) { 2612 /* check if data was consumed */ 2613 if (sc->sc_last_rx_status == 0) 2614 goto repeat; 2615 2616 /* disable RX FIFO level interrupt */ 2617 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2618 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2619 } 2620 2621 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2622 /* update host transfer schedule, so that new transfers can be issued */ 2623 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2624 goto repeat; 2625 } 2626 } 2627 2628 static void 2629 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2630 { 2631 struct usb_xfer *xfer; 2632 repeat: 2633 /* scan for completion events */ 2634 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2635 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2636 goto repeat; 2637 } 2638 } 2639 2640 static void 2641 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2642 { 2643 DPRINTFN(5, "vbus = %u\n", is_on); 2644 2645 /* 2646 * If the USB host mode is forced, then assume VBUS is always 2647 * present else rely on the input to this function: 2648 */ 2649 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2650 2651 if (!sc->sc_flags.status_vbus) { 2652 sc->sc_flags.status_vbus = 1; 2653 2654 /* complete root HUB interrupt endpoint */ 2655 2656 dwc_otg_root_intr(sc); 2657 } 2658 } else { 2659 if (sc->sc_flags.status_vbus) { 2660 sc->sc_flags.status_vbus = 0; 2661 sc->sc_flags.status_bus_reset = 0; 2662 sc->sc_flags.status_suspend = 0; 2663 sc->sc_flags.change_suspend = 0; 2664 sc->sc_flags.change_connect = 1; 2665 2666 /* complete root HUB interrupt endpoint */ 2667 2668 dwc_otg_root_intr(sc); 2669 } 2670 } 2671 } 2672 2673 int 2674 dwc_otg_filter_interrupt(void *arg) 2675 { 2676 struct dwc_otg_softc *sc = arg; 2677 int retval = FILTER_HANDLED; 2678 uint32_t status; 2679 2680 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2681 2682 /* read and clear interrupt status */ 2683 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2684 2685 /* clear interrupts we are handling here */ 2686 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2687 2688 /* check for USB state change interrupts */ 2689 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2690 retval = FILTER_SCHEDULE_THREAD; 2691 2692 /* clear all IN endpoint interrupts */ 2693 if (status & GINTSTS_IEPINT) { 2694 uint32_t temp; 2695 uint8_t x; 2696 2697 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2698 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2699 if (temp & DIEPMSK_XFERCOMPLMSK) { 2700 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2701 DIEPMSK_XFERCOMPLMSK); 2702 } 2703 } 2704 } 2705 2706 /* poll FIFOs, if any */ 2707 dwc_otg_interrupt_poll_locked(sc); 2708 2709 if (sc->sc_xfer_complete != 0) 2710 retval = FILTER_SCHEDULE_THREAD; 2711 2712 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2713 2714 return (retval); 2715 } 2716 2717 void 2718 dwc_otg_interrupt(void *arg) 2719 { 2720 struct dwc_otg_softc *sc = arg; 2721 uint32_t status; 2722 2723 USB_BUS_LOCK(&sc->sc_bus); 2724 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2725 2726 /* read and clear interrupt status */ 2727 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2728 2729 /* clear interrupts we are handling here */ 2730 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2731 2732 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2733 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2734 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2735 2736 if (status & GINTSTS_USBRST) { 2737 2738 /* set correct state */ 2739 sc->sc_flags.status_device_mode = 1; 2740 sc->sc_flags.status_bus_reset = 0; 2741 sc->sc_flags.status_suspend = 0; 2742 sc->sc_flags.change_suspend = 0; 2743 sc->sc_flags.change_connect = 1; 2744 2745 /* Disable SOF interrupt */ 2746 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2747 /* Enable RX frame interrupt */ 2748 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 2749 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2750 2751 /* complete root HUB interrupt endpoint */ 2752 dwc_otg_root_intr(sc); 2753 } 2754 2755 /* check for any bus state change interrupts */ 2756 if (status & GINTSTS_ENUMDONE) { 2757 2758 uint32_t temp; 2759 2760 DPRINTFN(5, "end of reset\n"); 2761 2762 /* set correct state */ 2763 sc->sc_flags.status_device_mode = 1; 2764 sc->sc_flags.status_bus_reset = 1; 2765 sc->sc_flags.status_suspend = 0; 2766 sc->sc_flags.change_suspend = 0; 2767 sc->sc_flags.change_connect = 1; 2768 sc->sc_flags.status_low_speed = 0; 2769 sc->sc_flags.port_enabled = 1; 2770 2771 /* reset FIFOs */ 2772 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2773 2774 /* reset function address */ 2775 dwc_otg_set_address(sc, 0); 2776 2777 /* figure out enumeration speed */ 2778 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2779 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2780 sc->sc_flags.status_high_speed = 1; 2781 else 2782 sc->sc_flags.status_high_speed = 0; 2783 2784 /* 2785 * Disable resume and SOF interrupt, and enable 2786 * suspend and RX frame interrupt: 2787 */ 2788 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2789 sc->sc_irq_mask |= (GINTMSK_USBSUSPMSK | GINTMSK_RXFLVLMSK); 2790 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2791 2792 /* complete root HUB interrupt endpoint */ 2793 dwc_otg_root_intr(sc); 2794 } 2795 2796 if (status & GINTSTS_PRTINT) { 2797 uint32_t hprt; 2798 2799 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2800 2801 /* clear change bits */ 2802 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2803 HPRT_PRTPWR | HPRT_PRTENCHNG | 2804 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2805 sc->sc_hprt_val); 2806 2807 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2808 2809 sc->sc_flags.status_device_mode = 0; 2810 2811 if (hprt & HPRT_PRTCONNSTS) 2812 sc->sc_flags.status_bus_reset = 1; 2813 else 2814 sc->sc_flags.status_bus_reset = 0; 2815 2816 if (hprt & HPRT_PRTENCHNG) 2817 sc->sc_flags.change_enabled = 1; 2818 2819 if (hprt & HPRT_PRTENA) 2820 sc->sc_flags.port_enabled = 1; 2821 else 2822 sc->sc_flags.port_enabled = 0; 2823 2824 if (hprt & HPRT_PRTOVRCURRCHNG) 2825 sc->sc_flags.change_over_current = 1; 2826 2827 if (hprt & HPRT_PRTOVRCURRACT) 2828 sc->sc_flags.port_over_current = 1; 2829 else 2830 sc->sc_flags.port_over_current = 0; 2831 2832 if (hprt & HPRT_PRTPWR) 2833 sc->sc_flags.port_powered = 1; 2834 else 2835 sc->sc_flags.port_powered = 0; 2836 2837 if (((hprt & HPRT_PRTSPD_MASK) 2838 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2839 sc->sc_flags.status_low_speed = 1; 2840 else 2841 sc->sc_flags.status_low_speed = 0; 2842 2843 if (((hprt & HPRT_PRTSPD_MASK) 2844 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2845 sc->sc_flags.status_high_speed = 1; 2846 else 2847 sc->sc_flags.status_high_speed = 0; 2848 2849 if (hprt & HPRT_PRTCONNDET) 2850 sc->sc_flags.change_connect = 1; 2851 2852 if (hprt & HPRT_PRTSUSP) 2853 dwc_otg_suspend_irq(sc); 2854 else 2855 dwc_otg_resume_irq(sc); 2856 2857 /* complete root HUB interrupt endpoint */ 2858 dwc_otg_root_intr(sc); 2859 2860 /* disable RX FIFO level interrupt */ 2861 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2862 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2863 2864 /* update host frame interval */ 2865 dwc_otg_update_host_frame_interval(sc); 2866 } 2867 2868 /* 2869 * If resume and suspend is set at the same time we interpret 2870 * that like RESUME. Resume is set when there is at least 3 2871 * milliseconds of inactivity on the USB BUS. 2872 */ 2873 if (status & GINTSTS_WKUPINT) { 2874 2875 DPRINTFN(5, "resume interrupt\n"); 2876 2877 dwc_otg_resume_irq(sc); 2878 2879 } else if (status & GINTSTS_USBSUSP) { 2880 2881 DPRINTFN(5, "suspend interrupt\n"); 2882 2883 dwc_otg_suspend_irq(sc); 2884 } 2885 /* check VBUS */ 2886 if (status & (GINTSTS_USBSUSP | 2887 GINTSTS_USBRST | 2888 GINTMSK_OTGINTMSK | 2889 GINTSTS_SESSREQINT)) { 2890 uint32_t temp; 2891 2892 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2893 2894 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2895 2896 dwc_otg_vbus_interrupt(sc, 2897 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2898 } 2899 2900 if (sc->sc_xfer_complete != 0) { 2901 sc->sc_xfer_complete = 0; 2902 2903 /* complete FIFOs, if any */ 2904 dwc_otg_interrupt_complete_locked(sc); 2905 2906 if (sc->sc_flags.status_device_mode == 0) { 2907 /* update host transfer schedule, so that new transfers can be issued */ 2908 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2909 dwc_otg_interrupt_poll_locked(sc); 2910 } 2911 } 2912 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2913 USB_BUS_UNLOCK(&sc->sc_bus); 2914 } 2915 2916 static void 2917 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2918 { 2919 struct dwc_otg_td *td; 2920 2921 /* get current Transfer Descriptor */ 2922 td = temp->td_next; 2923 temp->td = td; 2924 2925 /* prepare for next TD */ 2926 temp->td_next = td->obj_next; 2927 2928 /* fill out the Transfer Descriptor */ 2929 td->func = temp->func; 2930 td->pc = temp->pc; 2931 td->offset = temp->offset; 2932 td->remainder = temp->len; 2933 td->tx_bytes = 0; 2934 td->error_any = 0; 2935 td->error_stall = 0; 2936 td->npkt = 0; 2937 td->did_stall = temp->did_stall; 2938 td->short_pkt = temp->short_pkt; 2939 td->alt_next = temp->setup_alt_next; 2940 td->set_toggle = 0; 2941 td->got_short = 0; 2942 td->did_nak = 0; 2943 td->channel[0] = DWC_OTG_MAX_CHANNELS; 2944 td->channel[1] = DWC_OTG_MAX_CHANNELS; 2945 td->state = 0; 2946 td->errcnt = 0; 2947 td->tt_scheduled = 0; 2948 td->tt_channel_tog = 0; 2949 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2950 } 2951 2952 static void 2953 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2954 { 2955 struct dwc_otg_std_temp temp; 2956 struct dwc_otg_td *td; 2957 uint32_t x; 2958 uint8_t need_sync; 2959 uint8_t is_host; 2960 2961 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2962 xfer->address, UE_GET_ADDR(xfer->endpointno), 2963 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2964 2965 temp.max_frame_size = xfer->max_frame_size; 2966 2967 td = xfer->td_start[0]; 2968 xfer->td_transfer_first = td; 2969 xfer->td_transfer_cache = td; 2970 2971 /* setup temp */ 2972 2973 temp.pc = NULL; 2974 temp.td = NULL; 2975 temp.td_next = xfer->td_start[0]; 2976 temp.offset = 0; 2977 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 2978 xfer->flags_int.isochronous_xfr; 2979 temp.did_stall = !xfer->flags_int.control_stall; 2980 2981 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2982 2983 /* check if we should prepend a setup message */ 2984 2985 if (xfer->flags_int.control_xfr) { 2986 if (xfer->flags_int.control_hdr) { 2987 2988 if (is_host) 2989 temp.func = &dwc_otg_host_setup_tx; 2990 else 2991 temp.func = &dwc_otg_setup_rx; 2992 2993 temp.len = xfer->frlengths[0]; 2994 temp.pc = xfer->frbuffers + 0; 2995 temp.short_pkt = temp.len ? 1 : 0; 2996 2997 /* check for last frame */ 2998 if (xfer->nframes == 1) { 2999 /* no STATUS stage yet, SETUP is last */ 3000 if (xfer->flags_int.control_act) 3001 temp.setup_alt_next = 0; 3002 } 3003 3004 dwc_otg_setup_standard_chain_sub(&temp); 3005 } 3006 x = 1; 3007 } else { 3008 x = 0; 3009 } 3010 3011 if (x != xfer->nframes) { 3012 if (xfer->endpointno & UE_DIR_IN) { 3013 if (is_host) { 3014 temp.func = &dwc_otg_host_data_rx; 3015 need_sync = 0; 3016 } else { 3017 temp.func = &dwc_otg_data_tx; 3018 need_sync = 1; 3019 } 3020 } else { 3021 if (is_host) { 3022 temp.func = &dwc_otg_host_data_tx; 3023 need_sync = 0; 3024 } else { 3025 temp.func = &dwc_otg_data_rx; 3026 need_sync = 0; 3027 } 3028 } 3029 3030 /* setup "pc" pointer */ 3031 temp.pc = xfer->frbuffers + x; 3032 } else { 3033 need_sync = 0; 3034 } 3035 while (x != xfer->nframes) { 3036 3037 /* DATA0 / DATA1 message */ 3038 3039 temp.len = xfer->frlengths[x]; 3040 3041 x++; 3042 3043 if (x == xfer->nframes) { 3044 if (xfer->flags_int.control_xfr) { 3045 if (xfer->flags_int.control_act) { 3046 temp.setup_alt_next = 0; 3047 } 3048 } else { 3049 temp.setup_alt_next = 0; 3050 } 3051 } 3052 if (temp.len == 0) { 3053 3054 /* make sure that we send an USB packet */ 3055 3056 temp.short_pkt = 0; 3057 3058 } else { 3059 3060 /* regular data transfer */ 3061 3062 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3063 } 3064 3065 dwc_otg_setup_standard_chain_sub(&temp); 3066 3067 if (xfer->flags_int.isochronous_xfr) { 3068 temp.offset += temp.len; 3069 } else { 3070 /* get next Page Cache pointer */ 3071 temp.pc = xfer->frbuffers + x; 3072 } 3073 } 3074 3075 if (xfer->flags_int.control_xfr) { 3076 3077 /* always setup a valid "pc" pointer for status and sync */ 3078 temp.pc = xfer->frbuffers + 0; 3079 temp.len = 0; 3080 temp.short_pkt = 0; 3081 temp.setup_alt_next = 0; 3082 3083 /* check if we need to sync */ 3084 if (need_sync) { 3085 /* we need a SYNC point after TX */ 3086 temp.func = &dwc_otg_data_tx_sync; 3087 dwc_otg_setup_standard_chain_sub(&temp); 3088 } 3089 3090 /* check if we should append a status stage */ 3091 if (!xfer->flags_int.control_act) { 3092 3093 /* 3094 * Send a DATA1 message and invert the current 3095 * endpoint direction. 3096 */ 3097 if (xfer->endpointno & UE_DIR_IN) { 3098 if (is_host) { 3099 temp.func = &dwc_otg_host_data_tx; 3100 need_sync = 0; 3101 } else { 3102 temp.func = &dwc_otg_data_rx; 3103 need_sync = 0; 3104 } 3105 } else { 3106 if (is_host) { 3107 temp.func = &dwc_otg_host_data_rx; 3108 need_sync = 0; 3109 } else { 3110 temp.func = &dwc_otg_data_tx; 3111 need_sync = 1; 3112 } 3113 } 3114 3115 dwc_otg_setup_standard_chain_sub(&temp); 3116 3117 /* data toggle should be DATA1 */ 3118 td = temp.td; 3119 td->set_toggle = 1; 3120 3121 if (need_sync) { 3122 /* we need a SYNC point after TX */ 3123 temp.func = &dwc_otg_data_tx_sync; 3124 dwc_otg_setup_standard_chain_sub(&temp); 3125 } 3126 } 3127 } else { 3128 /* check if we need to sync */ 3129 if (need_sync) { 3130 3131 temp.pc = xfer->frbuffers + 0; 3132 temp.len = 0; 3133 temp.short_pkt = 0; 3134 temp.setup_alt_next = 0; 3135 3136 /* we need a SYNC point after TX */ 3137 temp.func = &dwc_otg_data_tx_sync; 3138 dwc_otg_setup_standard_chain_sub(&temp); 3139 } 3140 } 3141 3142 /* must have at least one frame! */ 3143 td = temp.td; 3144 xfer->td_transfer_last = td; 3145 3146 if (is_host) { 3147 3148 struct dwc_otg_softc *sc; 3149 uint32_t hcchar; 3150 uint32_t hcsplt; 3151 3152 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3153 3154 /* get first again */ 3155 td = xfer->td_transfer_first; 3156 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3157 3158 hcchar = 3159 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3160 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3161 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3162 HCCHAR_CHENA; 3163 3164 /* XXX stability hack - possible HW issue */ 3165 if (td->ep_type == UE_CONTROL) 3166 hcchar |= (UE_BULK << HCCHAR_EPTYPE_SHIFT); 3167 else 3168 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3169 3170 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3171 hcchar |= HCCHAR_LSPDDEV; 3172 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3173 hcchar |= HCCHAR_EPDIR_IN; 3174 3175 switch (xfer->xroot->udev->speed) { 3176 case USB_SPEED_FULL: 3177 case USB_SPEED_LOW: 3178 /* check if root HUB port is running High Speed */ 3179 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3180 hcsplt = HCSPLT_SPLTENA | 3181 (xfer->xroot->udev->hs_port_no << 3182 HCSPLT_PRTADDR_SHIFT) | 3183 (xfer->xroot->udev->hs_hub_addr << 3184 HCSPLT_HUBADDR_SHIFT); 3185 } else { 3186 hcsplt = 0; 3187 } 3188 if (td->ep_type == UE_INTERRUPT) { 3189 uint32_t ival; 3190 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3191 if (ival == 0) 3192 ival = 1; 3193 else if (ival > 127) 3194 ival = 127; 3195 td->tmr_val = sc->sc_tmr_val + ival; 3196 td->tmr_res = ival; 3197 } else if (td->ep_type == UE_ISOCHRONOUS) { 3198 td->tmr_val = 0; 3199 td->tmr_res = 1; 3200 } else { 3201 td->tmr_val = 0; 3202 td->tmr_res = 0; 3203 } 3204 break; 3205 case USB_SPEED_HIGH: 3206 hcsplt = 0; 3207 if (td->ep_type == UE_ISOCHRONOUS || 3208 td->ep_type == UE_INTERRUPT) { 3209 hcchar |= ((xfer->max_packet_count & 3) 3210 << HCCHAR_MC_SHIFT); 3211 } 3212 if (td->ep_type == UE_INTERRUPT) { 3213 uint32_t ival; 3214 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3215 if (ival == 0) 3216 ival = 1; 3217 else if (ival > 127) 3218 ival = 127; 3219 td->tmr_val = sc->sc_tmr_val + ival; 3220 td->tmr_res = ival; 3221 } else if (td->ep_type == UE_ISOCHRONOUS) { 3222 td->tmr_val = 0; 3223 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3224 } else { 3225 td->tmr_val = 0; 3226 td->tmr_res = 0; 3227 } 3228 break; 3229 default: 3230 hcsplt = 0; 3231 td->tmr_val = 0; 3232 td->tmr_res = 0; 3233 break; 3234 } 3235 3236 /* store configuration in all TD's */ 3237 while (1) { 3238 td->hcchar = hcchar; 3239 td->hcsplt = hcsplt; 3240 3241 if (((void *)td) == xfer->td_transfer_last) 3242 break; 3243 3244 td = td->obj_next; 3245 } 3246 } 3247 } 3248 3249 static void 3250 dwc_otg_timeout(void *arg) 3251 { 3252 struct usb_xfer *xfer = arg; 3253 3254 DPRINTF("xfer=%p\n", xfer); 3255 3256 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3257 3258 /* transfer is transferred */ 3259 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3260 } 3261 3262 static void 3263 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3264 { 3265 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3266 struct usb_xfer_root *xroot; 3267 struct dwc_otg_td *td; 3268 3269 DPRINTFN(9, "\n"); 3270 3271 /* 3272 * Poll one time in device mode, which will turn on the 3273 * endpoint interrupts. Else wait for SOF interrupt in host 3274 * mode. 3275 */ 3276 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3277 3278 if (sc->sc_flags.status_device_mode != 0) { 3279 dwc_otg_xfer_do_fifo(sc, xfer); 3280 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3281 goto done; 3282 } 3283 3284 /* put transfer on interrupt queue */ 3285 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3286 3287 /* start timeout, if any */ 3288 if (xfer->timeout != 0) { 3289 usbd_transfer_timeout_ms(xfer, 3290 &dwc_otg_timeout, xfer->timeout); 3291 } 3292 3293 if (sc->sc_flags.status_device_mode != 0) 3294 goto done; 3295 3296 /* enable SOF interrupt, if any */ 3297 dwc_otg_enable_sof_irq(sc); 3298 3299 td = xfer->td_transfer_cache; 3300 if (td->ep_type != UE_BULK) 3301 goto done; 3302 3303 xroot = xfer->xroot; 3304 3305 /* 3306 * Optimise the ping-pong effect by waking up other BULK 3307 * transfers belonging to the same device group: 3308 */ 3309 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3310 td = xfer->td_transfer_cache; 3311 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3312 continue; 3313 /* reset NAK counter */ 3314 td->did_nak = 0; 3315 } 3316 done: 3317 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3318 } 3319 3320 static void 3321 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3322 { 3323 DPRINTFN(9, "\n"); 3324 3325 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3326 3327 /* set port bit */ 3328 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3329 3330 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3331 sizeof(sc->sc_hub_idata)); 3332 } 3333 3334 static usb_error_t 3335 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3336 { 3337 struct dwc_otg_td *td; 3338 uint32_t len; 3339 usb_error_t error; 3340 3341 DPRINTFN(9, "\n"); 3342 3343 td = xfer->td_transfer_cache; 3344 3345 do { 3346 len = td->remainder; 3347 3348 /* store last data toggle */ 3349 xfer->endpoint->toggle_next = td->toggle; 3350 3351 if (xfer->aframes != xfer->nframes) { 3352 /* 3353 * Verify the length and subtract 3354 * the remainder from "frlengths[]": 3355 */ 3356 if (len > xfer->frlengths[xfer->aframes]) { 3357 td->error_any = 1; 3358 } else { 3359 xfer->frlengths[xfer->aframes] -= len; 3360 } 3361 } 3362 /* Check for transfer error */ 3363 if (td->error_any) { 3364 /* the transfer is finished */ 3365 error = (td->error_stall ? 3366 USB_ERR_STALLED : USB_ERR_IOERROR); 3367 td = NULL; 3368 break; 3369 } 3370 /* Check for short transfer */ 3371 if (len > 0) { 3372 if (xfer->flags_int.short_frames_ok || 3373 xfer->flags_int.isochronous_xfr) { 3374 /* follow alt next */ 3375 if (td->alt_next) { 3376 td = td->obj_next; 3377 } else { 3378 td = NULL; 3379 } 3380 } else { 3381 /* the transfer is finished */ 3382 td = NULL; 3383 } 3384 error = 0; 3385 break; 3386 } 3387 td = td->obj_next; 3388 3389 /* this USB frame is complete */ 3390 error = 0; 3391 break; 3392 3393 } while (0); 3394 3395 /* update transfer cache */ 3396 3397 xfer->td_transfer_cache = td; 3398 3399 return (error); 3400 } 3401 3402 static void 3403 dwc_otg_standard_done(struct usb_xfer *xfer) 3404 { 3405 usb_error_t err = 0; 3406 3407 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3408 xfer, xfer->endpoint); 3409 3410 /* reset scanner */ 3411 3412 xfer->td_transfer_cache = xfer->td_transfer_first; 3413 3414 if (xfer->flags_int.control_xfr) { 3415 3416 if (xfer->flags_int.control_hdr) { 3417 3418 err = dwc_otg_standard_done_sub(xfer); 3419 } 3420 xfer->aframes = 1; 3421 3422 if (xfer->td_transfer_cache == NULL) { 3423 goto done; 3424 } 3425 } 3426 while (xfer->aframes != xfer->nframes) { 3427 3428 err = dwc_otg_standard_done_sub(xfer); 3429 xfer->aframes++; 3430 3431 if (xfer->td_transfer_cache == NULL) { 3432 goto done; 3433 } 3434 } 3435 3436 if (xfer->flags_int.control_xfr && 3437 !xfer->flags_int.control_act) { 3438 3439 err = dwc_otg_standard_done_sub(xfer); 3440 } 3441 done: 3442 dwc_otg_device_done(xfer, err); 3443 } 3444 3445 /*------------------------------------------------------------------------* 3446 * dwc_otg_device_done 3447 * 3448 * NOTE: this function can be called more than one time on the 3449 * same USB transfer! 3450 *------------------------------------------------------------------------*/ 3451 static void 3452 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3453 { 3454 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3455 3456 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3457 xfer, xfer->endpoint, error); 3458 3459 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3460 3461 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3462 /* Interrupts are cleared by the interrupt handler */ 3463 } else { 3464 struct dwc_otg_td *td; 3465 3466 td = xfer->td_transfer_first; 3467 3468 if (td != NULL) { 3469 dwc_otg_host_channel_free(sc, td, 0); 3470 dwc_otg_host_channel_free(sc, td, 1); 3471 } 3472 } 3473 /* dequeue transfer and start next transfer */ 3474 usbd_transfer_done(xfer, error); 3475 3476 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3477 } 3478 3479 static void 3480 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3481 { 3482 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3483 } 3484 3485 static void 3486 dwc_otg_set_stall(struct usb_device *udev, 3487 struct usb_endpoint *ep, uint8_t *did_stall) 3488 { 3489 struct dwc_otg_softc *sc; 3490 uint32_t temp; 3491 uint32_t reg; 3492 uint8_t ep_no; 3493 3494 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3495 3496 /* check mode */ 3497 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3498 /* not supported */ 3499 return; 3500 } 3501 3502 sc = DWC_OTG_BUS2SC(udev->bus); 3503 3504 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3505 3506 /* get endpoint address */ 3507 ep_no = ep->edesc->bEndpointAddress; 3508 3509 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3510 3511 if (ep_no & UE_DIR_IN) { 3512 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3513 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3514 } else { 3515 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3516 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3517 } 3518 3519 /* disable and stall endpoint */ 3520 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3521 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3522 3523 /* clear active OUT ep */ 3524 if (!(ep_no & UE_DIR_IN)) { 3525 3526 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3527 3528 if (sc->sc_last_rx_status != 0 && 3529 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3530 sc->sc_last_rx_status)) { 3531 /* dump data */ 3532 dwc_otg_common_rx_ack(sc); 3533 /* poll interrupt */ 3534 dwc_otg_interrupt_poll_locked(sc); 3535 dwc_otg_interrupt_complete_locked(sc); 3536 } 3537 } 3538 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3539 } 3540 3541 static void 3542 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3543 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3544 { 3545 uint32_t reg; 3546 uint32_t temp; 3547 3548 if (ep_type == UE_CONTROL) { 3549 /* clearing stall is not needed */ 3550 return; 3551 } 3552 3553 if (ep_dir) { 3554 reg = DOTG_DIEPCTL(ep_no); 3555 } else { 3556 reg = DOTG_DOEPCTL(ep_no); 3557 sc->sc_active_rx_ep |= (1U << ep_no); 3558 } 3559 3560 /* round up and mask away the multiplier count */ 3561 mps = (mps + 3) & 0x7FC; 3562 3563 if (ep_type == UE_BULK) { 3564 temp = DIEPCTL_EPTYPE_SET( 3565 DIEPCTL_EPTYPE_BULK) | 3566 DIEPCTL_USBACTEP; 3567 } else if (ep_type == UE_INTERRUPT) { 3568 temp = DIEPCTL_EPTYPE_SET( 3569 DIEPCTL_EPTYPE_INTERRUPT) | 3570 DIEPCTL_USBACTEP; 3571 } else { 3572 temp = DIEPCTL_EPTYPE_SET( 3573 DIEPCTL_EPTYPE_ISOC) | 3574 DIEPCTL_USBACTEP; 3575 } 3576 3577 temp |= DIEPCTL_MPS_SET(mps); 3578 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3579 3580 if (ep_dir) 3581 sc->sc_in_ctl[ep_no] = temp; 3582 else 3583 sc->sc_out_ctl[ep_no] = temp; 3584 3585 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3586 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3587 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3588 3589 /* we only reset the transmit FIFO */ 3590 if (ep_dir) { 3591 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3592 GRSTCTL_TXFIFO(ep_no) | 3593 GRSTCTL_TXFFLSH); 3594 3595 DWC_OTG_WRITE_4(sc, 3596 DOTG_DIEPTSIZ(ep_no), 0); 3597 } 3598 3599 /* poll interrupt */ 3600 dwc_otg_interrupt_poll_locked(sc); 3601 dwc_otg_interrupt_complete_locked(sc); 3602 } 3603 3604 static void 3605 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3606 { 3607 struct dwc_otg_softc *sc; 3608 struct usb_endpoint_descriptor *ed; 3609 3610 DPRINTFN(5, "endpoint=%p\n", ep); 3611 3612 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3613 3614 /* check mode */ 3615 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3616 /* not supported */ 3617 return; 3618 } 3619 /* get softc */ 3620 sc = DWC_OTG_BUS2SC(udev->bus); 3621 3622 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3623 3624 /* get endpoint descriptor */ 3625 ed = ep->edesc; 3626 3627 /* reset endpoint */ 3628 dwc_otg_clear_stall_sub_locked(sc, 3629 UGETW(ed->wMaxPacketSize), 3630 (ed->bEndpointAddress & UE_ADDR), 3631 (ed->bmAttributes & UE_XFERTYPE), 3632 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3633 3634 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3635 } 3636 3637 static void 3638 dwc_otg_device_state_change(struct usb_device *udev) 3639 { 3640 struct dwc_otg_softc *sc; 3641 uint8_t x; 3642 3643 /* check mode */ 3644 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3645 /* not supported */ 3646 return; 3647 } 3648 3649 /* get softc */ 3650 sc = DWC_OTG_BUS2SC(udev->bus); 3651 3652 /* deactivate all other endpoint but the control endpoint */ 3653 if (udev->state == USB_STATE_CONFIGURED || 3654 udev->state == USB_STATE_ADDRESSED) { 3655 3656 USB_BUS_LOCK(&sc->sc_bus); 3657 3658 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3659 3660 if (x < sc->sc_dev_in_ep_max) { 3661 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3662 DIEPCTL_EPDIS); 3663 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3664 } 3665 3666 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3667 DOEPCTL_EPDIS); 3668 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3669 } 3670 USB_BUS_UNLOCK(&sc->sc_bus); 3671 } 3672 } 3673 3674 int 3675 dwc_otg_init(struct dwc_otg_softc *sc) 3676 { 3677 uint32_t temp; 3678 3679 DPRINTF("start\n"); 3680 3681 /* set up the bus structure */ 3682 sc->sc_bus.usbrev = USB_REV_2_0; 3683 sc->sc_bus.methods = &dwc_otg_bus_methods; 3684 3685 usb_callout_init_mtx(&sc->sc_timer, 3686 &sc->sc_bus.bus_mtx, 0); 3687 3688 USB_BUS_LOCK(&sc->sc_bus); 3689 3690 /* turn on clocks */ 3691 dwc_otg_clocks_on(sc); 3692 3693 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3694 DPRINTF("Version = 0x%08x\n", temp); 3695 3696 /* disconnect */ 3697 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3698 DCTL_SFTDISCON); 3699 3700 /* wait for host to detect disconnect */ 3701 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3702 3703 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3704 GRSTCTL_CSFTRST); 3705 3706 /* wait a little bit for block to reset */ 3707 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3708 3709 switch (sc->sc_mode) { 3710 case DWC_MODE_DEVICE: 3711 temp = GUSBCFG_FORCEDEVMODE; 3712 break; 3713 case DWC_MODE_HOST: 3714 temp = GUSBCFG_FORCEHOSTMODE; 3715 break; 3716 default: 3717 temp = 0; 3718 break; 3719 } 3720 3721 /* select HSIC or non-HSIC mode */ 3722 if (dwc_otg_use_hsic) { 3723 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3724 GUSBCFG_PHYIF | 3725 GUSBCFG_TRD_TIM_SET(5) | temp); 3726 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3727 0x000000EC); 3728 3729 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3730 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3731 temp & ~GLPMCFG_HSIC_CONN); 3732 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3733 temp | GLPMCFG_HSIC_CONN); 3734 } else { 3735 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3736 GUSBCFG_ULPI_UTMI_SEL | 3737 GUSBCFG_TRD_TIM_SET(5) | temp); 3738 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3739 3740 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3741 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3742 temp & ~GLPMCFG_HSIC_CONN); 3743 } 3744 3745 /* clear global nak */ 3746 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3747 DCTL_CGOUTNAK | 3748 DCTL_CGNPINNAK); 3749 3750 /* disable USB port */ 3751 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3752 3753 /* wait 10ms */ 3754 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3755 3756 /* enable USB port */ 3757 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3758 3759 /* wait 10ms */ 3760 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3761 3762 /* pull up D+ */ 3763 dwc_otg_pull_up(sc); 3764 3765 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3766 3767 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3768 3769 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3770 3771 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3772 3773 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3774 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3775 3776 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3777 3778 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3779 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3780 3781 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3782 3783 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3784 3785 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3786 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3787 sc->sc_host_ch_max); 3788 3789 /* setup FIFO */ 3790 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3791 USB_BUS_UNLOCK(&sc->sc_bus); 3792 return (EINVAL); 3793 } 3794 3795 /* enable interrupts */ 3796 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3797 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3798 3799 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3800 3801 /* enable all endpoint interrupts */ 3802 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3803 if (temp & GHWCFG2_MPI) { 3804 uint8_t x; 3805 3806 DPRINTF("Multi Process Interrupts\n"); 3807 3808 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3809 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3810 DIEPMSK_XFERCOMPLMSK); 3811 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3812 } 3813 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3814 } else { 3815 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3816 DIEPMSK_XFERCOMPLMSK); 3817 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3818 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3819 } 3820 } 3821 3822 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3823 /* setup clocks */ 3824 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3825 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3826 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3827 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3828 } 3829 3830 /* only enable global IRQ */ 3831 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3832 GAHBCFG_GLBLINTRMSK); 3833 3834 /* turn off clocks */ 3835 dwc_otg_clocks_off(sc); 3836 3837 /* read initial VBUS state */ 3838 3839 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3840 3841 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3842 3843 dwc_otg_vbus_interrupt(sc, 3844 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3845 3846 USB_BUS_UNLOCK(&sc->sc_bus); 3847 3848 /* catch any lost interrupts */ 3849 3850 dwc_otg_do_poll(&sc->sc_bus); 3851 3852 return (0); /* success */ 3853 } 3854 3855 void 3856 dwc_otg_uninit(struct dwc_otg_softc *sc) 3857 { 3858 USB_BUS_LOCK(&sc->sc_bus); 3859 3860 /* stop host timer */ 3861 dwc_otg_timer_stop(sc); 3862 3863 /* set disconnect */ 3864 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3865 DCTL_SFTDISCON); 3866 3867 /* turn off global IRQ */ 3868 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3869 3870 sc->sc_flags.port_enabled = 0; 3871 sc->sc_flags.port_powered = 0; 3872 sc->sc_flags.status_vbus = 0; 3873 sc->sc_flags.status_bus_reset = 0; 3874 sc->sc_flags.status_suspend = 0; 3875 sc->sc_flags.change_suspend = 0; 3876 sc->sc_flags.change_connect = 1; 3877 3878 dwc_otg_pull_down(sc); 3879 dwc_otg_clocks_off(sc); 3880 3881 USB_BUS_UNLOCK(&sc->sc_bus); 3882 3883 usb_callout_drain(&sc->sc_timer); 3884 } 3885 3886 static void 3887 dwc_otg_suspend(struct dwc_otg_softc *sc) 3888 { 3889 return; 3890 } 3891 3892 static void 3893 dwc_otg_resume(struct dwc_otg_softc *sc) 3894 { 3895 return; 3896 } 3897 3898 static void 3899 dwc_otg_do_poll(struct usb_bus *bus) 3900 { 3901 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3902 3903 USB_BUS_LOCK(&sc->sc_bus); 3904 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3905 dwc_otg_interrupt_poll_locked(sc); 3906 dwc_otg_interrupt_complete_locked(sc); 3907 if (sc->sc_flags.status_device_mode == 0) { 3908 /* update host transfer schedule, so that new transfers can be issued */ 3909 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3910 dwc_otg_interrupt_poll_locked(sc); 3911 } 3912 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3913 USB_BUS_UNLOCK(&sc->sc_bus); 3914 } 3915 3916 /*------------------------------------------------------------------------* 3917 * DWC OTG bulk support 3918 * DWC OTG control support 3919 * DWC OTG interrupt support 3920 *------------------------------------------------------------------------*/ 3921 static void 3922 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3923 { 3924 } 3925 3926 static void 3927 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3928 { 3929 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3930 } 3931 3932 static void 3933 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3934 { 3935 } 3936 3937 static void 3938 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3939 { 3940 /* setup TDs */ 3941 dwc_otg_setup_standard_chain(xfer); 3942 dwc_otg_start_standard_chain(xfer); 3943 } 3944 3945 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3946 { 3947 .open = dwc_otg_device_non_isoc_open, 3948 .close = dwc_otg_device_non_isoc_close, 3949 .enter = dwc_otg_device_non_isoc_enter, 3950 .start = dwc_otg_device_non_isoc_start, 3951 }; 3952 3953 /*------------------------------------------------------------------------* 3954 * DWC OTG full speed isochronous support 3955 *------------------------------------------------------------------------*/ 3956 static void 3957 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3958 { 3959 } 3960 3961 static void 3962 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3963 { 3964 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3965 } 3966 3967 static void 3968 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3969 { 3970 } 3971 3972 static void 3973 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3974 { 3975 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3976 uint32_t temp; 3977 uint32_t msframes; 3978 uint32_t framenum; 3979 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3980 3981 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3982 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3983 3984 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3985 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3986 3987 /* get the current frame index */ 3988 framenum = (temp & HFNUM_FRNUM_MASK); 3989 } else { 3990 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3991 3992 /* get the current frame index */ 3993 framenum = DSTS_SOFFN_GET(temp); 3994 } 3995 3996 if (xfer->xroot->udev->parent_hs_hub != NULL) 3997 framenum /= 8; 3998 3999 framenum &= DWC_OTG_FRAME_MASK; 4000 4001 /* 4002 * Compute number of milliseconds worth of data traffic for 4003 * this USB transfer: 4004 */ 4005 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4006 msframes = ((xfer->nframes << shift) + 7) / 8; 4007 else 4008 msframes = xfer->nframes; 4009 4010 /* 4011 * check if the frame index is within the window where the frames 4012 * will be inserted 4013 */ 4014 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4015 4016 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4017 /* 4018 * If there is data underflow or the pipe queue is 4019 * empty we schedule the transfer a few frames ahead 4020 * of the current frame position. Else two isochronous 4021 * transfers might overlap. 4022 */ 4023 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4024 xfer->endpoint->is_synced = 1; 4025 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4026 } 4027 /* 4028 * compute how many milliseconds the insertion is ahead of the 4029 * current frame position: 4030 */ 4031 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4032 4033 /* 4034 * pre-compute when the isochronous transfer will be finished: 4035 */ 4036 xfer->isoc_time_complete = 4037 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4038 4039 /* setup TDs */ 4040 dwc_otg_setup_standard_chain(xfer); 4041 4042 /* compute frame number for next insertion */ 4043 xfer->endpoint->isoc_next += msframes; 4044 4045 /* start TD chain */ 4046 dwc_otg_start_standard_chain(xfer); 4047 } 4048 4049 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4050 { 4051 .open = dwc_otg_device_isoc_open, 4052 .close = dwc_otg_device_isoc_close, 4053 .enter = dwc_otg_device_isoc_enter, 4054 .start = dwc_otg_device_isoc_start, 4055 }; 4056 4057 /*------------------------------------------------------------------------* 4058 * DWC OTG root control support 4059 *------------------------------------------------------------------------* 4060 * Simulate a hardware HUB by handling all the necessary requests. 4061 *------------------------------------------------------------------------*/ 4062 4063 static const struct usb_device_descriptor dwc_otg_devd = { 4064 .bLength = sizeof(struct usb_device_descriptor), 4065 .bDescriptorType = UDESC_DEVICE, 4066 .bcdUSB = {0x00, 0x02}, 4067 .bDeviceClass = UDCLASS_HUB, 4068 .bDeviceSubClass = UDSUBCLASS_HUB, 4069 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4070 .bMaxPacketSize = 64, 4071 .bcdDevice = {0x00, 0x01}, 4072 .iManufacturer = 1, 4073 .iProduct = 2, 4074 .bNumConfigurations = 1, 4075 }; 4076 4077 static const struct dwc_otg_config_desc dwc_otg_confd = { 4078 .confd = { 4079 .bLength = sizeof(struct usb_config_descriptor), 4080 .bDescriptorType = UDESC_CONFIG, 4081 .wTotalLength[0] = sizeof(dwc_otg_confd), 4082 .bNumInterface = 1, 4083 .bConfigurationValue = 1, 4084 .iConfiguration = 0, 4085 .bmAttributes = UC_SELF_POWERED, 4086 .bMaxPower = 0, 4087 }, 4088 .ifcd = { 4089 .bLength = sizeof(struct usb_interface_descriptor), 4090 .bDescriptorType = UDESC_INTERFACE, 4091 .bNumEndpoints = 1, 4092 .bInterfaceClass = UICLASS_HUB, 4093 .bInterfaceSubClass = UISUBCLASS_HUB, 4094 .bInterfaceProtocol = 0, 4095 }, 4096 .endpd = { 4097 .bLength = sizeof(struct usb_endpoint_descriptor), 4098 .bDescriptorType = UDESC_ENDPOINT, 4099 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4100 .bmAttributes = UE_INTERRUPT, 4101 .wMaxPacketSize[0] = 8, 4102 .bInterval = 255, 4103 }, 4104 }; 4105 4106 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4107 4108 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4109 .bDescLength = sizeof(dwc_otg_hubd), 4110 .bDescriptorType = UDESC_HUB, 4111 .bNbrPorts = 1, 4112 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4113 .bPwrOn2PwrGood = 50, 4114 .bHubContrCurrent = 0, 4115 .DeviceRemovable = {0}, /* port is removable */ 4116 }; 4117 4118 #define STRING_VENDOR \ 4119 "D\0W\0C\0O\0T\0G" 4120 4121 #define STRING_PRODUCT \ 4122 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4123 4124 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4125 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4126 4127 static usb_error_t 4128 dwc_otg_roothub_exec(struct usb_device *udev, 4129 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4130 { 4131 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4132 const void *ptr; 4133 uint16_t len; 4134 uint16_t value; 4135 uint16_t index; 4136 usb_error_t err; 4137 4138 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4139 4140 /* buffer reset */ 4141 ptr = (const void *)&sc->sc_hub_temp; 4142 len = 0; 4143 err = 0; 4144 4145 value = UGETW(req->wValue); 4146 index = UGETW(req->wIndex); 4147 4148 /* demultiplex the control request */ 4149 4150 switch (req->bmRequestType) { 4151 case UT_READ_DEVICE: 4152 switch (req->bRequest) { 4153 case UR_GET_DESCRIPTOR: 4154 goto tr_handle_get_descriptor; 4155 case UR_GET_CONFIG: 4156 goto tr_handle_get_config; 4157 case UR_GET_STATUS: 4158 goto tr_handle_get_status; 4159 default: 4160 goto tr_stalled; 4161 } 4162 break; 4163 4164 case UT_WRITE_DEVICE: 4165 switch (req->bRequest) { 4166 case UR_SET_ADDRESS: 4167 goto tr_handle_set_address; 4168 case UR_SET_CONFIG: 4169 goto tr_handle_set_config; 4170 case UR_CLEAR_FEATURE: 4171 goto tr_valid; /* nop */ 4172 case UR_SET_DESCRIPTOR: 4173 goto tr_valid; /* nop */ 4174 case UR_SET_FEATURE: 4175 default: 4176 goto tr_stalled; 4177 } 4178 break; 4179 4180 case UT_WRITE_ENDPOINT: 4181 switch (req->bRequest) { 4182 case UR_CLEAR_FEATURE: 4183 switch (UGETW(req->wValue)) { 4184 case UF_ENDPOINT_HALT: 4185 goto tr_handle_clear_halt; 4186 case UF_DEVICE_REMOTE_WAKEUP: 4187 goto tr_handle_clear_wakeup; 4188 default: 4189 goto tr_stalled; 4190 } 4191 break; 4192 case UR_SET_FEATURE: 4193 switch (UGETW(req->wValue)) { 4194 case UF_ENDPOINT_HALT: 4195 goto tr_handle_set_halt; 4196 case UF_DEVICE_REMOTE_WAKEUP: 4197 goto tr_handle_set_wakeup; 4198 default: 4199 goto tr_stalled; 4200 } 4201 break; 4202 case UR_SYNCH_FRAME: 4203 goto tr_valid; /* nop */ 4204 default: 4205 goto tr_stalled; 4206 } 4207 break; 4208 4209 case UT_READ_ENDPOINT: 4210 switch (req->bRequest) { 4211 case UR_GET_STATUS: 4212 goto tr_handle_get_ep_status; 4213 default: 4214 goto tr_stalled; 4215 } 4216 break; 4217 4218 case UT_WRITE_INTERFACE: 4219 switch (req->bRequest) { 4220 case UR_SET_INTERFACE: 4221 goto tr_handle_set_interface; 4222 case UR_CLEAR_FEATURE: 4223 goto tr_valid; /* nop */ 4224 case UR_SET_FEATURE: 4225 default: 4226 goto tr_stalled; 4227 } 4228 break; 4229 4230 case UT_READ_INTERFACE: 4231 switch (req->bRequest) { 4232 case UR_GET_INTERFACE: 4233 goto tr_handle_get_interface; 4234 case UR_GET_STATUS: 4235 goto tr_handle_get_iface_status; 4236 default: 4237 goto tr_stalled; 4238 } 4239 break; 4240 4241 case UT_WRITE_CLASS_INTERFACE: 4242 case UT_WRITE_VENDOR_INTERFACE: 4243 /* XXX forward */ 4244 break; 4245 4246 case UT_READ_CLASS_INTERFACE: 4247 case UT_READ_VENDOR_INTERFACE: 4248 /* XXX forward */ 4249 break; 4250 4251 case UT_WRITE_CLASS_DEVICE: 4252 switch (req->bRequest) { 4253 case UR_CLEAR_FEATURE: 4254 goto tr_valid; 4255 case UR_SET_DESCRIPTOR: 4256 case UR_SET_FEATURE: 4257 break; 4258 default: 4259 goto tr_stalled; 4260 } 4261 break; 4262 4263 case UT_WRITE_CLASS_OTHER: 4264 switch (req->bRequest) { 4265 case UR_CLEAR_FEATURE: 4266 goto tr_handle_clear_port_feature; 4267 case UR_SET_FEATURE: 4268 goto tr_handle_set_port_feature; 4269 case UR_CLEAR_TT_BUFFER: 4270 case UR_RESET_TT: 4271 case UR_STOP_TT: 4272 goto tr_valid; 4273 4274 default: 4275 goto tr_stalled; 4276 } 4277 break; 4278 4279 case UT_READ_CLASS_OTHER: 4280 switch (req->bRequest) { 4281 case UR_GET_TT_STATE: 4282 goto tr_handle_get_tt_state; 4283 case UR_GET_STATUS: 4284 goto tr_handle_get_port_status; 4285 default: 4286 goto tr_stalled; 4287 } 4288 break; 4289 4290 case UT_READ_CLASS_DEVICE: 4291 switch (req->bRequest) { 4292 case UR_GET_DESCRIPTOR: 4293 goto tr_handle_get_class_descriptor; 4294 case UR_GET_STATUS: 4295 goto tr_handle_get_class_status; 4296 4297 default: 4298 goto tr_stalled; 4299 } 4300 break; 4301 default: 4302 goto tr_stalled; 4303 } 4304 goto tr_valid; 4305 4306 tr_handle_get_descriptor: 4307 switch (value >> 8) { 4308 case UDESC_DEVICE: 4309 if (value & 0xff) { 4310 goto tr_stalled; 4311 } 4312 len = sizeof(dwc_otg_devd); 4313 ptr = (const void *)&dwc_otg_devd; 4314 goto tr_valid; 4315 case UDESC_CONFIG: 4316 if (value & 0xff) { 4317 goto tr_stalled; 4318 } 4319 len = sizeof(dwc_otg_confd); 4320 ptr = (const void *)&dwc_otg_confd; 4321 goto tr_valid; 4322 case UDESC_STRING: 4323 switch (value & 0xff) { 4324 case 0: /* Language table */ 4325 len = sizeof(usb_string_lang_en); 4326 ptr = (const void *)&usb_string_lang_en; 4327 goto tr_valid; 4328 4329 case 1: /* Vendor */ 4330 len = sizeof(dwc_otg_vendor); 4331 ptr = (const void *)&dwc_otg_vendor; 4332 goto tr_valid; 4333 4334 case 2: /* Product */ 4335 len = sizeof(dwc_otg_product); 4336 ptr = (const void *)&dwc_otg_product; 4337 goto tr_valid; 4338 default: 4339 break; 4340 } 4341 break; 4342 default: 4343 goto tr_stalled; 4344 } 4345 goto tr_stalled; 4346 4347 tr_handle_get_config: 4348 len = 1; 4349 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4350 goto tr_valid; 4351 4352 tr_handle_get_status: 4353 len = 2; 4354 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4355 goto tr_valid; 4356 4357 tr_handle_set_address: 4358 if (value & 0xFF00) { 4359 goto tr_stalled; 4360 } 4361 sc->sc_rt_addr = value; 4362 goto tr_valid; 4363 4364 tr_handle_set_config: 4365 if (value >= 2) { 4366 goto tr_stalled; 4367 } 4368 sc->sc_conf = value; 4369 goto tr_valid; 4370 4371 tr_handle_get_interface: 4372 len = 1; 4373 sc->sc_hub_temp.wValue[0] = 0; 4374 goto tr_valid; 4375 4376 tr_handle_get_tt_state: 4377 tr_handle_get_class_status: 4378 tr_handle_get_iface_status: 4379 tr_handle_get_ep_status: 4380 len = 2; 4381 USETW(sc->sc_hub_temp.wValue, 0); 4382 goto tr_valid; 4383 4384 tr_handle_set_halt: 4385 tr_handle_set_interface: 4386 tr_handle_set_wakeup: 4387 tr_handle_clear_wakeup: 4388 tr_handle_clear_halt: 4389 goto tr_valid; 4390 4391 tr_handle_clear_port_feature: 4392 if (index != 1) 4393 goto tr_stalled; 4394 4395 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4396 4397 switch (value) { 4398 case UHF_PORT_SUSPEND: 4399 dwc_otg_wakeup_peer(sc); 4400 break; 4401 4402 case UHF_PORT_ENABLE: 4403 if (sc->sc_flags.status_device_mode == 0) { 4404 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4405 sc->sc_hprt_val | HPRT_PRTENA); 4406 } 4407 sc->sc_flags.port_enabled = 0; 4408 break; 4409 4410 case UHF_C_PORT_RESET: 4411 sc->sc_flags.change_reset = 0; 4412 break; 4413 4414 case UHF_C_PORT_ENABLE: 4415 sc->sc_flags.change_enabled = 0; 4416 break; 4417 4418 case UHF_C_PORT_OVER_CURRENT: 4419 sc->sc_flags.change_over_current = 0; 4420 break; 4421 4422 case UHF_PORT_TEST: 4423 case UHF_PORT_INDICATOR: 4424 /* nops */ 4425 break; 4426 4427 case UHF_PORT_POWER: 4428 sc->sc_flags.port_powered = 0; 4429 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4430 sc->sc_hprt_val = 0; 4431 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4432 } 4433 dwc_otg_pull_down(sc); 4434 dwc_otg_clocks_off(sc); 4435 break; 4436 4437 case UHF_C_PORT_CONNECTION: 4438 /* clear connect change flag */ 4439 sc->sc_flags.change_connect = 0; 4440 break; 4441 4442 case UHF_C_PORT_SUSPEND: 4443 sc->sc_flags.change_suspend = 0; 4444 break; 4445 4446 default: 4447 err = USB_ERR_IOERROR; 4448 goto done; 4449 } 4450 goto tr_valid; 4451 4452 tr_handle_set_port_feature: 4453 if (index != 1) { 4454 goto tr_stalled; 4455 } 4456 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4457 4458 switch (value) { 4459 case UHF_PORT_ENABLE: 4460 break; 4461 4462 case UHF_PORT_SUSPEND: 4463 if (sc->sc_flags.status_device_mode == 0) { 4464 /* set suspend BIT */ 4465 sc->sc_hprt_val |= HPRT_PRTSUSP; 4466 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4467 4468 /* generate HUB suspend event */ 4469 dwc_otg_suspend_irq(sc); 4470 } 4471 break; 4472 4473 case UHF_PORT_RESET: 4474 if (sc->sc_flags.status_device_mode == 0) { 4475 4476 DPRINTF("PORT RESET\n"); 4477 4478 /* enable PORT reset */ 4479 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4480 4481 /* Wait 62.5ms for reset to complete */ 4482 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4483 4484 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4485 4486 /* Wait 62.5ms for reset to complete */ 4487 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4488 4489 /* reset FIFOs */ 4490 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4491 4492 sc->sc_flags.change_reset = 1; 4493 } else { 4494 err = USB_ERR_IOERROR; 4495 } 4496 break; 4497 4498 case UHF_PORT_TEST: 4499 case UHF_PORT_INDICATOR: 4500 /* nops */ 4501 break; 4502 case UHF_PORT_POWER: 4503 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4504 sc->sc_hprt_val |= HPRT_PRTPWR; 4505 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4506 } 4507 sc->sc_flags.port_powered = 1; 4508 break; 4509 default: 4510 err = USB_ERR_IOERROR; 4511 goto done; 4512 } 4513 goto tr_valid; 4514 4515 tr_handle_get_port_status: 4516 4517 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4518 4519 if (index != 1) 4520 goto tr_stalled; 4521 4522 if (sc->sc_flags.status_vbus) 4523 dwc_otg_clocks_on(sc); 4524 else 4525 dwc_otg_clocks_off(sc); 4526 4527 /* Select Device Side Mode */ 4528 4529 if (sc->sc_flags.status_device_mode) { 4530 value = UPS_PORT_MODE_DEVICE; 4531 dwc_otg_timer_stop(sc); 4532 } else { 4533 value = 0; 4534 dwc_otg_timer_start(sc); 4535 } 4536 4537 if (sc->sc_flags.status_high_speed) 4538 value |= UPS_HIGH_SPEED; 4539 else if (sc->sc_flags.status_low_speed) 4540 value |= UPS_LOW_SPEED; 4541 4542 if (sc->sc_flags.port_powered) 4543 value |= UPS_PORT_POWER; 4544 4545 if (sc->sc_flags.port_enabled) 4546 value |= UPS_PORT_ENABLED; 4547 4548 if (sc->sc_flags.port_over_current) 4549 value |= UPS_OVERCURRENT_INDICATOR; 4550 4551 if (sc->sc_flags.status_vbus && 4552 sc->sc_flags.status_bus_reset) 4553 value |= UPS_CURRENT_CONNECT_STATUS; 4554 4555 if (sc->sc_flags.status_suspend) 4556 value |= UPS_SUSPEND; 4557 4558 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4559 4560 value = 0; 4561 4562 if (sc->sc_flags.change_connect) 4563 value |= UPS_C_CONNECT_STATUS; 4564 if (sc->sc_flags.change_suspend) 4565 value |= UPS_C_SUSPEND; 4566 if (sc->sc_flags.change_reset) 4567 value |= UPS_C_PORT_RESET; 4568 if (sc->sc_flags.change_over_current) 4569 value |= UPS_C_OVERCURRENT_INDICATOR; 4570 4571 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4572 len = sizeof(sc->sc_hub_temp.ps); 4573 goto tr_valid; 4574 4575 tr_handle_get_class_descriptor: 4576 if (value & 0xFF) { 4577 goto tr_stalled; 4578 } 4579 ptr = (const void *)&dwc_otg_hubd; 4580 len = sizeof(dwc_otg_hubd); 4581 goto tr_valid; 4582 4583 tr_stalled: 4584 err = USB_ERR_STALLED; 4585 tr_valid: 4586 done: 4587 *plength = len; 4588 *pptr = ptr; 4589 return (err); 4590 } 4591 4592 static void 4593 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4594 { 4595 struct usb_xfer *xfer; 4596 void *last_obj; 4597 uint32_t ntd; 4598 uint32_t n; 4599 uint8_t ep_no; 4600 uint8_t ep_type; 4601 4602 xfer = parm->curr_xfer; 4603 4604 /* 4605 * NOTE: This driver does not use any of the parameters that 4606 * are computed from the following values. Just set some 4607 * reasonable dummies: 4608 */ 4609 parm->hc_max_packet_size = 0x500; 4610 parm->hc_max_packet_count = 3; 4611 parm->hc_max_frame_size = 3 * 0x500; 4612 4613 usbd_transfer_setup_sub(parm); 4614 4615 /* 4616 * compute maximum number of TDs 4617 */ 4618 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4619 4620 if (ep_type == UE_CONTROL) { 4621 4622 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4623 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4624 } else { 4625 4626 ntd = xfer->nframes + 1 /* SYNC */ ; 4627 } 4628 4629 /* 4630 * check if "usbd_transfer_setup_sub" set an error 4631 */ 4632 if (parm->err) 4633 return; 4634 4635 /* 4636 * allocate transfer descriptors 4637 */ 4638 last_obj = NULL; 4639 4640 ep_no = xfer->endpointno & UE_ADDR; 4641 4642 /* 4643 * Check for a valid endpoint profile in USB device mode: 4644 */ 4645 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4646 const struct usb_hw_ep_profile *pf; 4647 4648 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4649 4650 if (pf == NULL) { 4651 /* should not happen */ 4652 parm->err = USB_ERR_INVAL; 4653 return; 4654 } 4655 } 4656 4657 /* align data */ 4658 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4659 4660 for (n = 0; n != ntd; n++) { 4661 4662 struct dwc_otg_td *td; 4663 4664 if (parm->buf) { 4665 4666 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4667 4668 /* init TD */ 4669 td->max_packet_size = xfer->max_packet_size; 4670 td->max_packet_count = xfer->max_packet_count; 4671 td->ep_no = ep_no; 4672 td->ep_type = ep_type; 4673 td->obj_next = last_obj; 4674 4675 last_obj = td; 4676 } 4677 parm->size[0] += sizeof(*td); 4678 } 4679 4680 xfer->td_start[0] = last_obj; 4681 } 4682 4683 static void 4684 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4685 { 4686 return; 4687 } 4688 4689 static void 4690 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4691 struct usb_endpoint *ep) 4692 { 4693 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4694 4695 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4696 ep, udev->address, 4697 edesc->bEndpointAddress, udev->flags.usb_mode, 4698 sc->sc_rt_addr, udev->device_index); 4699 4700 if (udev->device_index != sc->sc_rt_addr) { 4701 4702 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4703 if (udev->speed != USB_SPEED_FULL && 4704 udev->speed != USB_SPEED_HIGH) { 4705 /* not supported */ 4706 return; 4707 } 4708 } else { 4709 if (udev->speed == USB_SPEED_HIGH) { 4710 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4711 /* high bandwidth endpoint - not tested */ 4712 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4713 return; 4714 } 4715 } 4716 } 4717 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4718 ep->methods = &dwc_otg_device_isoc_methods; 4719 else 4720 ep->methods = &dwc_otg_device_non_isoc_methods; 4721 } 4722 } 4723 4724 static void 4725 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4726 { 4727 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4728 4729 switch (state) { 4730 case USB_HW_POWER_SUSPEND: 4731 dwc_otg_suspend(sc); 4732 break; 4733 case USB_HW_POWER_SHUTDOWN: 4734 dwc_otg_uninit(sc); 4735 break; 4736 case USB_HW_POWER_RESUME: 4737 dwc_otg_resume(sc); 4738 break; 4739 default: 4740 break; 4741 } 4742 } 4743 4744 static void 4745 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4746 { 4747 /* DMA delay - wait until any use of memory is finished */ 4748 *pus = (2125); /* microseconds */ 4749 } 4750 4751 static void 4752 dwc_otg_device_resume(struct usb_device *udev) 4753 { 4754 DPRINTF("\n"); 4755 4756 /* poll all transfers again to restart resumed ones */ 4757 dwc_otg_do_poll(udev->bus); 4758 } 4759 4760 static void 4761 dwc_otg_device_suspend(struct usb_device *udev) 4762 { 4763 DPRINTF("\n"); 4764 } 4765 4766 static const struct usb_bus_methods dwc_otg_bus_methods = 4767 { 4768 .endpoint_init = &dwc_otg_ep_init, 4769 .xfer_setup = &dwc_otg_xfer_setup, 4770 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4771 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4772 .xfer_stall = &dwc_otg_xfer_stall, 4773 .set_stall = &dwc_otg_set_stall, 4774 .clear_stall = &dwc_otg_clear_stall, 4775 .roothub_exec = &dwc_otg_roothub_exec, 4776 .xfer_poll = &dwc_otg_do_poll, 4777 .device_state_change = &dwc_otg_device_state_change, 4778 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4779 .get_dma_delay = &dwc_otg_get_dma_delay, 4780 .device_resume = &dwc_otg_device_resume, 4781 .device_suspend = &dwc_otg_device_suspend, 4782 }; 4783