1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * This file contains the driver for the DesignWare series USB 2.0 OTG 28 * Controller. This driver currently only supports the device mode of 29 * the USB hardware. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 #include <dev/usb/controller/dwc_otgreg.h> 85 86 #define DWC_OTG_BUS2SC(bus) \ 87 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 89 90 #define DWC_OTG_PC2SC(pc) \ 91 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 92 93 #define DWC_OTG_MSK_GINT_ENABLED \ 94 (GINTSTS_ENUMDONE | \ 95 GINTSTS_USBRST | \ 96 GINTSTS_USBSUSP | \ 97 GINTSTS_IEPINT | \ 98 GINTSTS_RXFLVL | \ 99 GINTSTS_SESSREQINT) 100 101 #define DWC_OTG_USE_HSIC 0 102 103 #ifdef USB_DEBUG 104 static int dwc_otg_debug = 0; 105 106 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 107 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 108 &dwc_otg_debug, 0, "DWC OTG debug level"); 109 #endif 110 111 #define DWC_OTG_INTR_ENDPT 1 112 113 /* prototypes */ 114 115 struct usb_bus_methods dwc_otg_bus_methods; 116 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 117 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods; 118 119 static dwc_otg_cmd_t dwc_otg_setup_rx; 120 static dwc_otg_cmd_t dwc_otg_data_rx; 121 static dwc_otg_cmd_t dwc_otg_data_tx; 122 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 123 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 124 static void dwc_otg_do_poll(struct usb_bus *); 125 static void dwc_otg_standard_done(struct usb_xfer *); 126 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 127 128 /* 129 * Here is a configuration that the chip supports. 130 */ 131 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 132 133 [0] = { 134 .max_in_frame_size = 64,/* fixed */ 135 .max_out_frame_size = 64, /* fixed */ 136 .is_simplex = 1, 137 .support_control = 1, 138 } 139 }; 140 141 static void 142 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 143 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 144 { 145 struct dwc_otg_softc *sc; 146 147 sc = DWC_OTG_BUS2SC(udev->bus); 148 149 if (ep_addr < sc->sc_dev_ep_max) 150 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 151 else 152 *ppf = NULL; 153 } 154 155 static int 156 dwc_otg_init_fifo(struct dwc_otg_softc *sc) 157 { 158 struct dwc_otg_profile *pf; 159 uint32_t fifo_size; 160 uint32_t fifo_regs; 161 uint32_t tx_start; 162 uint8_t x; 163 164 fifo_size = sc->sc_fifo_size; 165 166 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 167 168 if (fifo_size >= fifo_regs) 169 fifo_size -= fifo_regs; 170 else 171 fifo_size = 0; 172 173 /* split equally for IN and OUT */ 174 fifo_size /= 2; 175 176 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 177 178 /* align to 4-bytes */ 179 fifo_size &= ~3; 180 181 tx_start = fifo_size; 182 183 if (fifo_size < 0x40) { 184 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 185 USB_BUS_UNLOCK(&sc->sc_bus); 186 return (EINVAL); 187 } 188 189 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4)); 190 fifo_size -= 0x40; 191 tx_start += 0x40; 192 193 /* setup control endpoint profile */ 194 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 195 196 for (x = 1; x != sc->sc_dev_ep_max; x++) { 197 198 pf = sc->sc_hw_ep_profile + x; 199 200 pf->usb.max_out_frame_size = 1024 * 3; 201 pf->usb.is_simplex = 0; /* assume duplex */ 202 pf->usb.support_bulk = 1; 203 pf->usb.support_interrupt = 1; 204 pf->usb.support_isochronous = 1; 205 pf->usb.support_out = 1; 206 207 if (x < sc->sc_dev_in_ep_max) { 208 uint32_t limit; 209 210 limit = (x == 1) ? DWC_OTG_MAX_TXN : 211 (DWC_OTG_MAX_TXN / 2); 212 213 if (fifo_size >= limit) { 214 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 215 ((limit / 4) << 16) | 216 (tx_start / 4)); 217 tx_start += limit; 218 fifo_size -= limit; 219 pf->usb.max_in_frame_size = 0x200; 220 pf->usb.support_in = 1; 221 pf->max_buffer = limit; 222 223 } else if (fifo_size >= 0x80) { 224 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 225 ((0x80 / 4) << 16) | (tx_start / 4)); 226 tx_start += 0x80; 227 fifo_size -= 0x80; 228 pf->usb.max_in_frame_size = 0x40; 229 pf->usb.support_in = 1; 230 231 } else { 232 pf->usb.is_simplex = 1; 233 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 234 (0x0 << 16) | (tx_start / 4)); 235 } 236 } else { 237 pf->usb.is_simplex = 1; 238 } 239 240 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 241 pf->usb.max_in_frame_size, 242 pf->usb.max_out_frame_size); 243 } 244 245 /* reset RX FIFO */ 246 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 247 GRSTCTL_RXFFLSH); 248 249 /* reset all TX FIFOs */ 250 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 251 GRSTCTL_TXFIFO(0x10) | 252 GRSTCTL_TXFFLSH); 253 254 return (0); 255 } 256 257 static void 258 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 259 { 260 if (sc->sc_flags.clocks_off && 261 sc->sc_flags.port_powered) { 262 263 DPRINTFN(5, "\n"); 264 265 /* TODO - platform specific */ 266 267 sc->sc_flags.clocks_off = 0; 268 } 269 } 270 271 static void 272 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 273 { 274 if (!sc->sc_flags.clocks_off) { 275 276 DPRINTFN(5, "\n"); 277 278 /* TODO - platform specific */ 279 280 sc->sc_flags.clocks_off = 1; 281 } 282 } 283 284 static void 285 dwc_otg_pull_up(struct dwc_otg_softc *sc) 286 { 287 uint32_t temp; 288 289 /* pullup D+, if possible */ 290 291 if (!sc->sc_flags.d_pulled_up && 292 sc->sc_flags.port_powered) { 293 sc->sc_flags.d_pulled_up = 1; 294 295 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 296 temp &= ~DCTL_SFTDISCON; 297 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 298 } 299 } 300 301 static void 302 dwc_otg_pull_down(struct dwc_otg_softc *sc) 303 { 304 uint32_t temp; 305 306 /* pulldown D+, if possible */ 307 308 if (sc->sc_flags.d_pulled_up) { 309 sc->sc_flags.d_pulled_up = 0; 310 311 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 312 temp |= DCTL_SFTDISCON; 313 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 314 } 315 } 316 317 static void 318 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 319 { 320 if (sc->sc_flags.status_suspend) { 321 /* update status bits */ 322 sc->sc_flags.status_suspend = 0; 323 sc->sc_flags.change_suspend = 1; 324 325 /* 326 * Disable resume interrupt and enable suspend 327 * interrupt: 328 */ 329 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 330 sc->sc_irq_mask |= GINTSTS_USBSUSP; 331 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 332 333 /* complete root HUB interrupt endpoint */ 334 dwc_otg_root_intr(sc); 335 } 336 } 337 338 static void 339 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 340 { 341 uint32_t temp; 342 343 if (!sc->sc_flags.status_suspend) 344 return; 345 346 DPRINTFN(5, "Remote wakeup\n"); 347 348 /* enable remote wakeup signalling */ 349 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 350 temp |= DCTL_RMTWKUPSIG; 351 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 352 353 /* Wait 8ms for remote wakeup to complete. */ 354 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 355 356 temp &= ~DCTL_RMTWKUPSIG; 357 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 358 359 /* need to fake resume IRQ */ 360 dwc_otg_resume_irq(sc); 361 } 362 363 static void 364 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 365 { 366 uint32_t temp; 367 368 DPRINTFN(5, "addr=%d\n", addr); 369 370 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 371 temp &= ~DCFG_DEVADDR_SET(0x7F); 372 temp |= DCFG_DEVADDR_SET(addr); 373 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 374 } 375 376 static void 377 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 378 { 379 DPRINTFN(5, "RX status clear\n"); 380 381 /* enable RX FIFO level interrupt */ 382 sc->sc_irq_mask |= GINTSTS_RXFLVL; 383 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 384 385 /* clear cached status */ 386 sc->sc_last_rx_status = 0; 387 } 388 389 static uint8_t 390 dwc_otg_setup_rx(struct dwc_otg_td *td) 391 { 392 struct dwc_otg_softc *sc; 393 struct usb_device_request req __aligned(4); 394 uint32_t temp; 395 uint16_t count; 396 397 /* get pointer to softc */ 398 sc = DWC_OTG_PC2SC(td->pc); 399 400 /* check endpoint status */ 401 402 if (sc->sc_last_rx_status == 0) 403 goto not_complete; 404 405 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 406 goto not_complete; 407 408 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 409 GRXSTSRD_DPID_DATA0) { 410 /* release FIFO */ 411 dwc_otg_common_rx_ack(sc); 412 goto not_complete; 413 } 414 415 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 416 GRXSTSRD_STP_DATA) { 417 /* release FIFO */ 418 dwc_otg_common_rx_ack(sc); 419 goto not_complete; 420 } 421 422 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 423 424 /* clear did stall */ 425 td->did_stall = 0; 426 427 /* get the packet byte count */ 428 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 429 430 /* verify data length */ 431 if (count != td->remainder) { 432 DPRINTFN(0, "Invalid SETUP packet " 433 "length, %d bytes\n", count); 434 /* release FIFO */ 435 dwc_otg_common_rx_ack(sc); 436 goto not_complete; 437 } 438 if (count != sizeof(req)) { 439 DPRINTFN(0, "Unsupported SETUP packet " 440 "length, %d bytes\n", count); 441 /* release FIFO */ 442 dwc_otg_common_rx_ack(sc); 443 goto not_complete; 444 } 445 446 /* copy in control request */ 447 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 448 449 /* copy data into real buffer */ 450 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 451 452 td->offset = sizeof(req); 453 td->remainder = 0; 454 455 /* sneak peek the set address */ 456 if ((req.bmRequestType == UT_WRITE_DEVICE) && 457 (req.bRequest == UR_SET_ADDRESS)) { 458 /* must write address before ZLP */ 459 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 460 } 461 462 /* don't send any data by default */ 463 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 464 DXEPTSIZ_SET_NPKT(0) | 465 DXEPTSIZ_SET_NBYTES(0)); 466 467 temp = sc->sc_in_ctl[0]; 468 469 /* enable IN endpoint */ 470 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 471 temp | DIEPCTL_EPENA); 472 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 473 temp | DIEPCTL_SNAK); 474 475 /* reset IN endpoint buffer */ 476 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 477 GRSTCTL_TXFIFO(0) | 478 GRSTCTL_TXFFLSH); 479 480 /* acknowledge RX status */ 481 dwc_otg_common_rx_ack(sc); 482 return (0); /* complete */ 483 484 not_complete: 485 /* abort any ongoing transfer, before enabling again */ 486 487 temp = sc->sc_out_ctl[0]; 488 489 temp |= DOEPCTL_EPENA | 490 DOEPCTL_SNAK; 491 492 /* enable OUT endpoint */ 493 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 494 495 if (!td->did_stall) { 496 td->did_stall = 1; 497 498 DPRINTFN(5, "stalling IN and OUT direction\n"); 499 500 /* set stall after enabling endpoint */ 501 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 502 temp | DOEPCTL_STALL); 503 504 temp = sc->sc_in_ctl[0]; 505 506 /* set stall assuming endpoint is enabled */ 507 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 508 temp | DIEPCTL_STALL); 509 } 510 511 /* setup number of buffers to receive */ 512 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 513 DXEPTSIZ_SET_MULTI(3) | 514 DXEPTSIZ_SET_NPKT(1) | 515 DXEPTSIZ_SET_NBYTES(sizeof(req))); 516 517 return (1); /* not complete */ 518 } 519 520 static uint8_t 521 dwc_otg_data_rx(struct dwc_otg_td *td) 522 { 523 struct dwc_otg_softc *sc; 524 uint32_t temp; 525 uint16_t count; 526 uint8_t got_short; 527 528 got_short = 0; 529 530 /* get pointer to softc */ 531 sc = DWC_OTG_PC2SC(td->pc); 532 533 /* check endpoint status */ 534 if (sc->sc_last_rx_status == 0) 535 goto not_complete; 536 537 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 538 goto not_complete; 539 540 /* check for SETUP packet */ 541 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 542 GRXSTSRD_STP_DATA) { 543 if (td->remainder == 0) { 544 /* 545 * We are actually complete and have 546 * received the next SETUP 547 */ 548 DPRINTFN(5, "faking complete\n"); 549 return (0); /* complete */ 550 } 551 /* 552 * USB Host Aborted the transfer. 553 */ 554 td->error = 1; 555 return (0); /* complete */ 556 } 557 558 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 559 GRXSTSRD_OUT_DATA) { 560 /* release FIFO */ 561 dwc_otg_common_rx_ack(sc); 562 goto not_complete; 563 } 564 565 /* get the packet byte count */ 566 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 567 568 /* verify the packet byte count */ 569 if (count != td->max_packet_size) { 570 if (count < td->max_packet_size) { 571 /* we have a short packet */ 572 td->short_pkt = 1; 573 got_short = 1; 574 } else { 575 /* invalid USB packet */ 576 td->error = 1; 577 578 /* release FIFO */ 579 dwc_otg_common_rx_ack(sc); 580 return (0); /* we are complete */ 581 } 582 } 583 /* verify the packet byte count */ 584 if (count > td->remainder) { 585 /* invalid USB packet */ 586 td->error = 1; 587 588 /* release FIFO */ 589 dwc_otg_common_rx_ack(sc); 590 return (0); /* we are complete */ 591 } 592 593 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 594 td->remainder -= count; 595 td->offset += count; 596 597 /* release FIFO */ 598 dwc_otg_common_rx_ack(sc); 599 600 /* check if we are complete */ 601 if ((td->remainder == 0) || got_short) { 602 if (td->short_pkt) { 603 /* we are complete */ 604 return (0); 605 } 606 /* else need to receive a zero length packet */ 607 } 608 609 not_complete: 610 611 temp = sc->sc_out_ctl[td->ep_no]; 612 613 temp |= DOEPCTL_EPENA | 614 DOEPCTL_CNAK; 615 616 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 617 618 /* enable SETUP and transfer complete interrupt */ 619 if (td->ep_no == 0) { 620 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 621 DXEPTSIZ_SET_NPKT(1) | 622 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 623 } else { 624 /* allow reception of multiple packets */ 625 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 626 DXEPTSIZ_SET_MULTI(1) | 627 DXEPTSIZ_SET_NPKT(4) | 628 DXEPTSIZ_SET_NBYTES(4 * 629 ((td->max_packet_size + 3) & ~3))); 630 } 631 return (1); /* not complete */ 632 } 633 634 static uint8_t 635 dwc_otg_data_tx(struct dwc_otg_td *td) 636 { 637 struct dwc_otg_softc *sc; 638 uint32_t max_buffer; 639 uint32_t count; 640 uint32_t fifo_left; 641 uint32_t mpkt; 642 uint32_t temp; 643 uint8_t to; 644 645 to = 3; /* don't loop forever! */ 646 647 /* get pointer to softc */ 648 sc = DWC_OTG_PC2SC(td->pc); 649 650 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 651 652 repeat: 653 /* check for for endpoint 0 data */ 654 655 temp = sc->sc_last_rx_status; 656 657 if ((td->ep_no == 0) && (temp != 0) && 658 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 659 660 if ((temp & GRXSTSRD_PKTSTS_MASK) != 661 GRXSTSRD_STP_DATA) { 662 663 /* dump data - wrong direction */ 664 dwc_otg_common_rx_ack(sc); 665 } else { 666 /* 667 * The current transfer was cancelled 668 * by the USB Host: 669 */ 670 td->error = 1; 671 return (0); /* complete */ 672 } 673 } 674 675 /* fill in more TX data, if possible */ 676 if (td->tx_bytes != 0) { 677 678 uint16_t cpkt; 679 680 /* check if packets have been transferred */ 681 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 682 683 /* get current packet number */ 684 cpkt = DXEPTSIZ_GET_NPKT(temp); 685 686 if (cpkt >= td->npkt) { 687 fifo_left = 0; 688 } else { 689 if (max_buffer != 0) { 690 fifo_left = (td->npkt - cpkt) * 691 td->max_packet_size; 692 693 if (fifo_left > max_buffer) 694 fifo_left = max_buffer; 695 } else { 696 fifo_left = td->max_packet_size; 697 } 698 } 699 700 count = td->tx_bytes; 701 if (count > fifo_left) 702 count = fifo_left; 703 704 if (count != 0) { 705 706 /* clear topmost word before copy */ 707 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 708 709 /* copy out data */ 710 usbd_copy_out(td->pc, td->offset, 711 sc->sc_tx_bounce_buffer, count); 712 713 /* transfer data into FIFO */ 714 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 715 DOTG_DFIFO(td->ep_no), 716 sc->sc_tx_bounce_buffer, (count + 3) / 4); 717 718 td->tx_bytes -= count; 719 td->remainder -= count; 720 td->offset += count; 721 td->npkt = cpkt; 722 } 723 if (td->tx_bytes != 0) 724 goto not_complete; 725 726 /* check remainder */ 727 if (td->remainder == 0) { 728 if (td->short_pkt) 729 return (0); /* complete */ 730 731 /* else we need to transmit a short packet */ 732 } 733 } 734 735 if (!to--) 736 goto not_complete; 737 738 /* check if not all packets have been transferred */ 739 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 740 741 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 742 743 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 744 "DIEPCTL=0x%08x\n", td->ep_no, 745 DXEPTSIZ_GET_NPKT(temp), 746 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 747 748 goto not_complete; 749 } 750 751 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 752 753 /* try to optimise by sending more data */ 754 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 755 756 /* send multiple packets at the same time */ 757 mpkt = max_buffer / td->max_packet_size; 758 759 if (mpkt > 0x3FE) 760 mpkt = 0x3FE; 761 762 count = td->remainder; 763 if (count > 0x7FFFFF) 764 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 765 766 td->npkt = count / td->max_packet_size; 767 768 /* 769 * NOTE: We could use 0x3FE instead of "mpkt" in the 770 * check below to get more throughput, but then we 771 * have a dependency towards non-generic chip features 772 * to disable the TX-FIFO-EMPTY interrupts on a per 773 * endpoint basis. Increase the maximum buffer size of 774 * the IN endpoint to increase the performance. 775 */ 776 if (td->npkt > mpkt) { 777 td->npkt = mpkt; 778 count = td->max_packet_size * mpkt; 779 } else if ((count == 0) || (count % td->max_packet_size)) { 780 /* we are transmitting a short packet */ 781 td->npkt++; 782 td->short_pkt = 1; 783 } 784 } else { 785 /* send one packet at a time */ 786 mpkt = 1; 787 count = td->max_packet_size; 788 if (td->remainder < count) { 789 /* we have a short packet */ 790 td->short_pkt = 1; 791 count = td->remainder; 792 } 793 td->npkt = 1; 794 } 795 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 796 DXEPTSIZ_SET_MULTI(1) | 797 DXEPTSIZ_SET_NPKT(td->npkt) | 798 DXEPTSIZ_SET_NBYTES(count)); 799 800 /* make room for buffering */ 801 td->npkt += mpkt; 802 803 temp = sc->sc_in_ctl[td->ep_no]; 804 805 /* must enable before writing data to FIFO */ 806 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 807 DIEPCTL_EPENA | 808 DIEPCTL_CNAK); 809 810 td->tx_bytes = count; 811 812 /* check remainder */ 813 if (td->tx_bytes == 0 && 814 td->remainder == 0) { 815 if (td->short_pkt) 816 return (0); /* complete */ 817 818 /* else we need to transmit a short packet */ 819 } 820 goto repeat; 821 822 not_complete: 823 return (1); /* not complete */ 824 } 825 826 static uint8_t 827 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 828 { 829 struct dwc_otg_softc *sc; 830 uint32_t temp; 831 832 /* get pointer to softc */ 833 sc = DWC_OTG_PC2SC(td->pc); 834 835 /* 836 * If all packets are transferred we are complete: 837 */ 838 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 839 840 /* check that all packets have been transferred */ 841 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 842 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 843 goto not_complete; 844 } 845 return (0); 846 847 not_complete: 848 849 /* we only want to know if there is a SETUP packet or free IN packet */ 850 851 temp = sc->sc_last_rx_status; 852 853 if ((td->ep_no == 0) && (temp != 0) && 854 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 855 856 if ((temp & GRXSTSRD_PKTSTS_MASK) == 857 GRXSTSRD_STP_DATA) { 858 DPRINTFN(5, "faking complete\n"); 859 /* 860 * Race condition: We are complete! 861 */ 862 return (0); 863 } else { 864 /* dump data - wrong direction */ 865 dwc_otg_common_rx_ack(sc); 866 } 867 } 868 return (1); /* not complete */ 869 } 870 871 static uint8_t 872 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 873 { 874 struct dwc_otg_td *td; 875 876 DPRINTFN(9, "\n"); 877 878 td = xfer->td_transfer_cache; 879 while (1) { 880 if ((td->func) (td)) { 881 /* operation in progress */ 882 break; 883 } 884 if (((void *)td) == xfer->td_transfer_last) { 885 goto done; 886 } 887 if (td->error) { 888 goto done; 889 } else if (td->remainder > 0) { 890 /* 891 * We had a short transfer. If there is no alternate 892 * next, stop processing ! 893 */ 894 if (!td->alt_next) 895 goto done; 896 } 897 898 /* 899 * Fetch the next transfer descriptor and transfer 900 * some flags to the next transfer descriptor 901 */ 902 td = td->obj_next; 903 xfer->td_transfer_cache = td; 904 } 905 return (1); /* not complete */ 906 907 done: 908 /* compute all actual lengths */ 909 910 dwc_otg_standard_done(xfer); 911 return (0); /* complete */ 912 } 913 914 static void 915 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 916 { 917 struct usb_xfer *xfer; 918 uint32_t temp; 919 uint8_t got_rx_status; 920 921 repeat: 922 if (sc->sc_last_rx_status == 0) { 923 924 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 925 if (temp & GINTSTS_RXFLVL) { 926 /* pop current status */ 927 sc->sc_last_rx_status = 928 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 929 } 930 931 if (sc->sc_last_rx_status != 0) { 932 933 uint8_t ep_no; 934 935 temp = GRXSTSRD_BCNT_GET( 936 sc->sc_last_rx_status); 937 ep_no = GRXSTSRD_CHNUM_GET( 938 sc->sc_last_rx_status); 939 940 /* receive data, if any */ 941 if (temp != 0) { 942 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 943 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 944 DOTG_DFIFO(ep_no), 945 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 946 } 947 948 temp = sc->sc_last_rx_status & 949 GRXSTSRD_PKTSTS_MASK; 950 951 /* non-data messages we simply skip */ 952 if (temp != GRXSTSRD_STP_DATA && 953 temp != GRXSTSRD_OUT_DATA) { 954 dwc_otg_common_rx_ack(sc); 955 goto repeat; 956 } 957 958 /* check if we should dump the data */ 959 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 960 dwc_otg_common_rx_ack(sc); 961 goto repeat; 962 } 963 964 got_rx_status = 1; 965 966 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 967 sc->sc_last_rx_status, ep_no, 968 (sc->sc_last_rx_status >> 15) & 3, 969 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 970 (sc->sc_last_rx_status >> 17) & 15); 971 } else { 972 got_rx_status = 0; 973 } 974 } else { 975 uint8_t ep_no; 976 977 ep_no = GRXSTSRD_CHNUM_GET( 978 sc->sc_last_rx_status); 979 980 /* check if we should dump the data */ 981 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 982 dwc_otg_common_rx_ack(sc); 983 goto repeat; 984 } 985 986 got_rx_status = 1; 987 } 988 989 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 990 if (!dwc_otg_xfer_do_fifo(xfer)) { 991 /* queue has been modified */ 992 goto repeat; 993 } 994 } 995 996 if (got_rx_status) { 997 if (sc->sc_last_rx_status == 0) 998 goto repeat; 999 1000 /* disable RX FIFO level interrupt */ 1001 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 1002 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1003 } 1004 } 1005 1006 static void 1007 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 1008 { 1009 DPRINTFN(5, "vbus = %u\n", is_on); 1010 1011 if (is_on) { 1012 if (!sc->sc_flags.status_vbus) { 1013 sc->sc_flags.status_vbus = 1; 1014 1015 /* complete root HUB interrupt endpoint */ 1016 1017 dwc_otg_root_intr(sc); 1018 } 1019 } else { 1020 if (sc->sc_flags.status_vbus) { 1021 sc->sc_flags.status_vbus = 0; 1022 sc->sc_flags.status_bus_reset = 0; 1023 sc->sc_flags.status_suspend = 0; 1024 sc->sc_flags.change_suspend = 0; 1025 sc->sc_flags.change_connect = 1; 1026 1027 /* complete root HUB interrupt endpoint */ 1028 1029 dwc_otg_root_intr(sc); 1030 } 1031 } 1032 } 1033 1034 void 1035 dwc_otg_interrupt(struct dwc_otg_softc *sc) 1036 { 1037 uint32_t status; 1038 1039 USB_BUS_LOCK(&sc->sc_bus); 1040 1041 /* read and clear interrupt status */ 1042 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 1043 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 1044 1045 DPRINTFN(14, "GINTSTS=0x%08x\n", status); 1046 1047 if (status & GINTSTS_USBRST) { 1048 1049 /* set correct state */ 1050 sc->sc_flags.status_bus_reset = 0; 1051 sc->sc_flags.status_suspend = 0; 1052 sc->sc_flags.change_suspend = 0; 1053 sc->sc_flags.change_connect = 1; 1054 1055 /* complete root HUB interrupt endpoint */ 1056 dwc_otg_root_intr(sc); 1057 } 1058 1059 /* check for any bus state change interrupts */ 1060 if (status & GINTSTS_ENUMDONE) { 1061 1062 uint32_t temp; 1063 1064 DPRINTFN(5, "end of reset\n"); 1065 1066 /* set correct state */ 1067 sc->sc_flags.status_bus_reset = 1; 1068 sc->sc_flags.status_suspend = 0; 1069 sc->sc_flags.change_suspend = 0; 1070 sc->sc_flags.change_connect = 1; 1071 1072 /* reset FIFOs */ 1073 dwc_otg_init_fifo(sc); 1074 1075 /* reset function address */ 1076 dwc_otg_set_address(sc, 0); 1077 1078 /* reset active endpoints */ 1079 sc->sc_active_out_ep = 1; 1080 1081 /* figure out enumeration speed */ 1082 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 1083 if (DSTS_ENUMSPD_GET(temp) == 1084 DSTS_ENUMSPD_HI) 1085 sc->sc_flags.status_high_speed = 1; 1086 else 1087 sc->sc_flags.status_high_speed = 0; 1088 1089 /* disable resume interrupt and enable suspend interrupt */ 1090 1091 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 1092 sc->sc_irq_mask |= GINTSTS_USBSUSP; 1093 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1094 1095 /* complete root HUB interrupt endpoint */ 1096 dwc_otg_root_intr(sc); 1097 } 1098 /* 1099 * If resume and suspend is set at the same time we interpret 1100 * that like RESUME. Resume is set when there is at least 3 1101 * milliseconds of inactivity on the USB BUS. 1102 */ 1103 if (status & GINTSTS_WKUPINT) { 1104 1105 DPRINTFN(5, "resume interrupt\n"); 1106 1107 dwc_otg_resume_irq(sc); 1108 1109 } else if (status & GINTSTS_USBSUSP) { 1110 1111 DPRINTFN(5, "suspend interrupt\n"); 1112 1113 if (!sc->sc_flags.status_suspend) { 1114 /* update status bits */ 1115 sc->sc_flags.status_suspend = 1; 1116 sc->sc_flags.change_suspend = 1; 1117 1118 /* 1119 * Disable suspend interrupt and enable resume 1120 * interrupt: 1121 */ 1122 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 1123 sc->sc_irq_mask |= GINTSTS_WKUPINT; 1124 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1125 1126 /* complete root HUB interrupt endpoint */ 1127 dwc_otg_root_intr(sc); 1128 } 1129 } 1130 /* check VBUS */ 1131 if (status & (GINTSTS_USBSUSP | 1132 GINTSTS_USBRST | 1133 GINTSTS_SESSREQINT)) { 1134 uint32_t temp; 1135 1136 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 1137 1138 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 1139 1140 dwc_otg_vbus_interrupt(sc, 1141 (temp & GOTGCTL_BSESVLD) ? 1 : 0); 1142 } 1143 1144 /* clear all IN endpoint interrupts */ 1145 if (status & GINTSTS_IEPINT) { 1146 uint32_t temp; 1147 uint8_t x; 1148 1149 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 1150 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 1151 if (temp & DIEPMSK_XFERCOMPLMSK) { 1152 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 1153 DIEPMSK_XFERCOMPLMSK); 1154 } 1155 } 1156 } 1157 1158 #if 0 1159 /* check if we should poll the FIFOs */ 1160 if (status & (GINTSTS_RXFLVL | GINTSTS_IEPINT)) 1161 #endif 1162 /* poll FIFO(s) */ 1163 dwc_otg_interrupt_poll(sc); 1164 1165 USB_BUS_UNLOCK(&sc->sc_bus); 1166 } 1167 1168 static void 1169 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 1170 { 1171 struct dwc_otg_td *td; 1172 1173 /* get current Transfer Descriptor */ 1174 td = temp->td_next; 1175 temp->td = td; 1176 1177 /* prepare for next TD */ 1178 temp->td_next = td->obj_next; 1179 1180 /* fill out the Transfer Descriptor */ 1181 td->func = temp->func; 1182 td->pc = temp->pc; 1183 td->offset = temp->offset; 1184 td->remainder = temp->len; 1185 td->tx_bytes = 0; 1186 td->error = 0; 1187 td->npkt = 1; 1188 td->did_stall = temp->did_stall; 1189 td->short_pkt = temp->short_pkt; 1190 td->alt_next = temp->setup_alt_next; 1191 } 1192 1193 static void 1194 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 1195 { 1196 struct dwc_otg_std_temp temp; 1197 struct dwc_otg_td *td; 1198 uint32_t x; 1199 uint8_t need_sync; 1200 1201 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1202 xfer->address, UE_GET_ADDR(xfer->endpointno), 1203 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1204 1205 temp.max_frame_size = xfer->max_frame_size; 1206 1207 td = xfer->td_start[0]; 1208 xfer->td_transfer_first = td; 1209 xfer->td_transfer_cache = td; 1210 1211 /* setup temp */ 1212 1213 temp.pc = NULL; 1214 temp.td = NULL; 1215 temp.td_next = xfer->td_start[0]; 1216 temp.offset = 0; 1217 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1218 temp.did_stall = !xfer->flags_int.control_stall; 1219 1220 /* check if we should prepend a setup message */ 1221 1222 if (xfer->flags_int.control_xfr) { 1223 if (xfer->flags_int.control_hdr) { 1224 1225 temp.func = &dwc_otg_setup_rx; 1226 temp.len = xfer->frlengths[0]; 1227 temp.pc = xfer->frbuffers + 0; 1228 temp.short_pkt = temp.len ? 1 : 0; 1229 1230 /* check for last frame */ 1231 if (xfer->nframes == 1) { 1232 /* no STATUS stage yet, SETUP is last */ 1233 if (xfer->flags_int.control_act) 1234 temp.setup_alt_next = 0; 1235 } 1236 1237 dwc_otg_setup_standard_chain_sub(&temp); 1238 } 1239 x = 1; 1240 } else { 1241 x = 0; 1242 } 1243 1244 if (x != xfer->nframes) { 1245 if (xfer->endpointno & UE_DIR_IN) { 1246 temp.func = &dwc_otg_data_tx; 1247 need_sync = 1; 1248 } else { 1249 temp.func = &dwc_otg_data_rx; 1250 need_sync = 0; 1251 } 1252 1253 /* setup "pc" pointer */ 1254 temp.pc = xfer->frbuffers + x; 1255 } else { 1256 need_sync = 0; 1257 } 1258 while (x != xfer->nframes) { 1259 1260 /* DATA0 / DATA1 message */ 1261 1262 temp.len = xfer->frlengths[x]; 1263 1264 x++; 1265 1266 if (x == xfer->nframes) { 1267 if (xfer->flags_int.control_xfr) { 1268 if (xfer->flags_int.control_act) { 1269 temp.setup_alt_next = 0; 1270 } 1271 } else { 1272 temp.setup_alt_next = 0; 1273 } 1274 } 1275 if (temp.len == 0) { 1276 1277 /* make sure that we send an USB packet */ 1278 1279 temp.short_pkt = 0; 1280 1281 } else { 1282 1283 /* regular data transfer */ 1284 1285 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 1286 } 1287 1288 dwc_otg_setup_standard_chain_sub(&temp); 1289 1290 if (xfer->flags_int.isochronous_xfr) { 1291 temp.offset += temp.len; 1292 } else { 1293 /* get next Page Cache pointer */ 1294 temp.pc = xfer->frbuffers + x; 1295 } 1296 } 1297 1298 if (xfer->flags_int.control_xfr) { 1299 1300 /* always setup a valid "pc" pointer for status and sync */ 1301 temp.pc = xfer->frbuffers + 0; 1302 temp.len = 0; 1303 temp.short_pkt = 0; 1304 temp.setup_alt_next = 0; 1305 1306 /* check if we need to sync */ 1307 if (need_sync) { 1308 /* we need a SYNC point after TX */ 1309 temp.func = &dwc_otg_data_tx_sync; 1310 dwc_otg_setup_standard_chain_sub(&temp); 1311 } 1312 1313 /* check if we should append a status stage */ 1314 if (!xfer->flags_int.control_act) { 1315 1316 /* 1317 * Send a DATA1 message and invert the current 1318 * endpoint direction. 1319 */ 1320 if (xfer->endpointno & UE_DIR_IN) { 1321 temp.func = &dwc_otg_data_rx; 1322 need_sync = 0; 1323 } else { 1324 temp.func = &dwc_otg_data_tx; 1325 need_sync = 1; 1326 } 1327 1328 dwc_otg_setup_standard_chain_sub(&temp); 1329 if (need_sync) { 1330 /* we need a SYNC point after TX */ 1331 temp.func = &dwc_otg_data_tx_sync; 1332 dwc_otg_setup_standard_chain_sub(&temp); 1333 } 1334 } 1335 } else { 1336 /* check if we need to sync */ 1337 if (need_sync) { 1338 1339 temp.pc = xfer->frbuffers + 0; 1340 temp.len = 0; 1341 temp.short_pkt = 0; 1342 temp.setup_alt_next = 0; 1343 1344 /* we need a SYNC point after TX */ 1345 temp.func = &dwc_otg_data_tx_sync; 1346 dwc_otg_setup_standard_chain_sub(&temp); 1347 } 1348 } 1349 1350 /* must have at least one frame! */ 1351 td = temp.td; 1352 xfer->td_transfer_last = td; 1353 } 1354 1355 static void 1356 dwc_otg_timeout(void *arg) 1357 { 1358 struct usb_xfer *xfer = arg; 1359 1360 DPRINTF("xfer=%p\n", xfer); 1361 1362 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1363 1364 /* transfer is transferred */ 1365 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 1366 } 1367 1368 static void 1369 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 1370 { 1371 DPRINTFN(9, "\n"); 1372 1373 /* poll one time - will turn on interrupts */ 1374 if (dwc_otg_xfer_do_fifo(xfer)) { 1375 1376 /* put transfer on interrupt queue */ 1377 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1378 1379 /* start timeout, if any */ 1380 if (xfer->timeout != 0) { 1381 usbd_transfer_timeout_ms(xfer, 1382 &dwc_otg_timeout, xfer->timeout); 1383 } 1384 } 1385 } 1386 1387 static void 1388 dwc_otg_root_intr(struct dwc_otg_softc *sc) 1389 { 1390 DPRINTFN(9, "\n"); 1391 1392 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1393 1394 /* set port bit */ 1395 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1396 1397 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1398 sizeof(sc->sc_hub_idata)); 1399 } 1400 1401 static usb_error_t 1402 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 1403 { 1404 struct dwc_otg_td *td; 1405 uint32_t len; 1406 uint8_t error; 1407 1408 DPRINTFN(9, "\n"); 1409 1410 td = xfer->td_transfer_cache; 1411 1412 do { 1413 len = td->remainder; 1414 1415 if (xfer->aframes != xfer->nframes) { 1416 /* 1417 * Verify the length and subtract 1418 * the remainder from "frlengths[]": 1419 */ 1420 if (len > xfer->frlengths[xfer->aframes]) { 1421 td->error = 1; 1422 } else { 1423 xfer->frlengths[xfer->aframes] -= len; 1424 } 1425 } 1426 /* Check for transfer error */ 1427 if (td->error) { 1428 /* the transfer is finished */ 1429 error = 1; 1430 td = NULL; 1431 break; 1432 } 1433 /* Check for short transfer */ 1434 if (len > 0) { 1435 if (xfer->flags_int.short_frames_ok) { 1436 /* follow alt next */ 1437 if (td->alt_next) { 1438 td = td->obj_next; 1439 } else { 1440 td = NULL; 1441 } 1442 } else { 1443 /* the transfer is finished */ 1444 td = NULL; 1445 } 1446 error = 0; 1447 break; 1448 } 1449 td = td->obj_next; 1450 1451 /* this USB frame is complete */ 1452 error = 0; 1453 break; 1454 1455 } while (0); 1456 1457 /* update transfer cache */ 1458 1459 xfer->td_transfer_cache = td; 1460 1461 return (error ? 1462 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1463 } 1464 1465 static void 1466 dwc_otg_standard_done(struct usb_xfer *xfer) 1467 { 1468 usb_error_t err = 0; 1469 1470 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1471 xfer, xfer->endpoint); 1472 1473 /* reset scanner */ 1474 1475 xfer->td_transfer_cache = xfer->td_transfer_first; 1476 1477 if (xfer->flags_int.control_xfr) { 1478 1479 if (xfer->flags_int.control_hdr) { 1480 1481 err = dwc_otg_standard_done_sub(xfer); 1482 } 1483 xfer->aframes = 1; 1484 1485 if (xfer->td_transfer_cache == NULL) { 1486 goto done; 1487 } 1488 } 1489 while (xfer->aframes != xfer->nframes) { 1490 1491 err = dwc_otg_standard_done_sub(xfer); 1492 xfer->aframes++; 1493 1494 if (xfer->td_transfer_cache == NULL) { 1495 goto done; 1496 } 1497 } 1498 1499 if (xfer->flags_int.control_xfr && 1500 !xfer->flags_int.control_act) { 1501 1502 err = dwc_otg_standard_done_sub(xfer); 1503 } 1504 done: 1505 dwc_otg_device_done(xfer, err); 1506 } 1507 1508 /*------------------------------------------------------------------------* 1509 * dwc_otg_device_done 1510 * 1511 * NOTE: this function can be called more than one time on the 1512 * same USB transfer! 1513 *------------------------------------------------------------------------*/ 1514 static void 1515 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 1516 { 1517 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1518 xfer, xfer->endpoint, error); 1519 1520 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1521 DPRINTFN(15, "disabled interrupts!\n"); 1522 } 1523 /* dequeue transfer and start next transfer */ 1524 usbd_transfer_done(xfer, error); 1525 } 1526 1527 static void 1528 dwc_otg_xfer_stall(struct usb_xfer *xfer) 1529 { 1530 dwc_otg_device_done(xfer, USB_ERR_STALLED); 1531 } 1532 1533 static void 1534 dwc_otg_set_stall(struct usb_device *udev, 1535 struct usb_endpoint *ep, uint8_t *did_stall) 1536 { 1537 struct dwc_otg_softc *sc; 1538 uint32_t temp; 1539 uint32_t reg; 1540 uint8_t ep_no; 1541 1542 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1543 1544 sc = DWC_OTG_BUS2SC(udev->bus); 1545 1546 /* get endpoint address */ 1547 ep_no = ep->edesc->bEndpointAddress; 1548 1549 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 1550 1551 if (ep_no & UE_DIR_IN) { 1552 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 1553 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 1554 } else { 1555 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 1556 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 1557 } 1558 1559 /* disable and stall endpoint */ 1560 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 1561 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 1562 1563 /* clear active OUT ep */ 1564 if (!(ep_no & UE_DIR_IN)) { 1565 1566 sc->sc_active_out_ep &= ~(1U << (ep_no & UE_ADDR)); 1567 1568 if (sc->sc_last_rx_status != 0 && 1569 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 1570 sc->sc_last_rx_status)) { 1571 /* dump data */ 1572 dwc_otg_common_rx_ack(sc); 1573 /* poll interrupt */ 1574 dwc_otg_interrupt_poll(sc); 1575 } 1576 } 1577 } 1578 1579 static void 1580 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 1581 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1582 { 1583 uint32_t reg; 1584 uint32_t temp; 1585 1586 if (ep_type == UE_CONTROL) { 1587 /* clearing stall is not needed */ 1588 return; 1589 } 1590 1591 if (ep_dir) { 1592 reg = DOTG_DIEPCTL(ep_no); 1593 } else { 1594 reg = DOTG_DOEPCTL(ep_no); 1595 sc->sc_active_out_ep |= (1U << ep_no); 1596 } 1597 1598 /* round up and mask away the multiplier count */ 1599 mps = (mps + 3) & 0x7FC; 1600 1601 if (ep_type == UE_BULK) { 1602 temp = DIEPCTL_EPTYPE_SET( 1603 DIEPCTL_EPTYPE_BULK) | 1604 DIEPCTL_USBACTEP; 1605 } else if (ep_type == UE_INTERRUPT) { 1606 temp = DIEPCTL_EPTYPE_SET( 1607 DIEPCTL_EPTYPE_INTERRUPT) | 1608 DIEPCTL_USBACTEP; 1609 } else { 1610 temp = DIEPCTL_EPTYPE_SET( 1611 DIEPCTL_EPTYPE_ISOC) | 1612 DIEPCTL_USBACTEP; 1613 } 1614 1615 temp |= DIEPCTL_MPS_SET(mps); 1616 temp |= DIEPCTL_TXFNUM_SET(ep_no); 1617 1618 if (ep_dir) 1619 sc->sc_in_ctl[ep_no] = temp; 1620 else 1621 sc->sc_out_ctl[ep_no] = temp; 1622 1623 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 1624 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 1625 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 1626 1627 /* we only reset the transmit FIFO */ 1628 if (ep_dir) { 1629 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1630 GRSTCTL_TXFIFO(ep_no) | 1631 GRSTCTL_TXFFLSH); 1632 1633 DWC_OTG_WRITE_4(sc, 1634 DOTG_DIEPTSIZ(ep_no), 0); 1635 } 1636 1637 /* poll interrupt */ 1638 dwc_otg_interrupt_poll(sc); 1639 } 1640 1641 static void 1642 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1643 { 1644 struct dwc_otg_softc *sc; 1645 struct usb_endpoint_descriptor *ed; 1646 1647 DPRINTFN(5, "endpoint=%p\n", ep); 1648 1649 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1650 1651 /* check mode */ 1652 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1653 /* not supported */ 1654 return; 1655 } 1656 /* get softc */ 1657 sc = DWC_OTG_BUS2SC(udev->bus); 1658 1659 /* get endpoint descriptor */ 1660 ed = ep->edesc; 1661 1662 /* reset endpoint */ 1663 dwc_otg_clear_stall_sub(sc, 1664 UGETW(ed->wMaxPacketSize), 1665 (ed->bEndpointAddress & UE_ADDR), 1666 (ed->bmAttributes & UE_XFERTYPE), 1667 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1668 } 1669 1670 static void 1671 dwc_otg_device_state_change(struct usb_device *udev) 1672 { 1673 struct dwc_otg_softc *sc; 1674 uint8_t x; 1675 1676 /* get softc */ 1677 sc = DWC_OTG_BUS2SC(udev->bus); 1678 1679 /* deactivate all other endpoint but the control endpoint */ 1680 if (udev->state == USB_STATE_CONFIGURED || 1681 udev->state == USB_STATE_ADDRESSED) { 1682 1683 USB_BUS_LOCK(&sc->sc_bus); 1684 1685 for (x = 1; x != sc->sc_dev_ep_max; x++) { 1686 1687 if (x < sc->sc_dev_in_ep_max) { 1688 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 1689 DIEPCTL_EPDIS); 1690 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 1691 } 1692 1693 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 1694 DOEPCTL_EPDIS); 1695 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 1696 } 1697 USB_BUS_UNLOCK(&sc->sc_bus); 1698 } 1699 } 1700 1701 int 1702 dwc_otg_init(struct dwc_otg_softc *sc) 1703 { 1704 uint32_t temp; 1705 1706 DPRINTF("start\n"); 1707 1708 /* set up the bus structure */ 1709 sc->sc_bus.usbrev = USB_REV_2_0; 1710 sc->sc_bus.methods = &dwc_otg_bus_methods; 1711 1712 /* reset active endpoints */ 1713 sc->sc_active_out_ep = 1; 1714 1715 USB_BUS_LOCK(&sc->sc_bus); 1716 1717 /* turn on clocks */ 1718 dwc_otg_clocks_on(sc); 1719 1720 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 1721 DPRINTF("Version = 0x%08x\n", temp); 1722 1723 /* disconnect */ 1724 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 1725 DCTL_SFTDISCON); 1726 1727 /* wait for host to detect disconnect */ 1728 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 1729 1730 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1731 GRSTCTL_CSFTRST); 1732 1733 /* wait a little bit for block to reset */ 1734 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 1735 1736 /* select HSIC or non-HSIC mode */ 1737 if (DWC_OTG_USE_HSIC) { 1738 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 1739 GUSBCFG_PHYIF | 1740 GUSBCFG_TRD_TIM_SET(5)); 1741 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 1742 0x000000EC); 1743 1744 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 1745 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 1746 temp & ~GLPMCFG_HSIC_CONN); 1747 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 1748 temp | GLPMCFG_HSIC_CONN); 1749 } else { 1750 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 1751 GUSBCFG_ULPI_UTMI_SEL | 1752 GUSBCFG_TRD_TIM_SET(5)); 1753 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 1754 1755 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 1756 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 1757 temp & ~GLPMCFG_HSIC_CONN); 1758 } 1759 1760 /* clear global nak */ 1761 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 1762 DCTL_CGOUTNAK | 1763 DCTL_CGNPINNAK); 1764 1765 /* enable USB port */ 1766 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 1767 1768 /* pull up D+ */ 1769 dwc_otg_pull_up(sc); 1770 1771 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 1772 1773 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 1774 1775 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 1776 1777 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 1778 1779 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 1780 1781 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 1782 1783 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d\n", 1784 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max); 1785 1786 /* setup FIFO */ 1787 if (dwc_otg_init_fifo(sc)) 1788 return (EINVAL); 1789 1790 /* enable interrupts */ 1791 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 1792 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1793 1794 /* enable all endpoint interrupts */ 1795 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 1796 if (temp & GHWCFG2_MPI) { 1797 uint8_t x; 1798 1799 DPRINTF("Multi Process Interrupts\n"); 1800 1801 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 1802 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 1803 DIEPMSK_XFERCOMPLMSK); 1804 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 1805 } 1806 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 1807 } else { 1808 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 1809 DIEPMSK_XFERCOMPLMSK); 1810 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 1811 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 1812 } 1813 1814 /* enable global IRQ */ 1815 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 1816 GAHBCFG_GLBLINTRMSK); 1817 1818 /* turn off clocks */ 1819 dwc_otg_clocks_off(sc); 1820 1821 /* read initial VBUS state */ 1822 1823 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 1824 1825 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 1826 1827 dwc_otg_vbus_interrupt(sc, 1828 (temp & GOTGCTL_BSESVLD) ? 1 : 0); 1829 1830 USB_BUS_UNLOCK(&sc->sc_bus); 1831 1832 /* catch any lost interrupts */ 1833 1834 dwc_otg_do_poll(&sc->sc_bus); 1835 1836 return (0); /* success */ 1837 } 1838 1839 void 1840 dwc_otg_uninit(struct dwc_otg_softc *sc) 1841 { 1842 USB_BUS_LOCK(&sc->sc_bus); 1843 1844 /* set disconnect */ 1845 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 1846 DCTL_SFTDISCON); 1847 1848 /* turn off global IRQ */ 1849 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 1850 1851 sc->sc_flags.port_powered = 0; 1852 sc->sc_flags.status_vbus = 0; 1853 sc->sc_flags.status_bus_reset = 0; 1854 sc->sc_flags.status_suspend = 0; 1855 sc->sc_flags.change_suspend = 0; 1856 sc->sc_flags.change_connect = 1; 1857 1858 dwc_otg_pull_down(sc); 1859 dwc_otg_clocks_off(sc); 1860 1861 USB_BUS_UNLOCK(&sc->sc_bus); 1862 } 1863 1864 static void 1865 dwc_otg_suspend(struct dwc_otg_softc *sc) 1866 { 1867 return; 1868 } 1869 1870 static void 1871 dwc_otg_resume(struct dwc_otg_softc *sc) 1872 { 1873 return; 1874 } 1875 1876 static void 1877 dwc_otg_do_poll(struct usb_bus *bus) 1878 { 1879 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 1880 1881 USB_BUS_LOCK(&sc->sc_bus); 1882 dwc_otg_interrupt_poll(sc); 1883 USB_BUS_UNLOCK(&sc->sc_bus); 1884 } 1885 1886 /*------------------------------------------------------------------------* 1887 * at91dci bulk support 1888 * at91dci control support 1889 * at91dci interrupt support 1890 *------------------------------------------------------------------------*/ 1891 static void 1892 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 1893 { 1894 return; 1895 } 1896 1897 static void 1898 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 1899 { 1900 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1901 } 1902 1903 static void 1904 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 1905 { 1906 return; 1907 } 1908 1909 static void 1910 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 1911 { 1912 /* setup TDs */ 1913 dwc_otg_setup_standard_chain(xfer); 1914 dwc_otg_start_standard_chain(xfer); 1915 } 1916 1917 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 1918 { 1919 .open = dwc_otg_device_non_isoc_open, 1920 .close = dwc_otg_device_non_isoc_close, 1921 .enter = dwc_otg_device_non_isoc_enter, 1922 .start = dwc_otg_device_non_isoc_start, 1923 }; 1924 1925 /*------------------------------------------------------------------------* 1926 * at91dci full speed isochronous support 1927 *------------------------------------------------------------------------*/ 1928 static void 1929 dwc_otg_device_isoc_fs_open(struct usb_xfer *xfer) 1930 { 1931 return; 1932 } 1933 1934 static void 1935 dwc_otg_device_isoc_fs_close(struct usb_xfer *xfer) 1936 { 1937 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1938 } 1939 1940 static void 1941 dwc_otg_device_isoc_fs_enter(struct usb_xfer *xfer) 1942 { 1943 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 1944 uint32_t temp; 1945 uint32_t nframes; 1946 1947 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1948 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1949 1950 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 1951 1952 /* get the current frame index */ 1953 1954 nframes = DSTS_SOFFN_GET(temp); 1955 1956 if (sc->sc_flags.status_high_speed) 1957 nframes /= 8; 1958 1959 nframes &= DWC_OTG_FRAME_MASK; 1960 1961 /* 1962 * check if the frame index is within the window where the frames 1963 * will be inserted 1964 */ 1965 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 1966 1967 if ((xfer->endpoint->is_synced == 0) || 1968 (temp < xfer->nframes)) { 1969 /* 1970 * If there is data underflow or the pipe queue is 1971 * empty we schedule the transfer a few frames ahead 1972 * of the current frame position. Else two isochronous 1973 * transfers might overlap. 1974 */ 1975 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 1976 xfer->endpoint->is_synced = 1; 1977 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1978 } 1979 /* 1980 * compute how many milliseconds the insertion is ahead of the 1981 * current frame position: 1982 */ 1983 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 1984 1985 /* 1986 * pre-compute when the isochronous transfer will be finished: 1987 */ 1988 xfer->isoc_time_complete = 1989 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1990 xfer->nframes; 1991 1992 /* compute frame number for next insertion */ 1993 xfer->endpoint->isoc_next += xfer->nframes; 1994 1995 /* setup TDs */ 1996 dwc_otg_setup_standard_chain(xfer); 1997 } 1998 1999 static void 2000 dwc_otg_device_isoc_fs_start(struct usb_xfer *xfer) 2001 { 2002 /* start TD chain */ 2003 dwc_otg_start_standard_chain(xfer); 2004 } 2005 2006 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods = 2007 { 2008 .open = dwc_otg_device_isoc_fs_open, 2009 .close = dwc_otg_device_isoc_fs_close, 2010 .enter = dwc_otg_device_isoc_fs_enter, 2011 .start = dwc_otg_device_isoc_fs_start, 2012 }; 2013 2014 /*------------------------------------------------------------------------* 2015 * at91dci root control support 2016 *------------------------------------------------------------------------* 2017 * Simulate a hardware HUB by handling all the necessary requests. 2018 *------------------------------------------------------------------------*/ 2019 2020 static const struct usb_device_descriptor dwc_otg_devd = { 2021 .bLength = sizeof(struct usb_device_descriptor), 2022 .bDescriptorType = UDESC_DEVICE, 2023 .bcdUSB = {0x00, 0x02}, 2024 .bDeviceClass = UDCLASS_HUB, 2025 .bDeviceSubClass = UDSUBCLASS_HUB, 2026 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2027 .bMaxPacketSize = 64, 2028 .bcdDevice = {0x00, 0x01}, 2029 .iManufacturer = 1, 2030 .iProduct = 2, 2031 .bNumConfigurations = 1, 2032 }; 2033 2034 static const struct dwc_otg_config_desc dwc_otg_confd = { 2035 .confd = { 2036 .bLength = sizeof(struct usb_config_descriptor), 2037 .bDescriptorType = UDESC_CONFIG, 2038 .wTotalLength[0] = sizeof(dwc_otg_confd), 2039 .bNumInterface = 1, 2040 .bConfigurationValue = 1, 2041 .iConfiguration = 0, 2042 .bmAttributes = UC_SELF_POWERED, 2043 .bMaxPower = 0, 2044 }, 2045 .ifcd = { 2046 .bLength = sizeof(struct usb_interface_descriptor), 2047 .bDescriptorType = UDESC_INTERFACE, 2048 .bNumEndpoints = 1, 2049 .bInterfaceClass = UICLASS_HUB, 2050 .bInterfaceSubClass = UISUBCLASS_HUB, 2051 .bInterfaceProtocol = 0, 2052 }, 2053 .endpd = { 2054 .bLength = sizeof(struct usb_endpoint_descriptor), 2055 .bDescriptorType = UDESC_ENDPOINT, 2056 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 2057 .bmAttributes = UE_INTERRUPT, 2058 .wMaxPacketSize[0] = 8, 2059 .bInterval = 255, 2060 }, 2061 }; 2062 2063 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2064 2065 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 2066 .bDescLength = sizeof(dwc_otg_hubd), 2067 .bDescriptorType = UDESC_HUB, 2068 .bNbrPorts = 1, 2069 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 2070 .bPwrOn2PwrGood = 50, 2071 .bHubContrCurrent = 0, 2072 .DeviceRemovable = {0}, /* port is removable */ 2073 }; 2074 2075 #define STRING_LANG \ 2076 0x09, 0x04, /* American English */ 2077 2078 #define STRING_VENDOR \ 2079 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 2080 2081 #define STRING_PRODUCT \ 2082 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 2083 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2084 'U', 0, 'B', 0, 2085 2086 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 2087 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 2088 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 2089 2090 static usb_error_t 2091 dwc_otg_roothub_exec(struct usb_device *udev, 2092 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2093 { 2094 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2095 const void *ptr; 2096 uint16_t len; 2097 uint16_t value; 2098 uint16_t index; 2099 usb_error_t err; 2100 2101 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2102 2103 /* buffer reset */ 2104 ptr = (const void *)&sc->sc_hub_temp; 2105 len = 0; 2106 err = 0; 2107 2108 value = UGETW(req->wValue); 2109 index = UGETW(req->wIndex); 2110 2111 /* demultiplex the control request */ 2112 2113 switch (req->bmRequestType) { 2114 case UT_READ_DEVICE: 2115 switch (req->bRequest) { 2116 case UR_GET_DESCRIPTOR: 2117 goto tr_handle_get_descriptor; 2118 case UR_GET_CONFIG: 2119 goto tr_handle_get_config; 2120 case UR_GET_STATUS: 2121 goto tr_handle_get_status; 2122 default: 2123 goto tr_stalled; 2124 } 2125 break; 2126 2127 case UT_WRITE_DEVICE: 2128 switch (req->bRequest) { 2129 case UR_SET_ADDRESS: 2130 goto tr_handle_set_address; 2131 case UR_SET_CONFIG: 2132 goto tr_handle_set_config; 2133 case UR_CLEAR_FEATURE: 2134 goto tr_valid; /* nop */ 2135 case UR_SET_DESCRIPTOR: 2136 goto tr_valid; /* nop */ 2137 case UR_SET_FEATURE: 2138 default: 2139 goto tr_stalled; 2140 } 2141 break; 2142 2143 case UT_WRITE_ENDPOINT: 2144 switch (req->bRequest) { 2145 case UR_CLEAR_FEATURE: 2146 switch (UGETW(req->wValue)) { 2147 case UF_ENDPOINT_HALT: 2148 goto tr_handle_clear_halt; 2149 case UF_DEVICE_REMOTE_WAKEUP: 2150 goto tr_handle_clear_wakeup; 2151 default: 2152 goto tr_stalled; 2153 } 2154 break; 2155 case UR_SET_FEATURE: 2156 switch (UGETW(req->wValue)) { 2157 case UF_ENDPOINT_HALT: 2158 goto tr_handle_set_halt; 2159 case UF_DEVICE_REMOTE_WAKEUP: 2160 goto tr_handle_set_wakeup; 2161 default: 2162 goto tr_stalled; 2163 } 2164 break; 2165 case UR_SYNCH_FRAME: 2166 goto tr_valid; /* nop */ 2167 default: 2168 goto tr_stalled; 2169 } 2170 break; 2171 2172 case UT_READ_ENDPOINT: 2173 switch (req->bRequest) { 2174 case UR_GET_STATUS: 2175 goto tr_handle_get_ep_status; 2176 default: 2177 goto tr_stalled; 2178 } 2179 break; 2180 2181 case UT_WRITE_INTERFACE: 2182 switch (req->bRequest) { 2183 case UR_SET_INTERFACE: 2184 goto tr_handle_set_interface; 2185 case UR_CLEAR_FEATURE: 2186 goto tr_valid; /* nop */ 2187 case UR_SET_FEATURE: 2188 default: 2189 goto tr_stalled; 2190 } 2191 break; 2192 2193 case UT_READ_INTERFACE: 2194 switch (req->bRequest) { 2195 case UR_GET_INTERFACE: 2196 goto tr_handle_get_interface; 2197 case UR_GET_STATUS: 2198 goto tr_handle_get_iface_status; 2199 default: 2200 goto tr_stalled; 2201 } 2202 break; 2203 2204 case UT_WRITE_CLASS_INTERFACE: 2205 case UT_WRITE_VENDOR_INTERFACE: 2206 /* XXX forward */ 2207 break; 2208 2209 case UT_READ_CLASS_INTERFACE: 2210 case UT_READ_VENDOR_INTERFACE: 2211 /* XXX forward */ 2212 break; 2213 2214 case UT_WRITE_CLASS_DEVICE: 2215 switch (req->bRequest) { 2216 case UR_CLEAR_FEATURE: 2217 goto tr_valid; 2218 case UR_SET_DESCRIPTOR: 2219 case UR_SET_FEATURE: 2220 break; 2221 default: 2222 goto tr_stalled; 2223 } 2224 break; 2225 2226 case UT_WRITE_CLASS_OTHER: 2227 switch (req->bRequest) { 2228 case UR_CLEAR_FEATURE: 2229 goto tr_handle_clear_port_feature; 2230 case UR_SET_FEATURE: 2231 goto tr_handle_set_port_feature; 2232 case UR_CLEAR_TT_BUFFER: 2233 case UR_RESET_TT: 2234 case UR_STOP_TT: 2235 goto tr_valid; 2236 2237 default: 2238 goto tr_stalled; 2239 } 2240 break; 2241 2242 case UT_READ_CLASS_OTHER: 2243 switch (req->bRequest) { 2244 case UR_GET_TT_STATE: 2245 goto tr_handle_get_tt_state; 2246 case UR_GET_STATUS: 2247 goto tr_handle_get_port_status; 2248 default: 2249 goto tr_stalled; 2250 } 2251 break; 2252 2253 case UT_READ_CLASS_DEVICE: 2254 switch (req->bRequest) { 2255 case UR_GET_DESCRIPTOR: 2256 goto tr_handle_get_class_descriptor; 2257 case UR_GET_STATUS: 2258 goto tr_handle_get_class_status; 2259 2260 default: 2261 goto tr_stalled; 2262 } 2263 break; 2264 default: 2265 goto tr_stalled; 2266 } 2267 goto tr_valid; 2268 2269 tr_handle_get_descriptor: 2270 switch (value >> 8) { 2271 case UDESC_DEVICE: 2272 if (value & 0xff) { 2273 goto tr_stalled; 2274 } 2275 len = sizeof(dwc_otg_devd); 2276 ptr = (const void *)&dwc_otg_devd; 2277 goto tr_valid; 2278 case UDESC_CONFIG: 2279 if (value & 0xff) { 2280 goto tr_stalled; 2281 } 2282 len = sizeof(dwc_otg_confd); 2283 ptr = (const void *)&dwc_otg_confd; 2284 goto tr_valid; 2285 case UDESC_STRING: 2286 switch (value & 0xff) { 2287 case 0: /* Language table */ 2288 len = sizeof(dwc_otg_langtab); 2289 ptr = (const void *)&dwc_otg_langtab; 2290 goto tr_valid; 2291 2292 case 1: /* Vendor */ 2293 len = sizeof(dwc_otg_vendor); 2294 ptr = (const void *)&dwc_otg_vendor; 2295 goto tr_valid; 2296 2297 case 2: /* Product */ 2298 len = sizeof(dwc_otg_product); 2299 ptr = (const void *)&dwc_otg_product; 2300 goto tr_valid; 2301 default: 2302 break; 2303 } 2304 break; 2305 default: 2306 goto tr_stalled; 2307 } 2308 goto tr_stalled; 2309 2310 tr_handle_get_config: 2311 len = 1; 2312 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2313 goto tr_valid; 2314 2315 tr_handle_get_status: 2316 len = 2; 2317 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2318 goto tr_valid; 2319 2320 tr_handle_set_address: 2321 if (value & 0xFF00) { 2322 goto tr_stalled; 2323 } 2324 sc->sc_rt_addr = value; 2325 goto tr_valid; 2326 2327 tr_handle_set_config: 2328 if (value >= 2) { 2329 goto tr_stalled; 2330 } 2331 sc->sc_conf = value; 2332 goto tr_valid; 2333 2334 tr_handle_get_interface: 2335 len = 1; 2336 sc->sc_hub_temp.wValue[0] = 0; 2337 goto tr_valid; 2338 2339 tr_handle_get_tt_state: 2340 tr_handle_get_class_status: 2341 tr_handle_get_iface_status: 2342 tr_handle_get_ep_status: 2343 len = 2; 2344 USETW(sc->sc_hub_temp.wValue, 0); 2345 goto tr_valid; 2346 2347 tr_handle_set_halt: 2348 tr_handle_set_interface: 2349 tr_handle_set_wakeup: 2350 tr_handle_clear_wakeup: 2351 tr_handle_clear_halt: 2352 goto tr_valid; 2353 2354 tr_handle_clear_port_feature: 2355 if (index != 1) { 2356 goto tr_stalled; 2357 } 2358 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2359 2360 switch (value) { 2361 case UHF_PORT_SUSPEND: 2362 dwc_otg_wakeup_peer(sc); 2363 break; 2364 2365 case UHF_PORT_ENABLE: 2366 sc->sc_flags.port_enabled = 0; 2367 break; 2368 2369 case UHF_PORT_TEST: 2370 case UHF_PORT_INDICATOR: 2371 case UHF_C_PORT_ENABLE: 2372 case UHF_C_PORT_OVER_CURRENT: 2373 case UHF_C_PORT_RESET: 2374 /* nops */ 2375 break; 2376 case UHF_PORT_POWER: 2377 sc->sc_flags.port_powered = 0; 2378 dwc_otg_pull_down(sc); 2379 dwc_otg_clocks_off(sc); 2380 break; 2381 case UHF_C_PORT_CONNECTION: 2382 /* clear connect change flag */ 2383 sc->sc_flags.change_connect = 0; 2384 2385 if (!sc->sc_flags.status_bus_reset) { 2386 /* we are not connected */ 2387 break; 2388 } 2389 break; 2390 case UHF_C_PORT_SUSPEND: 2391 sc->sc_flags.change_suspend = 0; 2392 break; 2393 default: 2394 err = USB_ERR_IOERROR; 2395 goto done; 2396 } 2397 goto tr_valid; 2398 2399 tr_handle_set_port_feature: 2400 if (index != 1) { 2401 goto tr_stalled; 2402 } 2403 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2404 2405 switch (value) { 2406 case UHF_PORT_ENABLE: 2407 sc->sc_flags.port_enabled = 1; 2408 break; 2409 case UHF_PORT_SUSPEND: 2410 case UHF_PORT_RESET: 2411 case UHF_PORT_TEST: 2412 case UHF_PORT_INDICATOR: 2413 /* nops */ 2414 break; 2415 case UHF_PORT_POWER: 2416 sc->sc_flags.port_powered = 1; 2417 break; 2418 default: 2419 err = USB_ERR_IOERROR; 2420 goto done; 2421 } 2422 goto tr_valid; 2423 2424 tr_handle_get_port_status: 2425 2426 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2427 2428 if (index != 1) { 2429 goto tr_stalled; 2430 } 2431 if (sc->sc_flags.status_vbus) { 2432 dwc_otg_clocks_on(sc); 2433 } else { 2434 dwc_otg_clocks_off(sc); 2435 } 2436 2437 /* Select Device Side Mode */ 2438 2439 value = UPS_PORT_MODE_DEVICE; 2440 2441 if (sc->sc_flags.status_high_speed) { 2442 value |= UPS_HIGH_SPEED; 2443 } 2444 if (sc->sc_flags.port_powered) { 2445 value |= UPS_PORT_POWER; 2446 } 2447 if (sc->sc_flags.port_enabled) { 2448 value |= UPS_PORT_ENABLED; 2449 } 2450 if (sc->sc_flags.status_vbus && 2451 sc->sc_flags.status_bus_reset) { 2452 value |= UPS_CURRENT_CONNECT_STATUS; 2453 } 2454 if (sc->sc_flags.status_suspend) { 2455 value |= UPS_SUSPEND; 2456 } 2457 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2458 2459 value = 0; 2460 2461 if (sc->sc_flags.change_connect) { 2462 value |= UPS_C_CONNECT_STATUS; 2463 } 2464 if (sc->sc_flags.change_suspend) { 2465 value |= UPS_C_SUSPEND; 2466 } 2467 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2468 len = sizeof(sc->sc_hub_temp.ps); 2469 goto tr_valid; 2470 2471 tr_handle_get_class_descriptor: 2472 if (value & 0xFF) { 2473 goto tr_stalled; 2474 } 2475 ptr = (const void *)&dwc_otg_hubd; 2476 len = sizeof(dwc_otg_hubd); 2477 goto tr_valid; 2478 2479 tr_stalled: 2480 err = USB_ERR_STALLED; 2481 tr_valid: 2482 done: 2483 *plength = len; 2484 *pptr = ptr; 2485 return (err); 2486 } 2487 2488 static void 2489 dwc_otg_xfer_setup(struct usb_setup_params *parm) 2490 { 2491 const struct usb_hw_ep_profile *pf; 2492 struct usb_xfer *xfer; 2493 void *last_obj; 2494 uint32_t ntd; 2495 uint32_t n; 2496 uint8_t ep_no; 2497 2498 xfer = parm->curr_xfer; 2499 2500 /* 2501 * NOTE: This driver does not use any of the parameters that 2502 * are computed from the following values. Just set some 2503 * reasonable dummies: 2504 */ 2505 parm->hc_max_packet_size = 0x500; 2506 parm->hc_max_packet_count = 1; 2507 parm->hc_max_frame_size = 0x500; 2508 2509 usbd_transfer_setup_sub(parm); 2510 2511 /* 2512 * compute maximum number of TDs 2513 */ 2514 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2515 2516 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2517 + 1 /* SYNC 2 */ ; 2518 } else { 2519 2520 ntd = xfer->nframes + 1 /* SYNC */ ; 2521 } 2522 2523 /* 2524 * check if "usbd_transfer_setup_sub" set an error 2525 */ 2526 if (parm->err) 2527 return; 2528 2529 /* 2530 * allocate transfer descriptors 2531 */ 2532 last_obj = NULL; 2533 2534 /* 2535 * get profile stuff 2536 */ 2537 ep_no = xfer->endpointno & UE_ADDR; 2538 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2539 2540 if (pf == NULL) { 2541 /* should not happen */ 2542 parm->err = USB_ERR_INVAL; 2543 return; 2544 } 2545 2546 /* align data */ 2547 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2548 2549 for (n = 0; n != ntd; n++) { 2550 2551 struct dwc_otg_td *td; 2552 2553 if (parm->buf) { 2554 2555 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2556 2557 /* init TD */ 2558 td->max_packet_size = xfer->max_packet_size; 2559 td->ep_no = ep_no; 2560 td->obj_next = last_obj; 2561 2562 last_obj = td; 2563 } 2564 parm->size[0] += sizeof(*td); 2565 } 2566 2567 xfer->td_start[0] = last_obj; 2568 } 2569 2570 static void 2571 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 2572 { 2573 return; 2574 } 2575 2576 static void 2577 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2578 struct usb_endpoint *ep) 2579 { 2580 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2581 2582 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2583 ep, udev->address, 2584 edesc->bEndpointAddress, udev->flags.usb_mode, 2585 sc->sc_rt_addr, udev->device_index); 2586 2587 if (udev->device_index != sc->sc_rt_addr) { 2588 2589 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2590 /* not supported */ 2591 return; 2592 } 2593 if (udev->speed != USB_SPEED_FULL && 2594 udev->speed != USB_SPEED_HIGH) { 2595 /* not supported */ 2596 return; 2597 } 2598 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2599 ep->methods = &dwc_otg_device_isoc_fs_methods; 2600 else 2601 ep->methods = &dwc_otg_device_non_isoc_methods; 2602 } 2603 } 2604 2605 static void 2606 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2607 { 2608 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 2609 2610 switch (state) { 2611 case USB_HW_POWER_SUSPEND: 2612 dwc_otg_suspend(sc); 2613 break; 2614 case USB_HW_POWER_SHUTDOWN: 2615 dwc_otg_uninit(sc); 2616 break; 2617 case USB_HW_POWER_RESUME: 2618 dwc_otg_resume(sc); 2619 break; 2620 default: 2621 break; 2622 } 2623 } 2624 2625 struct usb_bus_methods dwc_otg_bus_methods = 2626 { 2627 .endpoint_init = &dwc_otg_ep_init, 2628 .xfer_setup = &dwc_otg_xfer_setup, 2629 .xfer_unsetup = &dwc_otg_xfer_unsetup, 2630 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 2631 .xfer_stall = &dwc_otg_xfer_stall, 2632 .set_stall = &dwc_otg_set_stall, 2633 .clear_stall = &dwc_otg_clear_stall, 2634 .roothub_exec = &dwc_otg_roothub_exec, 2635 .xfer_poll = &dwc_otg_do_poll, 2636 .device_state_change = &dwc_otg_device_state_change, 2637 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 2638 }; 2639