1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 6 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 7 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * This file contains the driver for the DesignWare series USB 2.0 OTG 33 * Controller. 34 */ 35 36 /* 37 * LIMITATION: Drivers must be bound to all OUT endpoints in the 38 * active configuration for this driver to work properly. Blocking any 39 * OUT endpoint will block all OUT endpoints including the control 40 * endpoint. Usually this is not a problem. 41 */ 42 43 /* 44 * NOTE: Writing to non-existing registers appears to cause an 45 * internal reset. 46 */ 47 48 #ifdef USB_GLOBAL_INCLUDE_FILE 49 #include USB_GLOBAL_INCLUDE_FILE 50 #else 51 #include <sys/stdint.h> 52 #include <sys/stddef.h> 53 #include <sys/param.h> 54 #include <sys/queue.h> 55 #include <sys/types.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/bus.h> 59 #include <sys/module.h> 60 #include <sys/lock.h> 61 #include <sys/mutex.h> 62 #include <sys/condvar.h> 63 #include <sys/sysctl.h> 64 #include <sys/sx.h> 65 #include <sys/unistd.h> 66 #include <sys/callout.h> 67 #include <sys/malloc.h> 68 #include <sys/priv.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 73 #define USB_DEBUG_VAR dwc_otg_debug 74 75 #include <dev/usb/usb_core.h> 76 #include <dev/usb/usb_debug.h> 77 #include <dev/usb/usb_busdma.h> 78 #include <dev/usb/usb_process.h> 79 #include <dev/usb/usb_transfer.h> 80 #include <dev/usb/usb_device.h> 81 #include <dev/usb/usb_hub.h> 82 #include <dev/usb/usb_util.h> 83 84 #include <dev/usb/usb_controller.h> 85 #include <dev/usb/usb_bus.h> 86 #endif /* USB_GLOBAL_INCLUDE_FILE */ 87 88 #include <dev/usb/controller/dwc_otg.h> 89 #include <dev/usb/controller/dwc_otgreg.h> 90 91 #define DWC_OTG_BUS2SC(bus) \ 92 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 93 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 94 95 #define DWC_OTG_PC2UDEV(pc) \ 96 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 97 98 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 99 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 100 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 101 GINTSTS_SESSREQINT) 102 103 #ifndef DWC_OTG_PHY_DEFAULT 104 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 105 #endif 106 107 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 108 109 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 110 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 111 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+"); 112 113 #ifdef USB_DEBUG 114 static int dwc_otg_debug = 0; 115 116 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 117 &dwc_otg_debug, 0, "DWC OTG debug level"); 118 #endif 119 120 #define DWC_OTG_INTR_ENDPT 1 121 122 /* prototypes */ 123 124 static const struct usb_bus_methods dwc_otg_bus_methods; 125 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 126 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 127 128 static dwc_otg_cmd_t dwc_otg_setup_rx; 129 static dwc_otg_cmd_t dwc_otg_data_rx; 130 static dwc_otg_cmd_t dwc_otg_data_tx; 131 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 132 133 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 134 static dwc_otg_cmd_t dwc_otg_host_data_tx; 135 static dwc_otg_cmd_t dwc_otg_host_data_rx; 136 137 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 138 static void dwc_otg_do_poll(struct usb_bus *); 139 static void dwc_otg_standard_done(struct usb_xfer *); 140 static void dwc_otg_root_intr(struct dwc_otg_softc *); 141 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 142 143 /* 144 * Here is a configuration that the chip supports. 145 */ 146 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 147 148 [0] = { 149 .max_in_frame_size = 64,/* fixed */ 150 .max_out_frame_size = 64, /* fixed */ 151 .is_simplex = 1, 152 .support_control = 1, 153 } 154 }; 155 156 static void 157 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 158 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 159 { 160 struct dwc_otg_softc *sc; 161 162 sc = DWC_OTG_BUS2SC(udev->bus); 163 164 if (ep_addr < sc->sc_dev_ep_max) 165 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 166 else 167 *ppf = NULL; 168 } 169 170 static void 171 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 172 uint32_t offset, uint32_t fifo, uint32_t count) 173 { 174 uint32_t temp; 175 176 /* round down length to nearest 4-bytes */ 177 temp = count & ~3; 178 179 /* check if we can write the data directly */ 180 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 181 struct usb_page_search buf_res; 182 183 /* pre-subtract length */ 184 count -= temp; 185 186 /* iterate buffer list */ 187 do { 188 /* get current buffer pointer */ 189 usbd_get_page(pc, offset, &buf_res); 190 191 if (buf_res.length > temp) 192 buf_res.length = temp; 193 194 /* transfer data into FIFO */ 195 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 196 fifo, buf_res.buffer, buf_res.length / 4); 197 198 offset += buf_res.length; 199 fifo += buf_res.length; 200 temp -= buf_res.length; 201 } while (temp != 0); 202 } 203 204 /* check for remainder */ 205 if (count != 0) { 206 /* clear topmost word before copy */ 207 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 208 209 /* copy out data */ 210 usbd_copy_out(pc, offset, 211 sc->sc_bounce_buffer, count); 212 213 /* transfer data into FIFO */ 214 bus_space_write_region_4(sc->sc_io_tag, 215 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 216 (count + 3) / 4); 217 } 218 } 219 220 static void 221 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 222 uint32_t offset, uint32_t count) 223 { 224 uint32_t temp; 225 226 /* round down length to nearest 4-bytes */ 227 temp = count & ~3; 228 229 /* check if we can read the data directly */ 230 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 231 struct usb_page_search buf_res; 232 233 /* pre-subtract length */ 234 count -= temp; 235 236 /* iterate buffer list */ 237 do { 238 /* get current buffer pointer */ 239 usbd_get_page(pc, offset, &buf_res); 240 241 if (buf_res.length > temp) 242 buf_res.length = temp; 243 244 /* transfer data from FIFO */ 245 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 246 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 247 248 offset += buf_res.length; 249 sc->sc_current_rx_fifo += buf_res.length; 250 sc->sc_current_rx_bytes -= buf_res.length; 251 temp -= buf_res.length; 252 } while (temp != 0); 253 } 254 255 /* check for remainder */ 256 if (count != 0) { 257 /* read data into bounce buffer */ 258 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 259 sc->sc_current_rx_fifo, 260 sc->sc_bounce_buffer, (count + 3) / 4); 261 262 /* store data into proper buffer */ 263 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 264 265 /* round length up to nearest 4 bytes */ 266 count = (count + 3) & ~3; 267 268 /* update counters */ 269 sc->sc_current_rx_bytes -= count; 270 sc->sc_current_rx_fifo += count; 271 } 272 } 273 274 static void 275 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 276 { 277 uint32_t temp; 278 279 /* reset FIFO */ 280 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 281 282 /* wait for reset to complete */ 283 for (temp = 0; temp != 16; temp++) { 284 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 285 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 286 break; 287 } 288 } 289 290 static int 291 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 292 { 293 struct dwc_otg_profile *pf; 294 uint32_t fifo_size; 295 uint32_t fifo_regs; 296 uint32_t tx_start; 297 uint8_t x; 298 299 fifo_size = sc->sc_fifo_size; 300 301 /* 302 * NOTE: Reserved fixed size area at end of RAM, which must 303 * not be allocated to the FIFOs: 304 */ 305 fifo_regs = 4 * 16; 306 307 if (fifo_size < fifo_regs) { 308 DPRINTF("Too little FIFO\n"); 309 return (EINVAL); 310 } 311 312 /* subtract FIFO regs from total once */ 313 fifo_size -= fifo_regs; 314 315 /* split equally for IN and OUT */ 316 fifo_size /= 2; 317 318 /* Align to 4 bytes boundary (refer to PGM) */ 319 fifo_size &= ~3; 320 321 /* set global receive FIFO size */ 322 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 323 324 tx_start = fifo_size; 325 326 if (fifo_size < 64) { 327 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 328 return (EINVAL); 329 } 330 331 if (mode == DWC_MODE_HOST) { 332 333 /* reset active endpoints */ 334 sc->sc_active_rx_ep = 0; 335 336 /* split equally for periodic and non-periodic */ 337 fifo_size /= 2; 338 339 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 340 341 /* align to 4 bytes boundary */ 342 fifo_size &= ~3; 343 344 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 345 ((fifo_size / 4) << 16) | 346 (tx_start / 4)); 347 348 tx_start += fifo_size; 349 350 for (x = 0; x != sc->sc_host_ch_max; x++) { 351 /* enable all host interrupts */ 352 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 353 HCINT_DEFAULT_MASK); 354 } 355 356 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 357 ((fifo_size / 4) << 16) | 358 (tx_start / 4)); 359 360 /* reset host channel state */ 361 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 362 363 /* enable all host channel interrupts */ 364 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 365 (1U << sc->sc_host_ch_max) - 1U); 366 367 /* enable proper host channel interrupts */ 368 sc->sc_irq_mask |= GINTMSK_HCHINTMSK; 369 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; 370 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 371 } 372 373 if (mode == DWC_MODE_DEVICE) { 374 375 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 376 (0x10 << 16) | (tx_start / 4)); 377 fifo_size -= 0x40; 378 tx_start += 0x40; 379 380 /* setup control endpoint profile */ 381 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 382 383 /* reset active endpoints */ 384 sc->sc_active_rx_ep = 1; 385 386 for (x = 1; x != sc->sc_dev_ep_max; x++) { 387 388 pf = sc->sc_hw_ep_profile + x; 389 390 pf->usb.max_out_frame_size = 1024 * 3; 391 pf->usb.is_simplex = 0; /* assume duplex */ 392 pf->usb.support_bulk = 1; 393 pf->usb.support_interrupt = 1; 394 pf->usb.support_isochronous = 1; 395 pf->usb.support_out = 1; 396 397 if (x < sc->sc_dev_in_ep_max) { 398 uint32_t limit; 399 400 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 401 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 402 DWC_OTG_TX_MAX_FIFO_SIZE); 403 404 /* see if there is enough FIFO space */ 405 if (limit <= fifo_size) { 406 pf->max_buffer = limit; 407 pf->usb.support_in = 1; 408 } else { 409 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 410 if (limit <= fifo_size) { 411 pf->usb.support_in = 1; 412 } else { 413 pf->usb.is_simplex = 1; 414 limit = 0; 415 } 416 } 417 /* set FIFO size */ 418 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 419 ((limit / 4) << 16) | (tx_start / 4)); 420 tx_start += limit; 421 fifo_size -= limit; 422 pf->usb.max_in_frame_size = limit; 423 } else { 424 pf->usb.is_simplex = 1; 425 } 426 427 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 428 pf->usb.max_in_frame_size, 429 pf->usb.max_out_frame_size); 430 } 431 432 /* enable proper device channel interrupts */ 433 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; 434 sc->sc_irq_mask |= GINTMSK_IEPINTMSK; 435 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 436 } 437 438 /* reset RX FIFO */ 439 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 440 441 if (mode != DWC_MODE_OTG) { 442 /* reset all TX FIFOs */ 443 dwc_otg_tx_fifo_reset(sc, 444 GRSTCTL_TXFIFO(0x10) | 445 GRSTCTL_TXFFLSH); 446 } else { 447 /* reset active endpoints */ 448 sc->sc_active_rx_ep = 0; 449 450 /* reset host channel state */ 451 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 452 } 453 return (0); 454 } 455 456 static uint8_t 457 dwc_otg_uses_split(struct usb_device *udev) 458 { 459 /* 460 * When a LOW or FULL speed device is connected directly to 461 * the USB port we don't use split transactions: 462 */ 463 return (udev->speed != USB_SPEED_HIGH && 464 udev->parent_hs_hub != NULL && 465 udev->parent_hs_hub->parent_hub != NULL); 466 } 467 468 static void 469 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 470 { 471 472 /* 473 * Disabled until further. Assuming that the register is already 474 * programmed correctly by the boot loader. 475 */ 476 #if 0 477 uint32_t temp; 478 479 /* setup HOST frame interval register, based on existing value */ 480 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 481 if (temp >= 10000) 482 temp /= 1000; 483 else 484 temp /= 125; 485 486 /* figure out nearest X-tal value */ 487 if (temp >= 54) 488 temp = 60; /* MHz */ 489 else if (temp >= 39) 490 temp = 48; /* MHz */ 491 else 492 temp = 30; /* MHz */ 493 494 if (sc->sc_flags.status_high_speed) 495 temp *= 125; 496 else 497 temp *= 1000; 498 499 DPRINTF("HFIR=0x%08x\n", temp); 500 501 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 502 #endif 503 } 504 505 static void 506 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 507 { 508 if (sc->sc_flags.clocks_off && 509 sc->sc_flags.port_powered) { 510 511 DPRINTFN(5, "\n"); 512 513 /* TODO - platform specific */ 514 515 sc->sc_flags.clocks_off = 0; 516 } 517 } 518 519 static void 520 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 521 { 522 if (!sc->sc_flags.clocks_off) { 523 524 DPRINTFN(5, "\n"); 525 526 /* TODO - platform specific */ 527 528 sc->sc_flags.clocks_off = 1; 529 } 530 } 531 532 static void 533 dwc_otg_pull_up(struct dwc_otg_softc *sc) 534 { 535 uint32_t temp; 536 537 /* pullup D+, if possible */ 538 539 if (!sc->sc_flags.d_pulled_up && 540 sc->sc_flags.port_powered) { 541 sc->sc_flags.d_pulled_up = 1; 542 543 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 544 temp &= ~DCTL_SFTDISCON; 545 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 546 } 547 } 548 549 static void 550 dwc_otg_pull_down(struct dwc_otg_softc *sc) 551 { 552 uint32_t temp; 553 554 /* pulldown D+, if possible */ 555 556 if (sc->sc_flags.d_pulled_up) { 557 sc->sc_flags.d_pulled_up = 0; 558 559 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 560 temp |= DCTL_SFTDISCON; 561 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 562 } 563 } 564 565 static void 566 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 567 { 568 /* In device mode we don't use the SOF interrupt */ 569 if (sc->sc_flags.status_device_mode != 0) 570 return; 571 /* Ensure the SOF interrupt is not disabled */ 572 sc->sc_needsof = 1; 573 /* Check if the SOF interrupt is already enabled */ 574 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 575 return; 576 sc->sc_irq_mask |= GINTMSK_SOFMSK; 577 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 578 } 579 580 static void 581 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 582 { 583 if (sc->sc_flags.status_suspend) { 584 /* update status bits */ 585 sc->sc_flags.status_suspend = 0; 586 sc->sc_flags.change_suspend = 1; 587 588 if (sc->sc_flags.status_device_mode) { 589 /* 590 * Disable resume interrupt and enable suspend 591 * interrupt: 592 */ 593 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 594 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 595 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 596 } 597 598 /* complete root HUB interrupt endpoint */ 599 dwc_otg_root_intr(sc); 600 } 601 } 602 603 static void 604 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 605 { 606 if (!sc->sc_flags.status_suspend) { 607 /* update status bits */ 608 sc->sc_flags.status_suspend = 1; 609 sc->sc_flags.change_suspend = 1; 610 611 if (sc->sc_flags.status_device_mode) { 612 /* 613 * Disable suspend interrupt and enable resume 614 * interrupt: 615 */ 616 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 617 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 618 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 619 } 620 621 /* complete root HUB interrupt endpoint */ 622 dwc_otg_root_intr(sc); 623 } 624 } 625 626 static void 627 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 628 { 629 if (!sc->sc_flags.status_suspend) 630 return; 631 632 DPRINTFN(5, "Remote wakeup\n"); 633 634 if (sc->sc_flags.status_device_mode) { 635 uint32_t temp; 636 637 /* enable remote wakeup signalling */ 638 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 639 temp |= DCTL_RMTWKUPSIG; 640 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 641 642 /* Wait 8ms for remote wakeup to complete. */ 643 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 644 645 temp &= ~DCTL_RMTWKUPSIG; 646 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 647 } else { 648 /* enable USB port */ 649 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 650 651 /* wait 10ms */ 652 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 653 654 /* resume port */ 655 sc->sc_hprt_val |= HPRT_PRTRES; 656 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 657 658 /* Wait 100ms for resume signalling to complete. */ 659 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 660 661 /* clear suspend and resume */ 662 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 663 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 664 665 /* Wait 4ms */ 666 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 667 } 668 669 /* need to fake resume IRQ */ 670 dwc_otg_resume_irq(sc); 671 } 672 673 static void 674 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 675 { 676 uint32_t temp; 677 678 DPRINTFN(5, "addr=%d\n", addr); 679 680 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 681 temp &= ~DCFG_DEVADDR_SET(0x7F); 682 temp |= DCFG_DEVADDR_SET(addr); 683 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 684 } 685 686 static void 687 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 688 { 689 DPRINTFN(5, "RX status clear\n"); 690 691 /* enable RX FIFO level interrupt */ 692 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 693 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 694 695 if (sc->sc_current_rx_bytes != 0) { 696 /* need to dump remaining data */ 697 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 698 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 699 sc->sc_current_rx_bytes / 4); 700 /* clear number of active bytes to receive */ 701 sc->sc_current_rx_bytes = 0; 702 } 703 /* clear cached status */ 704 sc->sc_last_rx_status = 0; 705 } 706 707 static void 708 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 709 { 710 uint32_t hcint; 711 712 /* clear all pending interrupts */ 713 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 714 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 715 716 /* clear buffered interrupts */ 717 sc->sc_chan_state[x].hcint = 0; 718 } 719 720 static uint8_t 721 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 722 { 723 uint32_t temp; 724 725 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 726 727 if (td->ep_type == UE_ISOCHRONOUS) { 728 /* 729 * NOTE: USB INTERRUPT transactions are executed like 730 * USB CONTROL transactions! See the setup standard 731 * chain function for more information. 732 */ 733 if (!(temp & GINTSTS_PTXFEMP)) { 734 DPRINTF("Periodic TX FIFO is not empty\n"); 735 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 736 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 737 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 738 } 739 return (1); /* busy */ 740 } 741 } else { 742 if (!(temp & GINTSTS_NPTXFEMP)) { 743 DPRINTF("Non-periodic TX FIFO is not empty\n"); 744 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 745 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 746 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 747 } 748 return (1); /* busy */ 749 } 750 } 751 return (0); /* ready for transmit */ 752 } 753 754 static uint8_t 755 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 756 struct dwc_otg_td *td, uint8_t is_out) 757 { 758 uint8_t x; 759 uint8_t y; 760 uint8_t z; 761 762 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 763 return (0); /* already allocated */ 764 765 /* check if device is suspended */ 766 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 767 return (1); /* busy - cannot transfer data */ 768 769 /* compute needed TX FIFO size */ 770 if (is_out != 0) { 771 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 772 return (1); /* busy - cannot transfer data */ 773 } 774 z = td->max_packet_count; 775 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 776 /* check if channel is allocated */ 777 if (sc->sc_chan_state[x].allocated != 0) 778 continue; 779 /* check if channel is still enabled */ 780 if (sc->sc_chan_state[x].wait_halted != 0) 781 continue; 782 /* store channel number */ 783 td->channel[y++] = x; 784 /* check if we got all channels */ 785 if (y == z) 786 break; 787 } 788 if (y != z) { 789 /* reset channel variable */ 790 td->channel[0] = DWC_OTG_MAX_CHANNELS; 791 td->channel[1] = DWC_OTG_MAX_CHANNELS; 792 td->channel[2] = DWC_OTG_MAX_CHANNELS; 793 /* wait a bit */ 794 dwc_otg_enable_sof_irq(sc); 795 return (1); /* busy - not enough channels */ 796 } 797 798 for (y = 0; y != z; y++) { 799 x = td->channel[y]; 800 801 /* set allocated */ 802 sc->sc_chan_state[x].allocated = 1; 803 804 /* set wait halted */ 805 sc->sc_chan_state[x].wait_halted = 1; 806 807 /* clear interrupts */ 808 dwc_otg_clear_hcint(sc, x); 809 810 DPRINTF("CH=%d HCCHAR=0x%08x " 811 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 812 813 /* set active channel */ 814 sc->sc_active_rx_ep |= (1 << x); 815 } 816 return (0); /* allocated */ 817 } 818 819 static void 820 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 821 { 822 uint32_t hcchar; 823 uint8_t x; 824 825 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 826 return; /* already freed */ 827 828 /* free channel */ 829 x = td->channel[index]; 830 td->channel[index] = DWC_OTG_MAX_CHANNELS; 831 832 DPRINTF("CH=%d\n", x); 833 834 /* 835 * We need to let programmed host channels run till complete 836 * else the host channel will stop functioning. 837 */ 838 sc->sc_chan_state[x].allocated = 0; 839 840 /* ack any pending messages */ 841 if (sc->sc_last_rx_status != 0 && 842 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 843 dwc_otg_common_rx_ack(sc); 844 } 845 846 /* clear active channel */ 847 sc->sc_active_rx_ep &= ~(1 << x); 848 849 /* check if already halted */ 850 if (sc->sc_chan_state[x].wait_halted == 0) 851 return; 852 853 /* disable host channel */ 854 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 855 if (hcchar & HCCHAR_CHENA) { 856 DPRINTF("Halting channel %d\n", x); 857 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 858 hcchar | HCCHAR_CHDIS); 859 /* don't write HCCHAR until the channel is halted */ 860 } else { 861 sc->sc_chan_state[x].wait_halted = 0; 862 } 863 } 864 865 static void 866 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 867 { 868 uint8_t x; 869 for (x = 0; x != td->max_packet_count; x++) 870 dwc_otg_host_channel_free_sub(sc, td, x); 871 } 872 873 static void 874 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 875 { 876 uint8_t x; 877 /* dump any pending messages */ 878 if (sc->sc_last_rx_status == 0) 879 return; 880 for (x = 0; x != td->max_packet_count; x++) { 881 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 882 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 883 continue; 884 dwc_otg_common_rx_ack(sc); 885 break; 886 } 887 } 888 889 static uint8_t 890 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 891 { 892 struct usb_device_request req __aligned(4); 893 uint32_t hcint; 894 uint32_t hcchar; 895 uint8_t delta; 896 897 dwc_otg_host_dump_rx(sc, td); 898 899 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 900 hcint = sc->sc_chan_state[td->channel[0]].hcint; 901 902 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 903 td->channel[0], td->state, hcint, 904 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 905 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 906 } else { 907 hcint = 0; 908 goto check_state; 909 } 910 911 if (hcint & (HCINT_RETRY | 912 HCINT_ACK | HCINT_NYET)) { 913 /* give success bits priority over failure bits */ 914 } else if (hcint & HCINT_STALL) { 915 DPRINTF("CH=%d STALL\n", td->channel[0]); 916 td->error_stall = 1; 917 td->error_any = 1; 918 goto complete; 919 } else if (hcint & HCINT_ERRORS) { 920 DPRINTF("CH=%d ERROR\n", td->channel[0]); 921 td->errcnt++; 922 if (td->hcsplt != 0 || td->errcnt >= 3) { 923 td->error_any = 1; 924 goto complete; 925 } 926 } 927 928 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 929 HCINT_ACK | HCINT_NYET)) { 930 if (!(hcint & HCINT_ERRORS)) 931 td->errcnt = 0; 932 } 933 934 check_state: 935 switch (td->state) { 936 case DWC_CHAN_ST_START: 937 goto send_pkt; 938 939 case DWC_CHAN_ST_WAIT_ANE: 940 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 941 td->did_nak = 1; 942 td->tt_scheduled = 0; 943 goto send_pkt; 944 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 945 td->offset += td->tx_bytes; 946 td->remainder -= td->tx_bytes; 947 td->toggle = 1; 948 td->tt_scheduled = 0; 949 goto complete; 950 } 951 break; 952 953 case DWC_CHAN_ST_WAIT_S_ANE: 954 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 955 td->did_nak = 1; 956 td->tt_scheduled = 0; 957 goto send_pkt; 958 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 959 goto send_cpkt; 960 } 961 break; 962 963 case DWC_CHAN_ST_WAIT_C_ANE: 964 if (hcint & HCINT_NYET) { 965 goto send_cpkt; 966 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 967 td->did_nak = 1; 968 td->tt_scheduled = 0; 969 goto send_pkt; 970 } else if (hcint & HCINT_ACK) { 971 td->offset += td->tx_bytes; 972 td->remainder -= td->tx_bytes; 973 td->toggle = 1; 974 goto complete; 975 } 976 break; 977 978 case DWC_CHAN_ST_WAIT_C_PKT: 979 goto send_cpkt; 980 981 default: 982 break; 983 } 984 goto busy; 985 986 send_pkt: 987 /* free existing channel, if any */ 988 dwc_otg_host_channel_free(sc, td); 989 990 if (sizeof(req) != td->remainder) { 991 td->error_any = 1; 992 goto complete; 993 } 994 995 if (td->hcsplt != 0) { 996 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 997 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 998 td->state = DWC_CHAN_ST_START; 999 goto busy; 1000 } 1001 delta = sc->sc_last_frame_num - td->tt_start_slot; 1002 if (delta > 5) { 1003 /* missed it */ 1004 td->tt_scheduled = 0; 1005 td->state = DWC_CHAN_ST_START; 1006 goto busy; 1007 } 1008 } 1009 1010 /* allocate a new channel */ 1011 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1012 td->state = DWC_CHAN_ST_START; 1013 goto busy; 1014 } 1015 1016 if (td->hcsplt != 0) { 1017 td->hcsplt &= ~HCSPLT_COMPSPLT; 1018 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1019 } else { 1020 td->state = DWC_CHAN_ST_WAIT_ANE; 1021 } 1022 1023 /* copy out control request */ 1024 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1025 1026 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1027 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1028 (1 << HCTSIZ_PKTCNT_SHIFT) | 1029 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1030 1031 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1032 1033 hcchar = td->hcchar; 1034 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1035 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1036 1037 /* must enable channel before writing data to FIFO */ 1038 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1039 1040 /* transfer data into FIFO */ 1041 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1042 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1043 1044 /* wait until next slot before trying complete split */ 1045 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1046 1047 /* store number of bytes transmitted */ 1048 td->tx_bytes = sizeof(req); 1049 goto busy; 1050 1051 send_cpkt: 1052 /* free existing channel, if any */ 1053 dwc_otg_host_channel_free(sc, td); 1054 1055 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1056 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1057 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1058 goto busy; 1059 } 1060 delta = sc->sc_last_frame_num - td->tt_start_slot; 1061 if (delta > DWC_OTG_TT_SLOT_MAX) { 1062 /* we missed the service interval */ 1063 if (td->ep_type != UE_ISOCHRONOUS) 1064 td->error_any = 1; 1065 goto complete; 1066 } 1067 /* allocate a new channel */ 1068 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1069 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1070 goto busy; 1071 } 1072 1073 /* wait until next slot before trying complete split */ 1074 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1075 1076 td->hcsplt |= HCSPLT_COMPSPLT; 1077 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1078 1079 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1080 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1081 1082 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1083 1084 hcchar = td->hcchar; 1085 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1086 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1087 1088 /* must enable channel before writing data to FIFO */ 1089 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1090 1091 busy: 1092 return (1); /* busy */ 1093 1094 complete: 1095 dwc_otg_host_channel_free(sc, td); 1096 return (0); /* complete */ 1097 } 1098 1099 static uint8_t 1100 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1101 { 1102 struct usb_device_request req __aligned(4); 1103 uint32_t temp; 1104 uint16_t count; 1105 1106 /* check endpoint status */ 1107 1108 if (sc->sc_last_rx_status == 0) 1109 goto not_complete; 1110 1111 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1112 goto not_complete; 1113 1114 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1115 GRXSTSRD_STP_DATA) { 1116 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1117 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1118 /* release FIFO */ 1119 dwc_otg_common_rx_ack(sc); 1120 goto not_complete; 1121 } 1122 /* release FIFO */ 1123 dwc_otg_common_rx_ack(sc); 1124 return (0); /* complete */ 1125 } 1126 1127 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1128 GRXSTSRD_DPID_DATA0) { 1129 /* release FIFO */ 1130 dwc_otg_common_rx_ack(sc); 1131 goto not_complete; 1132 } 1133 1134 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1135 1136 /* clear did stall */ 1137 td->did_stall = 0; 1138 1139 /* get the packet byte count */ 1140 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1141 1142 if (count != sizeof(req)) { 1143 DPRINTFN(0, "Unsupported SETUP packet " 1144 "length, %d bytes\n", count); 1145 /* release FIFO */ 1146 dwc_otg_common_rx_ack(sc); 1147 goto not_complete; 1148 } 1149 1150 /* read FIFO */ 1151 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1152 1153 /* copy out control request */ 1154 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1155 1156 td->offset = sizeof(req); 1157 td->remainder = 0; 1158 1159 /* sneak peek the set address */ 1160 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1161 (req.bRequest == UR_SET_ADDRESS)) { 1162 /* must write address before ZLP */ 1163 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1164 } 1165 1166 /* don't send any data by default */ 1167 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1168 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1169 1170 /* reset IN endpoint buffer */ 1171 dwc_otg_tx_fifo_reset(sc, 1172 GRSTCTL_TXFIFO(0) | 1173 GRSTCTL_TXFFLSH); 1174 1175 /* acknowledge RX status */ 1176 dwc_otg_common_rx_ack(sc); 1177 td->did_stall = 1; 1178 1179 not_complete: 1180 /* abort any ongoing transfer, before enabling again */ 1181 if (!td->did_stall) { 1182 td->did_stall = 1; 1183 1184 DPRINTFN(5, "stalling IN and OUT direction\n"); 1185 1186 temp = sc->sc_out_ctl[0]; 1187 1188 /* set stall after enabling endpoint */ 1189 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1190 temp | DOEPCTL_STALL); 1191 1192 temp = sc->sc_in_ctl[0]; 1193 1194 /* set stall assuming endpoint is enabled */ 1195 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1196 temp | DIEPCTL_STALL); 1197 } 1198 return (1); /* not complete */ 1199 } 1200 1201 static uint8_t 1202 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1203 { 1204 uint8_t delta; 1205 1206 delta = sc->sc_tmr_val - td->tmr_val; 1207 if (delta >= 128) 1208 return (1); /* busy */ 1209 1210 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1211 1212 /* set toggle, if any */ 1213 if (td->set_toggle) { 1214 td->set_toggle = 0; 1215 td->toggle = 1; 1216 } 1217 return (0); 1218 } 1219 1220 static uint8_t 1221 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1222 { 1223 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1224 1225 if (td->ep_type == UE_ISOCHRONOUS) { 1226 /* non TT isochronous traffic */ 1227 if (frame_num & (td->tmr_res - 1)) 1228 goto busy; 1229 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1230 goto busy; 1231 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1232 td->toggle = 0; 1233 return (0); 1234 } else if (td->ep_type == UE_INTERRUPT) { 1235 if (!td->tt_scheduled) 1236 goto busy; 1237 td->tt_scheduled = 0; 1238 return (0); 1239 } else if (td->did_nak != 0) { 1240 /* check if we should pause sending queries for 125us */ 1241 if (td->tmr_res == frame_num) { 1242 /* wait a bit */ 1243 dwc_otg_enable_sof_irq(sc); 1244 goto busy; 1245 } 1246 } else if (td->set_toggle) { 1247 td->set_toggle = 0; 1248 td->toggle = 1; 1249 } 1250 /* query for data one more time */ 1251 td->tmr_res = frame_num; 1252 td->did_nak = 0; 1253 return (0); 1254 busy: 1255 return (1); 1256 } 1257 1258 static uint8_t 1259 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1260 uint8_t channel) 1261 { 1262 uint32_t count; 1263 1264 /* check endpoint status */ 1265 if (sc->sc_last_rx_status == 0) 1266 goto busy; 1267 1268 if (channel >= DWC_OTG_MAX_CHANNELS) 1269 goto busy; 1270 1271 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1272 goto busy; 1273 1274 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1275 case GRXSTSRH_IN_DATA: 1276 1277 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1278 (int)td->state, (int)sc->sc_last_rx_status); 1279 1280 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1281 /* 1282 * When using SPLIT transactions on interrupt 1283 * endpoints, sometimes data occurs twice. 1284 */ 1285 DPRINTF("Data already received\n"); 1286 break; 1287 } 1288 1289 /* get the packet byte count */ 1290 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1291 1292 /* check for ISOCHRONOUS endpoint */ 1293 if (td->ep_type == UE_ISOCHRONOUS) { 1294 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1295 GRXSTSRD_DPID_DATA0) { 1296 /* more data to be received */ 1297 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1298 } else { 1299 /* all data received */ 1300 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1301 /* verify the packet byte count */ 1302 if (count != td->remainder) { 1303 /* we have a short packet */ 1304 td->short_pkt = 1; 1305 td->got_short = 1; 1306 } 1307 } 1308 } else { 1309 /* verify the packet byte count */ 1310 if (count != td->max_packet_size) { 1311 if (count < td->max_packet_size) { 1312 /* we have a short packet */ 1313 td->short_pkt = 1; 1314 td->got_short = 1; 1315 } else { 1316 /* invalid USB packet */ 1317 td->error_any = 1; 1318 1319 /* release FIFO */ 1320 dwc_otg_common_rx_ack(sc); 1321 goto complete; 1322 } 1323 } 1324 td->toggle ^= 1; 1325 td->tt_scheduled = 0; 1326 } 1327 1328 /* verify the packet byte count */ 1329 if (count > td->remainder) { 1330 /* invalid USB packet */ 1331 td->error_any = 1; 1332 1333 /* release FIFO */ 1334 dwc_otg_common_rx_ack(sc); 1335 goto complete; 1336 } 1337 1338 /* read data from FIFO */ 1339 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1340 1341 td->remainder -= count; 1342 td->offset += count; 1343 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1344 break; 1345 default: 1346 break; 1347 } 1348 /* release FIFO */ 1349 dwc_otg_common_rx_ack(sc); 1350 busy: 1351 return (0); 1352 complete: 1353 return (1); 1354 } 1355 1356 static uint8_t 1357 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1358 { 1359 uint32_t hcint = 0; 1360 uint32_t hcchar; 1361 uint8_t delta; 1362 uint8_t channel; 1363 uint8_t x; 1364 1365 for (x = 0; x != td->max_packet_count; x++) { 1366 channel = td->channel[x]; 1367 if (channel >= DWC_OTG_MAX_CHANNELS) 1368 continue; 1369 hcint |= sc->sc_chan_state[channel].hcint; 1370 1371 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1372 channel, td->state, hcint, 1373 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1374 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1375 1376 /* check interrupt bits */ 1377 if (hcint & (HCINT_RETRY | 1378 HCINT_ACK | HCINT_NYET)) { 1379 /* give success bits priority over failure bits */ 1380 } else if (hcint & HCINT_STALL) { 1381 DPRINTF("CH=%d STALL\n", channel); 1382 td->error_stall = 1; 1383 td->error_any = 1; 1384 goto complete; 1385 } else if (hcint & HCINT_ERRORS) { 1386 DPRINTF("CH=%d ERROR\n", channel); 1387 td->errcnt++; 1388 if (td->hcsplt != 0 || td->errcnt >= 3) { 1389 if (td->ep_type != UE_ISOCHRONOUS) { 1390 td->error_any = 1; 1391 goto complete; 1392 } 1393 } 1394 } 1395 1396 /* check channels for data, if any */ 1397 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1398 goto complete; 1399 1400 /* refresh interrupt status */ 1401 hcint |= sc->sc_chan_state[channel].hcint; 1402 1403 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1404 HCINT_ACK | HCINT_NYET)) { 1405 if (!(hcint & HCINT_ERRORS)) 1406 td->errcnt = 0; 1407 } 1408 } 1409 1410 switch (td->state) { 1411 case DWC_CHAN_ST_START: 1412 if (td->hcsplt != 0) 1413 goto receive_spkt; 1414 else 1415 goto receive_pkt; 1416 1417 case DWC_CHAN_ST_WAIT_ANE: 1418 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1419 if (td->ep_type == UE_INTERRUPT) { 1420 /* 1421 * The USB specification does not 1422 * mandate a particular data toggle 1423 * value for USB INTERRUPT 1424 * transfers. Switch the data toggle 1425 * value to receive the packet 1426 * correctly: 1427 */ 1428 if (hcint & HCINT_DATATGLERR) { 1429 DPRINTF("Retrying packet due to " 1430 "data toggle error\n"); 1431 td->toggle ^= 1; 1432 goto receive_pkt; 1433 } 1434 } else if (td->ep_type == UE_ISOCHRONOUS) { 1435 goto complete; 1436 } 1437 td->did_nak = 1; 1438 td->tt_scheduled = 0; 1439 if (td->hcsplt != 0) 1440 goto receive_spkt; 1441 else 1442 goto receive_pkt; 1443 } else if (hcint & HCINT_NYET) { 1444 if (td->hcsplt != 0) { 1445 /* try again */ 1446 goto receive_pkt; 1447 } else { 1448 /* not a valid token for IN endpoints */ 1449 td->error_any = 1; 1450 goto complete; 1451 } 1452 } else if (hcint & HCINT_ACK) { 1453 /* wait for data - ACK arrived first */ 1454 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1455 goto busy; 1456 1457 if (td->ep_type == UE_ISOCHRONOUS) { 1458 /* check if we are complete */ 1459 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1460 goto complete; 1461 } else if (td->hcsplt != 0) { 1462 goto receive_pkt; 1463 } else { 1464 /* get more packets */ 1465 goto busy; 1466 } 1467 } else { 1468 /* check if we are complete */ 1469 if ((td->remainder == 0) || (td->got_short != 0)) { 1470 if (td->short_pkt) 1471 goto complete; 1472 1473 /* 1474 * Else need to receive a zero length 1475 * packet. 1476 */ 1477 } 1478 td->tt_scheduled = 0; 1479 td->did_nak = 0; 1480 if (td->hcsplt != 0) 1481 goto receive_spkt; 1482 else 1483 goto receive_pkt; 1484 } 1485 } 1486 break; 1487 1488 case DWC_CHAN_ST_WAIT_S_ANE: 1489 /* 1490 * NOTE: The DWC OTG hardware provides a fake ACK in 1491 * case of interrupt and isochronous transfers: 1492 */ 1493 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1494 td->did_nak = 1; 1495 td->tt_scheduled = 0; 1496 goto receive_spkt; 1497 } else if (hcint & HCINT_NYET) { 1498 td->tt_scheduled = 0; 1499 goto receive_spkt; 1500 } else if (hcint & HCINT_ACK) { 1501 td->did_nak = 0; 1502 goto receive_pkt; 1503 } 1504 break; 1505 1506 case DWC_CHAN_ST_WAIT_C_PKT: 1507 goto receive_pkt; 1508 1509 default: 1510 break; 1511 } 1512 goto busy; 1513 1514 receive_pkt: 1515 /* free existing channel, if any */ 1516 dwc_otg_host_channel_free(sc, td); 1517 1518 if (td->hcsplt != 0) { 1519 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1520 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1521 if (td->ep_type != UE_ISOCHRONOUS) { 1522 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1523 goto busy; 1524 } 1525 } 1526 delta = sc->sc_last_frame_num - td->tt_start_slot; 1527 if (delta > DWC_OTG_TT_SLOT_MAX) { 1528 if (td->ep_type != UE_ISOCHRONOUS) { 1529 /* we missed the service interval */ 1530 td->error_any = 1; 1531 } 1532 goto complete; 1533 } 1534 /* complete split */ 1535 td->hcsplt |= HCSPLT_COMPSPLT; 1536 } else if (dwc_otg_host_rate_check(sc, td)) { 1537 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1538 goto busy; 1539 } 1540 1541 /* allocate a new channel */ 1542 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1543 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1544 goto busy; 1545 } 1546 1547 /* set toggle, if any */ 1548 if (td->set_toggle) { 1549 td->set_toggle = 0; 1550 td->toggle = 1; 1551 } 1552 1553 td->state = DWC_CHAN_ST_WAIT_ANE; 1554 1555 for (x = 0; x != td->max_packet_count; x++) { 1556 channel = td->channel[x]; 1557 1558 /* receive one packet */ 1559 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1560 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1561 (1 << HCTSIZ_PKTCNT_SHIFT) | 1562 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1563 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1564 1565 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1566 1567 hcchar = td->hcchar; 1568 hcchar |= HCCHAR_EPDIR_IN; 1569 1570 if (td->ep_type == UE_ISOCHRONOUS) { 1571 if (td->hcsplt != 0) { 1572 /* continously buffer */ 1573 if (sc->sc_last_frame_num & 1) 1574 hcchar &= ~HCCHAR_ODDFRM; 1575 else 1576 hcchar |= HCCHAR_ODDFRM; 1577 } else { 1578 /* multi buffer, if any */ 1579 if (sc->sc_last_frame_num & 1) 1580 hcchar |= HCCHAR_ODDFRM; 1581 else 1582 hcchar &= ~HCCHAR_ODDFRM; 1583 } 1584 } else { 1585 hcchar &= ~HCCHAR_ODDFRM; 1586 } 1587 1588 /* must enable channel before data can be received */ 1589 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1590 } 1591 /* wait until next slot before trying complete split */ 1592 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1593 1594 goto busy; 1595 1596 receive_spkt: 1597 /* free existing channel(s), if any */ 1598 dwc_otg_host_channel_free(sc, td); 1599 1600 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1601 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1602 td->state = DWC_CHAN_ST_START; 1603 goto busy; 1604 } 1605 delta = sc->sc_last_frame_num - td->tt_start_slot; 1606 if (delta > 5) { 1607 /* missed it */ 1608 td->tt_scheduled = 0; 1609 td->state = DWC_CHAN_ST_START; 1610 goto busy; 1611 } 1612 1613 /* allocate a new channel */ 1614 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1615 td->state = DWC_CHAN_ST_START; 1616 goto busy; 1617 } 1618 1619 channel = td->channel[0]; 1620 1621 td->hcsplt &= ~HCSPLT_COMPSPLT; 1622 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1623 1624 /* receive one packet */ 1625 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1626 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1627 1628 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1629 1630 /* send after next SOF event */ 1631 if ((sc->sc_last_frame_num & 1) == 0 && 1632 td->ep_type == UE_ISOCHRONOUS) 1633 td->hcchar |= HCCHAR_ODDFRM; 1634 else 1635 td->hcchar &= ~HCCHAR_ODDFRM; 1636 1637 hcchar = td->hcchar; 1638 hcchar |= HCCHAR_EPDIR_IN; 1639 1640 /* wait until next slot before trying complete split */ 1641 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1642 1643 /* must enable channel before data can be received */ 1644 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1645 busy: 1646 return (1); /* busy */ 1647 1648 complete: 1649 dwc_otg_host_channel_free(sc, td); 1650 return (0); /* complete */ 1651 } 1652 1653 static uint8_t 1654 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1655 { 1656 uint32_t temp; 1657 uint16_t count; 1658 uint8_t got_short; 1659 1660 got_short = 0; 1661 1662 /* check endpoint status */ 1663 if (sc->sc_last_rx_status == 0) 1664 goto not_complete; 1665 1666 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1667 goto not_complete; 1668 1669 /* check for SETUP packet */ 1670 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1671 GRXSTSRD_STP_DATA || 1672 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1673 GRXSTSRD_STP_COMPLETE) { 1674 if (td->remainder == 0) { 1675 /* 1676 * We are actually complete and have 1677 * received the next SETUP 1678 */ 1679 DPRINTFN(5, "faking complete\n"); 1680 return (0); /* complete */ 1681 } 1682 /* 1683 * USB Host Aborted the transfer. 1684 */ 1685 td->error_any = 1; 1686 return (0); /* complete */ 1687 } 1688 1689 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1690 GRXSTSRD_OUT_DATA) { 1691 /* release FIFO */ 1692 dwc_otg_common_rx_ack(sc); 1693 goto not_complete; 1694 } 1695 1696 /* get the packet byte count */ 1697 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1698 1699 /* verify the packet byte count */ 1700 if (count != td->max_packet_size) { 1701 if (count < td->max_packet_size) { 1702 /* we have a short packet */ 1703 td->short_pkt = 1; 1704 got_short = 1; 1705 } else { 1706 /* invalid USB packet */ 1707 td->error_any = 1; 1708 1709 /* release FIFO */ 1710 dwc_otg_common_rx_ack(sc); 1711 return (0); /* we are complete */ 1712 } 1713 } 1714 /* verify the packet byte count */ 1715 if (count > td->remainder) { 1716 /* invalid USB packet */ 1717 td->error_any = 1; 1718 1719 /* release FIFO */ 1720 dwc_otg_common_rx_ack(sc); 1721 return (0); /* we are complete */ 1722 } 1723 1724 /* read data from FIFO */ 1725 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1726 1727 td->remainder -= count; 1728 td->offset += count; 1729 1730 /* release FIFO */ 1731 dwc_otg_common_rx_ack(sc); 1732 1733 temp = sc->sc_out_ctl[td->ep_no]; 1734 1735 /* check for isochronous mode */ 1736 if ((temp & DIEPCTL_EPTYPE_MASK) == 1737 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1738 /* toggle odd or even frame bit */ 1739 if (temp & DIEPCTL_SETD1PID) { 1740 temp &= ~DIEPCTL_SETD1PID; 1741 temp |= DIEPCTL_SETD0PID; 1742 } else { 1743 temp &= ~DIEPCTL_SETD0PID; 1744 temp |= DIEPCTL_SETD1PID; 1745 } 1746 sc->sc_out_ctl[td->ep_no] = temp; 1747 } 1748 1749 /* check if we are complete */ 1750 if ((td->remainder == 0) || got_short) { 1751 if (td->short_pkt) { 1752 /* we are complete */ 1753 return (0); 1754 } 1755 /* else need to receive a zero length packet */ 1756 } 1757 1758 not_complete: 1759 1760 /* enable SETUP and transfer complete interrupt */ 1761 if (td->ep_no == 0) { 1762 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1763 DXEPTSIZ_SET_MULTI(3) | 1764 DXEPTSIZ_SET_NPKT(1) | 1765 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1766 } else { 1767 /* allow reception of multiple packets */ 1768 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1769 DXEPTSIZ_SET_MULTI(1) | 1770 DXEPTSIZ_SET_NPKT(4) | 1771 DXEPTSIZ_SET_NBYTES(4 * 1772 ((td->max_packet_size + 3) & ~3))); 1773 } 1774 temp = sc->sc_out_ctl[td->ep_no]; 1775 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1776 DOEPCTL_EPENA | DOEPCTL_CNAK); 1777 1778 return (1); /* not complete */ 1779 } 1780 1781 static uint8_t 1782 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1783 { 1784 uint32_t count; 1785 uint32_t hcint; 1786 uint32_t hcchar; 1787 uint8_t delta; 1788 uint8_t channel; 1789 uint8_t x; 1790 1791 dwc_otg_host_dump_rx(sc, td); 1792 1793 /* check that last channel is complete */ 1794 channel = td->channel[td->npkt]; 1795 1796 if (channel < DWC_OTG_MAX_CHANNELS) { 1797 hcint = sc->sc_chan_state[channel].hcint; 1798 1799 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1800 channel, td->state, hcint, 1801 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1802 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1803 1804 if (hcint & (HCINT_RETRY | 1805 HCINT_ACK | HCINT_NYET)) { 1806 /* give success bits priority over failure bits */ 1807 } else if (hcint & HCINT_STALL) { 1808 DPRINTF("CH=%d STALL\n", channel); 1809 td->error_stall = 1; 1810 td->error_any = 1; 1811 goto complete; 1812 } else if (hcint & HCINT_ERRORS) { 1813 DPRINTF("CH=%d ERROR\n", channel); 1814 td->errcnt++; 1815 if (td->hcsplt != 0 || td->errcnt >= 3) { 1816 td->error_any = 1; 1817 goto complete; 1818 } 1819 } 1820 1821 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1822 HCINT_ACK | HCINT_NYET)) { 1823 1824 if (!(hcint & HCINT_ERRORS)) 1825 td->errcnt = 0; 1826 } 1827 } else { 1828 hcint = 0; 1829 } 1830 1831 switch (td->state) { 1832 case DWC_CHAN_ST_START: 1833 goto send_pkt; 1834 1835 case DWC_CHAN_ST_WAIT_ANE: 1836 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1837 td->did_nak = 1; 1838 td->tt_scheduled = 0; 1839 goto send_pkt; 1840 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1841 td->offset += td->tx_bytes; 1842 td->remainder -= td->tx_bytes; 1843 td->toggle ^= 1; 1844 /* check if next response will be a NAK */ 1845 if (hcint & HCINT_NYET) 1846 td->did_nak = 1; 1847 else 1848 td->did_nak = 0; 1849 td->tt_scheduled = 0; 1850 1851 /* check remainder */ 1852 if (td->remainder == 0) { 1853 if (td->short_pkt) 1854 goto complete; 1855 1856 /* 1857 * Else we need to transmit a short 1858 * packet: 1859 */ 1860 } 1861 goto send_pkt; 1862 } 1863 break; 1864 1865 case DWC_CHAN_ST_WAIT_S_ANE: 1866 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1867 td->did_nak = 1; 1868 td->tt_scheduled = 0; 1869 goto send_pkt; 1870 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1871 td->did_nak = 0; 1872 goto send_cpkt; 1873 } 1874 break; 1875 1876 case DWC_CHAN_ST_WAIT_C_ANE: 1877 if (hcint & HCINT_NYET) { 1878 goto send_cpkt; 1879 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1880 td->did_nak = 1; 1881 td->tt_scheduled = 0; 1882 goto send_pkt; 1883 } else if (hcint & HCINT_ACK) { 1884 td->offset += td->tx_bytes; 1885 td->remainder -= td->tx_bytes; 1886 td->toggle ^= 1; 1887 td->did_nak = 0; 1888 td->tt_scheduled = 0; 1889 1890 /* check remainder */ 1891 if (td->remainder == 0) { 1892 if (td->short_pkt) 1893 goto complete; 1894 1895 /* else we need to transmit a short packet */ 1896 } 1897 goto send_pkt; 1898 } 1899 break; 1900 1901 case DWC_CHAN_ST_WAIT_C_PKT: 1902 goto send_cpkt; 1903 1904 case DWC_CHAN_ST_TX_WAIT_ISOC: 1905 /* Check if ISOCHRONOUS OUT traffic is complete */ 1906 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1907 break; 1908 1909 td->offset += td->tx_bytes; 1910 td->remainder -= td->tx_bytes; 1911 goto complete; 1912 default: 1913 break; 1914 } 1915 goto busy; 1916 1917 send_pkt: 1918 /* free existing channel(s), if any */ 1919 dwc_otg_host_channel_free(sc, td); 1920 1921 if (td->hcsplt != 0) { 1922 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1923 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1924 td->state = DWC_CHAN_ST_START; 1925 goto busy; 1926 } 1927 delta = sc->sc_last_frame_num - td->tt_start_slot; 1928 if (delta > 5) { 1929 /* missed it */ 1930 td->tt_scheduled = 0; 1931 td->state = DWC_CHAN_ST_START; 1932 goto busy; 1933 } 1934 } else if (dwc_otg_host_rate_check(sc, td)) { 1935 td->state = DWC_CHAN_ST_START; 1936 goto busy; 1937 } 1938 1939 /* allocate a new channel */ 1940 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1941 td->state = DWC_CHAN_ST_START; 1942 goto busy; 1943 } 1944 1945 /* set toggle, if any */ 1946 if (td->set_toggle) { 1947 td->set_toggle = 0; 1948 td->toggle = 1; 1949 } 1950 1951 if (td->ep_type == UE_ISOCHRONOUS) { 1952 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1953 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1954 td->hcsplt &= ~HCSPLT_COMPSPLT; 1955 if (td->hcsplt != 0) { 1956 /* get maximum transfer length */ 1957 count = td->remainder; 1958 if (count > HCSPLT_XACTLEN_BURST) { 1959 DPRINTF("TT overflow\n"); 1960 td->error_any = 1; 1961 goto complete; 1962 } 1963 /* Update transaction position */ 1964 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1965 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1966 } 1967 } else if (td->hcsplt != 0) { 1968 td->hcsplt &= ~HCSPLT_COMPSPLT; 1969 /* Wait for ACK/NAK/ERR from TT */ 1970 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1971 } else { 1972 /* Wait for ACK/NAK/STALL from device */ 1973 td->state = DWC_CHAN_ST_WAIT_ANE; 1974 } 1975 1976 td->tx_bytes = 0; 1977 1978 for (x = 0; x != td->max_packet_count; x++) { 1979 uint32_t rem_bytes; 1980 1981 channel = td->channel[x]; 1982 1983 /* send one packet at a time */ 1984 count = td->max_packet_size; 1985 rem_bytes = td->remainder - td->tx_bytes; 1986 if (rem_bytes < count) { 1987 /* we have a short packet */ 1988 td->short_pkt = 1; 1989 count = rem_bytes; 1990 } 1991 if (count == rem_bytes) { 1992 /* last packet */ 1993 switch (x) { 1994 case 0: 1995 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1996 (count << HCTSIZ_XFERSIZE_SHIFT) | 1997 (1 << HCTSIZ_PKTCNT_SHIFT) | 1998 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1999 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2000 break; 2001 case 1: 2002 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2003 (count << HCTSIZ_XFERSIZE_SHIFT) | 2004 (1 << HCTSIZ_PKTCNT_SHIFT) | 2005 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 2006 break; 2007 default: 2008 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2009 (count << HCTSIZ_XFERSIZE_SHIFT) | 2010 (1 << HCTSIZ_PKTCNT_SHIFT) | 2011 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 2012 break; 2013 } 2014 } else if (td->ep_type == UE_ISOCHRONOUS && 2015 td->max_packet_count > 1) { 2016 /* ISOCHRONOUS multi packet */ 2017 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2018 (count << HCTSIZ_XFERSIZE_SHIFT) | 2019 (1 << HCTSIZ_PKTCNT_SHIFT) | 2020 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 2021 } else { 2022 /* TODO: HCTSIZ_DOPNG */ 2023 /* standard BULK/INTERRUPT/CONTROL packet */ 2024 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2025 (count << HCTSIZ_XFERSIZE_SHIFT) | 2026 (1 << HCTSIZ_PKTCNT_SHIFT) | 2027 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2028 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2029 } 2030 2031 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2032 2033 hcchar = td->hcchar; 2034 hcchar &= ~HCCHAR_EPDIR_IN; 2035 2036 /* send after next SOF event */ 2037 if ((sc->sc_last_frame_num & 1) == 0 && 2038 td->ep_type == UE_ISOCHRONOUS) 2039 hcchar |= HCCHAR_ODDFRM; 2040 else 2041 hcchar &= ~HCCHAR_ODDFRM; 2042 2043 /* must enable before writing data to FIFO */ 2044 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2045 2046 if (count != 0) { 2047 /* write data into FIFO */ 2048 dwc_otg_write_fifo(sc, td->pc, td->offset + 2049 td->tx_bytes, DOTG_DFIFO(channel), count); 2050 } 2051 2052 /* store number of bytes transmitted */ 2053 td->tx_bytes += count; 2054 2055 /* store last packet index */ 2056 td->npkt = x; 2057 2058 /* check for last packet */ 2059 if (count == rem_bytes) 2060 break; 2061 } 2062 goto busy; 2063 2064 send_cpkt: 2065 /* free existing channel, if any */ 2066 dwc_otg_host_channel_free(sc, td); 2067 2068 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2069 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2070 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2071 goto busy; 2072 } 2073 delta = sc->sc_last_frame_num - td->tt_start_slot; 2074 if (delta > DWC_OTG_TT_SLOT_MAX) { 2075 /* we missed the service interval */ 2076 if (td->ep_type != UE_ISOCHRONOUS) 2077 td->error_any = 1; 2078 goto complete; 2079 } 2080 2081 /* allocate a new channel */ 2082 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2083 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2084 goto busy; 2085 } 2086 2087 channel = td->channel[0]; 2088 2089 td->hcsplt |= HCSPLT_COMPSPLT; 2090 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2091 2092 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2093 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2094 2095 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2096 2097 hcchar = td->hcchar; 2098 hcchar &= ~HCCHAR_EPDIR_IN; 2099 2100 /* receive complete split ASAP */ 2101 if ((sc->sc_last_frame_num & 1) != 0 && 2102 td->ep_type == UE_ISOCHRONOUS) 2103 hcchar |= HCCHAR_ODDFRM; 2104 else 2105 hcchar &= ~HCCHAR_ODDFRM; 2106 2107 /* must enable channel before data can be received */ 2108 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2109 2110 /* wait until next slot before trying complete split */ 2111 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2112 busy: 2113 return (1); /* busy */ 2114 2115 complete: 2116 dwc_otg_host_channel_free(sc, td); 2117 return (0); /* complete */ 2118 } 2119 2120 static uint8_t 2121 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2122 { 2123 uint32_t max_buffer; 2124 uint32_t count; 2125 uint32_t fifo_left; 2126 uint32_t mpkt; 2127 uint32_t temp; 2128 uint8_t to; 2129 2130 to = 3; /* don't loop forever! */ 2131 2132 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2133 2134 repeat: 2135 /* check for for endpoint 0 data */ 2136 2137 temp = sc->sc_last_rx_status; 2138 2139 if ((td->ep_no == 0) && (temp != 0) && 2140 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2141 2142 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2143 GRXSTSRD_STP_DATA && 2144 (temp & GRXSTSRD_PKTSTS_MASK) != 2145 GRXSTSRD_STP_COMPLETE) { 2146 2147 /* dump data - wrong direction */ 2148 dwc_otg_common_rx_ack(sc); 2149 } else { 2150 /* 2151 * The current transfer was cancelled 2152 * by the USB Host: 2153 */ 2154 td->error_any = 1; 2155 return (0); /* complete */ 2156 } 2157 } 2158 2159 /* fill in more TX data, if possible */ 2160 if (td->tx_bytes != 0) { 2161 2162 uint16_t cpkt; 2163 2164 /* check if packets have been transferred */ 2165 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2166 2167 /* get current packet number */ 2168 cpkt = DXEPTSIZ_GET_NPKT(temp); 2169 2170 if (cpkt >= td->npkt) { 2171 fifo_left = 0; 2172 } else { 2173 if (max_buffer != 0) { 2174 fifo_left = (td->npkt - cpkt) * 2175 td->max_packet_size; 2176 2177 if (fifo_left > max_buffer) 2178 fifo_left = max_buffer; 2179 } else { 2180 fifo_left = td->max_packet_size; 2181 } 2182 } 2183 2184 count = td->tx_bytes; 2185 if (count > fifo_left) 2186 count = fifo_left; 2187 2188 if (count != 0) { 2189 /* write data into FIFO */ 2190 dwc_otg_write_fifo(sc, td->pc, td->offset, 2191 DOTG_DFIFO(td->ep_no), count); 2192 2193 td->tx_bytes -= count; 2194 td->remainder -= count; 2195 td->offset += count; 2196 td->npkt = cpkt; 2197 } 2198 if (td->tx_bytes != 0) 2199 goto not_complete; 2200 2201 /* check remainder */ 2202 if (td->remainder == 0) { 2203 if (td->short_pkt) 2204 return (0); /* complete */ 2205 2206 /* else we need to transmit a short packet */ 2207 } 2208 } 2209 2210 if (!to--) 2211 goto not_complete; 2212 2213 /* check if not all packets have been transferred */ 2214 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2215 2216 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2217 2218 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2219 "DIEPCTL=0x%08x\n", td->ep_no, 2220 DXEPTSIZ_GET_NPKT(temp), 2221 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2222 2223 goto not_complete; 2224 } 2225 2226 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2227 2228 /* try to optimise by sending more data */ 2229 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2230 2231 /* send multiple packets at the same time */ 2232 mpkt = max_buffer / td->max_packet_size; 2233 2234 if (mpkt > 0x3FE) 2235 mpkt = 0x3FE; 2236 2237 count = td->remainder; 2238 if (count > 0x7FFFFF) 2239 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2240 2241 td->npkt = count / td->max_packet_size; 2242 2243 /* 2244 * NOTE: We could use 0x3FE instead of "mpkt" in the 2245 * check below to get more throughput, but then we 2246 * have a dependency towards non-generic chip features 2247 * to disable the TX-FIFO-EMPTY interrupts on a per 2248 * endpoint basis. Increase the maximum buffer size of 2249 * the IN endpoint to increase the performance. 2250 */ 2251 if (td->npkt > mpkt) { 2252 td->npkt = mpkt; 2253 count = td->max_packet_size * mpkt; 2254 } else if ((count == 0) || (count % td->max_packet_size)) { 2255 /* we are transmitting a short packet */ 2256 td->npkt++; 2257 td->short_pkt = 1; 2258 } 2259 } else { 2260 /* send one packet at a time */ 2261 mpkt = 1; 2262 count = td->max_packet_size; 2263 if (td->remainder < count) { 2264 /* we have a short packet */ 2265 td->short_pkt = 1; 2266 count = td->remainder; 2267 } 2268 td->npkt = 1; 2269 } 2270 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2271 DXEPTSIZ_SET_MULTI(1) | 2272 DXEPTSIZ_SET_NPKT(td->npkt) | 2273 DXEPTSIZ_SET_NBYTES(count)); 2274 2275 /* make room for buffering */ 2276 td->npkt += mpkt; 2277 2278 temp = sc->sc_in_ctl[td->ep_no]; 2279 2280 /* check for isochronous mode */ 2281 if ((temp & DIEPCTL_EPTYPE_MASK) == 2282 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2283 /* toggle odd or even frame bit */ 2284 if (temp & DIEPCTL_SETD1PID) { 2285 temp &= ~DIEPCTL_SETD1PID; 2286 temp |= DIEPCTL_SETD0PID; 2287 } else { 2288 temp &= ~DIEPCTL_SETD0PID; 2289 temp |= DIEPCTL_SETD1PID; 2290 } 2291 sc->sc_in_ctl[td->ep_no] = temp; 2292 } 2293 2294 /* must enable before writing data to FIFO */ 2295 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2296 DIEPCTL_EPENA | DIEPCTL_CNAK); 2297 2298 td->tx_bytes = count; 2299 2300 /* check remainder */ 2301 if (td->tx_bytes == 0 && 2302 td->remainder == 0) { 2303 if (td->short_pkt) 2304 return (0); /* complete */ 2305 2306 /* else we need to transmit a short packet */ 2307 } 2308 goto repeat; 2309 2310 not_complete: 2311 return (1); /* not complete */ 2312 } 2313 2314 static uint8_t 2315 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2316 { 2317 uint32_t temp; 2318 2319 /* 2320 * If all packets are transferred we are complete: 2321 */ 2322 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2323 2324 /* check that all packets have been transferred */ 2325 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2326 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2327 goto not_complete; 2328 } 2329 return (0); 2330 2331 not_complete: 2332 2333 /* we only want to know if there is a SETUP packet or free IN packet */ 2334 2335 temp = sc->sc_last_rx_status; 2336 2337 if ((td->ep_no == 0) && (temp != 0) && 2338 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2339 2340 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2341 GRXSTSRD_STP_DATA || 2342 (temp & GRXSTSRD_PKTSTS_MASK) == 2343 GRXSTSRD_STP_COMPLETE) { 2344 DPRINTFN(5, "faking complete\n"); 2345 /* 2346 * Race condition: We are complete! 2347 */ 2348 return (0); 2349 } else { 2350 /* dump data - wrong direction */ 2351 dwc_otg_common_rx_ack(sc); 2352 } 2353 } 2354 return (1); /* not complete */ 2355 } 2356 2357 static void 2358 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2359 { 2360 struct dwc_otg_td *td; 2361 uint8_t toggle; 2362 uint8_t tmr_val; 2363 uint8_t tmr_res; 2364 2365 DPRINTFN(9, "\n"); 2366 2367 td = xfer->td_transfer_cache; 2368 if (td == NULL) 2369 return; 2370 2371 while (1) { 2372 if ((td->func) (sc, td)) { 2373 /* operation in progress */ 2374 break; 2375 } 2376 if (((void *)td) == xfer->td_transfer_last) { 2377 goto done; 2378 } 2379 if (td->error_any) { 2380 goto done; 2381 } else if (td->remainder > 0) { 2382 /* 2383 * We had a short transfer. If there is no alternate 2384 * next, stop processing ! 2385 */ 2386 if (!td->alt_next) 2387 goto done; 2388 } 2389 2390 /* 2391 * Fetch the next transfer descriptor and transfer 2392 * some flags to the next transfer descriptor 2393 */ 2394 tmr_res = td->tmr_res; 2395 tmr_val = td->tmr_val; 2396 toggle = td->toggle; 2397 td = td->obj_next; 2398 xfer->td_transfer_cache = td; 2399 td->toggle = toggle; /* transfer toggle */ 2400 td->tmr_res = tmr_res; 2401 td->tmr_val = tmr_val; 2402 } 2403 return; 2404 2405 done: 2406 xfer->td_transfer_cache = NULL; 2407 sc->sc_xfer_complete = 1; 2408 } 2409 2410 static uint8_t 2411 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2412 { 2413 struct dwc_otg_td *td; 2414 2415 DPRINTFN(9, "\n"); 2416 2417 td = xfer->td_transfer_cache; 2418 if (td == NULL) { 2419 /* compute all actual lengths */ 2420 dwc_otg_standard_done(xfer); 2421 return (1); 2422 } 2423 return (0); 2424 } 2425 2426 static void 2427 dwc_otg_timer(void *_sc) 2428 { 2429 struct dwc_otg_softc *sc = _sc; 2430 2431 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2432 2433 DPRINTF("\n"); 2434 2435 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2436 2437 /* increment timer value */ 2438 sc->sc_tmr_val++; 2439 2440 /* enable SOF interrupt, which will poll jobs */ 2441 dwc_otg_enable_sof_irq(sc); 2442 2443 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2444 2445 if (sc->sc_timer_active) { 2446 /* restart timer */ 2447 usb_callout_reset(&sc->sc_timer, 2448 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2449 &dwc_otg_timer, sc); 2450 } 2451 } 2452 2453 static void 2454 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2455 { 2456 if (sc->sc_timer_active != 0) 2457 return; 2458 2459 sc->sc_timer_active = 1; 2460 2461 /* restart timer */ 2462 usb_callout_reset(&sc->sc_timer, 2463 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2464 &dwc_otg_timer, sc); 2465 } 2466 2467 static void 2468 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2469 { 2470 if (sc->sc_timer_active == 0) 2471 return; 2472 2473 sc->sc_timer_active = 0; 2474 2475 /* stop timer */ 2476 usb_callout_stop(&sc->sc_timer); 2477 } 2478 2479 static uint16_t 2480 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2481 { 2482 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2483 pinfo->slot_index++; 2484 return (pinfo->slot_index); 2485 } 2486 2487 static uint8_t 2488 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2489 { 2490 TAILQ_HEAD(, usb_xfer) head; 2491 struct usb_xfer *xfer; 2492 struct usb_xfer *xfer_next; 2493 struct dwc_otg_td *td; 2494 uint16_t temp; 2495 uint16_t slot; 2496 2497 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2498 2499 if (sc->sc_last_frame_num == temp) 2500 return (0); 2501 2502 sc->sc_last_frame_num = temp; 2503 2504 TAILQ_INIT(&head); 2505 2506 if ((temp & 7) == 0) { 2507 2508 /* reset the schedule */ 2509 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2510 2511 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2512 td = xfer->td_transfer_cache; 2513 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2514 continue; 2515 2516 /* check for IN direction */ 2517 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2518 continue; 2519 2520 sc->sc_needsof = 1; 2521 2522 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2523 continue; 2524 2525 /* compute slot */ 2526 slot = dwc_otg_compute_isoc_rx_tt_slot( 2527 sc->sc_tt_info + td->tt_index); 2528 if (slot > 3) { 2529 /* 2530 * Not enough time to get complete 2531 * split executed. 2532 */ 2533 continue; 2534 } 2535 /* Delayed start */ 2536 td->tt_start_slot = temp + slot; 2537 td->tt_scheduled = 1; 2538 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2539 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2540 } 2541 2542 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2543 td = xfer->td_transfer_cache; 2544 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2545 continue; 2546 2547 /* check for OUT direction */ 2548 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2549 continue; 2550 2551 sc->sc_needsof = 1; 2552 2553 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2554 continue; 2555 2556 /* Start ASAP */ 2557 td->tt_start_slot = temp; 2558 td->tt_scheduled = 1; 2559 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2560 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2561 } 2562 2563 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2564 td = xfer->td_transfer_cache; 2565 if (td == NULL || td->ep_type != UE_INTERRUPT) 2566 continue; 2567 2568 if (td->tt_scheduled != 0) { 2569 sc->sc_needsof = 1; 2570 continue; 2571 } 2572 2573 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2574 continue; 2575 2576 if (td->hcsplt == 0) { 2577 sc->sc_needsof = 1; 2578 td->tt_scheduled = 1; 2579 continue; 2580 } 2581 2582 /* start ASAP */ 2583 td->tt_start_slot = temp; 2584 sc->sc_needsof = 1; 2585 td->tt_scheduled = 1; 2586 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2587 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2588 } 2589 2590 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2591 td = xfer->td_transfer_cache; 2592 if (td == NULL || 2593 td->ep_type != UE_CONTROL) { 2594 continue; 2595 } 2596 2597 sc->sc_needsof = 1; 2598 2599 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2600 continue; 2601 2602 /* start ASAP */ 2603 td->tt_start_slot = temp; 2604 td->tt_scheduled = 1; 2605 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2606 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2607 } 2608 } 2609 if ((temp & 7) < 6) { 2610 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2611 td = xfer->td_transfer_cache; 2612 if (td == NULL || 2613 td->ep_type != UE_BULK) { 2614 continue; 2615 } 2616 2617 sc->sc_needsof = 1; 2618 2619 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2620 continue; 2621 2622 /* start ASAP */ 2623 td->tt_start_slot = temp; 2624 td->tt_scheduled = 1; 2625 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2626 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2627 } 2628 } 2629 2630 /* Put TT transfers in execution order at the end */ 2631 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2632 2633 /* move all TT transfers in front, keeping the current order */ 2634 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2635 td = xfer->td_transfer_cache; 2636 if (td == NULL || td->hcsplt == 0) 2637 continue; 2638 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2639 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2640 } 2641 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2642 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2643 2644 /* put non-TT non-ISOCHRONOUS transfers last */ 2645 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2646 td = xfer->td_transfer_cache; 2647 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2648 continue; 2649 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2650 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2651 } 2652 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2653 2654 if ((temp & 7) == 0) { 2655 2656 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2657 (int)temp, (int)sc->sc_needsof); 2658 2659 /* update SOF IRQ mask */ 2660 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2661 if (sc->sc_needsof == 0) { 2662 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2663 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2664 } 2665 } else { 2666 if (sc->sc_needsof != 0) { 2667 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2668 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2669 } 2670 } 2671 2672 /* clear need SOF flag */ 2673 sc->sc_needsof = 0; 2674 } 2675 return (1); 2676 } 2677 2678 static void 2679 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2680 { 2681 struct usb_xfer *xfer; 2682 uint32_t count; 2683 uint32_t temp; 2684 uint32_t haint; 2685 uint8_t got_rx_status; 2686 uint8_t x; 2687 2688 if (sc->sc_flags.status_device_mode == 0) { 2689 /* 2690 * Update host transfer schedule, so that new 2691 * transfers can be issued: 2692 */ 2693 dwc_otg_update_host_transfer_schedule_locked(sc); 2694 } 2695 count = 0; 2696 repeat: 2697 if (++count == 16) { 2698 /* give other interrupts a chance */ 2699 DPRINTF("Yield\n"); 2700 return; 2701 } 2702 2703 /* get all host channel interrupts */ 2704 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2705 while (1) { 2706 x = ffs(haint) - 1; 2707 if (x >= sc->sc_host_ch_max) 2708 break; 2709 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2710 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2711 temp &= ~HCINT_SOFTWARE_ONLY; 2712 sc->sc_chan_state[x].hcint |= temp; 2713 haint &= ~(1U << x); 2714 } 2715 2716 if (sc->sc_last_rx_status == 0) { 2717 2718 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2719 if (temp & GINTSTS_RXFLVL) { 2720 /* pop current status */ 2721 sc->sc_last_rx_status = 2722 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2723 } 2724 2725 if (sc->sc_last_rx_status != 0) { 2726 2727 uint8_t ep_no; 2728 2729 temp = sc->sc_last_rx_status & 2730 GRXSTSRD_PKTSTS_MASK; 2731 2732 /* non-data messages we simply skip */ 2733 if (temp != GRXSTSRD_STP_DATA && 2734 temp != GRXSTSRD_STP_COMPLETE && 2735 temp != GRXSTSRD_OUT_DATA) { 2736 /* check for halted channel */ 2737 if (temp == GRXSTSRH_HALTED) { 2738 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2739 sc->sc_chan_state[ep_no].wait_halted = 0; 2740 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2741 } 2742 /* store bytes and FIFO offset */ 2743 sc->sc_current_rx_bytes = 0; 2744 sc->sc_current_rx_fifo = 0; 2745 2746 /* acknowledge status */ 2747 dwc_otg_common_rx_ack(sc); 2748 goto repeat; 2749 } 2750 2751 temp = GRXSTSRD_BCNT_GET( 2752 sc->sc_last_rx_status); 2753 ep_no = GRXSTSRD_CHNUM_GET( 2754 sc->sc_last_rx_status); 2755 2756 /* store bytes and FIFO offset */ 2757 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2758 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2759 2760 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2761 2762 /* check if we should dump the data */ 2763 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2764 dwc_otg_common_rx_ack(sc); 2765 goto repeat; 2766 } 2767 2768 got_rx_status = 1; 2769 2770 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2771 sc->sc_last_rx_status, ep_no, 2772 (sc->sc_last_rx_status >> 15) & 3, 2773 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2774 (sc->sc_last_rx_status >> 17) & 15); 2775 } else { 2776 got_rx_status = 0; 2777 } 2778 } else { 2779 uint8_t ep_no; 2780 2781 ep_no = GRXSTSRD_CHNUM_GET( 2782 sc->sc_last_rx_status); 2783 2784 /* check if we should dump the data */ 2785 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2786 dwc_otg_common_rx_ack(sc); 2787 goto repeat; 2788 } 2789 2790 got_rx_status = 1; 2791 } 2792 2793 /* execute FIFOs */ 2794 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2795 dwc_otg_xfer_do_fifo(sc, xfer); 2796 2797 if (got_rx_status) { 2798 /* check if data was consumed */ 2799 if (sc->sc_last_rx_status == 0) 2800 goto repeat; 2801 2802 /* disable RX FIFO level interrupt */ 2803 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2804 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2805 } 2806 } 2807 2808 static void 2809 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2810 { 2811 struct usb_xfer *xfer; 2812 repeat: 2813 /* scan for completion events */ 2814 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2815 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2816 goto repeat; 2817 } 2818 } 2819 2820 static void 2821 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2822 { 2823 DPRINTFN(5, "vbus = %u\n", is_on); 2824 2825 /* 2826 * If the USB host mode is forced, then assume VBUS is always 2827 * present else rely on the input to this function: 2828 */ 2829 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2830 2831 if (!sc->sc_flags.status_vbus) { 2832 sc->sc_flags.status_vbus = 1; 2833 2834 /* complete root HUB interrupt endpoint */ 2835 2836 dwc_otg_root_intr(sc); 2837 } 2838 } else { 2839 if (sc->sc_flags.status_vbus) { 2840 sc->sc_flags.status_vbus = 0; 2841 sc->sc_flags.status_bus_reset = 0; 2842 sc->sc_flags.status_suspend = 0; 2843 sc->sc_flags.change_suspend = 0; 2844 sc->sc_flags.change_connect = 1; 2845 2846 /* complete root HUB interrupt endpoint */ 2847 2848 dwc_otg_root_intr(sc); 2849 } 2850 } 2851 } 2852 2853 int 2854 dwc_otg_filter_interrupt(void *arg) 2855 { 2856 struct dwc_otg_softc *sc = arg; 2857 int retval = FILTER_HANDLED; 2858 uint32_t status; 2859 2860 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2861 2862 /* read and clear interrupt status */ 2863 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2864 2865 /* clear interrupts we are handling here */ 2866 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2867 2868 /* check for USB state change interrupts */ 2869 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2870 retval = FILTER_SCHEDULE_THREAD; 2871 2872 /* clear FIFO empty interrupts */ 2873 if (status & sc->sc_irq_mask & 2874 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2875 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2876 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2877 } 2878 /* clear all IN endpoint interrupts */ 2879 if (status & GINTSTS_IEPINT) { 2880 uint32_t temp; 2881 uint8_t x; 2882 2883 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2884 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2885 /* 2886 * NOTE: Need to clear all interrupt bits, 2887 * because some appears to be unmaskable and 2888 * can cause an interrupt loop: 2889 */ 2890 if (temp != 0) 2891 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); 2892 } 2893 } 2894 2895 /* poll FIFOs, if any */ 2896 dwc_otg_interrupt_poll_locked(sc); 2897 2898 if (sc->sc_xfer_complete != 0) 2899 retval = FILTER_SCHEDULE_THREAD; 2900 2901 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2902 2903 return (retval); 2904 } 2905 2906 void 2907 dwc_otg_interrupt(void *arg) 2908 { 2909 struct dwc_otg_softc *sc = arg; 2910 uint32_t status; 2911 2912 USB_BUS_LOCK(&sc->sc_bus); 2913 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2914 2915 /* read and clear interrupt status */ 2916 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2917 2918 /* clear interrupts we are handling here */ 2919 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2920 2921 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2922 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2923 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2924 2925 if (status & GINTSTS_USBRST) { 2926 2927 /* set correct state */ 2928 sc->sc_flags.status_device_mode = 1; 2929 sc->sc_flags.status_bus_reset = 0; 2930 sc->sc_flags.status_suspend = 0; 2931 sc->sc_flags.change_suspend = 0; 2932 sc->sc_flags.change_connect = 1; 2933 2934 /* Disable SOF interrupt */ 2935 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2936 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2937 2938 /* complete root HUB interrupt endpoint */ 2939 dwc_otg_root_intr(sc); 2940 } 2941 2942 /* check for any bus state change interrupts */ 2943 if (status & GINTSTS_ENUMDONE) { 2944 2945 uint32_t temp; 2946 2947 DPRINTFN(5, "end of reset\n"); 2948 2949 /* set correct state */ 2950 sc->sc_flags.status_device_mode = 1; 2951 sc->sc_flags.status_bus_reset = 1; 2952 sc->sc_flags.status_suspend = 0; 2953 sc->sc_flags.change_suspend = 0; 2954 sc->sc_flags.change_connect = 1; 2955 sc->sc_flags.status_low_speed = 0; 2956 sc->sc_flags.port_enabled = 1; 2957 2958 /* reset FIFOs */ 2959 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2960 2961 /* reset function address */ 2962 dwc_otg_set_address(sc, 0); 2963 2964 /* figure out enumeration speed */ 2965 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2966 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2967 sc->sc_flags.status_high_speed = 1; 2968 else 2969 sc->sc_flags.status_high_speed = 0; 2970 2971 /* 2972 * Disable resume and SOF interrupt, and enable 2973 * suspend and RX frame interrupt: 2974 */ 2975 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2976 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2977 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2978 2979 /* complete root HUB interrupt endpoint */ 2980 dwc_otg_root_intr(sc); 2981 } 2982 2983 if (status & GINTSTS_PRTINT) { 2984 uint32_t hprt; 2985 2986 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2987 2988 /* clear change bits */ 2989 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2990 HPRT_PRTPWR | HPRT_PRTENCHNG | 2991 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2992 sc->sc_hprt_val); 2993 2994 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2995 2996 sc->sc_flags.status_device_mode = 0; 2997 2998 if (hprt & HPRT_PRTCONNSTS) 2999 sc->sc_flags.status_bus_reset = 1; 3000 else 3001 sc->sc_flags.status_bus_reset = 0; 3002 3003 if ((hprt & HPRT_PRTENCHNG) && 3004 (hprt & HPRT_PRTENA) == 0) 3005 sc->sc_flags.change_enabled = 1; 3006 3007 if (hprt & HPRT_PRTENA) 3008 sc->sc_flags.port_enabled = 1; 3009 else 3010 sc->sc_flags.port_enabled = 0; 3011 3012 if (hprt & HPRT_PRTOVRCURRCHNG) 3013 sc->sc_flags.change_over_current = 1; 3014 3015 if (hprt & HPRT_PRTOVRCURRACT) 3016 sc->sc_flags.port_over_current = 1; 3017 else 3018 sc->sc_flags.port_over_current = 0; 3019 3020 if (hprt & HPRT_PRTPWR) 3021 sc->sc_flags.port_powered = 1; 3022 else 3023 sc->sc_flags.port_powered = 0; 3024 3025 if (((hprt & HPRT_PRTSPD_MASK) 3026 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 3027 sc->sc_flags.status_low_speed = 1; 3028 else 3029 sc->sc_flags.status_low_speed = 0; 3030 3031 if (((hprt & HPRT_PRTSPD_MASK) 3032 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3033 sc->sc_flags.status_high_speed = 1; 3034 else 3035 sc->sc_flags.status_high_speed = 0; 3036 3037 if (hprt & HPRT_PRTCONNDET) 3038 sc->sc_flags.change_connect = 1; 3039 3040 if (hprt & HPRT_PRTSUSP) 3041 dwc_otg_suspend_irq(sc); 3042 else 3043 dwc_otg_resume_irq(sc); 3044 3045 /* complete root HUB interrupt endpoint */ 3046 dwc_otg_root_intr(sc); 3047 3048 /* update host frame interval */ 3049 dwc_otg_update_host_frame_interval(sc); 3050 } 3051 3052 /* 3053 * If resume and suspend is set at the same time we interpret 3054 * that like RESUME. Resume is set when there is at least 3 3055 * milliseconds of inactivity on the USB BUS. 3056 */ 3057 if (status & GINTSTS_WKUPINT) { 3058 3059 DPRINTFN(5, "resume interrupt\n"); 3060 3061 dwc_otg_resume_irq(sc); 3062 3063 } else if (status & GINTSTS_USBSUSP) { 3064 3065 DPRINTFN(5, "suspend interrupt\n"); 3066 3067 dwc_otg_suspend_irq(sc); 3068 } 3069 /* check VBUS */ 3070 if (status & (GINTSTS_USBSUSP | 3071 GINTSTS_USBRST | 3072 GINTMSK_OTGINTMSK | 3073 GINTSTS_SESSREQINT)) { 3074 uint32_t temp; 3075 3076 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3077 3078 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3079 3080 dwc_otg_vbus_interrupt(sc, 3081 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3082 } 3083 3084 if (sc->sc_xfer_complete != 0) { 3085 sc->sc_xfer_complete = 0; 3086 3087 /* complete FIFOs, if any */ 3088 dwc_otg_interrupt_complete_locked(sc); 3089 } 3090 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3091 USB_BUS_UNLOCK(&sc->sc_bus); 3092 } 3093 3094 static void 3095 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3096 { 3097 struct dwc_otg_td *td; 3098 3099 /* get current Transfer Descriptor */ 3100 td = temp->td_next; 3101 temp->td = td; 3102 3103 /* prepare for next TD */ 3104 temp->td_next = td->obj_next; 3105 3106 /* fill out the Transfer Descriptor */ 3107 td->func = temp->func; 3108 td->pc = temp->pc; 3109 td->offset = temp->offset; 3110 td->remainder = temp->len; 3111 td->tx_bytes = 0; 3112 td->error_any = 0; 3113 td->error_stall = 0; 3114 td->npkt = 0; 3115 td->did_stall = temp->did_stall; 3116 td->short_pkt = temp->short_pkt; 3117 td->alt_next = temp->setup_alt_next; 3118 td->set_toggle = 0; 3119 td->got_short = 0; 3120 td->did_nak = 0; 3121 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3122 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3123 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3124 td->state = 0; 3125 td->errcnt = 0; 3126 td->tt_scheduled = 0; 3127 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3128 } 3129 3130 static void 3131 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3132 { 3133 struct dwc_otg_std_temp temp; 3134 struct dwc_otg_td *td; 3135 uint32_t x; 3136 uint8_t need_sync; 3137 uint8_t is_host; 3138 3139 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3140 xfer->address, UE_GET_ADDR(xfer->endpointno), 3141 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3142 3143 temp.max_frame_size = xfer->max_frame_size; 3144 3145 td = xfer->td_start[0]; 3146 xfer->td_transfer_first = td; 3147 xfer->td_transfer_cache = td; 3148 3149 /* setup temp */ 3150 3151 temp.pc = NULL; 3152 temp.td = NULL; 3153 temp.td_next = xfer->td_start[0]; 3154 temp.offset = 0; 3155 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3156 xfer->flags_int.isochronous_xfr; 3157 temp.did_stall = !xfer->flags_int.control_stall; 3158 3159 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3160 3161 /* check if we should prepend a setup message */ 3162 3163 if (xfer->flags_int.control_xfr) { 3164 if (xfer->flags_int.control_hdr) { 3165 3166 if (is_host) 3167 temp.func = &dwc_otg_host_setup_tx; 3168 else 3169 temp.func = &dwc_otg_setup_rx; 3170 3171 temp.len = xfer->frlengths[0]; 3172 temp.pc = xfer->frbuffers + 0; 3173 temp.short_pkt = temp.len ? 1 : 0; 3174 3175 /* check for last frame */ 3176 if (xfer->nframes == 1) { 3177 /* no STATUS stage yet, SETUP is last */ 3178 if (xfer->flags_int.control_act) 3179 temp.setup_alt_next = 0; 3180 } 3181 3182 dwc_otg_setup_standard_chain_sub(&temp); 3183 } 3184 x = 1; 3185 } else { 3186 x = 0; 3187 } 3188 3189 if (x != xfer->nframes) { 3190 if (xfer->endpointno & UE_DIR_IN) { 3191 if (is_host) { 3192 temp.func = &dwc_otg_host_data_rx; 3193 need_sync = 0; 3194 } else { 3195 temp.func = &dwc_otg_data_tx; 3196 need_sync = 1; 3197 } 3198 } else { 3199 if (is_host) { 3200 temp.func = &dwc_otg_host_data_tx; 3201 need_sync = 0; 3202 } else { 3203 temp.func = &dwc_otg_data_rx; 3204 need_sync = 0; 3205 } 3206 } 3207 3208 /* setup "pc" pointer */ 3209 temp.pc = xfer->frbuffers + x; 3210 } else { 3211 need_sync = 0; 3212 } 3213 while (x != xfer->nframes) { 3214 3215 /* DATA0 / DATA1 message */ 3216 3217 temp.len = xfer->frlengths[x]; 3218 3219 x++; 3220 3221 if (x == xfer->nframes) { 3222 if (xfer->flags_int.control_xfr) { 3223 if (xfer->flags_int.control_act) { 3224 temp.setup_alt_next = 0; 3225 } 3226 } else { 3227 temp.setup_alt_next = 0; 3228 } 3229 } 3230 if (temp.len == 0) { 3231 3232 /* make sure that we send an USB packet */ 3233 3234 temp.short_pkt = 0; 3235 3236 } else { 3237 3238 /* regular data transfer */ 3239 3240 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3241 } 3242 3243 dwc_otg_setup_standard_chain_sub(&temp); 3244 3245 if (xfer->flags_int.isochronous_xfr) { 3246 temp.offset += temp.len; 3247 } else { 3248 /* get next Page Cache pointer */ 3249 temp.pc = xfer->frbuffers + x; 3250 } 3251 } 3252 3253 if (xfer->flags_int.control_xfr) { 3254 3255 /* always setup a valid "pc" pointer for status and sync */ 3256 temp.pc = xfer->frbuffers + 0; 3257 temp.len = 0; 3258 temp.short_pkt = 0; 3259 temp.setup_alt_next = 0; 3260 3261 /* check if we need to sync */ 3262 if (need_sync) { 3263 /* we need a SYNC point after TX */ 3264 temp.func = &dwc_otg_data_tx_sync; 3265 dwc_otg_setup_standard_chain_sub(&temp); 3266 } 3267 3268 /* check if we should append a status stage */ 3269 if (!xfer->flags_int.control_act) { 3270 3271 /* 3272 * Send a DATA1 message and invert the current 3273 * endpoint direction. 3274 */ 3275 if (xfer->endpointno & UE_DIR_IN) { 3276 if (is_host) { 3277 temp.func = &dwc_otg_host_data_tx; 3278 need_sync = 0; 3279 } else { 3280 temp.func = &dwc_otg_data_rx; 3281 need_sync = 0; 3282 } 3283 } else { 3284 if (is_host) { 3285 temp.func = &dwc_otg_host_data_rx; 3286 need_sync = 0; 3287 } else { 3288 temp.func = &dwc_otg_data_tx; 3289 need_sync = 1; 3290 } 3291 } 3292 3293 dwc_otg_setup_standard_chain_sub(&temp); 3294 3295 /* data toggle should be DATA1 */ 3296 td = temp.td; 3297 td->set_toggle = 1; 3298 3299 if (need_sync) { 3300 /* we need a SYNC point after TX */ 3301 temp.func = &dwc_otg_data_tx_sync; 3302 dwc_otg_setup_standard_chain_sub(&temp); 3303 } 3304 } 3305 } else { 3306 /* check if we need to sync */ 3307 if (need_sync) { 3308 3309 temp.pc = xfer->frbuffers + 0; 3310 temp.len = 0; 3311 temp.short_pkt = 0; 3312 temp.setup_alt_next = 0; 3313 3314 /* we need a SYNC point after TX */ 3315 temp.func = &dwc_otg_data_tx_sync; 3316 dwc_otg_setup_standard_chain_sub(&temp); 3317 } 3318 } 3319 3320 /* must have at least one frame! */ 3321 td = temp.td; 3322 xfer->td_transfer_last = td; 3323 3324 if (is_host) { 3325 3326 struct dwc_otg_softc *sc; 3327 uint32_t hcchar; 3328 uint32_t hcsplt; 3329 3330 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3331 3332 /* get first again */ 3333 td = xfer->td_transfer_first; 3334 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3335 3336 hcchar = 3337 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3338 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3339 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3340 HCCHAR_CHENA; 3341 3342 /* 3343 * We are not always able to meet the timing 3344 * requirements of the USB interrupt endpoint's 3345 * complete split token, when doing transfers going 3346 * via a transaction translator. Use the CONTROL 3347 * transfer type instead of the INTERRUPT transfer 3348 * type in general, as a means to workaround 3349 * that. This trick should work for both FULL and LOW 3350 * speed USB traffic going through a TT. For non-TT 3351 * traffic it works as well. The reason for using 3352 * CONTROL type instead of BULK is that some TTs might 3353 * reject LOW speed BULK traffic. 3354 */ 3355 if (td->ep_type == UE_INTERRUPT) 3356 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3357 else 3358 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3359 3360 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3361 hcchar |= HCCHAR_EPDIR_IN; 3362 3363 switch (xfer->xroot->udev->speed) { 3364 case USB_SPEED_LOW: 3365 hcchar |= HCCHAR_LSPDDEV; 3366 /* FALLTHROUGH */ 3367 case USB_SPEED_FULL: 3368 /* check if root HUB port is running High Speed */ 3369 if (dwc_otg_uses_split(xfer->xroot->udev)) { 3370 hcsplt = HCSPLT_SPLTENA | 3371 (xfer->xroot->udev->hs_port_no << 3372 HCSPLT_PRTADDR_SHIFT) | 3373 (xfer->xroot->udev->hs_hub_addr << 3374 HCSPLT_HUBADDR_SHIFT); 3375 } else { 3376 hcsplt = 0; 3377 } 3378 if (td->ep_type == UE_INTERRUPT) { 3379 uint32_t ival; 3380 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3381 if (ival == 0) 3382 ival = 1; 3383 else if (ival > 127) 3384 ival = 127; 3385 td->tmr_val = sc->sc_tmr_val + ival; 3386 td->tmr_res = ival; 3387 } else if (td->ep_type == UE_ISOCHRONOUS) { 3388 td->tmr_res = 1; 3389 td->tmr_val = sc->sc_last_frame_num; 3390 if (td->hcchar & HCCHAR_EPDIR_IN) 3391 td->tmr_val++; 3392 } else { 3393 td->tmr_val = 0; 3394 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3395 } 3396 break; 3397 case USB_SPEED_HIGH: 3398 hcsplt = 0; 3399 if (td->ep_type == UE_INTERRUPT) { 3400 uint32_t ival; 3401 hcchar |= ((xfer->max_packet_count & 3) 3402 << HCCHAR_MC_SHIFT); 3403 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3404 if (ival == 0) 3405 ival = 1; 3406 else if (ival > 127) 3407 ival = 127; 3408 td->tmr_val = sc->sc_tmr_val + ival; 3409 td->tmr_res = ival; 3410 } else if (td->ep_type == UE_ISOCHRONOUS) { 3411 hcchar |= ((xfer->max_packet_count & 3) 3412 << HCCHAR_MC_SHIFT); 3413 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3414 td->tmr_val = sc->sc_last_frame_num; 3415 if (td->hcchar & HCCHAR_EPDIR_IN) 3416 td->tmr_val += td->tmr_res; 3417 3418 } else { 3419 td->tmr_val = 0; 3420 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3421 } 3422 break; 3423 default: 3424 hcsplt = 0; 3425 td->tmr_val = 0; 3426 td->tmr_res = 0; 3427 break; 3428 } 3429 3430 /* store configuration in all TD's */ 3431 while (1) { 3432 td->hcchar = hcchar; 3433 td->hcsplt = hcsplt; 3434 3435 if (((void *)td) == xfer->td_transfer_last) 3436 break; 3437 3438 td = td->obj_next; 3439 } 3440 } 3441 } 3442 3443 static void 3444 dwc_otg_timeout(void *arg) 3445 { 3446 struct usb_xfer *xfer = arg; 3447 3448 DPRINTF("xfer=%p\n", xfer); 3449 3450 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3451 3452 /* transfer is transferred */ 3453 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3454 } 3455 3456 static void 3457 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3458 { 3459 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3460 3461 DPRINTFN(9, "\n"); 3462 3463 /* 3464 * Poll one time in device mode, which will turn on the 3465 * endpoint interrupts. Else wait for SOF interrupt in host 3466 * mode. 3467 */ 3468 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3469 3470 if (sc->sc_flags.status_device_mode != 0) { 3471 dwc_otg_xfer_do_fifo(sc, xfer); 3472 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3473 goto done; 3474 } else { 3475 struct dwc_otg_td *td = xfer->td_transfer_cache; 3476 if (td->ep_type == UE_ISOCHRONOUS && 3477 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3478 /* 3479 * Need to start ISOCHRONOUS OUT transfer ASAP 3480 * because execution is delayed by one 125us 3481 * microframe: 3482 */ 3483 dwc_otg_xfer_do_fifo(sc, xfer); 3484 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3485 goto done; 3486 } 3487 } 3488 3489 /* put transfer on interrupt queue */ 3490 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3491 3492 /* start timeout, if any */ 3493 if (xfer->timeout != 0) { 3494 usbd_transfer_timeout_ms(xfer, 3495 &dwc_otg_timeout, xfer->timeout); 3496 } 3497 3498 if (sc->sc_flags.status_device_mode != 0) 3499 goto done; 3500 3501 /* enable SOF interrupt, if any */ 3502 dwc_otg_enable_sof_irq(sc); 3503 done: 3504 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3505 } 3506 3507 static void 3508 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3509 { 3510 DPRINTFN(9, "\n"); 3511 3512 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3513 3514 /* set port bit */ 3515 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3516 3517 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3518 sizeof(sc->sc_hub_idata)); 3519 } 3520 3521 static usb_error_t 3522 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3523 { 3524 struct dwc_otg_td *td; 3525 uint32_t len; 3526 usb_error_t error; 3527 3528 DPRINTFN(9, "\n"); 3529 3530 td = xfer->td_transfer_cache; 3531 3532 do { 3533 len = td->remainder; 3534 3535 /* store last data toggle */ 3536 xfer->endpoint->toggle_next = td->toggle; 3537 3538 if (xfer->aframes != xfer->nframes) { 3539 /* 3540 * Verify the length and subtract 3541 * the remainder from "frlengths[]": 3542 */ 3543 if (len > xfer->frlengths[xfer->aframes]) { 3544 td->error_any = 1; 3545 } else { 3546 xfer->frlengths[xfer->aframes] -= len; 3547 } 3548 } 3549 /* Check for transfer error */ 3550 if (td->error_any) { 3551 /* the transfer is finished */ 3552 error = (td->error_stall ? 3553 USB_ERR_STALLED : USB_ERR_IOERROR); 3554 td = NULL; 3555 break; 3556 } 3557 /* Check for short transfer */ 3558 if (len > 0) { 3559 if (xfer->flags_int.short_frames_ok || 3560 xfer->flags_int.isochronous_xfr) { 3561 /* follow alt next */ 3562 if (td->alt_next) { 3563 td = td->obj_next; 3564 } else { 3565 td = NULL; 3566 } 3567 } else { 3568 /* the transfer is finished */ 3569 td = NULL; 3570 } 3571 error = 0; 3572 break; 3573 } 3574 td = td->obj_next; 3575 3576 /* this USB frame is complete */ 3577 error = 0; 3578 break; 3579 3580 } while (0); 3581 3582 /* update transfer cache */ 3583 3584 xfer->td_transfer_cache = td; 3585 3586 return (error); 3587 } 3588 3589 static void 3590 dwc_otg_standard_done(struct usb_xfer *xfer) 3591 { 3592 usb_error_t err = 0; 3593 3594 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3595 xfer, xfer->endpoint); 3596 3597 /* reset scanner */ 3598 3599 xfer->td_transfer_cache = xfer->td_transfer_first; 3600 3601 if (xfer->flags_int.control_xfr) { 3602 3603 if (xfer->flags_int.control_hdr) { 3604 3605 err = dwc_otg_standard_done_sub(xfer); 3606 } 3607 xfer->aframes = 1; 3608 3609 if (xfer->td_transfer_cache == NULL) { 3610 goto done; 3611 } 3612 } 3613 while (xfer->aframes != xfer->nframes) { 3614 3615 err = dwc_otg_standard_done_sub(xfer); 3616 xfer->aframes++; 3617 3618 if (xfer->td_transfer_cache == NULL) { 3619 goto done; 3620 } 3621 } 3622 3623 if (xfer->flags_int.control_xfr && 3624 !xfer->flags_int.control_act) { 3625 3626 err = dwc_otg_standard_done_sub(xfer); 3627 } 3628 done: 3629 dwc_otg_device_done(xfer, err); 3630 } 3631 3632 /*------------------------------------------------------------------------* 3633 * dwc_otg_device_done 3634 * 3635 * NOTE: this function can be called more than one time on the 3636 * same USB transfer! 3637 *------------------------------------------------------------------------*/ 3638 static void 3639 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3640 { 3641 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3642 3643 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3644 xfer, xfer->endpoint, error); 3645 3646 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3647 3648 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3649 /* Interrupts are cleared by the interrupt handler */ 3650 } else { 3651 struct dwc_otg_td *td; 3652 3653 td = xfer->td_transfer_cache; 3654 if (td != NULL) 3655 dwc_otg_host_channel_free(sc, td); 3656 } 3657 /* dequeue transfer and start next transfer */ 3658 usbd_transfer_done(xfer, error); 3659 3660 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3661 } 3662 3663 static void 3664 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3665 { 3666 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3667 } 3668 3669 static void 3670 dwc_otg_set_stall(struct usb_device *udev, 3671 struct usb_endpoint *ep, uint8_t *did_stall) 3672 { 3673 struct dwc_otg_softc *sc; 3674 uint32_t temp; 3675 uint32_t reg; 3676 uint8_t ep_no; 3677 3678 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3679 3680 /* check mode */ 3681 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3682 /* not supported */ 3683 return; 3684 } 3685 3686 sc = DWC_OTG_BUS2SC(udev->bus); 3687 3688 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3689 3690 /* get endpoint address */ 3691 ep_no = ep->edesc->bEndpointAddress; 3692 3693 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3694 3695 if (ep_no & UE_DIR_IN) { 3696 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3697 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3698 } else { 3699 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3700 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3701 } 3702 3703 /* disable and stall endpoint */ 3704 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3705 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3706 3707 /* clear active OUT ep */ 3708 if (!(ep_no & UE_DIR_IN)) { 3709 3710 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3711 3712 if (sc->sc_last_rx_status != 0 && 3713 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3714 sc->sc_last_rx_status)) { 3715 /* dump data */ 3716 dwc_otg_common_rx_ack(sc); 3717 /* poll interrupt */ 3718 dwc_otg_interrupt_poll_locked(sc); 3719 dwc_otg_interrupt_complete_locked(sc); 3720 } 3721 } 3722 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3723 } 3724 3725 static void 3726 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3727 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3728 { 3729 uint32_t reg; 3730 uint32_t temp; 3731 3732 if (ep_type == UE_CONTROL) { 3733 /* clearing stall is not needed */ 3734 return; 3735 } 3736 3737 if (ep_dir) { 3738 reg = DOTG_DIEPCTL(ep_no); 3739 } else { 3740 reg = DOTG_DOEPCTL(ep_no); 3741 sc->sc_active_rx_ep |= (1U << ep_no); 3742 } 3743 3744 /* round up and mask away the multiplier count */ 3745 mps = (mps + 3) & 0x7FC; 3746 3747 if (ep_type == UE_BULK) { 3748 temp = DIEPCTL_EPTYPE_SET( 3749 DIEPCTL_EPTYPE_BULK) | 3750 DIEPCTL_USBACTEP; 3751 } else if (ep_type == UE_INTERRUPT) { 3752 temp = DIEPCTL_EPTYPE_SET( 3753 DIEPCTL_EPTYPE_INTERRUPT) | 3754 DIEPCTL_USBACTEP; 3755 } else { 3756 temp = DIEPCTL_EPTYPE_SET( 3757 DIEPCTL_EPTYPE_ISOC) | 3758 DIEPCTL_USBACTEP; 3759 } 3760 3761 temp |= DIEPCTL_MPS_SET(mps); 3762 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3763 3764 if (ep_dir) 3765 sc->sc_in_ctl[ep_no] = temp; 3766 else 3767 sc->sc_out_ctl[ep_no] = temp; 3768 3769 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3770 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3771 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3772 3773 /* we only reset the transmit FIFO */ 3774 if (ep_dir) { 3775 dwc_otg_tx_fifo_reset(sc, 3776 GRSTCTL_TXFIFO(ep_no) | 3777 GRSTCTL_TXFFLSH); 3778 3779 DWC_OTG_WRITE_4(sc, 3780 DOTG_DIEPTSIZ(ep_no), 0); 3781 } 3782 3783 /* poll interrupt */ 3784 dwc_otg_interrupt_poll_locked(sc); 3785 dwc_otg_interrupt_complete_locked(sc); 3786 } 3787 3788 static void 3789 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3790 { 3791 struct dwc_otg_softc *sc; 3792 struct usb_endpoint_descriptor *ed; 3793 3794 DPRINTFN(5, "endpoint=%p\n", ep); 3795 3796 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3797 3798 /* check mode */ 3799 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3800 /* not supported */ 3801 return; 3802 } 3803 /* get softc */ 3804 sc = DWC_OTG_BUS2SC(udev->bus); 3805 3806 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3807 3808 /* get endpoint descriptor */ 3809 ed = ep->edesc; 3810 3811 /* reset endpoint */ 3812 dwc_otg_clear_stall_sub_locked(sc, 3813 UGETW(ed->wMaxPacketSize), 3814 (ed->bEndpointAddress & UE_ADDR), 3815 (ed->bmAttributes & UE_XFERTYPE), 3816 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3817 3818 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3819 } 3820 3821 static void 3822 dwc_otg_device_state_change(struct usb_device *udev) 3823 { 3824 struct dwc_otg_softc *sc; 3825 uint8_t x; 3826 3827 /* check mode */ 3828 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3829 /* not supported */ 3830 return; 3831 } 3832 3833 /* get softc */ 3834 sc = DWC_OTG_BUS2SC(udev->bus); 3835 3836 /* deactivate all other endpoint but the control endpoint */ 3837 if (udev->state == USB_STATE_CONFIGURED || 3838 udev->state == USB_STATE_ADDRESSED) { 3839 3840 USB_BUS_LOCK(&sc->sc_bus); 3841 3842 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3843 3844 if (x < sc->sc_dev_in_ep_max) { 3845 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3846 DIEPCTL_EPDIS); 3847 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3848 } 3849 3850 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3851 DOEPCTL_EPDIS); 3852 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3853 } 3854 USB_BUS_UNLOCK(&sc->sc_bus); 3855 } 3856 } 3857 3858 int 3859 dwc_otg_init(struct dwc_otg_softc *sc) 3860 { 3861 uint32_t temp; 3862 3863 DPRINTF("start\n"); 3864 3865 /* set up the bus structure */ 3866 sc->sc_bus.usbrev = USB_REV_2_0; 3867 sc->sc_bus.methods = &dwc_otg_bus_methods; 3868 3869 usb_callout_init_mtx(&sc->sc_timer, 3870 &sc->sc_bus.bus_mtx, 0); 3871 3872 USB_BUS_LOCK(&sc->sc_bus); 3873 3874 /* turn on clocks */ 3875 dwc_otg_clocks_on(sc); 3876 3877 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3878 DPRINTF("Version = 0x%08x\n", temp); 3879 3880 /* disconnect */ 3881 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3882 DCTL_SFTDISCON); 3883 3884 /* wait for host to detect disconnect */ 3885 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3886 3887 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3888 GRSTCTL_CSFTRST); 3889 3890 /* wait a little bit for block to reset */ 3891 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3892 3893 switch (sc->sc_mode) { 3894 case DWC_MODE_DEVICE: 3895 temp = GUSBCFG_FORCEDEVMODE; 3896 break; 3897 case DWC_MODE_HOST: 3898 temp = GUSBCFG_FORCEHOSTMODE; 3899 break; 3900 default: 3901 temp = 0; 3902 break; 3903 } 3904 3905 if (sc->sc_phy_type == 0) 3906 sc->sc_phy_type = dwc_otg_phy_type + 1; 3907 if (sc->sc_phy_bits == 0) 3908 sc->sc_phy_bits = 16; 3909 3910 /* select HSIC, ULPI, UTMI+ or internal PHY mode */ 3911 switch (sc->sc_phy_type) { 3912 case DWC_OTG_PHY_HSIC: 3913 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3914 GUSBCFG_PHYIF | 3915 GUSBCFG_TRD_TIM_SET(5) | temp); 3916 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3917 0x000000EC); 3918 3919 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3920 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3921 temp & ~GLPMCFG_HSIC_CONN); 3922 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3923 temp | GLPMCFG_HSIC_CONN); 3924 break; 3925 case DWC_OTG_PHY_ULPI: 3926 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3927 GUSBCFG_ULPI_UTMI_SEL | 3928 GUSBCFG_TRD_TIM_SET(5) | temp); 3929 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3930 3931 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3932 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3933 temp & ~GLPMCFG_HSIC_CONN); 3934 break; 3935 case DWC_OTG_PHY_UTMI: 3936 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3937 (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) | 3938 GUSBCFG_TRD_TIM_SET(5) | temp); 3939 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3940 3941 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3942 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3943 temp & ~GLPMCFG_HSIC_CONN); 3944 break; 3945 case DWC_OTG_PHY_INTERNAL: 3946 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3947 GUSBCFG_PHYSEL | 3948 GUSBCFG_TRD_TIM_SET(5) | temp); 3949 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3950 3951 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3952 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3953 temp & ~GLPMCFG_HSIC_CONN); 3954 3955 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3956 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3957 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3958 DOTG_GGPIO_PWRDWN); 3959 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3960 break; 3961 default: 3962 break; 3963 } 3964 3965 /* clear global nak */ 3966 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3967 DCTL_CGOUTNAK | 3968 DCTL_CGNPINNAK); 3969 3970 /* disable USB port */ 3971 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3972 3973 /* wait 10ms */ 3974 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3975 3976 /* enable USB port */ 3977 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3978 3979 /* wait 10ms */ 3980 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3981 3982 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3983 3984 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3985 3986 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3987 3988 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3989 3990 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3991 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3992 3993 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3994 3995 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3996 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3997 3998 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3999 4000 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 4001 4002 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 4003 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 4004 sc->sc_host_ch_max); 4005 4006 /* setup FIFO */ 4007 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 4008 USB_BUS_UNLOCK(&sc->sc_bus); 4009 return (EINVAL); 4010 } 4011 4012 /* enable interrupts */ 4013 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; 4014 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 4015 4016 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 4017 4018 /* enable all endpoint interrupts */ 4019 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 4020 if (temp & GHWCFG2_MPI) { 4021 uint8_t x; 4022 4023 DPRINTF("Disable Multi Process Interrupts\n"); 4024 4025 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 4026 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 4027 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 4028 } 4029 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 4030 } 4031 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 4032 DIEPMSK_XFERCOMPLMSK); 4033 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 4034 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 4035 } 4036 4037 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 4038 /* setup clocks */ 4039 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 4040 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 4041 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 4042 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4043 } 4044 4045 /* only enable global IRQ */ 4046 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4047 GAHBCFG_GLBLINTRMSK); 4048 4049 /* turn off clocks */ 4050 dwc_otg_clocks_off(sc); 4051 4052 /* read initial VBUS state */ 4053 4054 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4055 4056 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4057 4058 dwc_otg_vbus_interrupt(sc, 4059 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4060 4061 USB_BUS_UNLOCK(&sc->sc_bus); 4062 4063 /* catch any lost interrupts */ 4064 4065 dwc_otg_do_poll(&sc->sc_bus); 4066 4067 return (0); /* success */ 4068 } 4069 4070 void 4071 dwc_otg_uninit(struct dwc_otg_softc *sc) 4072 { 4073 USB_BUS_LOCK(&sc->sc_bus); 4074 4075 /* stop host timer */ 4076 dwc_otg_timer_stop(sc); 4077 4078 /* set disconnect */ 4079 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4080 DCTL_SFTDISCON); 4081 4082 /* turn off global IRQ */ 4083 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4084 4085 sc->sc_flags.port_enabled = 0; 4086 sc->sc_flags.port_powered = 0; 4087 sc->sc_flags.status_vbus = 0; 4088 sc->sc_flags.status_bus_reset = 0; 4089 sc->sc_flags.status_suspend = 0; 4090 sc->sc_flags.change_suspend = 0; 4091 sc->sc_flags.change_connect = 1; 4092 4093 dwc_otg_pull_down(sc); 4094 dwc_otg_clocks_off(sc); 4095 4096 USB_BUS_UNLOCK(&sc->sc_bus); 4097 4098 usb_callout_drain(&sc->sc_timer); 4099 } 4100 4101 static void 4102 dwc_otg_suspend(struct dwc_otg_softc *sc) 4103 { 4104 return; 4105 } 4106 4107 static void 4108 dwc_otg_resume(struct dwc_otg_softc *sc) 4109 { 4110 return; 4111 } 4112 4113 static void 4114 dwc_otg_do_poll(struct usb_bus *bus) 4115 { 4116 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4117 4118 USB_BUS_LOCK(&sc->sc_bus); 4119 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4120 dwc_otg_interrupt_poll_locked(sc); 4121 dwc_otg_interrupt_complete_locked(sc); 4122 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4123 USB_BUS_UNLOCK(&sc->sc_bus); 4124 } 4125 4126 /*------------------------------------------------------------------------* 4127 * DWC OTG bulk support 4128 * DWC OTG control support 4129 * DWC OTG interrupt support 4130 *------------------------------------------------------------------------*/ 4131 static void 4132 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4133 { 4134 } 4135 4136 static void 4137 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4138 { 4139 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4140 } 4141 4142 static void 4143 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4144 { 4145 } 4146 4147 static void 4148 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4149 { 4150 /* setup TDs */ 4151 dwc_otg_setup_standard_chain(xfer); 4152 dwc_otg_start_standard_chain(xfer); 4153 } 4154 4155 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4156 { 4157 .open = dwc_otg_device_non_isoc_open, 4158 .close = dwc_otg_device_non_isoc_close, 4159 .enter = dwc_otg_device_non_isoc_enter, 4160 .start = dwc_otg_device_non_isoc_start, 4161 }; 4162 4163 /*------------------------------------------------------------------------* 4164 * DWC OTG full speed isochronous support 4165 *------------------------------------------------------------------------*/ 4166 static void 4167 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4168 { 4169 } 4170 4171 static void 4172 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4173 { 4174 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4175 } 4176 4177 static void 4178 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4179 { 4180 } 4181 4182 static void 4183 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4184 { 4185 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4186 uint32_t temp; 4187 uint32_t msframes; 4188 uint32_t framenum; 4189 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4190 4191 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4192 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4193 4194 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4195 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4196 4197 /* get the current frame index */ 4198 framenum = (temp & HFNUM_FRNUM_MASK); 4199 } else { 4200 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4201 4202 /* get the current frame index */ 4203 framenum = DSTS_SOFFN_GET(temp); 4204 } 4205 4206 /* 4207 * Check if port is doing 8000 or 1000 frames per second: 4208 */ 4209 if (sc->sc_flags.status_high_speed) 4210 framenum /= 8; 4211 4212 framenum &= DWC_OTG_FRAME_MASK; 4213 4214 /* 4215 * Compute number of milliseconds worth of data traffic for 4216 * this USB transfer: 4217 */ 4218 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4219 msframes = ((xfer->nframes << shift) + 7) / 8; 4220 else 4221 msframes = xfer->nframes; 4222 4223 /* 4224 * check if the frame index is within the window where the frames 4225 * will be inserted 4226 */ 4227 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4228 4229 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4230 /* 4231 * If there is data underflow or the pipe queue is 4232 * empty we schedule the transfer a few frames ahead 4233 * of the current frame position. Else two isochronous 4234 * transfers might overlap. 4235 */ 4236 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4237 xfer->endpoint->is_synced = 1; 4238 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4239 } 4240 /* 4241 * compute how many milliseconds the insertion is ahead of the 4242 * current frame position: 4243 */ 4244 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4245 4246 /* 4247 * pre-compute when the isochronous transfer will be finished: 4248 */ 4249 xfer->isoc_time_complete = 4250 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4251 4252 /* setup TDs */ 4253 dwc_otg_setup_standard_chain(xfer); 4254 4255 /* compute frame number for next insertion */ 4256 xfer->endpoint->isoc_next += msframes; 4257 4258 /* start TD chain */ 4259 dwc_otg_start_standard_chain(xfer); 4260 } 4261 4262 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4263 { 4264 .open = dwc_otg_device_isoc_open, 4265 .close = dwc_otg_device_isoc_close, 4266 .enter = dwc_otg_device_isoc_enter, 4267 .start = dwc_otg_device_isoc_start, 4268 }; 4269 4270 /*------------------------------------------------------------------------* 4271 * DWC OTG root control support 4272 *------------------------------------------------------------------------* 4273 * Simulate a hardware HUB by handling all the necessary requests. 4274 *------------------------------------------------------------------------*/ 4275 4276 static const struct usb_device_descriptor dwc_otg_devd = { 4277 .bLength = sizeof(struct usb_device_descriptor), 4278 .bDescriptorType = UDESC_DEVICE, 4279 .bcdUSB = {0x00, 0x02}, 4280 .bDeviceClass = UDCLASS_HUB, 4281 .bDeviceSubClass = UDSUBCLASS_HUB, 4282 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4283 .bMaxPacketSize = 64, 4284 .bcdDevice = {0x00, 0x01}, 4285 .iManufacturer = 1, 4286 .iProduct = 2, 4287 .bNumConfigurations = 1, 4288 }; 4289 4290 static const struct dwc_otg_config_desc dwc_otg_confd = { 4291 .confd = { 4292 .bLength = sizeof(struct usb_config_descriptor), 4293 .bDescriptorType = UDESC_CONFIG, 4294 .wTotalLength[0] = sizeof(dwc_otg_confd), 4295 .bNumInterface = 1, 4296 .bConfigurationValue = 1, 4297 .iConfiguration = 0, 4298 .bmAttributes = UC_SELF_POWERED, 4299 .bMaxPower = 0, 4300 }, 4301 .ifcd = { 4302 .bLength = sizeof(struct usb_interface_descriptor), 4303 .bDescriptorType = UDESC_INTERFACE, 4304 .bNumEndpoints = 1, 4305 .bInterfaceClass = UICLASS_HUB, 4306 .bInterfaceSubClass = UISUBCLASS_HUB, 4307 .bInterfaceProtocol = 0, 4308 }, 4309 .endpd = { 4310 .bLength = sizeof(struct usb_endpoint_descriptor), 4311 .bDescriptorType = UDESC_ENDPOINT, 4312 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4313 .bmAttributes = UE_INTERRUPT, 4314 .wMaxPacketSize[0] = 8, 4315 .bInterval = 255, 4316 }, 4317 }; 4318 4319 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4320 4321 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4322 .bDescLength = sizeof(dwc_otg_hubd), 4323 .bDescriptorType = UDESC_HUB, 4324 .bNbrPorts = 1, 4325 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4326 .bPwrOn2PwrGood = 50, 4327 .bHubContrCurrent = 0, 4328 .DeviceRemovable = {0}, /* port is removable */ 4329 }; 4330 4331 #define STRING_VENDOR \ 4332 "D\0W\0C\0O\0T\0G" 4333 4334 #define STRING_PRODUCT \ 4335 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4336 4337 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4338 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4339 4340 static usb_error_t 4341 dwc_otg_roothub_exec(struct usb_device *udev, 4342 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4343 { 4344 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4345 const void *ptr; 4346 uint16_t len; 4347 uint16_t value; 4348 uint16_t index; 4349 usb_error_t err; 4350 4351 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4352 4353 /* buffer reset */ 4354 ptr = (const void *)&sc->sc_hub_temp; 4355 len = 0; 4356 err = 0; 4357 4358 value = UGETW(req->wValue); 4359 index = UGETW(req->wIndex); 4360 4361 /* demultiplex the control request */ 4362 4363 switch (req->bmRequestType) { 4364 case UT_READ_DEVICE: 4365 switch (req->bRequest) { 4366 case UR_GET_DESCRIPTOR: 4367 goto tr_handle_get_descriptor; 4368 case UR_GET_CONFIG: 4369 goto tr_handle_get_config; 4370 case UR_GET_STATUS: 4371 goto tr_handle_get_status; 4372 default: 4373 goto tr_stalled; 4374 } 4375 break; 4376 4377 case UT_WRITE_DEVICE: 4378 switch (req->bRequest) { 4379 case UR_SET_ADDRESS: 4380 goto tr_handle_set_address; 4381 case UR_SET_CONFIG: 4382 goto tr_handle_set_config; 4383 case UR_CLEAR_FEATURE: 4384 goto tr_valid; /* nop */ 4385 case UR_SET_DESCRIPTOR: 4386 goto tr_valid; /* nop */ 4387 case UR_SET_FEATURE: 4388 default: 4389 goto tr_stalled; 4390 } 4391 break; 4392 4393 case UT_WRITE_ENDPOINT: 4394 switch (req->bRequest) { 4395 case UR_CLEAR_FEATURE: 4396 switch (UGETW(req->wValue)) { 4397 case UF_ENDPOINT_HALT: 4398 goto tr_handle_clear_halt; 4399 case UF_DEVICE_REMOTE_WAKEUP: 4400 goto tr_handle_clear_wakeup; 4401 default: 4402 goto tr_stalled; 4403 } 4404 break; 4405 case UR_SET_FEATURE: 4406 switch (UGETW(req->wValue)) { 4407 case UF_ENDPOINT_HALT: 4408 goto tr_handle_set_halt; 4409 case UF_DEVICE_REMOTE_WAKEUP: 4410 goto tr_handle_set_wakeup; 4411 default: 4412 goto tr_stalled; 4413 } 4414 break; 4415 case UR_SYNCH_FRAME: 4416 goto tr_valid; /* nop */ 4417 default: 4418 goto tr_stalled; 4419 } 4420 break; 4421 4422 case UT_READ_ENDPOINT: 4423 switch (req->bRequest) { 4424 case UR_GET_STATUS: 4425 goto tr_handle_get_ep_status; 4426 default: 4427 goto tr_stalled; 4428 } 4429 break; 4430 4431 case UT_WRITE_INTERFACE: 4432 switch (req->bRequest) { 4433 case UR_SET_INTERFACE: 4434 goto tr_handle_set_interface; 4435 case UR_CLEAR_FEATURE: 4436 goto tr_valid; /* nop */ 4437 case UR_SET_FEATURE: 4438 default: 4439 goto tr_stalled; 4440 } 4441 break; 4442 4443 case UT_READ_INTERFACE: 4444 switch (req->bRequest) { 4445 case UR_GET_INTERFACE: 4446 goto tr_handle_get_interface; 4447 case UR_GET_STATUS: 4448 goto tr_handle_get_iface_status; 4449 default: 4450 goto tr_stalled; 4451 } 4452 break; 4453 4454 case UT_WRITE_CLASS_INTERFACE: 4455 case UT_WRITE_VENDOR_INTERFACE: 4456 /* XXX forward */ 4457 break; 4458 4459 case UT_READ_CLASS_INTERFACE: 4460 case UT_READ_VENDOR_INTERFACE: 4461 /* XXX forward */ 4462 break; 4463 4464 case UT_WRITE_CLASS_DEVICE: 4465 switch (req->bRequest) { 4466 case UR_CLEAR_FEATURE: 4467 goto tr_valid; 4468 case UR_SET_DESCRIPTOR: 4469 case UR_SET_FEATURE: 4470 break; 4471 default: 4472 goto tr_stalled; 4473 } 4474 break; 4475 4476 case UT_WRITE_CLASS_OTHER: 4477 switch (req->bRequest) { 4478 case UR_CLEAR_FEATURE: 4479 goto tr_handle_clear_port_feature; 4480 case UR_SET_FEATURE: 4481 goto tr_handle_set_port_feature; 4482 case UR_CLEAR_TT_BUFFER: 4483 case UR_RESET_TT: 4484 case UR_STOP_TT: 4485 goto tr_valid; 4486 4487 default: 4488 goto tr_stalled; 4489 } 4490 break; 4491 4492 case UT_READ_CLASS_OTHER: 4493 switch (req->bRequest) { 4494 case UR_GET_TT_STATE: 4495 goto tr_handle_get_tt_state; 4496 case UR_GET_STATUS: 4497 goto tr_handle_get_port_status; 4498 default: 4499 goto tr_stalled; 4500 } 4501 break; 4502 4503 case UT_READ_CLASS_DEVICE: 4504 switch (req->bRequest) { 4505 case UR_GET_DESCRIPTOR: 4506 goto tr_handle_get_class_descriptor; 4507 case UR_GET_STATUS: 4508 goto tr_handle_get_class_status; 4509 4510 default: 4511 goto tr_stalled; 4512 } 4513 break; 4514 default: 4515 goto tr_stalled; 4516 } 4517 goto tr_valid; 4518 4519 tr_handle_get_descriptor: 4520 switch (value >> 8) { 4521 case UDESC_DEVICE: 4522 if (value & 0xff) { 4523 goto tr_stalled; 4524 } 4525 len = sizeof(dwc_otg_devd); 4526 ptr = (const void *)&dwc_otg_devd; 4527 goto tr_valid; 4528 case UDESC_CONFIG: 4529 if (value & 0xff) { 4530 goto tr_stalled; 4531 } 4532 len = sizeof(dwc_otg_confd); 4533 ptr = (const void *)&dwc_otg_confd; 4534 goto tr_valid; 4535 case UDESC_STRING: 4536 switch (value & 0xff) { 4537 case 0: /* Language table */ 4538 len = sizeof(usb_string_lang_en); 4539 ptr = (const void *)&usb_string_lang_en; 4540 goto tr_valid; 4541 4542 case 1: /* Vendor */ 4543 len = sizeof(dwc_otg_vendor); 4544 ptr = (const void *)&dwc_otg_vendor; 4545 goto tr_valid; 4546 4547 case 2: /* Product */ 4548 len = sizeof(dwc_otg_product); 4549 ptr = (const void *)&dwc_otg_product; 4550 goto tr_valid; 4551 default: 4552 break; 4553 } 4554 break; 4555 default: 4556 goto tr_stalled; 4557 } 4558 goto tr_stalled; 4559 4560 tr_handle_get_config: 4561 len = 1; 4562 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4563 goto tr_valid; 4564 4565 tr_handle_get_status: 4566 len = 2; 4567 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4568 goto tr_valid; 4569 4570 tr_handle_set_address: 4571 if (value & 0xFF00) { 4572 goto tr_stalled; 4573 } 4574 sc->sc_rt_addr = value; 4575 goto tr_valid; 4576 4577 tr_handle_set_config: 4578 if (value >= 2) { 4579 goto tr_stalled; 4580 } 4581 sc->sc_conf = value; 4582 goto tr_valid; 4583 4584 tr_handle_get_interface: 4585 len = 1; 4586 sc->sc_hub_temp.wValue[0] = 0; 4587 goto tr_valid; 4588 4589 tr_handle_get_tt_state: 4590 tr_handle_get_class_status: 4591 tr_handle_get_iface_status: 4592 tr_handle_get_ep_status: 4593 len = 2; 4594 USETW(sc->sc_hub_temp.wValue, 0); 4595 goto tr_valid; 4596 4597 tr_handle_set_halt: 4598 tr_handle_set_interface: 4599 tr_handle_set_wakeup: 4600 tr_handle_clear_wakeup: 4601 tr_handle_clear_halt: 4602 goto tr_valid; 4603 4604 tr_handle_clear_port_feature: 4605 if (index != 1) 4606 goto tr_stalled; 4607 4608 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4609 4610 switch (value) { 4611 case UHF_PORT_SUSPEND: 4612 dwc_otg_wakeup_peer(sc); 4613 break; 4614 4615 case UHF_PORT_ENABLE: 4616 if (sc->sc_flags.status_device_mode == 0) { 4617 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4618 sc->sc_hprt_val | HPRT_PRTENA); 4619 } 4620 sc->sc_flags.port_enabled = 0; 4621 break; 4622 4623 case UHF_C_PORT_RESET: 4624 sc->sc_flags.change_reset = 0; 4625 break; 4626 4627 case UHF_C_PORT_ENABLE: 4628 sc->sc_flags.change_enabled = 0; 4629 break; 4630 4631 case UHF_C_PORT_OVER_CURRENT: 4632 sc->sc_flags.change_over_current = 0; 4633 break; 4634 4635 case UHF_PORT_TEST: 4636 case UHF_PORT_INDICATOR: 4637 /* nops */ 4638 break; 4639 4640 case UHF_PORT_POWER: 4641 sc->sc_flags.port_powered = 0; 4642 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4643 sc->sc_hprt_val = 0; 4644 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4645 } 4646 dwc_otg_pull_down(sc); 4647 dwc_otg_clocks_off(sc); 4648 break; 4649 4650 case UHF_C_PORT_CONNECTION: 4651 /* clear connect change flag */ 4652 sc->sc_flags.change_connect = 0; 4653 break; 4654 4655 case UHF_C_PORT_SUSPEND: 4656 sc->sc_flags.change_suspend = 0; 4657 break; 4658 4659 default: 4660 err = USB_ERR_IOERROR; 4661 goto done; 4662 } 4663 goto tr_valid; 4664 4665 tr_handle_set_port_feature: 4666 if (index != 1) { 4667 goto tr_stalled; 4668 } 4669 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4670 4671 switch (value) { 4672 case UHF_PORT_ENABLE: 4673 break; 4674 4675 case UHF_PORT_SUSPEND: 4676 if (sc->sc_flags.status_device_mode == 0) { 4677 /* set suspend BIT */ 4678 sc->sc_hprt_val |= HPRT_PRTSUSP; 4679 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4680 4681 /* generate HUB suspend event */ 4682 dwc_otg_suspend_irq(sc); 4683 } 4684 break; 4685 4686 case UHF_PORT_RESET: 4687 if (sc->sc_flags.status_device_mode == 0) { 4688 4689 DPRINTF("PORT RESET\n"); 4690 4691 /* enable PORT reset */ 4692 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4693 4694 /* Wait 62.5ms for reset to complete */ 4695 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4696 4697 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4698 4699 /* Wait 62.5ms for reset to complete */ 4700 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4701 4702 /* reset FIFOs */ 4703 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4704 4705 sc->sc_flags.change_reset = 1; 4706 } else { 4707 err = USB_ERR_IOERROR; 4708 } 4709 break; 4710 4711 case UHF_PORT_TEST: 4712 case UHF_PORT_INDICATOR: 4713 /* nops */ 4714 break; 4715 case UHF_PORT_POWER: 4716 sc->sc_flags.port_powered = 1; 4717 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4718 sc->sc_hprt_val |= HPRT_PRTPWR; 4719 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4720 } 4721 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4722 /* pull up D+, if any */ 4723 dwc_otg_pull_up(sc); 4724 } 4725 break; 4726 default: 4727 err = USB_ERR_IOERROR; 4728 goto done; 4729 } 4730 goto tr_valid; 4731 4732 tr_handle_get_port_status: 4733 4734 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4735 4736 if (index != 1) 4737 goto tr_stalled; 4738 4739 if (sc->sc_flags.status_vbus) 4740 dwc_otg_clocks_on(sc); 4741 else 4742 dwc_otg_clocks_off(sc); 4743 4744 /* Select Device Side Mode */ 4745 4746 if (sc->sc_flags.status_device_mode) { 4747 value = UPS_PORT_MODE_DEVICE; 4748 dwc_otg_timer_stop(sc); 4749 } else { 4750 value = 0; 4751 dwc_otg_timer_start(sc); 4752 } 4753 4754 if (sc->sc_flags.status_high_speed) 4755 value |= UPS_HIGH_SPEED; 4756 else if (sc->sc_flags.status_low_speed) 4757 value |= UPS_LOW_SPEED; 4758 4759 if (sc->sc_flags.port_powered) 4760 value |= UPS_PORT_POWER; 4761 4762 if (sc->sc_flags.port_enabled) 4763 value |= UPS_PORT_ENABLED; 4764 4765 if (sc->sc_flags.port_over_current) 4766 value |= UPS_OVERCURRENT_INDICATOR; 4767 4768 if (sc->sc_flags.status_vbus && 4769 sc->sc_flags.status_bus_reset) 4770 value |= UPS_CURRENT_CONNECT_STATUS; 4771 4772 if (sc->sc_flags.status_suspend) 4773 value |= UPS_SUSPEND; 4774 4775 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4776 4777 value = 0; 4778 4779 if (sc->sc_flags.change_enabled) 4780 value |= UPS_C_PORT_ENABLED; 4781 if (sc->sc_flags.change_connect) 4782 value |= UPS_C_CONNECT_STATUS; 4783 if (sc->sc_flags.change_suspend) 4784 value |= UPS_C_SUSPEND; 4785 if (sc->sc_flags.change_reset) 4786 value |= UPS_C_PORT_RESET; 4787 if (sc->sc_flags.change_over_current) 4788 value |= UPS_C_OVERCURRENT_INDICATOR; 4789 4790 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4791 len = sizeof(sc->sc_hub_temp.ps); 4792 goto tr_valid; 4793 4794 tr_handle_get_class_descriptor: 4795 if (value & 0xFF) { 4796 goto tr_stalled; 4797 } 4798 ptr = (const void *)&dwc_otg_hubd; 4799 len = sizeof(dwc_otg_hubd); 4800 goto tr_valid; 4801 4802 tr_stalled: 4803 err = USB_ERR_STALLED; 4804 tr_valid: 4805 done: 4806 *plength = len; 4807 *pptr = ptr; 4808 return (err); 4809 } 4810 4811 static void 4812 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4813 { 4814 struct usb_xfer *xfer; 4815 void *last_obj; 4816 uint32_t ntd; 4817 uint32_t n; 4818 uint8_t ep_no; 4819 uint8_t ep_type; 4820 4821 xfer = parm->curr_xfer; 4822 4823 /* 4824 * NOTE: This driver does not use any of the parameters that 4825 * are computed from the following values. Just set some 4826 * reasonable dummies: 4827 */ 4828 parm->hc_max_packet_size = 0x500; 4829 parm->hc_max_packet_count = 3; 4830 parm->hc_max_frame_size = 3 * 0x500; 4831 4832 usbd_transfer_setup_sub(parm); 4833 4834 /* 4835 * compute maximum number of TDs 4836 */ 4837 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4838 4839 if (ep_type == UE_CONTROL) { 4840 4841 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4842 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4843 } else { 4844 4845 ntd = xfer->nframes + 1 /* SYNC */ ; 4846 } 4847 4848 /* 4849 * check if "usbd_transfer_setup_sub" set an error 4850 */ 4851 if (parm->err) 4852 return; 4853 4854 /* 4855 * allocate transfer descriptors 4856 */ 4857 last_obj = NULL; 4858 4859 ep_no = xfer->endpointno & UE_ADDR; 4860 4861 /* 4862 * Check for a valid endpoint profile in USB device mode: 4863 */ 4864 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4865 const struct usb_hw_ep_profile *pf; 4866 4867 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4868 4869 if (pf == NULL) { 4870 /* should not happen */ 4871 parm->err = USB_ERR_INVAL; 4872 return; 4873 } 4874 } 4875 4876 /* align data */ 4877 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4878 4879 for (n = 0; n != ntd; n++) { 4880 4881 struct dwc_otg_td *td; 4882 4883 if (parm->buf) { 4884 4885 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4886 4887 /* compute shared bandwidth resource index for TT */ 4888 if (dwc_otg_uses_split(parm->udev)) { 4889 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4890 td->tt_index = parm->udev->device_index; 4891 else 4892 td->tt_index = parm->udev->parent_hs_hub->device_index; 4893 } else { 4894 td->tt_index = parm->udev->device_index; 4895 } 4896 4897 /* init TD */ 4898 td->max_packet_size = xfer->max_packet_size; 4899 td->max_packet_count = xfer->max_packet_count; 4900 /* range check */ 4901 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4902 td->max_packet_count = 1; 4903 td->ep_no = ep_no; 4904 td->ep_type = ep_type; 4905 td->obj_next = last_obj; 4906 4907 last_obj = td; 4908 } 4909 parm->size[0] += sizeof(*td); 4910 } 4911 4912 xfer->td_start[0] = last_obj; 4913 } 4914 4915 static void 4916 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4917 { 4918 return; 4919 } 4920 4921 static void 4922 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4923 struct usb_endpoint *ep) 4924 { 4925 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4926 4927 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4928 ep, udev->address, 4929 edesc->bEndpointAddress, udev->flags.usb_mode, 4930 sc->sc_rt_addr, udev->device_index); 4931 4932 if (udev->device_index != sc->sc_rt_addr) { 4933 4934 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4935 if (udev->speed != USB_SPEED_FULL && 4936 udev->speed != USB_SPEED_HIGH) { 4937 /* not supported */ 4938 return; 4939 } 4940 } else { 4941 if (udev->speed == USB_SPEED_HIGH && 4942 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4943 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4944 /* not supported */ 4945 DPRINTFN(-1, "Non-isochronous high bandwidth " 4946 "endpoint not supported\n"); 4947 return; 4948 } 4949 } 4950 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4951 ep->methods = &dwc_otg_device_isoc_methods; 4952 else 4953 ep->methods = &dwc_otg_device_non_isoc_methods; 4954 } 4955 } 4956 4957 static void 4958 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4959 { 4960 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4961 4962 switch (state) { 4963 case USB_HW_POWER_SUSPEND: 4964 dwc_otg_suspend(sc); 4965 break; 4966 case USB_HW_POWER_SHUTDOWN: 4967 dwc_otg_uninit(sc); 4968 break; 4969 case USB_HW_POWER_RESUME: 4970 dwc_otg_resume(sc); 4971 break; 4972 default: 4973 break; 4974 } 4975 } 4976 4977 static void 4978 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4979 { 4980 /* DMA delay - wait until any use of memory is finished */ 4981 *pus = (2125); /* microseconds */ 4982 } 4983 4984 static void 4985 dwc_otg_device_resume(struct usb_device *udev) 4986 { 4987 DPRINTF("\n"); 4988 4989 /* poll all transfers again to restart resumed ones */ 4990 dwc_otg_do_poll(udev->bus); 4991 } 4992 4993 static void 4994 dwc_otg_device_suspend(struct usb_device *udev) 4995 { 4996 DPRINTF("\n"); 4997 } 4998 4999 static const struct usb_bus_methods dwc_otg_bus_methods = 5000 { 5001 .endpoint_init = &dwc_otg_ep_init, 5002 .xfer_setup = &dwc_otg_xfer_setup, 5003 .xfer_unsetup = &dwc_otg_xfer_unsetup, 5004 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 5005 .xfer_stall = &dwc_otg_xfer_stall, 5006 .set_stall = &dwc_otg_set_stall, 5007 .clear_stall = &dwc_otg_clear_stall, 5008 .roothub_exec = &dwc_otg_roothub_exec, 5009 .xfer_poll = &dwc_otg_do_poll, 5010 .device_state_change = &dwc_otg_device_state_change, 5011 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 5012 .get_dma_delay = &dwc_otg_get_dma_delay, 5013 .device_resume = &dwc_otg_device_resume, 5014 .device_suspend = &dwc_otg_device_suspend, 5015 }; 5016