1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * This file contains the driver for the DesignWare series USB 2.0 OTG 28 * Controller. This driver currently only supports the device mode of 29 * the USB hardware. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 85 #define DWC_OTG_BUS2SC(bus) \ 86 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 87 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 88 89 #define DWC_OTG_PC2SC(pc) \ 90 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 91 92 #define DWC_OTG_MSK_GINT_ENABLED \ 93 (DWC_OTG_MSK_GINT_ENUM_DONE | \ 94 DWC_OTG_MSK_GINT_USB_SUSPEND | \ 95 DWC_OTG_MSK_GINT_INEP | \ 96 DWC_OTG_MSK_GINT_RXFLVL | \ 97 DWC_OTG_MSK_GINT_SESSREQINT) 98 99 #define DWC_OTG_USE_HSIC 0 100 101 #ifdef USB_DEBUG 102 static int dwc_otg_debug = 0; 103 104 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 105 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 106 &dwc_otg_debug, 0, "DWC OTG debug level"); 107 #endif 108 109 #define DWC_OTG_INTR_ENDPT 1 110 111 /* prototypes */ 112 113 struct usb_bus_methods dwc_otg_bus_methods; 114 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 115 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods; 116 117 static dwc_otg_cmd_t dwc_otg_setup_rx; 118 static dwc_otg_cmd_t dwc_otg_data_rx; 119 static dwc_otg_cmd_t dwc_otg_data_tx; 120 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 121 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 122 static void dwc_otg_do_poll(struct usb_bus *); 123 static void dwc_otg_standard_done(struct usb_xfer *); 124 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 125 126 /* 127 * Here is a configuration that the chip supports. 128 */ 129 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 130 131 [0] = { 132 .max_in_frame_size = 64,/* fixed */ 133 .max_out_frame_size = 64, /* fixed */ 134 .is_simplex = 1, 135 .support_control = 1, 136 } 137 }; 138 139 static void 140 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 141 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 142 { 143 struct dwc_otg_softc *sc; 144 145 sc = DWC_OTG_BUS2SC(udev->bus); 146 147 if (ep_addr < sc->sc_dev_ep_max) 148 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 149 else 150 *ppf = NULL; 151 } 152 153 static int 154 dwc_otg_init_fifo(struct dwc_otg_softc *sc) 155 { 156 struct dwc_otg_profile *pf; 157 uint32_t fifo_size; 158 uint32_t fifo_regs; 159 uint32_t tx_start; 160 uint8_t x; 161 162 fifo_size = sc->sc_fifo_size; 163 164 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 165 166 if (fifo_size >= fifo_regs) 167 fifo_size -= fifo_regs; 168 else 169 fifo_size = 0; 170 171 /* split equally for IN and OUT */ 172 fifo_size /= 2; 173 174 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRXFSIZ, fifo_size / 4); 175 176 /* align to 4-bytes */ 177 fifo_size &= ~3; 178 179 tx_start = fifo_size; 180 181 if (fifo_size < 0x40) { 182 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 183 USB_BUS_UNLOCK(&sc->sc_bus); 184 return (EINVAL); 185 } 186 187 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4)); 188 fifo_size -= 0x40; 189 tx_start += 0x40; 190 191 /* setup control endpoint profile */ 192 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 193 194 for (x = 1; x != sc->sc_dev_ep_max; x++) { 195 196 pf = sc->sc_hw_ep_profile + x; 197 198 pf->usb.max_out_frame_size = 1024 * 3; 199 pf->usb.is_simplex = 0; /* assume duplex */ 200 pf->usb.support_bulk = 1; 201 pf->usb.support_interrupt = 1; 202 pf->usb.support_isochronous = 1; 203 pf->usb.support_out = 1; 204 205 if (x < sc->sc_dev_in_ep_max) { 206 uint32_t limit; 207 208 limit = (x == 1) ? DWC_OTG_MAX_TXN : 209 (DWC_OTG_MAX_TXN / 2); 210 211 if (fifo_size >= limit) { 212 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 213 ((limit / 4) << 16) | 214 (tx_start / 4)); 215 tx_start += limit; 216 fifo_size -= limit; 217 pf->usb.max_in_frame_size = 0x200; 218 pf->usb.support_in = 1; 219 pf->max_buffer = limit; 220 221 } else if (fifo_size >= 0x80) { 222 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 223 ((0x80 / 4) << 16) | (tx_start / 4)); 224 tx_start += 0x80; 225 fifo_size -= 0x80; 226 pf->usb.max_in_frame_size = 0x40; 227 pf->usb.support_in = 1; 228 229 } else { 230 pf->usb.is_simplex = 1; 231 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 232 (0x0 << 16) | (tx_start / 4)); 233 } 234 } else { 235 pf->usb.is_simplex = 1; 236 } 237 238 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 239 pf->usb.max_in_frame_size, 240 pf->usb.max_out_frame_size); 241 } 242 243 /* reset RX FIFO */ 244 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 245 DWC_OTG_MSK_GRSTCTL_RXFFLUSH); 246 247 /* reset all TX FIFOs */ 248 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 249 DWC_OTG_MSK_GRSTCTL_TXFIFO(0x10) | 250 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 251 252 return (0); 253 } 254 255 static void 256 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 257 { 258 if (sc->sc_flags.clocks_off && 259 sc->sc_flags.port_powered) { 260 261 DPRINTFN(5, "\n"); 262 263 /* TODO - platform specific */ 264 265 sc->sc_flags.clocks_off = 0; 266 } 267 } 268 269 static void 270 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 271 { 272 if (!sc->sc_flags.clocks_off) { 273 274 DPRINTFN(5, "\n"); 275 276 /* TODO - platform specific */ 277 278 sc->sc_flags.clocks_off = 1; 279 } 280 } 281 282 static void 283 dwc_otg_pull_up(struct dwc_otg_softc *sc) 284 { 285 uint32_t temp; 286 287 /* pullup D+, if possible */ 288 289 if (!sc->sc_flags.d_pulled_up && 290 sc->sc_flags.port_powered) { 291 sc->sc_flags.d_pulled_up = 1; 292 293 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 294 temp &= ~DWC_OTG_MSK_DCTL_SOFT_DISC; 295 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 296 } 297 } 298 299 static void 300 dwc_otg_pull_down(struct dwc_otg_softc *sc) 301 { 302 uint32_t temp; 303 304 /* pulldown D+, if possible */ 305 306 if (sc->sc_flags.d_pulled_up) { 307 sc->sc_flags.d_pulled_up = 0; 308 309 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 310 temp |= DWC_OTG_MSK_DCTL_SOFT_DISC; 311 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 312 } 313 } 314 315 static void 316 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 317 { 318 if (sc->sc_flags.status_suspend) { 319 /* update status bits */ 320 sc->sc_flags.status_suspend = 0; 321 sc->sc_flags.change_suspend = 1; 322 323 /* 324 * Disable resume interrupt and enable suspend 325 * interrupt: 326 */ 327 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT; 328 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND; 329 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 330 331 /* complete root HUB interrupt endpoint */ 332 dwc_otg_root_intr(sc); 333 } 334 } 335 336 static void 337 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 338 { 339 uint32_t temp; 340 341 if (!sc->sc_flags.status_suspend) 342 return; 343 344 DPRINTFN(5, "Remote wakeup\n"); 345 346 /* enable remote wakeup signalling */ 347 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 348 temp |= DWC_OTG_MSK_DCTL_REMOTE_WAKEUP; 349 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 350 351 /* Wait 8ms for remote wakeup to complete. */ 352 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 353 354 temp &= ~DWC_OTG_MSK_DCTL_REMOTE_WAKEUP; 355 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 356 357 /* need to fake resume IRQ */ 358 dwc_otg_resume_irq(sc); 359 } 360 361 static void 362 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 363 { 364 uint32_t temp; 365 366 DPRINTFN(5, "addr=%d\n", addr); 367 368 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCFG); 369 temp &= ~DWC_OTG_MSK_DCFG_SET_DEV_ADDR(0x7F); 370 temp |= DWC_OTG_MSK_DCFG_SET_DEV_ADDR(addr); 371 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCFG, temp); 372 } 373 374 static void 375 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 376 { 377 DPRINTFN(5, "RX status clear\n"); 378 379 /* enable RX FIFO level interrupt */ 380 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_RXFLVL; 381 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 382 383 /* clear cached status */ 384 sc->sc_last_rx_status = 0; 385 } 386 387 static uint8_t 388 dwc_otg_setup_rx(struct dwc_otg_td *td) 389 { 390 struct dwc_otg_softc *sc; 391 struct usb_device_request req __aligned(4); 392 uint32_t temp; 393 uint16_t count; 394 395 /* get pointer to softc */ 396 sc = DWC_OTG_PC2SC(td->pc); 397 398 /* check endpoint status */ 399 400 if (sc->sc_last_rx_status == 0) 401 goto not_complete; 402 403 if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != 0) 404 goto not_complete; 405 406 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PID) != 407 DWC_OTG_MSK_GRXSTS_PID_DATA0) { 408 /* release FIFO */ 409 dwc_otg_common_rx_ack(sc); 410 goto not_complete; 411 } 412 413 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 414 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 415 /* release FIFO */ 416 dwc_otg_common_rx_ack(sc); 417 goto not_complete; 418 } 419 420 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 421 422 /* clear did stall */ 423 td->did_stall = 0; 424 425 /* get the packet byte count */ 426 count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status); 427 428 /* verify data length */ 429 if (count != td->remainder) { 430 DPRINTFN(0, "Invalid SETUP packet " 431 "length, %d bytes\n", count); 432 /* release FIFO */ 433 dwc_otg_common_rx_ack(sc); 434 goto not_complete; 435 } 436 if (count != sizeof(req)) { 437 DPRINTFN(0, "Unsupported SETUP packet " 438 "length, %d bytes\n", count); 439 /* release FIFO */ 440 dwc_otg_common_rx_ack(sc); 441 goto not_complete; 442 } 443 444 /* copy in control request */ 445 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 446 447 /* copy data into real buffer */ 448 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 449 450 td->offset = sizeof(req); 451 td->remainder = 0; 452 453 /* sneak peek the set address */ 454 if ((req.bmRequestType == UT_WRITE_DEVICE) && 455 (req.bRequest == UR_SET_ADDRESS)) { 456 /* must write address before ZLP */ 457 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 458 } 459 460 /* don't send any data by default */ 461 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(0), 462 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(0) | 463 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(0)); 464 465 temp = sc->sc_in_ctl[0]; 466 467 /* enable IN endpoint */ 468 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 469 temp | DWC_OTG_MSK_DIEPCTL_ENABLE); 470 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 471 temp | DWC_OTG_MSK_DIEPCTL_SET_NAK); 472 473 /* reset IN endpoint buffer */ 474 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 475 DWC_OTG_MSK_GRSTCTL_TXFIFO(0) | 476 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 477 478 /* acknowledge RX status */ 479 dwc_otg_common_rx_ack(sc); 480 return (0); /* complete */ 481 482 not_complete: 483 /* abort any ongoing transfer, before enabling again */ 484 485 temp = sc->sc_out_ctl[0]; 486 487 temp |= DWC_OTG_MSK_DOEPCTL_ENABLE | 488 DWC_OTG_MSK_DOEPCTL_SET_NAK; 489 490 /* enable OUT endpoint */ 491 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0), temp); 492 493 if (!td->did_stall) { 494 td->did_stall = 1; 495 496 DPRINTFN(5, "stalling IN and OUT direction\n"); 497 498 /* set stall after enabling endpoint */ 499 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0), 500 temp | DWC_OTG_MSK_DOEPCTL_STALL); 501 502 temp = sc->sc_in_ctl[0]; 503 504 /* set stall assuming endpoint is enabled */ 505 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 506 temp | DWC_OTG_MSK_DIEPCTL_STALL); 507 } 508 509 /* setup number of buffers to receive */ 510 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0), 511 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(3) | 512 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 513 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(sizeof(req))); 514 515 return (1); /* not complete */ 516 } 517 518 static uint8_t 519 dwc_otg_data_rx(struct dwc_otg_td *td) 520 { 521 struct dwc_otg_softc *sc; 522 uint32_t temp; 523 uint16_t count; 524 uint8_t got_short; 525 526 got_short = 0; 527 528 /* get pointer to softc */ 529 sc = DWC_OTG_PC2SC(td->pc); 530 531 /* check endpoint status */ 532 if (sc->sc_last_rx_status == 0) 533 goto not_complete; 534 535 if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != td->ep_no) 536 goto not_complete; 537 538 /* check for SETUP packet */ 539 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) == 540 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 541 if (td->remainder == 0) { 542 /* 543 * We are actually complete and have 544 * received the next SETUP 545 */ 546 DPRINTFN(5, "faking complete\n"); 547 return (0); /* complete */ 548 } 549 /* 550 * USB Host Aborted the transfer. 551 */ 552 td->error = 1; 553 return (0); /* complete */ 554 } 555 556 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 557 DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) { 558 /* release FIFO */ 559 dwc_otg_common_rx_ack(sc); 560 goto not_complete; 561 } 562 563 /* get the packet byte count */ 564 count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status); 565 566 /* verify the packet byte count */ 567 if (count != td->max_packet_size) { 568 if (count < td->max_packet_size) { 569 /* we have a short packet */ 570 td->short_pkt = 1; 571 got_short = 1; 572 } else { 573 /* invalid USB packet */ 574 td->error = 1; 575 576 /* release FIFO */ 577 dwc_otg_common_rx_ack(sc); 578 return (0); /* we are complete */ 579 } 580 } 581 /* verify the packet byte count */ 582 if (count > td->remainder) { 583 /* invalid USB packet */ 584 td->error = 1; 585 586 /* release FIFO */ 587 dwc_otg_common_rx_ack(sc); 588 return (0); /* we are complete */ 589 } 590 591 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 592 td->remainder -= count; 593 td->offset += count; 594 595 /* release FIFO */ 596 dwc_otg_common_rx_ack(sc); 597 598 /* check if we are complete */ 599 if ((td->remainder == 0) || got_short) { 600 if (td->short_pkt) { 601 /* we are complete */ 602 return (0); 603 } 604 /* else need to receive a zero length packet */ 605 } 606 607 not_complete: 608 609 temp = sc->sc_out_ctl[td->ep_no]; 610 611 temp |= DWC_OTG_MSK_DOEPCTL_ENABLE | 612 DWC_OTG_MSK_DOEPCTL_CLR_NAK; 613 614 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(td->ep_no), temp); 615 616 /* enable SETUP and transfer complete interrupt */ 617 if (td->ep_no == 0) { 618 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0), 619 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 620 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 621 } else { 622 /* allow reception of multiple packets */ 623 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(td->ep_no), 624 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) | 625 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(4) | 626 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(4 * 627 ((td->max_packet_size + 3) & ~3))); 628 } 629 return (1); /* not complete */ 630 } 631 632 static uint8_t 633 dwc_otg_data_tx(struct dwc_otg_td *td) 634 { 635 struct dwc_otg_softc *sc; 636 uint32_t max_buffer; 637 uint32_t count; 638 uint32_t fifo_left; 639 uint32_t mpkt; 640 uint32_t temp; 641 uint8_t to; 642 643 to = 3; /* don't loop forever! */ 644 645 /* get pointer to softc */ 646 sc = DWC_OTG_PC2SC(td->pc); 647 648 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 649 650 repeat: 651 /* check for for endpoint 0 data */ 652 653 temp = sc->sc_last_rx_status; 654 655 if ((td->ep_no == 0) && (temp != 0) && 656 (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) { 657 658 if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 659 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 660 661 /* dump data - wrong direction */ 662 dwc_otg_common_rx_ack(sc); 663 } else { 664 /* 665 * The current transfer was cancelled 666 * by the USB Host: 667 */ 668 td->error = 1; 669 return (0); /* complete */ 670 } 671 } 672 673 /* fill in more TX data, if possible */ 674 if (td->tx_bytes != 0) { 675 676 uint16_t cpkt; 677 678 /* check if packets have been transferred */ 679 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 680 681 /* get current packet number */ 682 cpkt = DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp); 683 684 if (cpkt >= td->npkt) { 685 fifo_left = 0; 686 } else { 687 if (max_buffer != 0) { 688 fifo_left = (td->npkt - cpkt) * 689 td->max_packet_size; 690 691 if (fifo_left > max_buffer) 692 fifo_left = max_buffer; 693 } else { 694 fifo_left = td->max_packet_size; 695 } 696 } 697 698 count = td->tx_bytes; 699 if (count > fifo_left) 700 count = fifo_left; 701 702 if (count != 0) { 703 704 /* clear topmost word before copy */ 705 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 706 707 /* copy out data */ 708 usbd_copy_out(td->pc, td->offset, 709 sc->sc_tx_bounce_buffer, count); 710 711 /* transfer data into FIFO */ 712 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 713 DWC_OTG_REG_DFIFO(td->ep_no), 714 sc->sc_tx_bounce_buffer, (count + 3) / 4); 715 716 td->tx_bytes -= count; 717 td->remainder -= count; 718 td->offset += count; 719 td->npkt = cpkt; 720 } 721 if (td->tx_bytes != 0) 722 goto not_complete; 723 724 /* check remainder */ 725 if (td->remainder == 0) { 726 if (td->short_pkt) 727 return (0); /* complete */ 728 729 /* else we need to transmit a short packet */ 730 } 731 } 732 733 /* check if no packets have been transferred */ 734 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 735 736 if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) { 737 738 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 739 "DIEPCTL=0x%08x\n", td->ep_no, 740 DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp), 741 temp, DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no))); 742 743 goto not_complete; 744 } 745 746 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 747 748 /* try to optimise by sending more data */ 749 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 750 751 /* send multiple packets at the same time */ 752 mpkt = max_buffer / td->max_packet_size; 753 754 if (mpkt > 0x3FE) 755 mpkt = 0x3FE; 756 757 count = td->remainder; 758 if (count > 0x7FFFFF) 759 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 760 761 td->npkt = count / td->max_packet_size; 762 763 /* 764 * NOTE: We could use 0x3FE instead of "mpkt" in the 765 * check below to get more throughput, but then we 766 * have a dependency towards non-generic chip features 767 * to disable the TX-FIFO-EMPTY interrupts on a per 768 * endpoint basis. Increase the maximum buffer size of 769 * the IN endpoint to increase the performance. 770 */ 771 if (td->npkt > mpkt) { 772 td->npkt = mpkt; 773 count = td->max_packet_size * mpkt; 774 } else if ((count == 0) || (count % td->max_packet_size)) { 775 /* we are transmitting a short packet */ 776 td->npkt++; 777 td->short_pkt = 1; 778 } 779 } else { 780 /* send one packet at a time */ 781 mpkt = 1; 782 count = td->max_packet_size; 783 if (td->remainder < count) { 784 /* we have a short packet */ 785 td->short_pkt = 1; 786 count = td->remainder; 787 } 788 td->npkt = 1; 789 } 790 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no), 791 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) | 792 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(td->npkt) | 793 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(count)); 794 795 /* make room for buffering */ 796 td->npkt += mpkt; 797 798 temp = sc->sc_in_ctl[td->ep_no]; 799 800 /* must enable before writing data to FIFO */ 801 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no), temp | 802 DWC_OTG_MSK_DIEPCTL_ENABLE | 803 DWC_OTG_MSK_DIEPCTL_CLR_NAK); 804 805 td->tx_bytes = count; 806 807 /* check remainder */ 808 if (td->tx_bytes == 0 && 809 td->remainder == 0) { 810 if (td->short_pkt) 811 return (0); /* complete */ 812 813 /* else we need to transmit a short packet */ 814 } 815 816 if (--to) 817 goto repeat; 818 819 not_complete: 820 return (1); /* not complete */ 821 } 822 823 static uint8_t 824 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 825 { 826 struct dwc_otg_softc *sc; 827 uint32_t temp; 828 829 /* get pointer to softc */ 830 sc = DWC_OTG_PC2SC(td->pc); 831 832 /* 833 * If all packets are transferred we are complete: 834 */ 835 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 836 837 /* check that all packets have been transferred */ 838 if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) { 839 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 840 goto not_complete; 841 } 842 return (0); 843 844 not_complete: 845 846 /* we only want to know if there is a SETUP packet or free IN packet */ 847 848 temp = sc->sc_last_rx_status; 849 850 if ((td->ep_no == 0) && (temp != 0) && 851 (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) { 852 853 if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) == 854 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 855 DPRINTFN(5, "faking complete\n"); 856 /* 857 * Race condition: We are complete! 858 */ 859 return (0); 860 } else { 861 /* dump data - wrong direction */ 862 dwc_otg_common_rx_ack(sc); 863 } 864 } 865 return (1); /* not complete */ 866 } 867 868 static uint8_t 869 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 870 { 871 struct dwc_otg_td *td; 872 873 DPRINTFN(9, "\n"); 874 875 td = xfer->td_transfer_cache; 876 while (1) { 877 if ((td->func) (td)) { 878 /* operation in progress */ 879 break; 880 } 881 if (((void *)td) == xfer->td_transfer_last) { 882 goto done; 883 } 884 if (td->error) { 885 goto done; 886 } else if (td->remainder > 0) { 887 /* 888 * We had a short transfer. If there is no alternate 889 * next, stop processing ! 890 */ 891 if (!td->alt_next) 892 goto done; 893 } 894 895 /* 896 * Fetch the next transfer descriptor and transfer 897 * some flags to the next transfer descriptor 898 */ 899 td = td->obj_next; 900 xfer->td_transfer_cache = td; 901 } 902 return (1); /* not complete */ 903 904 done: 905 /* compute all actual lengths */ 906 907 dwc_otg_standard_done(xfer); 908 return (0); /* complete */ 909 } 910 911 static void 912 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 913 { 914 struct usb_xfer *xfer; 915 uint32_t temp; 916 uint8_t got_rx_status; 917 918 repeat: 919 if (sc->sc_last_rx_status == 0) { 920 921 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS); 922 if (temp & DWC_OTG_MSK_GINT_RXFLVL) { 923 /* pop current status */ 924 sc->sc_last_rx_status = 925 DWC_OTG_READ_4(sc, DWC_OTG_REG_GRXSTSP); 926 } 927 928 if (sc->sc_last_rx_status != 0) { 929 930 uint32_t temp; 931 uint8_t ep_no; 932 933 temp = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT( 934 sc->sc_last_rx_status); 935 ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 936 sc->sc_last_rx_status); 937 938 /* receive data, if any */ 939 if (temp != 0) { 940 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 941 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 942 DWC_OTG_REG_DFIFO(ep_no), 943 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 944 } 945 946 temp = sc->sc_last_rx_status & 947 DWC_OTG_MSK_GRXSTS_PACKET_STS; 948 949 /* non-data messages we simply skip */ 950 if (temp != DWC_OTG_MSK_GRXSTS_DEV_STP_DATA && 951 temp != DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) { 952 dwc_otg_common_rx_ack(sc); 953 goto repeat; 954 } 955 956 /* check if we should dump the data */ 957 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 958 dwc_otg_common_rx_ack(sc); 959 goto repeat; 960 } 961 962 got_rx_status = 1; 963 964 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 965 sc->sc_last_rx_status, ep_no, 966 (sc->sc_last_rx_status >> 15) & 3, 967 DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status), 968 (sc->sc_last_rx_status >> 17) & 15); 969 } else { 970 got_rx_status = 0; 971 } 972 } else { 973 uint8_t ep_no; 974 975 ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 976 sc->sc_last_rx_status); 977 978 /* check if we should dump the data */ 979 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 980 dwc_otg_common_rx_ack(sc); 981 goto repeat; 982 } 983 984 got_rx_status = 1; 985 } 986 987 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 988 if (!dwc_otg_xfer_do_fifo(xfer)) { 989 /* queue has been modified */ 990 goto repeat; 991 } 992 } 993 994 if (got_rx_status) { 995 if (sc->sc_last_rx_status == 0) 996 goto repeat; 997 998 /* disable RX FIFO level interrupt */ 999 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_RXFLVL; 1000 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1001 } 1002 } 1003 1004 static void 1005 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 1006 { 1007 DPRINTFN(5, "vbus = %u\n", is_on); 1008 1009 if (is_on) { 1010 if (!sc->sc_flags.status_vbus) { 1011 sc->sc_flags.status_vbus = 1; 1012 1013 /* complete root HUB interrupt endpoint */ 1014 1015 dwc_otg_root_intr(sc); 1016 } 1017 } else { 1018 if (sc->sc_flags.status_vbus) { 1019 sc->sc_flags.status_vbus = 0; 1020 sc->sc_flags.status_bus_reset = 0; 1021 sc->sc_flags.status_suspend = 0; 1022 sc->sc_flags.change_suspend = 0; 1023 sc->sc_flags.change_connect = 1; 1024 1025 /* complete root HUB interrupt endpoint */ 1026 1027 dwc_otg_root_intr(sc); 1028 } 1029 } 1030 } 1031 1032 void 1033 dwc_otg_interrupt(struct dwc_otg_softc *sc) 1034 { 1035 uint32_t status; 1036 1037 USB_BUS_LOCK(&sc->sc_bus); 1038 1039 /* read and clear interrupt status */ 1040 status = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS); 1041 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTSTS, status); 1042 1043 DPRINTFN(14, "GINTSTS=0x%08x\n", status); 1044 1045 /* check for any bus state change interrupts */ 1046 if (status & DWC_OTG_MSK_GINT_ENUM_DONE) { 1047 1048 uint32_t temp; 1049 1050 DPRINTFN(5, "end of reset\n"); 1051 1052 /* set correct state */ 1053 sc->sc_flags.status_bus_reset = 1; 1054 sc->sc_flags.status_suspend = 0; 1055 sc->sc_flags.change_suspend = 0; 1056 sc->sc_flags.change_connect = 1; 1057 1058 /* reset FIFOs */ 1059 dwc_otg_init_fifo(sc); 1060 1061 /* reset function address */ 1062 dwc_otg_set_address(sc, 0); 1063 1064 /* reset active endpoints */ 1065 sc->sc_active_out_ep = 1; 1066 1067 /* figure out enumeration speed */ 1068 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS); 1069 if (DWC_OTG_MSK_DSTS_GET_ENUM_SPEED(temp) == 1070 DWC_OTG_MSK_DSTS_ENUM_SPEED_HI) 1071 sc->sc_flags.status_high_speed = 1; 1072 else 1073 sc->sc_flags.status_high_speed = 0; 1074 1075 /* disable resume interrupt and enable suspend interrupt */ 1076 1077 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT; 1078 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND; 1079 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1080 1081 /* complete root HUB interrupt endpoint */ 1082 dwc_otg_root_intr(sc); 1083 } 1084 /* 1085 * If resume and suspend is set at the same time we interpret 1086 * that like RESUME. Resume is set when there is at least 3 1087 * milliseconds of inactivity on the USB BUS. 1088 */ 1089 if (status & DWC_OTG_MSK_GINT_WKUPINT) { 1090 1091 DPRINTFN(5, "resume interrupt\n"); 1092 1093 dwc_otg_resume_irq(sc); 1094 1095 } else if (status & DWC_OTG_MSK_GINT_USB_SUSPEND) { 1096 1097 DPRINTFN(5, "suspend interrupt\n"); 1098 1099 if (!sc->sc_flags.status_suspend) { 1100 /* update status bits */ 1101 sc->sc_flags.status_suspend = 1; 1102 sc->sc_flags.change_suspend = 1; 1103 1104 /* 1105 * Disable suspend interrupt and enable resume 1106 * interrupt: 1107 */ 1108 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_USB_SUSPEND; 1109 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_WKUPINT; 1110 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1111 1112 /* complete root HUB interrupt endpoint */ 1113 dwc_otg_root_intr(sc); 1114 } 1115 } 1116 /* check VBUS */ 1117 if (status & (DWC_OTG_MSK_GINT_USB_SUSPEND | 1118 DWC_OTG_MSK_GINT_SESSREQINT)) { 1119 uint32_t temp; 1120 1121 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL); 1122 1123 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 1124 1125 dwc_otg_vbus_interrupt(sc, 1126 (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0); 1127 } 1128 1129 /* clear all IN endpoint interrupts */ 1130 if (status & DWC_OTG_MSK_GINT_INEP) { 1131 uint32_t temp; 1132 uint8_t x; 1133 1134 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 1135 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPINT(x)); 1136 if (temp == 0) 1137 continue; 1138 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPINT(x), temp); 1139 } 1140 } 1141 1142 #if 0 1143 /* check if we should poll the FIFOs */ 1144 if (status & (DWC_OTG_MSK_GINT_RXFLVL | DWC_OTG_MSK_GINT_INEP)) 1145 #endif 1146 /* poll FIFO(s) */ 1147 dwc_otg_interrupt_poll(sc); 1148 1149 USB_BUS_UNLOCK(&sc->sc_bus); 1150 } 1151 1152 static void 1153 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 1154 { 1155 struct dwc_otg_td *td; 1156 1157 /* get current Transfer Descriptor */ 1158 td = temp->td_next; 1159 temp->td = td; 1160 1161 /* prepare for next TD */ 1162 temp->td_next = td->obj_next; 1163 1164 /* fill out the Transfer Descriptor */ 1165 td->func = temp->func; 1166 td->pc = temp->pc; 1167 td->offset = temp->offset; 1168 td->remainder = temp->len; 1169 td->tx_bytes = 0; 1170 td->error = 0; 1171 td->npkt = 1; 1172 td->did_stall = temp->did_stall; 1173 td->short_pkt = temp->short_pkt; 1174 td->alt_next = temp->setup_alt_next; 1175 } 1176 1177 static void 1178 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 1179 { 1180 struct dwc_otg_std_temp temp; 1181 struct dwc_otg_td *td; 1182 uint32_t x; 1183 uint8_t need_sync; 1184 1185 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1186 xfer->address, UE_GET_ADDR(xfer->endpointno), 1187 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1188 1189 temp.max_frame_size = xfer->max_frame_size; 1190 1191 td = xfer->td_start[0]; 1192 xfer->td_transfer_first = td; 1193 xfer->td_transfer_cache = td; 1194 1195 /* setup temp */ 1196 1197 temp.pc = NULL; 1198 temp.td = NULL; 1199 temp.td_next = xfer->td_start[0]; 1200 temp.offset = 0; 1201 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1202 temp.did_stall = !xfer->flags_int.control_stall; 1203 1204 /* check if we should prepend a setup message */ 1205 1206 if (xfer->flags_int.control_xfr) { 1207 if (xfer->flags_int.control_hdr) { 1208 1209 temp.func = &dwc_otg_setup_rx; 1210 temp.len = xfer->frlengths[0]; 1211 temp.pc = xfer->frbuffers + 0; 1212 temp.short_pkt = temp.len ? 1 : 0; 1213 1214 /* check for last frame */ 1215 if (xfer->nframes == 1) { 1216 /* no STATUS stage yet, SETUP is last */ 1217 if (xfer->flags_int.control_act) 1218 temp.setup_alt_next = 0; 1219 } 1220 1221 dwc_otg_setup_standard_chain_sub(&temp); 1222 } 1223 x = 1; 1224 } else { 1225 x = 0; 1226 } 1227 1228 if (x != xfer->nframes) { 1229 if (xfer->endpointno & UE_DIR_IN) { 1230 temp.func = &dwc_otg_data_tx; 1231 need_sync = 1; 1232 } else { 1233 temp.func = &dwc_otg_data_rx; 1234 need_sync = 0; 1235 } 1236 1237 /* setup "pc" pointer */ 1238 temp.pc = xfer->frbuffers + x; 1239 } else { 1240 need_sync = 0; 1241 } 1242 while (x != xfer->nframes) { 1243 1244 /* DATA0 / DATA1 message */ 1245 1246 temp.len = xfer->frlengths[x]; 1247 1248 x++; 1249 1250 if (x == xfer->nframes) { 1251 if (xfer->flags_int.control_xfr) { 1252 if (xfer->flags_int.control_act) { 1253 temp.setup_alt_next = 0; 1254 } 1255 } else { 1256 temp.setup_alt_next = 0; 1257 } 1258 } 1259 if (temp.len == 0) { 1260 1261 /* make sure that we send an USB packet */ 1262 1263 temp.short_pkt = 0; 1264 1265 } else { 1266 1267 /* regular data transfer */ 1268 1269 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 1270 } 1271 1272 dwc_otg_setup_standard_chain_sub(&temp); 1273 1274 if (xfer->flags_int.isochronous_xfr) { 1275 temp.offset += temp.len; 1276 } else { 1277 /* get next Page Cache pointer */ 1278 temp.pc = xfer->frbuffers + x; 1279 } 1280 } 1281 1282 if (xfer->flags_int.control_xfr) { 1283 1284 /* always setup a valid "pc" pointer for status and sync */ 1285 temp.pc = xfer->frbuffers + 0; 1286 temp.len = 0; 1287 temp.short_pkt = 0; 1288 temp.setup_alt_next = 0; 1289 1290 /* check if we need to sync */ 1291 if (need_sync) { 1292 /* we need a SYNC point after TX */ 1293 temp.func = &dwc_otg_data_tx_sync; 1294 dwc_otg_setup_standard_chain_sub(&temp); 1295 } 1296 1297 /* check if we should append a status stage */ 1298 if (!xfer->flags_int.control_act) { 1299 1300 /* 1301 * Send a DATA1 message and invert the current 1302 * endpoint direction. 1303 */ 1304 if (xfer->endpointno & UE_DIR_IN) { 1305 temp.func = &dwc_otg_data_rx; 1306 need_sync = 0; 1307 } else { 1308 temp.func = &dwc_otg_data_tx; 1309 need_sync = 1; 1310 } 1311 1312 dwc_otg_setup_standard_chain_sub(&temp); 1313 if (need_sync) { 1314 /* we need a SYNC point after TX */ 1315 temp.func = &dwc_otg_data_tx_sync; 1316 dwc_otg_setup_standard_chain_sub(&temp); 1317 } 1318 } 1319 } else { 1320 /* check if we need to sync */ 1321 if (need_sync) { 1322 1323 temp.pc = xfer->frbuffers + 0; 1324 temp.len = 0; 1325 temp.short_pkt = 0; 1326 temp.setup_alt_next = 0; 1327 1328 /* we need a SYNC point after TX */ 1329 temp.func = &dwc_otg_data_tx_sync; 1330 dwc_otg_setup_standard_chain_sub(&temp); 1331 } 1332 } 1333 1334 /* must have at least one frame! */ 1335 td = temp.td; 1336 xfer->td_transfer_last = td; 1337 } 1338 1339 static void 1340 dwc_otg_timeout(void *arg) 1341 { 1342 struct usb_xfer *xfer = arg; 1343 1344 DPRINTF("xfer=%p\n", xfer); 1345 1346 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1347 1348 /* transfer is transferred */ 1349 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 1350 } 1351 1352 static void 1353 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 1354 { 1355 DPRINTFN(9, "\n"); 1356 1357 /* poll one time - will turn on interrupts */ 1358 if (dwc_otg_xfer_do_fifo(xfer)) { 1359 1360 /* put transfer on interrupt queue */ 1361 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1362 1363 /* start timeout, if any */ 1364 if (xfer->timeout != 0) { 1365 usbd_transfer_timeout_ms(xfer, 1366 &dwc_otg_timeout, xfer->timeout); 1367 } 1368 } 1369 } 1370 1371 static void 1372 dwc_otg_root_intr(struct dwc_otg_softc *sc) 1373 { 1374 DPRINTFN(9, "\n"); 1375 1376 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1377 1378 /* set port bit */ 1379 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1380 1381 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1382 sizeof(sc->sc_hub_idata)); 1383 } 1384 1385 static usb_error_t 1386 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 1387 { 1388 struct dwc_otg_td *td; 1389 uint32_t len; 1390 uint8_t error; 1391 1392 DPRINTFN(9, "\n"); 1393 1394 td = xfer->td_transfer_cache; 1395 1396 do { 1397 len = td->remainder; 1398 1399 if (xfer->aframes != xfer->nframes) { 1400 /* 1401 * Verify the length and subtract 1402 * the remainder from "frlengths[]": 1403 */ 1404 if (len > xfer->frlengths[xfer->aframes]) { 1405 td->error = 1; 1406 } else { 1407 xfer->frlengths[xfer->aframes] -= len; 1408 } 1409 } 1410 /* Check for transfer error */ 1411 if (td->error) { 1412 /* the transfer is finished */ 1413 error = 1; 1414 td = NULL; 1415 break; 1416 } 1417 /* Check for short transfer */ 1418 if (len > 0) { 1419 if (xfer->flags_int.short_frames_ok) { 1420 /* follow alt next */ 1421 if (td->alt_next) { 1422 td = td->obj_next; 1423 } else { 1424 td = NULL; 1425 } 1426 } else { 1427 /* the transfer is finished */ 1428 td = NULL; 1429 } 1430 error = 0; 1431 break; 1432 } 1433 td = td->obj_next; 1434 1435 /* this USB frame is complete */ 1436 error = 0; 1437 break; 1438 1439 } while (0); 1440 1441 /* update transfer cache */ 1442 1443 xfer->td_transfer_cache = td; 1444 1445 return (error ? 1446 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1447 } 1448 1449 static void 1450 dwc_otg_standard_done(struct usb_xfer *xfer) 1451 { 1452 usb_error_t err = 0; 1453 1454 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1455 xfer, xfer->endpoint); 1456 1457 /* reset scanner */ 1458 1459 xfer->td_transfer_cache = xfer->td_transfer_first; 1460 1461 if (xfer->flags_int.control_xfr) { 1462 1463 if (xfer->flags_int.control_hdr) { 1464 1465 err = dwc_otg_standard_done_sub(xfer); 1466 } 1467 xfer->aframes = 1; 1468 1469 if (xfer->td_transfer_cache == NULL) { 1470 goto done; 1471 } 1472 } 1473 while (xfer->aframes != xfer->nframes) { 1474 1475 err = dwc_otg_standard_done_sub(xfer); 1476 xfer->aframes++; 1477 1478 if (xfer->td_transfer_cache == NULL) { 1479 goto done; 1480 } 1481 } 1482 1483 if (xfer->flags_int.control_xfr && 1484 !xfer->flags_int.control_act) { 1485 1486 err = dwc_otg_standard_done_sub(xfer); 1487 } 1488 done: 1489 dwc_otg_device_done(xfer, err); 1490 } 1491 1492 /*------------------------------------------------------------------------* 1493 * dwc_otg_device_done 1494 * 1495 * NOTE: this function can be called more than one time on the 1496 * same USB transfer! 1497 *------------------------------------------------------------------------*/ 1498 static void 1499 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 1500 { 1501 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1502 xfer, xfer->endpoint, error); 1503 1504 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1505 DPRINTFN(15, "disabled interrupts!\n"); 1506 } 1507 /* dequeue transfer and start next transfer */ 1508 usbd_transfer_done(xfer, error); 1509 } 1510 1511 static void 1512 dwc_otg_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1513 struct usb_endpoint *ep, uint8_t *did_stall) 1514 { 1515 struct dwc_otg_softc *sc; 1516 uint32_t temp; 1517 uint32_t reg; 1518 uint8_t ep_no; 1519 1520 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1521 1522 if (xfer) { 1523 /* cancel any ongoing transfers */ 1524 dwc_otg_device_done(xfer, USB_ERR_STALLED); 1525 } 1526 sc = DWC_OTG_BUS2SC(udev->bus); 1527 1528 /* get endpoint address */ 1529 ep_no = ep->edesc->bEndpointAddress; 1530 1531 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 1532 1533 if (ep_no & UE_DIR_IN) { 1534 reg = DWC_OTG_REG_DIEPCTL(ep_no & UE_ADDR); 1535 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 1536 } else { 1537 reg = DWC_OTG_REG_DOEPCTL(ep_no & UE_ADDR); 1538 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 1539 } 1540 1541 /* disable and stall endpoint */ 1542 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE); 1543 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_STALL); 1544 1545 /* clear active OUT ep */ 1546 if (!(ep_no & UE_DIR_IN)) { 1547 1548 sc->sc_active_out_ep &= ~(1U << (ep_no & UE_ADDR)); 1549 1550 if (sc->sc_last_rx_status != 0 && 1551 (ep_no & UE_ADDR) == DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 1552 sc->sc_last_rx_status)) { 1553 /* dump data */ 1554 dwc_otg_common_rx_ack(sc); 1555 /* poll interrupt */ 1556 dwc_otg_interrupt_poll(sc); 1557 } 1558 } 1559 } 1560 1561 static void 1562 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 1563 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1564 { 1565 uint32_t reg; 1566 uint32_t temp; 1567 1568 if (ep_type == UE_CONTROL) { 1569 /* clearing stall is not needed */ 1570 return; 1571 } 1572 1573 if (ep_dir) { 1574 reg = DWC_OTG_REG_DIEPCTL(ep_no); 1575 } else { 1576 reg = DWC_OTG_REG_DOEPCTL(ep_no); 1577 sc->sc_active_out_ep |= (1U << ep_no); 1578 } 1579 1580 /* round up and mask away the multiplier count */ 1581 mps = (mps + 3) & 0x7FC; 1582 1583 if (ep_type == UE_BULK) { 1584 temp = DWC_OTG_MSK_EP_SET_TYPE( 1585 DWC_OTG_MSK_EP_TYPE_BULK) | 1586 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1587 } else if (ep_type == UE_INTERRUPT) { 1588 temp = DWC_OTG_MSK_EP_SET_TYPE( 1589 DWC_OTG_MSK_EP_TYPE_INTERRUPT) | 1590 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1591 } else { 1592 temp = DWC_OTG_MSK_EP_SET_TYPE( 1593 DWC_OTG_MSK_EP_TYPE_ISOC) | 1594 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1595 } 1596 1597 temp |= DWC_OTG_MSK_DIEPCTL_MPS(mps); 1598 temp |= DWC_OTG_MSK_DIEPCTL_FNUM(ep_no); 1599 1600 if (ep_dir) 1601 sc->sc_in_ctl[ep_no] = temp; 1602 else 1603 sc->sc_out_ctl[ep_no] = temp; 1604 1605 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE); 1606 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_SET_DATA0); 1607 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DIEPCTL_SET_NAK); 1608 1609 /* we only reset the transmit FIFO */ 1610 if (ep_dir) { 1611 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 1612 DWC_OTG_MSK_GRSTCTL_TXFIFO(ep_no) | 1613 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 1614 1615 DWC_OTG_WRITE_4(sc, 1616 DWC_OTG_REG_DIEPTSIZ(ep_no), 0); 1617 } 1618 1619 /* poll interrupt */ 1620 dwc_otg_interrupt_poll(sc); 1621 } 1622 1623 static void 1624 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1625 { 1626 struct dwc_otg_softc *sc; 1627 struct usb_endpoint_descriptor *ed; 1628 1629 DPRINTFN(5, "endpoint=%p\n", ep); 1630 1631 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1632 1633 /* check mode */ 1634 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1635 /* not supported */ 1636 return; 1637 } 1638 /* get softc */ 1639 sc = DWC_OTG_BUS2SC(udev->bus); 1640 1641 /* get endpoint descriptor */ 1642 ed = ep->edesc; 1643 1644 /* reset endpoint */ 1645 dwc_otg_clear_stall_sub(sc, 1646 UGETW(ed->wMaxPacketSize), 1647 (ed->bEndpointAddress & UE_ADDR), 1648 (ed->bmAttributes & UE_XFERTYPE), 1649 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1650 } 1651 1652 static void 1653 dwc_otg_device_state_change(struct usb_device *udev) 1654 { 1655 struct dwc_otg_softc *sc; 1656 uint8_t x; 1657 1658 /* get softc */ 1659 sc = DWC_OTG_BUS2SC(udev->bus); 1660 1661 /* deactivate all other endpoint but the control endpoint */ 1662 if (udev->state == USB_STATE_CONFIGURED || 1663 udev->state == USB_STATE_ADDRESSED) { 1664 1665 USB_BUS_LOCK(&sc->sc_bus); 1666 1667 for (x = 1; x != sc->sc_dev_ep_max; x++) { 1668 1669 if (x < sc->sc_dev_in_ep_max) { 1670 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x), 1671 DWC_OTG_MSK_DIEPCTL_DISABLE); 1672 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x), 0); 1673 } 1674 1675 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x), 1676 DWC_OTG_MSK_DOEPCTL_DISABLE); 1677 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x), 0); 1678 } 1679 USB_BUS_UNLOCK(&sc->sc_bus); 1680 } 1681 } 1682 1683 int 1684 dwc_otg_init(struct dwc_otg_softc *sc) 1685 { 1686 uint32_t temp; 1687 1688 DPRINTF("start\n"); 1689 1690 /* set up the bus structure */ 1691 sc->sc_bus.usbrev = USB_REV_2_0; 1692 sc->sc_bus.methods = &dwc_otg_bus_methods; 1693 1694 /* reset active endpoints */ 1695 sc->sc_active_out_ep = 1; 1696 1697 USB_BUS_LOCK(&sc->sc_bus); 1698 1699 /* turn on clocks */ 1700 dwc_otg_clocks_on(sc); 1701 1702 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GSNPSID); 1703 DPRINTF("Version = 0x%08x\n", temp); 1704 1705 /* disconnect */ 1706 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1707 DWC_OTG_MSK_DCTL_SOFT_DISC); 1708 1709 /* wait for host to detect disconnect */ 1710 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 1711 1712 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 1713 DWC_OTG_MSK_GRSTCTL_CSFTRST); 1714 1715 /* wait a little bit for block to reset */ 1716 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 1717 1718 /* select HSIC or non-HSIC mode */ 1719 if (DWC_OTG_USE_HSIC) { 1720 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG, 1721 DWC_OTG_MSK_GUSBCFG_PHY_INTF | 1722 DWC_OTG_MSK_GUSBCFG_TRD_TIM(5)); 1723 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL, 1724 0x000000EC); 1725 1726 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG); 1727 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1728 temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1729 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1730 temp | DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1731 } else { 1732 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG, 1733 DWC_OTG_MSK_GUSBCFG_ULPI_UMTI_SEL | 1734 DWC_OTG_MSK_GUSBCFG_TRD_TIM(5)); 1735 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL, 0); 1736 1737 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG); 1738 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1739 temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1740 } 1741 1742 /* clear global nak */ 1743 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1744 DWC_OTG_MSK_DCTL_CGOUT_NAK | 1745 DWC_OTG_MSK_DCTL_CGNPIN_NAK); 1746 1747 /* enable USB port */ 1748 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_PCGCCTL, 0); 1749 1750 /* pull up D+ */ 1751 dwc_otg_pull_up(sc); 1752 1753 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG3); 1754 1755 sc->sc_fifo_size = 4 * DWC_OTG_MSK_GHWCFG3_GET_DFIFO(temp); 1756 1757 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2); 1758 1759 sc->sc_dev_ep_max = DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(temp); 1760 1761 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG4); 1762 1763 sc->sc_dev_in_ep_max = DWC_OTG_MSK_GHWCFG4_NUM_IN_EPS(temp); 1764 1765 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d\n", 1766 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max); 1767 1768 /* setup FIFO */ 1769 if (dwc_otg_init_fifo(sc)) 1770 return (EINVAL); 1771 1772 /* enable interrupts */ 1773 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 1774 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1775 1776 /* 1777 * Disable all endpoint interrupts, 1778 * we use the SOF IRQ for transmit: 1779 */ 1780 1781 /* enable all endpoint interrupts */ 1782 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPMSK, 1783 /* DWC_OTG_MSK_DIEP_FIFO_EMPTY | */ 1784 DWC_OTG_MSK_DIEP_XFER_COMPLETE); 1785 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPMSK, 0); 1786 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DAINTMSK, 0xFFFF); 1787 1788 /* enable global IRQ */ 1789 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, 1790 DWC_OTG_MSK_GAHBCFG_GLOBAL_IRQ); 1791 1792 /* turn off clocks */ 1793 dwc_otg_clocks_off(sc); 1794 1795 /* read initial VBUS state */ 1796 1797 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL); 1798 1799 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 1800 1801 dwc_otg_vbus_interrupt(sc, 1802 (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0); 1803 1804 USB_BUS_UNLOCK(&sc->sc_bus); 1805 1806 /* catch any lost interrupts */ 1807 1808 dwc_otg_do_poll(&sc->sc_bus); 1809 1810 return (0); /* success */ 1811 } 1812 1813 void 1814 dwc_otg_uninit(struct dwc_otg_softc *sc) 1815 { 1816 USB_BUS_LOCK(&sc->sc_bus); 1817 1818 /* set disconnect */ 1819 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1820 DWC_OTG_MSK_DCTL_SOFT_DISC); 1821 1822 /* turn off global IRQ */ 1823 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, 0); 1824 1825 sc->sc_flags.port_powered = 0; 1826 sc->sc_flags.status_vbus = 0; 1827 sc->sc_flags.status_bus_reset = 0; 1828 sc->sc_flags.status_suspend = 0; 1829 sc->sc_flags.change_suspend = 0; 1830 sc->sc_flags.change_connect = 1; 1831 1832 dwc_otg_pull_down(sc); 1833 dwc_otg_clocks_off(sc); 1834 1835 USB_BUS_UNLOCK(&sc->sc_bus); 1836 } 1837 1838 static void 1839 dwc_otg_suspend(struct dwc_otg_softc *sc) 1840 { 1841 return; 1842 } 1843 1844 static void 1845 dwc_otg_resume(struct dwc_otg_softc *sc) 1846 { 1847 return; 1848 } 1849 1850 static void 1851 dwc_otg_do_poll(struct usb_bus *bus) 1852 { 1853 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 1854 1855 USB_BUS_LOCK(&sc->sc_bus); 1856 dwc_otg_interrupt_poll(sc); 1857 USB_BUS_UNLOCK(&sc->sc_bus); 1858 } 1859 1860 /*------------------------------------------------------------------------* 1861 * at91dci bulk support 1862 * at91dci control support 1863 * at91dci interrupt support 1864 *------------------------------------------------------------------------*/ 1865 static void 1866 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 1867 { 1868 return; 1869 } 1870 1871 static void 1872 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 1873 { 1874 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1875 } 1876 1877 static void 1878 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 1879 { 1880 return; 1881 } 1882 1883 static void 1884 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 1885 { 1886 /* setup TDs */ 1887 dwc_otg_setup_standard_chain(xfer); 1888 dwc_otg_start_standard_chain(xfer); 1889 } 1890 1891 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 1892 { 1893 .open = dwc_otg_device_non_isoc_open, 1894 .close = dwc_otg_device_non_isoc_close, 1895 .enter = dwc_otg_device_non_isoc_enter, 1896 .start = dwc_otg_device_non_isoc_start, 1897 }; 1898 1899 /*------------------------------------------------------------------------* 1900 * at91dci full speed isochronous support 1901 *------------------------------------------------------------------------*/ 1902 static void 1903 dwc_otg_device_isoc_fs_open(struct usb_xfer *xfer) 1904 { 1905 return; 1906 } 1907 1908 static void 1909 dwc_otg_device_isoc_fs_close(struct usb_xfer *xfer) 1910 { 1911 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1912 } 1913 1914 static void 1915 dwc_otg_device_isoc_fs_enter(struct usb_xfer *xfer) 1916 { 1917 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 1918 uint32_t temp; 1919 uint32_t nframes; 1920 1921 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1922 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1923 1924 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS); 1925 1926 /* get the current frame index */ 1927 1928 nframes = DWC_OTG_MSK_DSTS_GET_FNUM(temp); 1929 1930 if (sc->sc_flags.status_high_speed) 1931 nframes /= 8; 1932 1933 nframes &= DWC_OTG_FRAME_MASK; 1934 1935 /* 1936 * check if the frame index is within the window where the frames 1937 * will be inserted 1938 */ 1939 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 1940 1941 if ((xfer->endpoint->is_synced == 0) || 1942 (temp < xfer->nframes)) { 1943 /* 1944 * If there is data underflow or the pipe queue is 1945 * empty we schedule the transfer a few frames ahead 1946 * of the current frame position. Else two isochronous 1947 * transfers might overlap. 1948 */ 1949 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 1950 xfer->endpoint->is_synced = 1; 1951 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1952 } 1953 /* 1954 * compute how many milliseconds the insertion is ahead of the 1955 * current frame position: 1956 */ 1957 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 1958 1959 /* 1960 * pre-compute when the isochronous transfer will be finished: 1961 */ 1962 xfer->isoc_time_complete = 1963 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1964 xfer->nframes; 1965 1966 /* compute frame number for next insertion */ 1967 xfer->endpoint->isoc_next += xfer->nframes; 1968 1969 /* setup TDs */ 1970 dwc_otg_setup_standard_chain(xfer); 1971 } 1972 1973 static void 1974 dwc_otg_device_isoc_fs_start(struct usb_xfer *xfer) 1975 { 1976 /* start TD chain */ 1977 dwc_otg_start_standard_chain(xfer); 1978 } 1979 1980 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods = 1981 { 1982 .open = dwc_otg_device_isoc_fs_open, 1983 .close = dwc_otg_device_isoc_fs_close, 1984 .enter = dwc_otg_device_isoc_fs_enter, 1985 .start = dwc_otg_device_isoc_fs_start, 1986 }; 1987 1988 /*------------------------------------------------------------------------* 1989 * at91dci root control support 1990 *------------------------------------------------------------------------* 1991 * Simulate a hardware HUB by handling all the necessary requests. 1992 *------------------------------------------------------------------------*/ 1993 1994 static const struct usb_device_descriptor dwc_otg_devd = { 1995 .bLength = sizeof(struct usb_device_descriptor), 1996 .bDescriptorType = UDESC_DEVICE, 1997 .bcdUSB = {0x00, 0x02}, 1998 .bDeviceClass = UDCLASS_HUB, 1999 .bDeviceSubClass = UDSUBCLASS_HUB, 2000 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2001 .bMaxPacketSize = 64, 2002 .bcdDevice = {0x00, 0x01}, 2003 .iManufacturer = 1, 2004 .iProduct = 2, 2005 .bNumConfigurations = 1, 2006 }; 2007 2008 static const struct dwc_otg_config_desc dwc_otg_confd = { 2009 .confd = { 2010 .bLength = sizeof(struct usb_config_descriptor), 2011 .bDescriptorType = UDESC_CONFIG, 2012 .wTotalLength[0] = sizeof(dwc_otg_confd), 2013 .bNumInterface = 1, 2014 .bConfigurationValue = 1, 2015 .iConfiguration = 0, 2016 .bmAttributes = UC_SELF_POWERED, 2017 .bMaxPower = 0, 2018 }, 2019 .ifcd = { 2020 .bLength = sizeof(struct usb_interface_descriptor), 2021 .bDescriptorType = UDESC_INTERFACE, 2022 .bNumEndpoints = 1, 2023 .bInterfaceClass = UICLASS_HUB, 2024 .bInterfaceSubClass = UISUBCLASS_HUB, 2025 .bInterfaceProtocol = 0, 2026 }, 2027 .endpd = { 2028 .bLength = sizeof(struct usb_endpoint_descriptor), 2029 .bDescriptorType = UDESC_ENDPOINT, 2030 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 2031 .bmAttributes = UE_INTERRUPT, 2032 .wMaxPacketSize[0] = 8, 2033 .bInterval = 255, 2034 }, 2035 }; 2036 2037 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 2038 .bDescLength = sizeof(dwc_otg_hubd), 2039 .bDescriptorType = UDESC_HUB, 2040 .bNbrPorts = 1, 2041 .wHubCharacteristics[0] = 2042 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 2043 .wHubCharacteristics[1] = 2044 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 2045 .bPwrOn2PwrGood = 50, 2046 .bHubContrCurrent = 0, 2047 .DeviceRemovable = {0}, /* port is removable */ 2048 }; 2049 2050 #define STRING_LANG \ 2051 0x09, 0x04, /* American English */ 2052 2053 #define STRING_VENDOR \ 2054 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 2055 2056 #define STRING_PRODUCT \ 2057 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 2058 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2059 'U', 0, 'B', 0, 2060 2061 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 2062 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 2063 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 2064 2065 static usb_error_t 2066 dwc_otg_roothub_exec(struct usb_device *udev, 2067 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2068 { 2069 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2070 const void *ptr; 2071 uint16_t len; 2072 uint16_t value; 2073 uint16_t index; 2074 usb_error_t err; 2075 2076 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2077 2078 /* buffer reset */ 2079 ptr = (const void *)&sc->sc_hub_temp; 2080 len = 0; 2081 err = 0; 2082 2083 value = UGETW(req->wValue); 2084 index = UGETW(req->wIndex); 2085 2086 /* demultiplex the control request */ 2087 2088 switch (req->bmRequestType) { 2089 case UT_READ_DEVICE: 2090 switch (req->bRequest) { 2091 case UR_GET_DESCRIPTOR: 2092 goto tr_handle_get_descriptor; 2093 case UR_GET_CONFIG: 2094 goto tr_handle_get_config; 2095 case UR_GET_STATUS: 2096 goto tr_handle_get_status; 2097 default: 2098 goto tr_stalled; 2099 } 2100 break; 2101 2102 case UT_WRITE_DEVICE: 2103 switch (req->bRequest) { 2104 case UR_SET_ADDRESS: 2105 goto tr_handle_set_address; 2106 case UR_SET_CONFIG: 2107 goto tr_handle_set_config; 2108 case UR_CLEAR_FEATURE: 2109 goto tr_valid; /* nop */ 2110 case UR_SET_DESCRIPTOR: 2111 goto tr_valid; /* nop */ 2112 case UR_SET_FEATURE: 2113 default: 2114 goto tr_stalled; 2115 } 2116 break; 2117 2118 case UT_WRITE_ENDPOINT: 2119 switch (req->bRequest) { 2120 case UR_CLEAR_FEATURE: 2121 switch (UGETW(req->wValue)) { 2122 case UF_ENDPOINT_HALT: 2123 goto tr_handle_clear_halt; 2124 case UF_DEVICE_REMOTE_WAKEUP: 2125 goto tr_handle_clear_wakeup; 2126 default: 2127 goto tr_stalled; 2128 } 2129 break; 2130 case UR_SET_FEATURE: 2131 switch (UGETW(req->wValue)) { 2132 case UF_ENDPOINT_HALT: 2133 goto tr_handle_set_halt; 2134 case UF_DEVICE_REMOTE_WAKEUP: 2135 goto tr_handle_set_wakeup; 2136 default: 2137 goto tr_stalled; 2138 } 2139 break; 2140 case UR_SYNCH_FRAME: 2141 goto tr_valid; /* nop */ 2142 default: 2143 goto tr_stalled; 2144 } 2145 break; 2146 2147 case UT_READ_ENDPOINT: 2148 switch (req->bRequest) { 2149 case UR_GET_STATUS: 2150 goto tr_handle_get_ep_status; 2151 default: 2152 goto tr_stalled; 2153 } 2154 break; 2155 2156 case UT_WRITE_INTERFACE: 2157 switch (req->bRequest) { 2158 case UR_SET_INTERFACE: 2159 goto tr_handle_set_interface; 2160 case UR_CLEAR_FEATURE: 2161 goto tr_valid; /* nop */ 2162 case UR_SET_FEATURE: 2163 default: 2164 goto tr_stalled; 2165 } 2166 break; 2167 2168 case UT_READ_INTERFACE: 2169 switch (req->bRequest) { 2170 case UR_GET_INTERFACE: 2171 goto tr_handle_get_interface; 2172 case UR_GET_STATUS: 2173 goto tr_handle_get_iface_status; 2174 default: 2175 goto tr_stalled; 2176 } 2177 break; 2178 2179 case UT_WRITE_CLASS_INTERFACE: 2180 case UT_WRITE_VENDOR_INTERFACE: 2181 /* XXX forward */ 2182 break; 2183 2184 case UT_READ_CLASS_INTERFACE: 2185 case UT_READ_VENDOR_INTERFACE: 2186 /* XXX forward */ 2187 break; 2188 2189 case UT_WRITE_CLASS_DEVICE: 2190 switch (req->bRequest) { 2191 case UR_CLEAR_FEATURE: 2192 goto tr_valid; 2193 case UR_SET_DESCRIPTOR: 2194 case UR_SET_FEATURE: 2195 break; 2196 default: 2197 goto tr_stalled; 2198 } 2199 break; 2200 2201 case UT_WRITE_CLASS_OTHER: 2202 switch (req->bRequest) { 2203 case UR_CLEAR_FEATURE: 2204 goto tr_handle_clear_port_feature; 2205 case UR_SET_FEATURE: 2206 goto tr_handle_set_port_feature; 2207 case UR_CLEAR_TT_BUFFER: 2208 case UR_RESET_TT: 2209 case UR_STOP_TT: 2210 goto tr_valid; 2211 2212 default: 2213 goto tr_stalled; 2214 } 2215 break; 2216 2217 case UT_READ_CLASS_OTHER: 2218 switch (req->bRequest) { 2219 case UR_GET_TT_STATE: 2220 goto tr_handle_get_tt_state; 2221 case UR_GET_STATUS: 2222 goto tr_handle_get_port_status; 2223 default: 2224 goto tr_stalled; 2225 } 2226 break; 2227 2228 case UT_READ_CLASS_DEVICE: 2229 switch (req->bRequest) { 2230 case UR_GET_DESCRIPTOR: 2231 goto tr_handle_get_class_descriptor; 2232 case UR_GET_STATUS: 2233 goto tr_handle_get_class_status; 2234 2235 default: 2236 goto tr_stalled; 2237 } 2238 break; 2239 default: 2240 goto tr_stalled; 2241 } 2242 goto tr_valid; 2243 2244 tr_handle_get_descriptor: 2245 switch (value >> 8) { 2246 case UDESC_DEVICE: 2247 if (value & 0xff) { 2248 goto tr_stalled; 2249 } 2250 len = sizeof(dwc_otg_devd); 2251 ptr = (const void *)&dwc_otg_devd; 2252 goto tr_valid; 2253 case UDESC_CONFIG: 2254 if (value & 0xff) { 2255 goto tr_stalled; 2256 } 2257 len = sizeof(dwc_otg_confd); 2258 ptr = (const void *)&dwc_otg_confd; 2259 goto tr_valid; 2260 case UDESC_STRING: 2261 switch (value & 0xff) { 2262 case 0: /* Language table */ 2263 len = sizeof(dwc_otg_langtab); 2264 ptr = (const void *)&dwc_otg_langtab; 2265 goto tr_valid; 2266 2267 case 1: /* Vendor */ 2268 len = sizeof(dwc_otg_vendor); 2269 ptr = (const void *)&dwc_otg_vendor; 2270 goto tr_valid; 2271 2272 case 2: /* Product */ 2273 len = sizeof(dwc_otg_product); 2274 ptr = (const void *)&dwc_otg_product; 2275 goto tr_valid; 2276 default: 2277 break; 2278 } 2279 break; 2280 default: 2281 goto tr_stalled; 2282 } 2283 goto tr_stalled; 2284 2285 tr_handle_get_config: 2286 len = 1; 2287 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2288 goto tr_valid; 2289 2290 tr_handle_get_status: 2291 len = 2; 2292 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2293 goto tr_valid; 2294 2295 tr_handle_set_address: 2296 if (value & 0xFF00) { 2297 goto tr_stalled; 2298 } 2299 sc->sc_rt_addr = value; 2300 goto tr_valid; 2301 2302 tr_handle_set_config: 2303 if (value >= 2) { 2304 goto tr_stalled; 2305 } 2306 sc->sc_conf = value; 2307 goto tr_valid; 2308 2309 tr_handle_get_interface: 2310 len = 1; 2311 sc->sc_hub_temp.wValue[0] = 0; 2312 goto tr_valid; 2313 2314 tr_handle_get_tt_state: 2315 tr_handle_get_class_status: 2316 tr_handle_get_iface_status: 2317 tr_handle_get_ep_status: 2318 len = 2; 2319 USETW(sc->sc_hub_temp.wValue, 0); 2320 goto tr_valid; 2321 2322 tr_handle_set_halt: 2323 tr_handle_set_interface: 2324 tr_handle_set_wakeup: 2325 tr_handle_clear_wakeup: 2326 tr_handle_clear_halt: 2327 goto tr_valid; 2328 2329 tr_handle_clear_port_feature: 2330 if (index != 1) { 2331 goto tr_stalled; 2332 } 2333 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2334 2335 switch (value) { 2336 case UHF_PORT_SUSPEND: 2337 dwc_otg_wakeup_peer(sc); 2338 break; 2339 2340 case UHF_PORT_ENABLE: 2341 sc->sc_flags.port_enabled = 0; 2342 break; 2343 2344 case UHF_PORT_TEST: 2345 case UHF_PORT_INDICATOR: 2346 case UHF_C_PORT_ENABLE: 2347 case UHF_C_PORT_OVER_CURRENT: 2348 case UHF_C_PORT_RESET: 2349 /* nops */ 2350 break; 2351 case UHF_PORT_POWER: 2352 sc->sc_flags.port_powered = 0; 2353 dwc_otg_pull_down(sc); 2354 dwc_otg_clocks_off(sc); 2355 break; 2356 case UHF_C_PORT_CONNECTION: 2357 /* clear connect change flag */ 2358 sc->sc_flags.change_connect = 0; 2359 2360 if (!sc->sc_flags.status_bus_reset) { 2361 /* we are not connected */ 2362 break; 2363 } 2364 break; 2365 case UHF_C_PORT_SUSPEND: 2366 sc->sc_flags.change_suspend = 0; 2367 break; 2368 default: 2369 err = USB_ERR_IOERROR; 2370 goto done; 2371 } 2372 goto tr_valid; 2373 2374 tr_handle_set_port_feature: 2375 if (index != 1) { 2376 goto tr_stalled; 2377 } 2378 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2379 2380 switch (value) { 2381 case UHF_PORT_ENABLE: 2382 sc->sc_flags.port_enabled = 1; 2383 break; 2384 case UHF_PORT_SUSPEND: 2385 case UHF_PORT_RESET: 2386 case UHF_PORT_TEST: 2387 case UHF_PORT_INDICATOR: 2388 /* nops */ 2389 break; 2390 case UHF_PORT_POWER: 2391 sc->sc_flags.port_powered = 1; 2392 break; 2393 default: 2394 err = USB_ERR_IOERROR; 2395 goto done; 2396 } 2397 goto tr_valid; 2398 2399 tr_handle_get_port_status: 2400 2401 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2402 2403 if (index != 1) { 2404 goto tr_stalled; 2405 } 2406 if (sc->sc_flags.status_vbus) { 2407 dwc_otg_clocks_on(sc); 2408 } else { 2409 dwc_otg_clocks_off(sc); 2410 } 2411 2412 /* Select Device Side Mode */ 2413 2414 value = UPS_PORT_MODE_DEVICE; 2415 2416 if (sc->sc_flags.status_high_speed) { 2417 value |= UPS_HIGH_SPEED; 2418 } 2419 if (sc->sc_flags.port_powered) { 2420 value |= UPS_PORT_POWER; 2421 } 2422 if (sc->sc_flags.port_enabled) { 2423 value |= UPS_PORT_ENABLED; 2424 } 2425 if (sc->sc_flags.status_vbus && 2426 sc->sc_flags.status_bus_reset) { 2427 value |= UPS_CURRENT_CONNECT_STATUS; 2428 } 2429 if (sc->sc_flags.status_suspend) { 2430 value |= UPS_SUSPEND; 2431 } 2432 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2433 2434 value = 0; 2435 2436 if (sc->sc_flags.change_connect) { 2437 value |= UPS_C_CONNECT_STATUS; 2438 } 2439 if (sc->sc_flags.change_suspend) { 2440 value |= UPS_C_SUSPEND; 2441 } 2442 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2443 len = sizeof(sc->sc_hub_temp.ps); 2444 goto tr_valid; 2445 2446 tr_handle_get_class_descriptor: 2447 if (value & 0xFF) { 2448 goto tr_stalled; 2449 } 2450 ptr = (const void *)&dwc_otg_hubd; 2451 len = sizeof(dwc_otg_hubd); 2452 goto tr_valid; 2453 2454 tr_stalled: 2455 err = USB_ERR_STALLED; 2456 tr_valid: 2457 done: 2458 *plength = len; 2459 *pptr = ptr; 2460 return (err); 2461 } 2462 2463 static void 2464 dwc_otg_xfer_setup(struct usb_setup_params *parm) 2465 { 2466 const struct usb_hw_ep_profile *pf; 2467 struct usb_xfer *xfer; 2468 void *last_obj; 2469 uint32_t ntd; 2470 uint32_t n; 2471 uint8_t ep_no; 2472 2473 xfer = parm->curr_xfer; 2474 2475 /* 2476 * NOTE: This driver does not use any of the parameters that 2477 * are computed from the following values. Just set some 2478 * reasonable dummies: 2479 */ 2480 parm->hc_max_packet_size = 0x500; 2481 parm->hc_max_packet_count = 1; 2482 parm->hc_max_frame_size = 0x500; 2483 2484 usbd_transfer_setup_sub(parm); 2485 2486 /* 2487 * compute maximum number of TDs 2488 */ 2489 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2490 2491 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2492 + 1 /* SYNC 2 */ ; 2493 } else { 2494 2495 ntd = xfer->nframes + 1 /* SYNC */ ; 2496 } 2497 2498 /* 2499 * check if "usbd_transfer_setup_sub" set an error 2500 */ 2501 if (parm->err) 2502 return; 2503 2504 /* 2505 * allocate transfer descriptors 2506 */ 2507 last_obj = NULL; 2508 2509 /* 2510 * get profile stuff 2511 */ 2512 ep_no = xfer->endpointno & UE_ADDR; 2513 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2514 2515 if (pf == NULL) { 2516 /* should not happen */ 2517 parm->err = USB_ERR_INVAL; 2518 return; 2519 } 2520 2521 /* align data */ 2522 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2523 2524 for (n = 0; n != ntd; n++) { 2525 2526 struct dwc_otg_td *td; 2527 2528 if (parm->buf) { 2529 2530 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2531 2532 /* init TD */ 2533 td->max_packet_size = xfer->max_packet_size; 2534 td->ep_no = ep_no; 2535 td->obj_next = last_obj; 2536 2537 last_obj = td; 2538 } 2539 parm->size[0] += sizeof(*td); 2540 } 2541 2542 xfer->td_start[0] = last_obj; 2543 } 2544 2545 static void 2546 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 2547 { 2548 return; 2549 } 2550 2551 static void 2552 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2553 struct usb_endpoint *ep) 2554 { 2555 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2556 2557 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2558 ep, udev->address, 2559 edesc->bEndpointAddress, udev->flags.usb_mode, 2560 sc->sc_rt_addr, udev->device_index); 2561 2562 if (udev->device_index != sc->sc_rt_addr) { 2563 2564 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2565 /* not supported */ 2566 return; 2567 } 2568 if (udev->speed != USB_SPEED_FULL && 2569 udev->speed != USB_SPEED_HIGH) { 2570 /* not supported */ 2571 return; 2572 } 2573 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2574 ep->methods = &dwc_otg_device_isoc_fs_methods; 2575 else 2576 ep->methods = &dwc_otg_device_non_isoc_methods; 2577 } 2578 } 2579 2580 static void 2581 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2582 { 2583 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 2584 2585 switch (state) { 2586 case USB_HW_POWER_SUSPEND: 2587 dwc_otg_suspend(sc); 2588 break; 2589 case USB_HW_POWER_SHUTDOWN: 2590 dwc_otg_uninit(sc); 2591 break; 2592 case USB_HW_POWER_RESUME: 2593 dwc_otg_resume(sc); 2594 break; 2595 default: 2596 break; 2597 } 2598 } 2599 2600 struct usb_bus_methods dwc_otg_bus_methods = 2601 { 2602 .endpoint_init = &dwc_otg_ep_init, 2603 .xfer_setup = &dwc_otg_xfer_setup, 2604 .xfer_unsetup = &dwc_otg_xfer_unsetup, 2605 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 2606 .set_stall = &dwc_otg_set_stall, 2607 .clear_stall = &dwc_otg_clear_stall, 2608 .roothub_exec = &dwc_otg_roothub_exec, 2609 .xfer_poll = &dwc_otg_do_poll, 2610 .device_state_change = &dwc_otg_device_state_change, 2611 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 2612 }; 2613