1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2SC(pc) \ 93 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTSTS_ENUMDONE | \ 97 GINTSTS_USBRST | \ 98 GINTSTS_USBSUSP | \ 99 GINTSTS_IEPINT | \ 100 GINTSTS_RXFLVL | \ 101 GINTSTS_SESSREQINT | \ 102 GINTMSK_OTGINTMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTSTS_PRTINT) 105 106 static int dwc_otg_use_hsic; 107 108 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 109 110 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 111 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 112 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 113 114 #ifdef USB_DEBUG 115 static int dwc_otg_debug; 116 117 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 118 &dwc_otg_debug, 0, "DWC OTG debug level"); 119 #endif 120 121 #define DWC_OTG_INTR_ENDPT 1 122 123 /* prototypes */ 124 125 static const struct usb_bus_methods dwc_otg_bus_methods; 126 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 127 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 128 129 static dwc_otg_cmd_t dwc_otg_setup_rx; 130 static dwc_otg_cmd_t dwc_otg_data_rx; 131 static dwc_otg_cmd_t dwc_otg_data_tx; 132 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 133 134 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 135 static dwc_otg_cmd_t dwc_otg_host_data_tx; 136 static dwc_otg_cmd_t dwc_otg_host_data_rx; 137 138 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 139 static void dwc_otg_do_poll(struct usb_bus *); 140 static void dwc_otg_standard_done(struct usb_xfer *); 141 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 142 static void dwc_otg_interrupt_poll(struct dwc_otg_softc *sc); 143 144 /* 145 * Here is a configuration that the chip supports. 146 */ 147 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 148 149 [0] = { 150 .max_in_frame_size = 64,/* fixed */ 151 .max_out_frame_size = 64, /* fixed */ 152 .is_simplex = 1, 153 .support_control = 1, 154 } 155 }; 156 157 static void 158 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 159 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 160 { 161 struct dwc_otg_softc *sc; 162 163 sc = DWC_OTG_BUS2SC(udev->bus); 164 165 if (ep_addr < sc->sc_dev_ep_max) 166 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 167 else 168 *ppf = NULL; 169 } 170 171 static int 172 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 173 { 174 struct dwc_otg_profile *pf; 175 uint32_t fifo_size; 176 uint32_t fifo_regs; 177 uint32_t tx_start; 178 uint8_t x; 179 180 fifo_size = sc->sc_fifo_size; 181 182 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 183 184 if (fifo_size >= fifo_regs) 185 fifo_size -= fifo_regs; 186 else 187 fifo_size = 0; 188 189 /* split equally for IN and OUT */ 190 fifo_size /= 2; 191 192 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 193 194 /* align to 4-bytes */ 195 fifo_size &= ~3; 196 197 tx_start = fifo_size; 198 199 if (fifo_size < 0x40) { 200 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 201 USB_BUS_UNLOCK(&sc->sc_bus); 202 return (EINVAL); 203 } 204 205 if (mode == DWC_MODE_HOST) { 206 207 /* reset active endpoints */ 208 sc->sc_active_rx_ep = 0; 209 210 fifo_size /= 2; 211 212 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 213 ((fifo_size / 4) << 16) | 214 (tx_start / 4)); 215 216 tx_start += fifo_size; 217 218 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 219 ((fifo_size / 4) << 16) | 220 (tx_start / 4)); 221 222 for (x = 0; x != sc->sc_host_ch_max; x++) { 223 /* enable interrupts */ 224 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 225 HCINT_STALL | HCINT_BBLERR | 226 HCINT_XACTERR | 227 HCINT_NAK | HCINT_ACK | HCINT_NYET | 228 HCINT_CHHLTD | HCINT_FRMOVRUN | 229 HCINT_DATATGLERR); 230 } 231 232 /* enable host channel interrupts */ 233 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 234 (1U << sc->sc_host_ch_max) - 1U); 235 } 236 237 if (mode == DWC_MODE_DEVICE) { 238 239 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 240 (0x10 << 16) | (tx_start / 4)); 241 fifo_size -= 0x40; 242 tx_start += 0x40; 243 244 /* setup control endpoint profile */ 245 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 246 247 /* reset active endpoints */ 248 sc->sc_active_rx_ep = 1; 249 250 for (x = 1; x != sc->sc_dev_ep_max; x++) { 251 252 pf = sc->sc_hw_ep_profile + x; 253 254 pf->usb.max_out_frame_size = 1024 * 3; 255 pf->usb.is_simplex = 0; /* assume duplex */ 256 pf->usb.support_bulk = 1; 257 pf->usb.support_interrupt = 1; 258 pf->usb.support_isochronous = 1; 259 pf->usb.support_out = 1; 260 261 if (x < sc->sc_dev_in_ep_max) { 262 uint32_t limit; 263 264 limit = (x == 1) ? DWC_OTG_MAX_TXN : 265 (DWC_OTG_MAX_TXN / 2); 266 267 if (fifo_size >= limit) { 268 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 269 ((limit / 4) << 16) | 270 (tx_start / 4)); 271 tx_start += limit; 272 fifo_size -= limit; 273 pf->usb.max_in_frame_size = 0x200; 274 pf->usb.support_in = 1; 275 pf->max_buffer = limit; 276 277 } else if (fifo_size >= 0x80) { 278 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 279 ((0x80 / 4) << 16) | (tx_start / 4)); 280 tx_start += 0x80; 281 fifo_size -= 0x80; 282 pf->usb.max_in_frame_size = 0x40; 283 pf->usb.support_in = 1; 284 285 } else { 286 pf->usb.is_simplex = 1; 287 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 288 (0x0 << 16) | (tx_start / 4)); 289 } 290 } else { 291 pf->usb.is_simplex = 1; 292 } 293 294 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 295 pf->usb.max_in_frame_size, 296 pf->usb.max_out_frame_size); 297 } 298 } 299 300 /* reset RX FIFO */ 301 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 302 GRSTCTL_RXFFLSH); 303 304 if (mode != DWC_MODE_OTG) { 305 /* reset all TX FIFOs */ 306 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 307 GRSTCTL_TXFIFO(0x10) | 308 GRSTCTL_TXFFLSH); 309 } else { 310 /* reset active endpoints */ 311 sc->sc_active_rx_ep = 0; 312 } 313 return (0); 314 } 315 316 static void 317 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 318 { 319 if (sc->sc_flags.clocks_off && 320 sc->sc_flags.port_powered) { 321 322 DPRINTFN(5, "\n"); 323 324 /* TODO - platform specific */ 325 326 sc->sc_flags.clocks_off = 0; 327 } 328 } 329 330 static void 331 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 332 { 333 if (!sc->sc_flags.clocks_off) { 334 335 DPRINTFN(5, "\n"); 336 337 /* TODO - platform specific */ 338 339 sc->sc_flags.clocks_off = 1; 340 } 341 } 342 343 static void 344 dwc_otg_pull_up(struct dwc_otg_softc *sc) 345 { 346 uint32_t temp; 347 348 /* pullup D+, if possible */ 349 350 if (!sc->sc_flags.d_pulled_up && 351 sc->sc_flags.port_powered) { 352 sc->sc_flags.d_pulled_up = 1; 353 354 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 355 temp &= ~DCTL_SFTDISCON; 356 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 357 } 358 } 359 360 static void 361 dwc_otg_pull_down(struct dwc_otg_softc *sc) 362 { 363 uint32_t temp; 364 365 /* pulldown D+, if possible */ 366 367 if (sc->sc_flags.d_pulled_up) { 368 sc->sc_flags.d_pulled_up = 0; 369 370 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 371 temp |= DCTL_SFTDISCON; 372 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 373 } 374 } 375 376 static void 377 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 378 { 379 if (sc->sc_irq_mask & GINTSTS_SOF) 380 return; 381 sc->sc_irq_mask |= GINTSTS_SOF; 382 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 383 } 384 385 static void 386 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 387 { 388 if (sc->sc_flags.status_suspend) { 389 /* update status bits */ 390 sc->sc_flags.status_suspend = 0; 391 sc->sc_flags.change_suspend = 1; 392 393 if (sc->sc_flags.status_device_mode) { 394 /* 395 * Disable resume interrupt and enable suspend 396 * interrupt: 397 */ 398 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 399 sc->sc_irq_mask |= GINTSTS_USBSUSP; 400 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 401 } 402 403 /* complete root HUB interrupt endpoint */ 404 dwc_otg_root_intr(sc); 405 } 406 } 407 408 static void 409 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 410 { 411 if (!sc->sc_flags.status_suspend) { 412 /* update status bits */ 413 sc->sc_flags.status_suspend = 1; 414 sc->sc_flags.change_suspend = 1; 415 416 if (sc->sc_flags.status_device_mode) { 417 /* 418 * Disable suspend interrupt and enable resume 419 * interrupt: 420 */ 421 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 422 sc->sc_irq_mask |= GINTSTS_WKUPINT; 423 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 424 } 425 426 /* complete root HUB interrupt endpoint */ 427 dwc_otg_root_intr(sc); 428 } 429 } 430 431 static void 432 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 433 { 434 if (!sc->sc_flags.status_suspend) 435 return; 436 437 DPRINTFN(5, "Remote wakeup\n"); 438 439 if (sc->sc_flags.status_device_mode) { 440 uint32_t temp; 441 442 /* enable remote wakeup signalling */ 443 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 444 temp |= DCTL_RMTWKUPSIG; 445 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 446 447 /* Wait 8ms for remote wakeup to complete. */ 448 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 449 450 temp &= ~DCTL_RMTWKUPSIG; 451 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 452 } else { 453 /* enable USB port */ 454 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 455 456 /* wait 10ms */ 457 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 458 459 /* resume port */ 460 sc->sc_hprt_val |= HPRT_PRTRES; 461 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 462 463 /* Wait 100ms for resume signalling to complete. */ 464 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 465 466 /* clear suspend and resume */ 467 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 468 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 469 470 /* Wait 4ms */ 471 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 472 } 473 474 /* need to fake resume IRQ */ 475 dwc_otg_resume_irq(sc); 476 } 477 478 static void 479 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 480 { 481 uint32_t temp; 482 483 DPRINTFN(5, "addr=%d\n", addr); 484 485 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 486 temp &= ~DCFG_DEVADDR_SET(0x7F); 487 temp |= DCFG_DEVADDR_SET(addr); 488 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 489 } 490 491 static void 492 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 493 { 494 DPRINTFN(5, "RX status clear\n"); 495 496 /* enable RX FIFO level interrupt */ 497 sc->sc_irq_mask |= GINTSTS_RXFLVL; 498 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 499 500 /* clear cached status */ 501 sc->sc_last_rx_status = 0; 502 } 503 504 static void 505 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 506 { 507 uint32_t hcint; 508 509 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 510 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 511 512 /* clear buffered interrupts */ 513 sc->sc_chan_state[x].hcint = 0; 514 } 515 516 static uint8_t 517 dwc_otg_host_channel_wait(struct dwc_otg_td *td) 518 { 519 struct dwc_otg_softc *sc; 520 uint8_t x; 521 522 x = td->channel; 523 524 DPRINTF("CH=%d\n", x); 525 526 /* get pointer to softc */ 527 sc = DWC_OTG_PC2SC(td->pc); 528 529 if (sc->sc_chan_state[x].wait_sof == 0) { 530 dwc_otg_clear_hcint(sc, x); 531 return (1); /* done */ 532 } 533 534 if (x == 0) 535 return (0); /* wait */ 536 537 /* find new disabled channel */ 538 for (x = 1; x != sc->sc_host_ch_max; x++) { 539 540 if (sc->sc_chan_state[x].allocated) 541 continue; 542 if (sc->sc_chan_state[x].wait_sof != 0) 543 continue; 544 545 sc->sc_chan_state[td->channel].allocated = 0; 546 sc->sc_chan_state[x].allocated = 1; 547 548 if (sc->sc_chan_state[td->channel].suspended) { 549 sc->sc_chan_state[td->channel].suspended = 0; 550 sc->sc_chan_state[x].suspended = 1; 551 } 552 553 /* clear interrupts */ 554 dwc_otg_clear_hcint(sc, x); 555 556 DPRINTF("CH=%d HCCHAR=0x%08x " 557 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 558 559 /* ack any pending messages */ 560 if (sc->sc_last_rx_status != 0 && 561 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == td->channel) { 562 /* get rid of message */ 563 dwc_otg_common_rx_ack(sc); 564 } 565 566 /* move active channel */ 567 sc->sc_active_rx_ep &= ~(1 << td->channel); 568 sc->sc_active_rx_ep |= (1 << x); 569 570 /* set channel */ 571 td->channel = x; 572 573 return (1); /* new channel allocated */ 574 } 575 return (0); /* wait */ 576 } 577 578 static uint8_t 579 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 580 { 581 struct dwc_otg_softc *sc; 582 uint8_t x; 583 uint8_t max_channel; 584 585 if (td->channel < DWC_OTG_MAX_CHANNELS) 586 return (0); /* already allocated */ 587 588 /* get pointer to softc */ 589 sc = DWC_OTG_PC2SC(td->pc); 590 591 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 592 max_channel = 1; 593 x = 0; 594 } else { 595 max_channel = sc->sc_host_ch_max; 596 x = 1; 597 } 598 599 for (; x != max_channel; x++) { 600 601 if (sc->sc_chan_state[x].allocated) 602 continue; 603 if (sc->sc_chan_state[x].wait_sof != 0) 604 continue; 605 606 sc->sc_chan_state[x].allocated = 1; 607 608 /* clear interrupts */ 609 dwc_otg_clear_hcint(sc, x); 610 611 DPRINTF("CH=%d HCCHAR=0x%08x " 612 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 613 614 /* set active channel */ 615 sc->sc_active_rx_ep |= (1 << x); 616 617 /* set channel */ 618 td->channel = x; 619 620 return (0); /* allocated */ 621 } 622 return (1); /* busy */ 623 } 624 625 static void 626 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 627 { 628 uint32_t hcchar; 629 if (sc->sc_chan_state[x].wait_sof != 0) 630 return; 631 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 632 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 633 /* disable channel */ 634 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 635 HCCHAR_CHENA | HCCHAR_CHDIS); 636 /* don't re-use channel until next SOF is transmitted */ 637 sc->sc_chan_state[x].wait_sof = 2; 638 /* enable SOF interrupt */ 639 dwc_otg_enable_sof_irq(sc); 640 } 641 } 642 643 static void 644 dwc_otg_host_channel_free(struct dwc_otg_td *td) 645 { 646 struct dwc_otg_softc *sc; 647 uint8_t x; 648 649 if (td->channel >= DWC_OTG_MAX_CHANNELS) 650 return; /* already freed */ 651 652 /* free channel */ 653 x = td->channel; 654 td->channel = DWC_OTG_MAX_CHANNELS; 655 656 DPRINTF("CH=%d\n", x); 657 658 /* get pointer to softc */ 659 sc = DWC_OTG_PC2SC(td->pc); 660 661 dwc_otg_host_channel_disable(sc, x); 662 663 sc->sc_chan_state[x].allocated = 0; 664 sc->sc_chan_state[x].suspended = 0; 665 666 /* ack any pending messages */ 667 if (sc->sc_last_rx_status != 0 && 668 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 669 dwc_otg_common_rx_ack(sc); 670 } 671 672 /* clear active channel */ 673 sc->sc_active_rx_ep &= ~(1 << x); 674 } 675 676 static uint8_t 677 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 678 { 679 struct usb_device_request req __aligned(4); 680 struct dwc_otg_softc *sc; 681 uint32_t hcint; 682 uint32_t hcchar; 683 684 if (dwc_otg_host_channel_alloc(td)) 685 return (1); /* busy */ 686 687 /* get pointer to softc */ 688 sc = DWC_OTG_PC2SC(td->pc); 689 690 hcint = sc->sc_chan_state[td->channel].hcint; 691 692 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 693 td->channel, td->state, hcint, 694 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 695 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 696 697 if (hcint & (HCINT_RETRY | 698 HCINT_ACK | HCINT_NYET)) { 699 /* give success bits priority over failure bits */ 700 } else if (hcint & HCINT_STALL) { 701 DPRINTF("CH=%d STALL\n", td->channel); 702 td->error_stall = 1; 703 td->error_any = 1; 704 return (0); /* complete */ 705 } else if (hcint & HCINT_ERRORS) { 706 DPRINTF("CH=%d ERROR\n", td->channel); 707 td->errcnt++; 708 if (td->hcsplt != 0 || td->errcnt >= 3) { 709 td->error_any = 1; 710 return (0); /* complete */ 711 } 712 } 713 714 /* channel must be disabled before we can complete the transfer */ 715 716 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 717 HCINT_ACK | HCINT_NYET)) { 718 719 dwc_otg_host_channel_disable(sc, td->channel); 720 721 if (!(hcint & HCINT_ERRORS)) 722 td->errcnt = 0; 723 } 724 725 switch (td->state) { 726 case DWC_CHAN_ST_START: 727 goto send_pkt; 728 729 case DWC_CHAN_ST_WAIT_ANE: 730 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 731 if (!dwc_otg_host_channel_wait(td)) 732 break; 733 td->did_nak = 1; 734 goto send_pkt; 735 } 736 if (hcint & (HCINT_ACK | HCINT_NYET)) { 737 if (!dwc_otg_host_channel_wait(td)) 738 break; 739 td->offset += td->tx_bytes; 740 td->remainder -= td->tx_bytes; 741 td->toggle = 1; 742 return (0); /* complete */ 743 } 744 break; 745 case DWC_CHAN_ST_WAIT_S_ANE: 746 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 747 if (!dwc_otg_host_channel_wait(td)) 748 break; 749 td->did_nak = 1; 750 goto send_pkt; 751 } 752 if (hcint & (HCINT_ACK | HCINT_NYET)) { 753 if (!dwc_otg_host_channel_wait(td)) 754 break; 755 goto send_cpkt; 756 } 757 break; 758 case DWC_CHAN_ST_WAIT_C_ANE: 759 if (hcint & HCINT_NYET) { 760 if (!dwc_otg_host_channel_wait(td)) 761 break; 762 goto send_cpkt; 763 } 764 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 765 if (!dwc_otg_host_channel_wait(td)) 766 break; 767 td->did_nak = 1; 768 goto send_pkt; 769 } 770 if (hcint & HCINT_ACK) { 771 if (!dwc_otg_host_channel_wait(td)) 772 break; 773 td->offset += td->tx_bytes; 774 td->remainder -= td->tx_bytes; 775 td->toggle = 1; 776 return (0); /* complete */ 777 } 778 break; 779 case DWC_CHAN_ST_TX_PKT_SYNC: 780 goto send_pkt_sync; 781 default: 782 break; 783 } 784 return (1); /* busy */ 785 786 send_pkt: 787 if (sizeof(req) != td->remainder) { 788 td->error_any = 1; 789 return (0); /* complete */ 790 } 791 792 send_pkt_sync: 793 if (td->hcsplt != 0) { 794 uint32_t count; 795 796 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 797 /* check for not first microframe */ 798 if (count != 0) { 799 /* enable SOF interrupt */ 800 dwc_otg_enable_sof_irq(sc); 801 /* set state */ 802 td->state = DWC_CHAN_ST_TX_PKT_SYNC; 803 dwc_otg_host_channel_free(td); 804 return (1); /* busy */ 805 } 806 807 td->hcsplt &= ~HCSPLT_COMPSPLT; 808 td->state = DWC_CHAN_ST_WAIT_S_ANE; 809 } else { 810 td->state = DWC_CHAN_ST_WAIT_ANE; 811 } 812 813 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 814 815 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 816 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 817 (1 << HCTSIZ_PKTCNT_SHIFT) | 818 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 819 820 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 821 822 hcchar = td->hcchar; 823 hcchar &= ~HCCHAR_EPDIR_IN; 824 825 /* must enable channel before writing data to FIFO */ 826 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 827 828 /* transfer data into FIFO */ 829 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 830 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 831 832 /* store number of bytes transmitted */ 833 td->tx_bytes = sizeof(req); 834 835 return (1); /* busy */ 836 837 send_cpkt: 838 td->hcsplt |= HCSPLT_COMPSPLT; 839 td->state = DWC_CHAN_ST_WAIT_C_ANE; 840 841 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 842 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 843 844 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 845 846 hcchar = td->hcchar; 847 hcchar &= ~HCCHAR_EPDIR_IN; 848 849 /* must enable channel before writing data to FIFO */ 850 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 851 852 return (1); /* busy */ 853 } 854 855 static uint8_t 856 dwc_otg_setup_rx(struct dwc_otg_td *td) 857 { 858 struct dwc_otg_softc *sc; 859 struct usb_device_request req __aligned(4); 860 uint32_t temp; 861 uint16_t count; 862 863 /* get pointer to softc */ 864 sc = DWC_OTG_PC2SC(td->pc); 865 866 /* check endpoint status */ 867 868 if (sc->sc_last_rx_status == 0) 869 goto not_complete; 870 871 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 872 goto not_complete; 873 874 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 875 GRXSTSRD_DPID_DATA0) { 876 /* release FIFO */ 877 dwc_otg_common_rx_ack(sc); 878 goto not_complete; 879 } 880 881 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 882 GRXSTSRD_STP_DATA) { 883 /* release FIFO */ 884 dwc_otg_common_rx_ack(sc); 885 goto not_complete; 886 } 887 888 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 889 890 /* clear did stall */ 891 td->did_stall = 0; 892 893 /* get the packet byte count */ 894 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 895 896 /* verify data length */ 897 if (count != td->remainder) { 898 DPRINTFN(0, "Invalid SETUP packet " 899 "length, %d bytes\n", count); 900 /* release FIFO */ 901 dwc_otg_common_rx_ack(sc); 902 goto not_complete; 903 } 904 if (count != sizeof(req)) { 905 DPRINTFN(0, "Unsupported SETUP packet " 906 "length, %d bytes\n", count); 907 /* release FIFO */ 908 dwc_otg_common_rx_ack(sc); 909 goto not_complete; 910 } 911 912 /* copy in control request */ 913 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 914 915 /* copy data into real buffer */ 916 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 917 918 td->offset = sizeof(req); 919 td->remainder = 0; 920 921 /* sneak peek the set address */ 922 if ((req.bmRequestType == UT_WRITE_DEVICE) && 923 (req.bRequest == UR_SET_ADDRESS)) { 924 /* must write address before ZLP */ 925 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 926 } 927 928 /* don't send any data by default */ 929 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 930 DXEPTSIZ_SET_NPKT(0) | 931 DXEPTSIZ_SET_NBYTES(0)); 932 933 temp = sc->sc_in_ctl[0]; 934 935 /* enable IN endpoint */ 936 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 937 temp | DIEPCTL_EPENA); 938 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 939 temp | DIEPCTL_SNAK); 940 941 /* reset IN endpoint buffer */ 942 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 943 GRSTCTL_TXFIFO(0) | 944 GRSTCTL_TXFFLSH); 945 946 /* acknowledge RX status */ 947 dwc_otg_common_rx_ack(sc); 948 return (0); /* complete */ 949 950 not_complete: 951 /* abort any ongoing transfer, before enabling again */ 952 953 temp = sc->sc_out_ctl[0]; 954 955 temp |= DOEPCTL_EPENA | 956 DOEPCTL_SNAK; 957 958 /* enable OUT endpoint */ 959 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 960 961 if (!td->did_stall) { 962 td->did_stall = 1; 963 964 DPRINTFN(5, "stalling IN and OUT direction\n"); 965 966 /* set stall after enabling endpoint */ 967 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 968 temp | DOEPCTL_STALL); 969 970 temp = sc->sc_in_ctl[0]; 971 972 /* set stall assuming endpoint is enabled */ 973 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 974 temp | DIEPCTL_STALL); 975 } 976 977 /* setup number of buffers to receive */ 978 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 979 DXEPTSIZ_SET_MULTI(3) | 980 DXEPTSIZ_SET_NPKT(1) | 981 DXEPTSIZ_SET_NBYTES(sizeof(req))); 982 983 return (1); /* not complete */ 984 } 985 986 static uint8_t 987 dwc_otg_host_rate_check(struct dwc_otg_td *td) 988 { 989 struct dwc_otg_softc *sc; 990 uint8_t ep_type; 991 992 /* get pointer to softc */ 993 sc = DWC_OTG_PC2SC(td->pc); 994 995 ep_type = ((td->hcchar & 996 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 997 998 if (sc->sc_chan_state[td->channel].suspended) 999 goto busy; 1000 1001 if (ep_type == UE_ISOCHRONOUS) { 1002 if (td->tmr_val & 1) 1003 td->hcchar |= HCCHAR_ODDFRM; 1004 else 1005 td->hcchar &= ~HCCHAR_ODDFRM; 1006 td->tmr_val += td->tmr_res; 1007 } else if (ep_type == UE_INTERRUPT) { 1008 uint8_t delta; 1009 1010 delta = sc->sc_tmr_val - td->tmr_val; 1011 if (delta >= 128) 1012 goto busy; 1013 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1014 } else if (td->did_nak != 0) { 1015 goto busy; 1016 } 1017 1018 if (ep_type == UE_ISOCHRONOUS) { 1019 td->toggle = 0; 1020 } else if (td->set_toggle) { 1021 td->set_toggle = 0; 1022 td->toggle = 1; 1023 } 1024 return (0); 1025 busy: 1026 return (1); 1027 } 1028 1029 static uint8_t 1030 dwc_otg_host_data_rx(struct dwc_otg_td *td) 1031 { 1032 struct dwc_otg_softc *sc; 1033 uint32_t hcint; 1034 uint32_t hcchar; 1035 uint32_t count; 1036 uint8_t ep_type; 1037 1038 if (dwc_otg_host_channel_alloc(td)) 1039 return (1); /* busy */ 1040 1041 /* get pointer to softc */ 1042 sc = DWC_OTG_PC2SC(td->pc); 1043 1044 ep_type = ((td->hcchar & 1045 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1046 1047 hcint = sc->sc_chan_state[td->channel].hcint; 1048 1049 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1050 td->channel, td->state, hcint, 1051 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1052 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1053 1054 /* check interrupt bits */ 1055 1056 if (hcint & (HCINT_RETRY | 1057 HCINT_ACK | HCINT_NYET)) { 1058 /* give success bits priority over failure bits */ 1059 } else if (hcint & HCINT_STALL) { 1060 DPRINTF("CH=%d STALL\n", td->channel); 1061 td->error_stall = 1; 1062 td->error_any = 1; 1063 return (0); /* complete */ 1064 } else if (hcint & HCINT_ERRORS) { 1065 DPRINTF("CH=%d ERROR\n", td->channel); 1066 td->errcnt++; 1067 if (td->hcsplt != 0 || td->errcnt >= 3) { 1068 td->error_any = 1; 1069 return (0); /* complete */ 1070 } 1071 } 1072 1073 /* channel must be disabled before we can complete the transfer */ 1074 1075 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1076 HCINT_ACK | HCINT_NYET)) { 1077 1078 dwc_otg_host_channel_disable(sc, td->channel); 1079 1080 if (!(hcint & HCINT_ERRORS)) 1081 td->errcnt = 0; 1082 } 1083 1084 /* check endpoint status */ 1085 if (sc->sc_last_rx_status == 0) 1086 goto check_state; 1087 1088 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 1089 goto check_state; 1090 1091 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1092 case GRXSTSRH_IN_DATA: 1093 1094 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1095 (int)td->state, (int)sc->sc_last_rx_status); 1096 1097 if (hcint & HCINT_SOFTWARE_ONLY) { 1098 /* 1099 * When using SPLIT transactions on interrupt 1100 * endpoints, sometimes data occurs twice. 1101 */ 1102 DPRINTF("Data already received\n"); 1103 break; 1104 } 1105 1106 td->toggle ^= 1; 1107 1108 /* get the packet byte count */ 1109 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1110 1111 /* verify the packet byte count */ 1112 if (count != td->max_packet_size) { 1113 if (count < td->max_packet_size) { 1114 /* we have a short packet */ 1115 td->short_pkt = 1; 1116 td->got_short = 1; 1117 } else { 1118 /* invalid USB packet */ 1119 td->error_any = 1; 1120 1121 /* release FIFO */ 1122 dwc_otg_common_rx_ack(sc); 1123 return (0); /* we are complete */ 1124 } 1125 } 1126 1127 /* verify the packet byte count */ 1128 if (count > td->remainder) { 1129 /* invalid USB packet */ 1130 td->error_any = 1; 1131 1132 /* release FIFO */ 1133 dwc_otg_common_rx_ack(sc); 1134 return (0); /* we are complete */ 1135 } 1136 1137 usbd_copy_in(td->pc, td->offset, 1138 sc->sc_rx_bounce_buffer, count); 1139 1140 td->remainder -= count; 1141 td->offset += count; 1142 hcint |= HCINT_SOFTWARE_ONLY | HCINT_ACK; 1143 sc->sc_chan_state[td->channel].hcint = hcint; 1144 break; 1145 1146 default: 1147 DPRINTF("OTHER\n"); 1148 break; 1149 } 1150 /* release FIFO */ 1151 dwc_otg_common_rx_ack(sc); 1152 1153 check_state: 1154 switch (td->state) { 1155 case DWC_CHAN_ST_START: 1156 if (td->hcsplt != 0) 1157 goto receive_spkt; 1158 else 1159 goto receive_pkt; 1160 1161 case DWC_CHAN_ST_WAIT_ANE: 1162 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1163 if (!dwc_otg_host_channel_wait(td)) 1164 break; 1165 1166 td->did_nak = 1; 1167 if (td->hcsplt != 0) 1168 goto receive_spkt; 1169 else 1170 goto receive_pkt; 1171 } 1172 if (!(hcint & HCINT_SOFTWARE_ONLY)) { 1173 if (hcint & HCINT_NYET) { 1174 if (td->hcsplt != 0) { 1175 if (!dwc_otg_host_channel_wait(td)) 1176 break; 1177 goto receive_pkt; 1178 } 1179 } 1180 break; 1181 } 1182 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1183 if (!dwc_otg_host_channel_wait(td)) 1184 break; 1185 1186 /* check if we are complete */ 1187 if ((td->remainder == 0) || (td->got_short != 0)) { 1188 if (td->short_pkt) 1189 return (0); /* complete */ 1190 1191 /* 1192 * Else need to receive a zero length 1193 * packet. 1194 */ 1195 } 1196 if (td->hcsplt != 0) 1197 goto receive_spkt; 1198 else 1199 goto receive_pkt; 1200 } 1201 break; 1202 1203 case DWC_CHAN_ST_WAIT_S_ANE: 1204 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1205 if (!dwc_otg_host_channel_wait(td)) 1206 break; 1207 1208 td->did_nak = 1; 1209 goto receive_spkt; 1210 } 1211 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1212 if (!dwc_otg_host_channel_wait(td)) 1213 break; 1214 goto receive_pkt; 1215 } 1216 break; 1217 1218 case DWC_CHAN_ST_RX_PKT: 1219 goto receive_pkt; 1220 1221 case DWC_CHAN_ST_RX_SPKT: 1222 goto receive_spkt; 1223 1224 case DWC_CHAN_ST_RX_SPKT_SYNC: 1225 goto receive_spkt_sync; 1226 1227 default: 1228 break; 1229 } 1230 goto busy; 1231 1232 receive_pkt: 1233 if (td->hcsplt != 0) { 1234 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1235 1236 /* check for even microframes */ 1237 if (count == td->curr_frame) { 1238 td->state = DWC_CHAN_ST_RX_PKT; 1239 dwc_otg_host_channel_free(td); 1240 /* enable SOF interrupt */ 1241 dwc_otg_enable_sof_irq(sc); 1242 goto busy; 1243 } else if (count == 0) { 1244 /* check for start split timeout */ 1245 goto receive_spkt; 1246 } 1247 1248 td->curr_frame = count; 1249 td->hcsplt |= HCSPLT_COMPSPLT; 1250 } else if (dwc_otg_host_rate_check(td)) { 1251 td->state = DWC_CHAN_ST_RX_PKT; 1252 dwc_otg_host_channel_free(td); 1253 goto busy; 1254 } 1255 1256 td->state = DWC_CHAN_ST_WAIT_ANE; 1257 1258 /* receive one packet */ 1259 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1260 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1261 (1 << HCTSIZ_PKTCNT_SHIFT) | 1262 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1263 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1264 1265 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1266 1267 hcchar = td->hcchar; 1268 hcchar |= HCCHAR_EPDIR_IN; 1269 1270 /* must enable channel before data can be received */ 1271 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1272 1273 goto busy; 1274 1275 receive_spkt: 1276 if (dwc_otg_host_rate_check(td)) { 1277 td->state = DWC_CHAN_ST_RX_SPKT; 1278 dwc_otg_host_channel_free(td); 1279 goto busy; 1280 } 1281 1282 receive_spkt_sync: 1283 if (ep_type == UE_INTERRUPT || 1284 ep_type == UE_ISOCHRONOUS) { 1285 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1286 td->curr_frame = count; 1287 1288 /* check for non-zero microframe */ 1289 if (count != 0) { 1290 /* enable SOF interrupt */ 1291 dwc_otg_enable_sof_irq(sc); 1292 /* set state */ 1293 td->state = DWC_CHAN_ST_RX_SPKT_SYNC; 1294 dwc_otg_host_channel_free(td); 1295 goto busy; 1296 } 1297 } else { 1298 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1299 td->curr_frame = count; 1300 1301 /* check for two last frames */ 1302 if (count >= 6) { 1303 /* enable SOF interrupt */ 1304 dwc_otg_enable_sof_irq(sc); 1305 /* set state */ 1306 td->state = DWC_CHAN_ST_RX_SPKT_SYNC; 1307 dwc_otg_host_channel_free(td); 1308 goto busy; 1309 } 1310 } 1311 1312 td->hcsplt &= ~HCSPLT_COMPSPLT; 1313 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1314 1315 /* receive one packet */ 1316 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1317 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1318 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1319 1320 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1321 1322 hcchar = td->hcchar; 1323 hcchar |= HCCHAR_EPDIR_IN; 1324 1325 /* must enable channel before data can be received */ 1326 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1327 1328 busy: 1329 return (1); /* busy */ 1330 } 1331 1332 static uint8_t 1333 dwc_otg_data_rx(struct dwc_otg_td *td) 1334 { 1335 struct dwc_otg_softc *sc; 1336 uint32_t temp; 1337 uint16_t count; 1338 uint8_t got_short; 1339 1340 got_short = 0; 1341 1342 /* get pointer to softc */ 1343 sc = DWC_OTG_PC2SC(td->pc); 1344 1345 /* check endpoint status */ 1346 if (sc->sc_last_rx_status == 0) 1347 goto not_complete; 1348 1349 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1350 goto not_complete; 1351 1352 /* check for SETUP packet */ 1353 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1354 GRXSTSRD_STP_DATA) { 1355 if (td->remainder == 0) { 1356 /* 1357 * We are actually complete and have 1358 * received the next SETUP 1359 */ 1360 DPRINTFN(5, "faking complete\n"); 1361 return (0); /* complete */ 1362 } 1363 /* 1364 * USB Host Aborted the transfer. 1365 */ 1366 td->error_any = 1; 1367 return (0); /* complete */ 1368 } 1369 1370 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1371 GRXSTSRD_OUT_DATA) { 1372 /* release FIFO */ 1373 dwc_otg_common_rx_ack(sc); 1374 goto not_complete; 1375 } 1376 1377 /* get the packet byte count */ 1378 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1379 1380 /* verify the packet byte count */ 1381 if (count != td->max_packet_size) { 1382 if (count < td->max_packet_size) { 1383 /* we have a short packet */ 1384 td->short_pkt = 1; 1385 got_short = 1; 1386 } else { 1387 /* invalid USB packet */ 1388 td->error_any = 1; 1389 1390 /* release FIFO */ 1391 dwc_otg_common_rx_ack(sc); 1392 return (0); /* we are complete */ 1393 } 1394 } 1395 /* verify the packet byte count */ 1396 if (count > td->remainder) { 1397 /* invalid USB packet */ 1398 td->error_any = 1; 1399 1400 /* release FIFO */ 1401 dwc_otg_common_rx_ack(sc); 1402 return (0); /* we are complete */ 1403 } 1404 1405 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1406 td->remainder -= count; 1407 td->offset += count; 1408 1409 /* release FIFO */ 1410 dwc_otg_common_rx_ack(sc); 1411 1412 /* check if we are complete */ 1413 if ((td->remainder == 0) || got_short) { 1414 if (td->short_pkt) { 1415 /* we are complete */ 1416 return (0); 1417 } 1418 /* else need to receive a zero length packet */ 1419 } 1420 1421 not_complete: 1422 1423 temp = sc->sc_out_ctl[td->ep_no]; 1424 1425 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1426 1427 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1428 1429 /* enable SETUP and transfer complete interrupt */ 1430 if (td->ep_no == 0) { 1431 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1432 DXEPTSIZ_SET_NPKT(1) | 1433 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1434 } else { 1435 /* allow reception of multiple packets */ 1436 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1437 DXEPTSIZ_SET_MULTI(1) | 1438 DXEPTSIZ_SET_NPKT(4) | 1439 DXEPTSIZ_SET_NBYTES(4 * 1440 ((td->max_packet_size + 3) & ~3))); 1441 } 1442 return (1); /* not complete */ 1443 } 1444 1445 static uint8_t 1446 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1447 { 1448 struct dwc_otg_softc *sc; 1449 uint32_t count; 1450 uint32_t hcint; 1451 uint32_t hcchar; 1452 uint8_t ep_type; 1453 1454 if (dwc_otg_host_channel_alloc(td)) 1455 return (1); /* busy */ 1456 1457 /* get pointer to softc */ 1458 sc = DWC_OTG_PC2SC(td->pc); 1459 1460 ep_type = ((td->hcchar & 1461 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1462 1463 hcint = sc->sc_chan_state[td->channel].hcint; 1464 1465 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1466 td->channel, td->state, hcint, 1467 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1468 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1469 1470 if (hcint & (HCINT_RETRY | 1471 HCINT_ACK | HCINT_NYET)) { 1472 /* give success bits priority over failure bits */ 1473 } else if (hcint & HCINT_STALL) { 1474 DPRINTF("CH=%d STALL\n", td->channel); 1475 td->error_stall = 1; 1476 td->error_any = 1; 1477 return (0); /* complete */ 1478 } else if (hcint & HCINT_ERRORS) { 1479 DPRINTF("CH=%d ERROR\n", td->channel); 1480 td->errcnt++; 1481 if (td->hcsplt != 0 || td->errcnt >= 3) { 1482 td->error_any = 1; 1483 return (0); /* complete */ 1484 } 1485 } 1486 1487 /* channel must be disabled before we can complete the transfer */ 1488 1489 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1490 HCINT_ACK | HCINT_NYET)) { 1491 1492 dwc_otg_host_channel_disable(sc, td->channel); 1493 1494 if (!(hcint & HCINT_ERRORS)) 1495 td->errcnt = 0; 1496 } 1497 1498 switch (td->state) { 1499 case DWC_CHAN_ST_START: 1500 goto send_pkt; 1501 1502 case DWC_CHAN_ST_WAIT_ANE: 1503 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1504 if (!dwc_otg_host_channel_wait(td)) 1505 break; 1506 td->did_nak = 1; 1507 goto send_pkt; 1508 } 1509 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1510 if (!dwc_otg_host_channel_wait(td)) 1511 break; 1512 1513 td->offset += td->tx_bytes; 1514 td->remainder -= td->tx_bytes; 1515 td->toggle ^= 1; 1516 1517 /* check remainder */ 1518 if (td->remainder == 0) { 1519 if (td->short_pkt) 1520 return (0); /* complete */ 1521 1522 /* 1523 * Else we need to transmit a short 1524 * packet: 1525 */ 1526 } 1527 goto send_pkt; 1528 } 1529 break; 1530 case DWC_CHAN_ST_WAIT_S_ANE: 1531 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1532 if (!dwc_otg_host_channel_wait(td)) 1533 break; 1534 td->did_nak = 1; 1535 goto send_pkt; 1536 } 1537 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1538 if (!dwc_otg_host_channel_wait(td)) 1539 break; 1540 goto send_cpkt; 1541 } 1542 break; 1543 case DWC_CHAN_ST_WAIT_C_ANE: 1544 if (hcint & HCINT_NYET) { 1545 if (!dwc_otg_host_channel_wait(td)) 1546 break; 1547 goto send_cpkt; 1548 } 1549 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1550 if (!dwc_otg_host_channel_wait(td)) 1551 break; 1552 td->did_nak = 1; 1553 goto send_pkt; 1554 } 1555 if (hcint & HCINT_ACK) { 1556 if (!dwc_otg_host_channel_wait(td)) 1557 break; 1558 td->offset += td->tx_bytes; 1559 td->remainder -= td->tx_bytes; 1560 td->toggle ^= 1; 1561 1562 /* check remainder */ 1563 if (td->remainder == 0) { 1564 if (td->short_pkt) 1565 return (0); /* complete */ 1566 1567 /* else we need to transmit a short packet */ 1568 } 1569 goto send_pkt; 1570 } 1571 break; 1572 1573 case DWC_CHAN_ST_TX_PKT: 1574 goto send_pkt; 1575 1576 case DWC_CHAN_ST_TX_PKT_SYNC: 1577 goto send_pkt_sync; 1578 1579 case DWC_CHAN_ST_TX_CPKT: 1580 goto send_cpkt; 1581 1582 default: 1583 break; 1584 } 1585 goto busy; 1586 1587 send_pkt: 1588 if (dwc_otg_host_rate_check(td)) { 1589 td->state = DWC_CHAN_ST_TX_PKT; 1590 dwc_otg_host_channel_free(td); 1591 goto busy; 1592 } 1593 1594 send_pkt_sync: 1595 if (td->hcsplt != 0) { 1596 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1597 /* check for first or last microframe */ 1598 if (count == 7 || count == 0) { 1599 /* enable SOF interrupt */ 1600 dwc_otg_enable_sof_irq(sc); 1601 /* set state */ 1602 td->state = DWC_CHAN_ST_TX_PKT_SYNC; 1603 dwc_otg_host_channel_free(td); 1604 goto busy; 1605 } 1606 1607 td->hcsplt &= ~HCSPLT_COMPSPLT; 1608 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1609 } else { 1610 td->state = DWC_CHAN_ST_WAIT_ANE; 1611 } 1612 1613 /* send one packet at a time */ 1614 count = td->max_packet_size; 1615 if (td->remainder < count) { 1616 /* we have a short packet */ 1617 td->short_pkt = 1; 1618 count = td->remainder; 1619 } 1620 1621 /* TODO: HCTSIZ_DOPNG */ 1622 1623 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1624 (count << HCTSIZ_XFERSIZE_SHIFT) | 1625 (1 << HCTSIZ_PKTCNT_SHIFT) | 1626 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1627 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1628 1629 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1630 1631 hcchar = td->hcchar; 1632 hcchar &= ~HCCHAR_EPDIR_IN; 1633 1634 /* must enable before writing data to FIFO */ 1635 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1636 1637 if (count != 0) { 1638 1639 /* clear topmost word before copy */ 1640 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1641 1642 /* copy out data */ 1643 usbd_copy_out(td->pc, td->offset, 1644 sc->sc_tx_bounce_buffer, count); 1645 1646 /* transfer data into FIFO */ 1647 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1648 DOTG_DFIFO(td->channel), 1649 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1650 } 1651 1652 /* store number of bytes transmitted */ 1653 td->tx_bytes = count; 1654 1655 goto busy; 1656 1657 send_cpkt: 1658 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1659 /* check for first microframe */ 1660 if (count == 0) { 1661 /* send packet again */ 1662 goto send_pkt; 1663 } 1664 1665 td->hcsplt |= HCSPLT_COMPSPLT; 1666 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1667 1668 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1669 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1670 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1671 1672 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1673 1674 hcchar = td->hcchar; 1675 hcchar &= ~HCCHAR_EPDIR_IN; 1676 1677 /* must enable channel before writing data to FIFO */ 1678 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1679 1680 busy: 1681 return (1); /* busy */ 1682 } 1683 1684 static uint8_t 1685 dwc_otg_data_tx(struct dwc_otg_td *td) 1686 { 1687 struct dwc_otg_softc *sc; 1688 uint32_t max_buffer; 1689 uint32_t count; 1690 uint32_t fifo_left; 1691 uint32_t mpkt; 1692 uint32_t temp; 1693 uint8_t to; 1694 1695 to = 3; /* don't loop forever! */ 1696 1697 /* get pointer to softc */ 1698 sc = DWC_OTG_PC2SC(td->pc); 1699 1700 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1701 1702 repeat: 1703 /* check for for endpoint 0 data */ 1704 1705 temp = sc->sc_last_rx_status; 1706 1707 if ((td->ep_no == 0) && (temp != 0) && 1708 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1709 1710 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1711 GRXSTSRD_STP_DATA) { 1712 1713 /* dump data - wrong direction */ 1714 dwc_otg_common_rx_ack(sc); 1715 } else { 1716 /* 1717 * The current transfer was cancelled 1718 * by the USB Host: 1719 */ 1720 td->error_any = 1; 1721 return (0); /* complete */ 1722 } 1723 } 1724 1725 /* fill in more TX data, if possible */ 1726 if (td->tx_bytes != 0) { 1727 1728 uint16_t cpkt; 1729 1730 /* check if packets have been transferred */ 1731 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1732 1733 /* get current packet number */ 1734 cpkt = DXEPTSIZ_GET_NPKT(temp); 1735 1736 if (cpkt >= td->npkt) { 1737 fifo_left = 0; 1738 } else { 1739 if (max_buffer != 0) { 1740 fifo_left = (td->npkt - cpkt) * 1741 td->max_packet_size; 1742 1743 if (fifo_left > max_buffer) 1744 fifo_left = max_buffer; 1745 } else { 1746 fifo_left = td->max_packet_size; 1747 } 1748 } 1749 1750 count = td->tx_bytes; 1751 if (count > fifo_left) 1752 count = fifo_left; 1753 1754 if (count != 0) { 1755 1756 /* clear topmost word before copy */ 1757 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1758 1759 /* copy out data */ 1760 usbd_copy_out(td->pc, td->offset, 1761 sc->sc_tx_bounce_buffer, count); 1762 1763 /* transfer data into FIFO */ 1764 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1765 DOTG_DFIFO(td->ep_no), 1766 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1767 1768 td->tx_bytes -= count; 1769 td->remainder -= count; 1770 td->offset += count; 1771 td->npkt = cpkt; 1772 } 1773 if (td->tx_bytes != 0) 1774 goto not_complete; 1775 1776 /* check remainder */ 1777 if (td->remainder == 0) { 1778 if (td->short_pkt) 1779 return (0); /* complete */ 1780 1781 /* else we need to transmit a short packet */ 1782 } 1783 } 1784 1785 if (!to--) 1786 goto not_complete; 1787 1788 /* check if not all packets have been transferred */ 1789 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1790 1791 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1792 1793 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 1794 "DIEPCTL=0x%08x\n", td->ep_no, 1795 DXEPTSIZ_GET_NPKT(temp), 1796 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 1797 1798 goto not_complete; 1799 } 1800 1801 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 1802 1803 /* try to optimise by sending more data */ 1804 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 1805 1806 /* send multiple packets at the same time */ 1807 mpkt = max_buffer / td->max_packet_size; 1808 1809 if (mpkt > 0x3FE) 1810 mpkt = 0x3FE; 1811 1812 count = td->remainder; 1813 if (count > 0x7FFFFF) 1814 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 1815 1816 td->npkt = count / td->max_packet_size; 1817 1818 /* 1819 * NOTE: We could use 0x3FE instead of "mpkt" in the 1820 * check below to get more throughput, but then we 1821 * have a dependency towards non-generic chip features 1822 * to disable the TX-FIFO-EMPTY interrupts on a per 1823 * endpoint basis. Increase the maximum buffer size of 1824 * the IN endpoint to increase the performance. 1825 */ 1826 if (td->npkt > mpkt) { 1827 td->npkt = mpkt; 1828 count = td->max_packet_size * mpkt; 1829 } else if ((count == 0) || (count % td->max_packet_size)) { 1830 /* we are transmitting a short packet */ 1831 td->npkt++; 1832 td->short_pkt = 1; 1833 } 1834 } else { 1835 /* send one packet at a time */ 1836 mpkt = 1; 1837 count = td->max_packet_size; 1838 if (td->remainder < count) { 1839 /* we have a short packet */ 1840 td->short_pkt = 1; 1841 count = td->remainder; 1842 } 1843 td->npkt = 1; 1844 } 1845 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 1846 DXEPTSIZ_SET_MULTI(1) | 1847 DXEPTSIZ_SET_NPKT(td->npkt) | 1848 DXEPTSIZ_SET_NBYTES(count)); 1849 1850 /* make room for buffering */ 1851 td->npkt += mpkt; 1852 1853 temp = sc->sc_in_ctl[td->ep_no]; 1854 1855 /* must enable before writing data to FIFO */ 1856 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 1857 DIEPCTL_EPENA | 1858 DIEPCTL_CNAK); 1859 1860 td->tx_bytes = count; 1861 1862 /* check remainder */ 1863 if (td->tx_bytes == 0 && 1864 td->remainder == 0) { 1865 if (td->short_pkt) 1866 return (0); /* complete */ 1867 1868 /* else we need to transmit a short packet */ 1869 } 1870 goto repeat; 1871 1872 not_complete: 1873 return (1); /* not complete */ 1874 } 1875 1876 static uint8_t 1877 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 1878 { 1879 struct dwc_otg_softc *sc; 1880 uint32_t temp; 1881 1882 /* get pointer to softc */ 1883 sc = DWC_OTG_PC2SC(td->pc); 1884 1885 /* 1886 * If all packets are transferred we are complete: 1887 */ 1888 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1889 1890 /* check that all packets have been transferred */ 1891 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1892 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 1893 goto not_complete; 1894 } 1895 return (0); 1896 1897 not_complete: 1898 1899 /* we only want to know if there is a SETUP packet or free IN packet */ 1900 1901 temp = sc->sc_last_rx_status; 1902 1903 if ((td->ep_no == 0) && (temp != 0) && 1904 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1905 1906 if ((temp & GRXSTSRD_PKTSTS_MASK) == 1907 GRXSTSRD_STP_DATA) { 1908 DPRINTFN(5, "faking complete\n"); 1909 /* 1910 * Race condition: We are complete! 1911 */ 1912 return (0); 1913 } else { 1914 /* dump data - wrong direction */ 1915 dwc_otg_common_rx_ack(sc); 1916 } 1917 } 1918 return (1); /* not complete */ 1919 } 1920 1921 static uint8_t 1922 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 1923 { 1924 struct dwc_otg_td *td; 1925 uint8_t toggle; 1926 uint8_t channel; 1927 uint8_t tmr_val; 1928 uint8_t tmr_res; 1929 1930 DPRINTFN(9, "\n"); 1931 1932 td = xfer->td_transfer_cache; 1933 1934 /* 1935 * If we are suspended in host mode and no channel is 1936 * allocated, simply return: 1937 */ 1938 if (xfer->xroot->udev->flags.self_suspended != 0 && 1939 xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST && 1940 td->channel >= DWC_OTG_MAX_CHANNELS) { 1941 return (1); /* not complete */ 1942 } 1943 while (1) { 1944 if ((td->func) (td)) { 1945 /* operation in progress */ 1946 break; 1947 } 1948 if (((void *)td) == xfer->td_transfer_last) { 1949 goto done; 1950 } 1951 if (td->error_any) { 1952 goto done; 1953 } else if (td->remainder > 0) { 1954 /* 1955 * We had a short transfer. If there is no alternate 1956 * next, stop processing ! 1957 */ 1958 if (!td->alt_next) 1959 goto done; 1960 } 1961 1962 /* 1963 * Fetch the next transfer descriptor and transfer 1964 * some flags to the next transfer descriptor 1965 */ 1966 tmr_res = td->tmr_res; 1967 tmr_val = td->tmr_val; 1968 toggle = td->toggle; 1969 channel = td->channel; 1970 td = td->obj_next; 1971 xfer->td_transfer_cache = td; 1972 td->toggle = toggle; /* transfer toggle */ 1973 td->channel = channel; /* transfer channel */ 1974 td->tmr_res = tmr_res; 1975 td->tmr_val = tmr_val; 1976 } 1977 return (1); /* not complete */ 1978 1979 done: 1980 /* compute all actual lengths */ 1981 1982 dwc_otg_standard_done(xfer); 1983 return (0); /* complete */ 1984 } 1985 1986 static void 1987 dwc_otg_timer(void *_sc) 1988 { 1989 struct dwc_otg_softc *sc = _sc; 1990 struct usb_xfer *xfer; 1991 struct dwc_otg_td *td; 1992 1993 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1994 1995 DPRINTF("\n"); 1996 1997 /* increment timer value */ 1998 sc->sc_tmr_val++; 1999 2000 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2001 td = xfer->td_transfer_cache; 2002 if (td != NULL) 2003 td->did_nak = 0; 2004 } 2005 2006 /* poll jobs */ 2007 dwc_otg_interrupt_poll(sc); 2008 2009 if (sc->sc_timer_active) { 2010 /* restart timer */ 2011 usb_callout_reset(&sc->sc_timer, 2012 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2013 &dwc_otg_timer, sc); 2014 } 2015 } 2016 2017 static void 2018 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2019 { 2020 if (sc->sc_timer_active != 0) 2021 return; 2022 2023 sc->sc_timer_active = 1; 2024 2025 /* restart timer */ 2026 usb_callout_reset(&sc->sc_timer, 2027 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2028 &dwc_otg_timer, sc); 2029 } 2030 2031 static void 2032 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2033 { 2034 if (sc->sc_timer_active == 0) 2035 return; 2036 2037 sc->sc_timer_active = 0; 2038 2039 /* stop timer */ 2040 usb_callout_stop(&sc->sc_timer); 2041 } 2042 2043 static void 2044 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 2045 { 2046 struct usb_xfer *xfer; 2047 uint32_t temp; 2048 uint8_t got_rx_status; 2049 uint8_t x; 2050 2051 repeat: 2052 /* get all channel interrupts */ 2053 for (x = 0; x != sc->sc_host_ch_max; x++) { 2054 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2055 if (temp != 0) { 2056 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2057 temp &= ~HCINT_SOFTWARE_ONLY; 2058 sc->sc_chan_state[x].hcint |= temp; 2059 } 2060 } 2061 2062 if (sc->sc_last_rx_status == 0) { 2063 2064 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2065 if (temp & GINTSTS_RXFLVL) { 2066 /* pop current status */ 2067 sc->sc_last_rx_status = 2068 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2069 } 2070 2071 if (sc->sc_last_rx_status != 0) { 2072 2073 uint8_t ep_no; 2074 2075 temp = sc->sc_last_rx_status & 2076 GRXSTSRD_PKTSTS_MASK; 2077 2078 /* non-data messages we simply skip */ 2079 if (temp != GRXSTSRD_STP_DATA && 2080 temp != GRXSTSRD_OUT_DATA) { 2081 dwc_otg_common_rx_ack(sc); 2082 goto repeat; 2083 } 2084 2085 temp = GRXSTSRD_BCNT_GET( 2086 sc->sc_last_rx_status); 2087 ep_no = GRXSTSRD_CHNUM_GET( 2088 sc->sc_last_rx_status); 2089 2090 /* receive data, if any */ 2091 if (temp != 0) { 2092 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2093 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2094 DOTG_DFIFO(ep_no), 2095 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2096 } 2097 2098 /* check if we should dump the data */ 2099 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2100 dwc_otg_common_rx_ack(sc); 2101 goto repeat; 2102 } 2103 2104 got_rx_status = 1; 2105 2106 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2107 sc->sc_last_rx_status, ep_no, 2108 (sc->sc_last_rx_status >> 15) & 3, 2109 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2110 (sc->sc_last_rx_status >> 17) & 15); 2111 } else { 2112 got_rx_status = 0; 2113 } 2114 } else { 2115 uint8_t ep_no; 2116 2117 ep_no = GRXSTSRD_CHNUM_GET( 2118 sc->sc_last_rx_status); 2119 2120 /* check if we should dump the data */ 2121 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2122 dwc_otg_common_rx_ack(sc); 2123 goto repeat; 2124 } 2125 2126 got_rx_status = 1; 2127 } 2128 2129 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2130 if (!dwc_otg_xfer_do_fifo(xfer)) { 2131 /* queue has been modified */ 2132 goto repeat; 2133 } 2134 } 2135 2136 if (got_rx_status) { 2137 /* check if data was consumed */ 2138 if (sc->sc_last_rx_status == 0) 2139 goto repeat; 2140 2141 /* disable RX FIFO level interrupt */ 2142 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 2143 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2144 } 2145 } 2146 2147 static void 2148 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2149 { 2150 DPRINTFN(5, "vbus = %u\n", is_on); 2151 2152 /* 2153 * If the USB host mode is forced, then assume VBUS is always 2154 * present else rely on the input to this function: 2155 */ 2156 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2157 2158 if (!sc->sc_flags.status_vbus) { 2159 sc->sc_flags.status_vbus = 1; 2160 2161 /* complete root HUB interrupt endpoint */ 2162 2163 dwc_otg_root_intr(sc); 2164 } 2165 } else { 2166 if (sc->sc_flags.status_vbus) { 2167 sc->sc_flags.status_vbus = 0; 2168 sc->sc_flags.status_bus_reset = 0; 2169 sc->sc_flags.status_suspend = 0; 2170 sc->sc_flags.change_suspend = 0; 2171 sc->sc_flags.change_connect = 1; 2172 2173 /* complete root HUB interrupt endpoint */ 2174 2175 dwc_otg_root_intr(sc); 2176 } 2177 } 2178 } 2179 2180 void 2181 dwc_otg_interrupt(struct dwc_otg_softc *sc) 2182 { 2183 uint32_t status; 2184 2185 USB_BUS_LOCK(&sc->sc_bus); 2186 2187 /* read and clear interrupt status */ 2188 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2189 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 2190 2191 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2192 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2193 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2194 2195 if (status & GINTSTS_USBRST) { 2196 2197 /* set correct state */ 2198 sc->sc_flags.status_device_mode = 1; 2199 sc->sc_flags.status_bus_reset = 0; 2200 sc->sc_flags.status_suspend = 0; 2201 sc->sc_flags.change_suspend = 0; 2202 sc->sc_flags.change_connect = 1; 2203 2204 /* complete root HUB interrupt endpoint */ 2205 dwc_otg_root_intr(sc); 2206 } 2207 2208 /* check for any bus state change interrupts */ 2209 if (status & GINTSTS_ENUMDONE) { 2210 2211 uint32_t temp; 2212 2213 DPRINTFN(5, "end of reset\n"); 2214 2215 /* set correct state */ 2216 sc->sc_flags.status_device_mode = 1; 2217 sc->sc_flags.status_bus_reset = 1; 2218 sc->sc_flags.status_suspend = 0; 2219 sc->sc_flags.change_suspend = 0; 2220 sc->sc_flags.change_connect = 1; 2221 sc->sc_flags.status_low_speed = 0; 2222 sc->sc_flags.port_enabled = 1; 2223 2224 /* reset FIFOs */ 2225 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2226 2227 /* reset function address */ 2228 dwc_otg_set_address(sc, 0); 2229 2230 /* figure out enumeration speed */ 2231 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2232 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2233 sc->sc_flags.status_high_speed = 1; 2234 else 2235 sc->sc_flags.status_high_speed = 0; 2236 2237 /* disable resume interrupt and enable suspend interrupt */ 2238 2239 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 2240 sc->sc_irq_mask |= GINTSTS_USBSUSP; 2241 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2242 2243 /* complete root HUB interrupt endpoint */ 2244 dwc_otg_root_intr(sc); 2245 } 2246 2247 if (status & GINTSTS_PRTINT) { 2248 uint32_t hprt; 2249 2250 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2251 2252 /* clear change bits */ 2253 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2254 HPRT_PRTPWR | HPRT_PRTENCHNG | 2255 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2256 sc->sc_hprt_val); 2257 2258 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2259 2260 sc->sc_flags.status_device_mode = 0; 2261 2262 if (hprt & HPRT_PRTCONNSTS) 2263 sc->sc_flags.status_bus_reset = 1; 2264 else 2265 sc->sc_flags.status_bus_reset = 0; 2266 2267 if (hprt & HPRT_PRTENCHNG) 2268 sc->sc_flags.change_enabled = 1; 2269 2270 if (hprt & HPRT_PRTENA) 2271 sc->sc_flags.port_enabled = 1; 2272 else 2273 sc->sc_flags.port_enabled = 0; 2274 2275 if (hprt & HPRT_PRTOVRCURRCHNG) 2276 sc->sc_flags.change_over_current = 1; 2277 2278 if (hprt & HPRT_PRTOVRCURRACT) 2279 sc->sc_flags.port_over_current = 1; 2280 else 2281 sc->sc_flags.port_over_current = 0; 2282 2283 if (hprt & HPRT_PRTPWR) 2284 sc->sc_flags.port_powered = 1; 2285 else 2286 sc->sc_flags.port_powered = 0; 2287 2288 if (((hprt & HPRT_PRTSPD_MASK) 2289 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2290 sc->sc_flags.status_low_speed = 1; 2291 else 2292 sc->sc_flags.status_low_speed = 0; 2293 2294 if (((hprt & HPRT_PRTSPD_MASK) 2295 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2296 sc->sc_flags.status_high_speed = 1; 2297 else 2298 sc->sc_flags.status_high_speed = 0; 2299 2300 if (hprt & HPRT_PRTCONNDET) 2301 sc->sc_flags.change_connect = 1; 2302 2303 if (hprt & HPRT_PRTSUSP) 2304 dwc_otg_suspend_irq(sc); 2305 else 2306 dwc_otg_resume_irq(sc); 2307 2308 /* complete root HUB interrupt endpoint */ 2309 dwc_otg_root_intr(sc); 2310 } 2311 2312 /* 2313 * If resume and suspend is set at the same time we interpret 2314 * that like RESUME. Resume is set when there is at least 3 2315 * milliseconds of inactivity on the USB BUS. 2316 */ 2317 if (status & GINTSTS_WKUPINT) { 2318 2319 DPRINTFN(5, "resume interrupt\n"); 2320 2321 dwc_otg_resume_irq(sc); 2322 2323 } else if (status & GINTSTS_USBSUSP) { 2324 2325 DPRINTFN(5, "suspend interrupt\n"); 2326 2327 dwc_otg_suspend_irq(sc); 2328 } 2329 /* check VBUS */ 2330 if (status & (GINTSTS_USBSUSP | 2331 GINTSTS_USBRST | 2332 GINTMSK_OTGINTMSK | 2333 GINTSTS_SESSREQINT)) { 2334 uint32_t temp; 2335 2336 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2337 2338 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2339 2340 dwc_otg_vbus_interrupt(sc, 2341 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2342 } 2343 2344 /* clear all IN endpoint interrupts */ 2345 if (status & GINTSTS_IEPINT) { 2346 uint32_t temp; 2347 uint8_t x; 2348 2349 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2350 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2351 if (temp & DIEPMSK_XFERCOMPLMSK) { 2352 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2353 DIEPMSK_XFERCOMPLMSK); 2354 } 2355 } 2356 } 2357 2358 /* check for SOF interrupt */ 2359 if (status & GINTSTS_SOF) { 2360 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2361 uint8_t x; 2362 uint8_t y; 2363 2364 DPRINTFN(12, "SOF interrupt\n"); 2365 2366 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 2367 if (sc->sc_chan_state[x].wait_sof != 0) { 2368 if (--(sc->sc_chan_state[x].wait_sof) != 0) 2369 y = 1; 2370 } 2371 } 2372 if (y == 0) { 2373 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2374 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2375 } 2376 } 2377 } 2378 2379 /* poll FIFO(s) */ 2380 dwc_otg_interrupt_poll(sc); 2381 2382 USB_BUS_UNLOCK(&sc->sc_bus); 2383 } 2384 2385 static void 2386 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2387 { 2388 struct dwc_otg_td *td; 2389 2390 /* get current Transfer Descriptor */ 2391 td = temp->td_next; 2392 temp->td = td; 2393 2394 /* prepare for next TD */ 2395 temp->td_next = td->obj_next; 2396 2397 /* fill out the Transfer Descriptor */ 2398 td->func = temp->func; 2399 td->pc = temp->pc; 2400 td->offset = temp->offset; 2401 td->remainder = temp->len; 2402 td->tx_bytes = 0; 2403 td->error_any = 0; 2404 td->error_stall = 0; 2405 td->npkt = 0; 2406 td->did_stall = temp->did_stall; 2407 td->short_pkt = temp->short_pkt; 2408 td->alt_next = temp->setup_alt_next; 2409 td->set_toggle = 0; 2410 td->got_short = 0; 2411 td->did_nak = 0; 2412 td->channel = DWC_OTG_MAX_CHANNELS; 2413 td->state = 0; 2414 td->errcnt = 0; 2415 } 2416 2417 static void 2418 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2419 { 2420 struct dwc_otg_std_temp temp; 2421 struct dwc_otg_td *td; 2422 uint32_t x; 2423 uint8_t need_sync; 2424 uint8_t is_host; 2425 2426 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2427 xfer->address, UE_GET_ADDR(xfer->endpointno), 2428 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2429 2430 temp.max_frame_size = xfer->max_frame_size; 2431 2432 td = xfer->td_start[0]; 2433 xfer->td_transfer_first = td; 2434 xfer->td_transfer_cache = td; 2435 2436 /* setup temp */ 2437 2438 temp.pc = NULL; 2439 temp.td = NULL; 2440 temp.td_next = xfer->td_start[0]; 2441 temp.offset = 0; 2442 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2443 temp.did_stall = !xfer->flags_int.control_stall; 2444 2445 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2446 2447 /* check if we should prepend a setup message */ 2448 2449 if (xfer->flags_int.control_xfr) { 2450 if (xfer->flags_int.control_hdr) { 2451 2452 if (is_host) 2453 temp.func = &dwc_otg_host_setup_tx; 2454 else 2455 temp.func = &dwc_otg_setup_rx; 2456 2457 temp.len = xfer->frlengths[0]; 2458 temp.pc = xfer->frbuffers + 0; 2459 temp.short_pkt = temp.len ? 1 : 0; 2460 2461 /* check for last frame */ 2462 if (xfer->nframes == 1) { 2463 /* no STATUS stage yet, SETUP is last */ 2464 if (xfer->flags_int.control_act) 2465 temp.setup_alt_next = 0; 2466 } 2467 2468 dwc_otg_setup_standard_chain_sub(&temp); 2469 } 2470 x = 1; 2471 } else { 2472 x = 0; 2473 } 2474 2475 if (x != xfer->nframes) { 2476 if (xfer->endpointno & UE_DIR_IN) { 2477 if (is_host) { 2478 temp.func = &dwc_otg_host_data_rx; 2479 need_sync = 0; 2480 } else { 2481 temp.func = &dwc_otg_data_tx; 2482 need_sync = 1; 2483 } 2484 } else { 2485 if (is_host) { 2486 temp.func = &dwc_otg_host_data_tx; 2487 need_sync = 0; 2488 } else { 2489 temp.func = &dwc_otg_data_rx; 2490 need_sync = 0; 2491 } 2492 } 2493 2494 /* setup "pc" pointer */ 2495 temp.pc = xfer->frbuffers + x; 2496 } else { 2497 need_sync = 0; 2498 } 2499 while (x != xfer->nframes) { 2500 2501 /* DATA0 / DATA1 message */ 2502 2503 temp.len = xfer->frlengths[x]; 2504 2505 x++; 2506 2507 if (x == xfer->nframes) { 2508 if (xfer->flags_int.control_xfr) { 2509 if (xfer->flags_int.control_act) { 2510 temp.setup_alt_next = 0; 2511 } 2512 } else { 2513 temp.setup_alt_next = 0; 2514 } 2515 } 2516 if (temp.len == 0) { 2517 2518 /* make sure that we send an USB packet */ 2519 2520 temp.short_pkt = 0; 2521 2522 } else { 2523 2524 /* regular data transfer */ 2525 2526 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2527 } 2528 2529 dwc_otg_setup_standard_chain_sub(&temp); 2530 2531 if (xfer->flags_int.isochronous_xfr) { 2532 temp.offset += temp.len; 2533 } else { 2534 /* get next Page Cache pointer */ 2535 temp.pc = xfer->frbuffers + x; 2536 } 2537 } 2538 2539 if (xfer->flags_int.control_xfr) { 2540 2541 /* always setup a valid "pc" pointer for status and sync */ 2542 temp.pc = xfer->frbuffers + 0; 2543 temp.len = 0; 2544 temp.short_pkt = 0; 2545 temp.setup_alt_next = 0; 2546 2547 /* check if we need to sync */ 2548 if (need_sync) { 2549 /* we need a SYNC point after TX */ 2550 temp.func = &dwc_otg_data_tx_sync; 2551 dwc_otg_setup_standard_chain_sub(&temp); 2552 } 2553 2554 /* check if we should append a status stage */ 2555 if (!xfer->flags_int.control_act) { 2556 2557 /* 2558 * Send a DATA1 message and invert the current 2559 * endpoint direction. 2560 */ 2561 if (xfer->endpointno & UE_DIR_IN) { 2562 if (is_host) { 2563 temp.func = &dwc_otg_host_data_tx; 2564 need_sync = 0; 2565 } else { 2566 temp.func = &dwc_otg_data_rx; 2567 need_sync = 0; 2568 } 2569 } else { 2570 if (is_host) { 2571 temp.func = &dwc_otg_host_data_rx; 2572 need_sync = 0; 2573 } else { 2574 temp.func = &dwc_otg_data_tx; 2575 need_sync = 1; 2576 } 2577 } 2578 2579 dwc_otg_setup_standard_chain_sub(&temp); 2580 2581 /* data toggle should be DATA1 */ 2582 td = temp.td; 2583 td->set_toggle = 1; 2584 2585 if (need_sync) { 2586 /* we need a SYNC point after TX */ 2587 temp.func = &dwc_otg_data_tx_sync; 2588 dwc_otg_setup_standard_chain_sub(&temp); 2589 } 2590 } 2591 } else { 2592 /* check if we need to sync */ 2593 if (need_sync) { 2594 2595 temp.pc = xfer->frbuffers + 0; 2596 temp.len = 0; 2597 temp.short_pkt = 0; 2598 temp.setup_alt_next = 0; 2599 2600 /* we need a SYNC point after TX */ 2601 temp.func = &dwc_otg_data_tx_sync; 2602 dwc_otg_setup_standard_chain_sub(&temp); 2603 } 2604 } 2605 2606 /* must have at least one frame! */ 2607 td = temp.td; 2608 xfer->td_transfer_last = td; 2609 2610 if (is_host) { 2611 2612 struct dwc_otg_softc *sc; 2613 uint32_t hcchar; 2614 uint32_t hcsplt; 2615 uint8_t xfer_type; 2616 2617 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2618 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2619 2620 /* get first again */ 2621 td = xfer->td_transfer_first; 2622 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 2623 2624 hcchar = 2625 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 2626 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 2627 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 2628 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 2629 HCCHAR_CHENA; 2630 2631 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 2632 hcchar |= HCCHAR_LSPDDEV; 2633 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2634 hcchar |= HCCHAR_EPDIR_IN; 2635 2636 switch (xfer->xroot->udev->speed) { 2637 case USB_SPEED_FULL: 2638 case USB_SPEED_LOW: 2639 /* check if root HUB port is running High Speed */ 2640 if (sc->sc_flags.status_high_speed != 0) { 2641 hcsplt = HCSPLT_SPLTENA | 2642 (xfer->xroot->udev->hs_port_no << 2643 HCSPLT_PRTADDR_SHIFT) | 2644 (xfer->xroot->udev->hs_hub_addr << 2645 HCSPLT_HUBADDR_SHIFT); 2646 if (xfer_type == UE_ISOCHRONOUS) /* XXX */ 2647 hcsplt |= (3 << HCSPLT_XACTPOS_SHIFT); 2648 } else { 2649 hcsplt = 0; 2650 } 2651 if (xfer_type == UE_INTERRUPT) { 2652 uint32_t ival; 2653 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2654 if (ival == 0) 2655 ival = 1; 2656 else if (ival > 127) 2657 ival = 127; 2658 td->tmr_val = sc->sc_tmr_val + ival; 2659 td->tmr_res = ival; 2660 } 2661 break; 2662 case USB_SPEED_HIGH: 2663 hcsplt = 0; 2664 if (xfer_type == UE_ISOCHRONOUS || 2665 xfer_type == UE_INTERRUPT) { 2666 hcchar |= ((xfer->max_packet_count & 3) 2667 << HCCHAR_MC_SHIFT); 2668 } 2669 if (xfer_type == UE_INTERRUPT) { 2670 uint32_t ival; 2671 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2672 if (ival == 0) 2673 ival = 1; 2674 else if (ival > 127) 2675 ival = 127; 2676 td->tmr_val = sc->sc_tmr_val + ival; 2677 td->tmr_res = ival; 2678 } 2679 break; 2680 default: 2681 hcsplt = 0; 2682 break; 2683 } 2684 2685 if (xfer_type == UE_ISOCHRONOUS) { 2686 td->tmr_val = xfer->endpoint->isoc_next & 0xFF; 2687 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 2688 } else if (xfer_type != UE_INTERRUPT) { 2689 td->tmr_val = 0; 2690 td->tmr_res = 0; 2691 } 2692 2693 /* store configuration in all TD's */ 2694 while (1) { 2695 td->hcchar = hcchar; 2696 td->hcsplt = hcsplt; 2697 2698 if (((void *)td) == xfer->td_transfer_last) 2699 break; 2700 2701 td = td->obj_next; 2702 } 2703 } 2704 } 2705 2706 static void 2707 dwc_otg_timeout(void *arg) 2708 { 2709 struct usb_xfer *xfer = arg; 2710 2711 DPRINTF("xfer=%p\n", xfer); 2712 2713 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2714 2715 /* transfer is transferred */ 2716 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 2717 } 2718 2719 static void 2720 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 2721 { 2722 DPRINTFN(9, "\n"); 2723 2724 /* poll one time - will turn on interrupts */ 2725 if (dwc_otg_xfer_do_fifo(xfer)) { 2726 2727 /* put transfer on interrupt queue */ 2728 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2729 2730 /* start timeout, if any */ 2731 if (xfer->timeout != 0) { 2732 usbd_transfer_timeout_ms(xfer, 2733 &dwc_otg_timeout, xfer->timeout); 2734 } 2735 } 2736 } 2737 2738 static void 2739 dwc_otg_root_intr(struct dwc_otg_softc *sc) 2740 { 2741 DPRINTFN(9, "\n"); 2742 2743 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2744 2745 /* set port bit */ 2746 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2747 2748 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2749 sizeof(sc->sc_hub_idata)); 2750 } 2751 2752 static usb_error_t 2753 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 2754 { 2755 struct dwc_otg_td *td; 2756 uint32_t len; 2757 usb_error_t error; 2758 2759 DPRINTFN(9, "\n"); 2760 2761 td = xfer->td_transfer_cache; 2762 2763 do { 2764 len = td->remainder; 2765 2766 /* store last data toggle */ 2767 xfer->endpoint->toggle_next = td->toggle; 2768 2769 if (xfer->aframes != xfer->nframes) { 2770 /* 2771 * Verify the length and subtract 2772 * the remainder from "frlengths[]": 2773 */ 2774 if (len > xfer->frlengths[xfer->aframes]) { 2775 td->error_any = 1; 2776 } else { 2777 xfer->frlengths[xfer->aframes] -= len; 2778 } 2779 } 2780 /* Check for transfer error */ 2781 if (td->error_any) { 2782 /* the transfer is finished */ 2783 error = (td->error_stall ? 2784 USB_ERR_STALLED : USB_ERR_IOERROR); 2785 td = NULL; 2786 break; 2787 } 2788 /* Check for short transfer */ 2789 if (len > 0) { 2790 if (xfer->flags_int.short_frames_ok) { 2791 /* follow alt next */ 2792 if (td->alt_next) { 2793 td = td->obj_next; 2794 } else { 2795 td = NULL; 2796 } 2797 } else { 2798 /* the transfer is finished */ 2799 td = NULL; 2800 } 2801 error = 0; 2802 break; 2803 } 2804 td = td->obj_next; 2805 2806 /* this USB frame is complete */ 2807 error = 0; 2808 break; 2809 2810 } while (0); 2811 2812 /* update transfer cache */ 2813 2814 xfer->td_transfer_cache = td; 2815 2816 return (error); 2817 } 2818 2819 static void 2820 dwc_otg_standard_done(struct usb_xfer *xfer) 2821 { 2822 usb_error_t err = 0; 2823 2824 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2825 xfer, xfer->endpoint); 2826 2827 /* reset scanner */ 2828 2829 xfer->td_transfer_cache = xfer->td_transfer_first; 2830 2831 if (xfer->flags_int.control_xfr) { 2832 2833 if (xfer->flags_int.control_hdr) { 2834 2835 err = dwc_otg_standard_done_sub(xfer); 2836 } 2837 xfer->aframes = 1; 2838 2839 if (xfer->td_transfer_cache == NULL) { 2840 goto done; 2841 } 2842 } 2843 while (xfer->aframes != xfer->nframes) { 2844 2845 err = dwc_otg_standard_done_sub(xfer); 2846 xfer->aframes++; 2847 2848 if (xfer->td_transfer_cache == NULL) { 2849 goto done; 2850 } 2851 } 2852 2853 if (xfer->flags_int.control_xfr && 2854 !xfer->flags_int.control_act) { 2855 2856 err = dwc_otg_standard_done_sub(xfer); 2857 } 2858 done: 2859 dwc_otg_device_done(xfer, err); 2860 } 2861 2862 /*------------------------------------------------------------------------* 2863 * dwc_otg_device_done 2864 * 2865 * NOTE: this function can be called more than one time on the 2866 * same USB transfer! 2867 *------------------------------------------------------------------------*/ 2868 static void 2869 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 2870 { 2871 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 2872 xfer, xfer->endpoint, error); 2873 2874 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 2875 DPRINTFN(15, "disabled interrupts!\n"); 2876 } else { 2877 struct dwc_otg_td *td; 2878 2879 td = xfer->td_transfer_first; 2880 2881 if (td != NULL) 2882 dwc_otg_host_channel_free(td); 2883 } 2884 /* dequeue transfer and start next transfer */ 2885 usbd_transfer_done(xfer, error); 2886 } 2887 2888 static void 2889 dwc_otg_xfer_stall(struct usb_xfer *xfer) 2890 { 2891 dwc_otg_device_done(xfer, USB_ERR_STALLED); 2892 } 2893 2894 static void 2895 dwc_otg_set_stall(struct usb_device *udev, 2896 struct usb_endpoint *ep, uint8_t *did_stall) 2897 { 2898 struct dwc_otg_softc *sc; 2899 uint32_t temp; 2900 uint32_t reg; 2901 uint8_t ep_no; 2902 2903 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2904 2905 /* check mode */ 2906 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2907 /* not supported */ 2908 return; 2909 } 2910 2911 sc = DWC_OTG_BUS2SC(udev->bus); 2912 2913 /* get endpoint address */ 2914 ep_no = ep->edesc->bEndpointAddress; 2915 2916 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 2917 2918 if (ep_no & UE_DIR_IN) { 2919 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 2920 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 2921 } else { 2922 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 2923 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 2924 } 2925 2926 /* disable and stall endpoint */ 2927 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2928 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 2929 2930 /* clear active OUT ep */ 2931 if (!(ep_no & UE_DIR_IN)) { 2932 2933 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 2934 2935 if (sc->sc_last_rx_status != 0 && 2936 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 2937 sc->sc_last_rx_status)) { 2938 /* dump data */ 2939 dwc_otg_common_rx_ack(sc); 2940 /* poll interrupt */ 2941 dwc_otg_interrupt_poll(sc); 2942 } 2943 } 2944 } 2945 2946 static void 2947 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 2948 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2949 { 2950 uint32_t reg; 2951 uint32_t temp; 2952 2953 if (ep_type == UE_CONTROL) { 2954 /* clearing stall is not needed */ 2955 return; 2956 } 2957 2958 if (ep_dir) { 2959 reg = DOTG_DIEPCTL(ep_no); 2960 } else { 2961 reg = DOTG_DOEPCTL(ep_no); 2962 sc->sc_active_rx_ep |= (1U << ep_no); 2963 } 2964 2965 /* round up and mask away the multiplier count */ 2966 mps = (mps + 3) & 0x7FC; 2967 2968 if (ep_type == UE_BULK) { 2969 temp = DIEPCTL_EPTYPE_SET( 2970 DIEPCTL_EPTYPE_BULK) | 2971 DIEPCTL_USBACTEP; 2972 } else if (ep_type == UE_INTERRUPT) { 2973 temp = DIEPCTL_EPTYPE_SET( 2974 DIEPCTL_EPTYPE_INTERRUPT) | 2975 DIEPCTL_USBACTEP; 2976 } else { 2977 temp = DIEPCTL_EPTYPE_SET( 2978 DIEPCTL_EPTYPE_ISOC) | 2979 DIEPCTL_USBACTEP; 2980 } 2981 2982 temp |= DIEPCTL_MPS_SET(mps); 2983 temp |= DIEPCTL_TXFNUM_SET(ep_no); 2984 2985 if (ep_dir) 2986 sc->sc_in_ctl[ep_no] = temp; 2987 else 2988 sc->sc_out_ctl[ep_no] = temp; 2989 2990 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2991 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 2992 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 2993 2994 /* we only reset the transmit FIFO */ 2995 if (ep_dir) { 2996 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2997 GRSTCTL_TXFIFO(ep_no) | 2998 GRSTCTL_TXFFLSH); 2999 3000 DWC_OTG_WRITE_4(sc, 3001 DOTG_DIEPTSIZ(ep_no), 0); 3002 } 3003 3004 /* poll interrupt */ 3005 dwc_otg_interrupt_poll(sc); 3006 } 3007 3008 static void 3009 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3010 { 3011 struct dwc_otg_softc *sc; 3012 struct usb_endpoint_descriptor *ed; 3013 3014 DPRINTFN(5, "endpoint=%p\n", ep); 3015 3016 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3017 3018 /* check mode */ 3019 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3020 /* not supported */ 3021 return; 3022 } 3023 /* get softc */ 3024 sc = DWC_OTG_BUS2SC(udev->bus); 3025 3026 /* get endpoint descriptor */ 3027 ed = ep->edesc; 3028 3029 /* reset endpoint */ 3030 dwc_otg_clear_stall_sub(sc, 3031 UGETW(ed->wMaxPacketSize), 3032 (ed->bEndpointAddress & UE_ADDR), 3033 (ed->bmAttributes & UE_XFERTYPE), 3034 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3035 } 3036 3037 static void 3038 dwc_otg_device_state_change(struct usb_device *udev) 3039 { 3040 struct dwc_otg_softc *sc; 3041 uint8_t x; 3042 3043 /* check mode */ 3044 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3045 /* not supported */ 3046 return; 3047 } 3048 3049 /* get softc */ 3050 sc = DWC_OTG_BUS2SC(udev->bus); 3051 3052 /* deactivate all other endpoint but the control endpoint */ 3053 if (udev->state == USB_STATE_CONFIGURED || 3054 udev->state == USB_STATE_ADDRESSED) { 3055 3056 USB_BUS_LOCK(&sc->sc_bus); 3057 3058 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3059 3060 if (x < sc->sc_dev_in_ep_max) { 3061 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3062 DIEPCTL_EPDIS); 3063 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3064 } 3065 3066 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3067 DOEPCTL_EPDIS); 3068 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3069 } 3070 USB_BUS_UNLOCK(&sc->sc_bus); 3071 } 3072 } 3073 3074 int 3075 dwc_otg_init(struct dwc_otg_softc *sc) 3076 { 3077 uint32_t temp; 3078 3079 DPRINTF("start\n"); 3080 3081 /* set up the bus structure */ 3082 sc->sc_bus.usbrev = USB_REV_2_0; 3083 sc->sc_bus.methods = &dwc_otg_bus_methods; 3084 3085 usb_callout_init_mtx(&sc->sc_timer, 3086 &sc->sc_bus.bus_mtx, 0); 3087 3088 USB_BUS_LOCK(&sc->sc_bus); 3089 3090 /* turn on clocks */ 3091 dwc_otg_clocks_on(sc); 3092 3093 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3094 DPRINTF("Version = 0x%08x\n", temp); 3095 3096 /* disconnect */ 3097 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3098 DCTL_SFTDISCON); 3099 3100 /* wait for host to detect disconnect */ 3101 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3102 3103 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3104 GRSTCTL_CSFTRST); 3105 3106 /* wait a little bit for block to reset */ 3107 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3108 3109 switch (sc->sc_mode) { 3110 case DWC_MODE_DEVICE: 3111 temp = GUSBCFG_FORCEDEVMODE; 3112 break; 3113 case DWC_MODE_HOST: 3114 temp = GUSBCFG_FORCEHOSTMODE; 3115 break; 3116 default: 3117 temp = 0; 3118 break; 3119 } 3120 3121 /* select HSIC or non-HSIC mode */ 3122 if (dwc_otg_use_hsic) { 3123 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3124 GUSBCFG_PHYIF | 3125 GUSBCFG_TRD_TIM_SET(5) | temp); 3126 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3127 0x000000EC); 3128 3129 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3130 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3131 temp & ~GLPMCFG_HSIC_CONN); 3132 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3133 temp | GLPMCFG_HSIC_CONN); 3134 } else { 3135 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3136 GUSBCFG_ULPI_UTMI_SEL | 3137 GUSBCFG_TRD_TIM_SET(5) | temp); 3138 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3139 3140 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3141 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3142 temp & ~GLPMCFG_HSIC_CONN); 3143 } 3144 3145 /* clear global nak */ 3146 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3147 DCTL_CGOUTNAK | 3148 DCTL_CGNPINNAK); 3149 3150 /* disable USB port */ 3151 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3152 3153 /* wait 10ms */ 3154 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3155 3156 /* enable USB port */ 3157 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3158 3159 /* wait 10ms */ 3160 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3161 3162 /* pull up D+ */ 3163 dwc_otg_pull_up(sc); 3164 3165 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3166 3167 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3168 3169 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3170 3171 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3172 3173 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3174 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3175 3176 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3177 3178 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3179 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3180 3181 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3182 3183 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3184 3185 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3186 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3187 sc->sc_host_ch_max); 3188 3189 /* setup FIFO */ 3190 if (dwc_otg_init_fifo(sc, sc->sc_mode)) 3191 return (EINVAL); 3192 3193 /* enable interrupts */ 3194 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3195 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3196 3197 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3198 3199 /* enable all endpoint interrupts */ 3200 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3201 if (temp & GHWCFG2_MPI) { 3202 uint8_t x; 3203 3204 DPRINTF("Multi Process Interrupts\n"); 3205 3206 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3207 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3208 DIEPMSK_XFERCOMPLMSK); 3209 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3210 } 3211 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3212 } else { 3213 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3214 DIEPMSK_XFERCOMPLMSK); 3215 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3216 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3217 } 3218 } 3219 3220 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3221 /* setup clocks */ 3222 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3223 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3224 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3225 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3226 } 3227 3228 /* only enable global IRQ */ 3229 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3230 GAHBCFG_GLBLINTRMSK); 3231 3232 /* turn off clocks */ 3233 dwc_otg_clocks_off(sc); 3234 3235 /* read initial VBUS state */ 3236 3237 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3238 3239 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3240 3241 dwc_otg_vbus_interrupt(sc, 3242 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3243 3244 USB_BUS_UNLOCK(&sc->sc_bus); 3245 3246 /* catch any lost interrupts */ 3247 3248 dwc_otg_do_poll(&sc->sc_bus); 3249 3250 return (0); /* success */ 3251 } 3252 3253 void 3254 dwc_otg_uninit(struct dwc_otg_softc *sc) 3255 { 3256 USB_BUS_LOCK(&sc->sc_bus); 3257 3258 /* stop host timer */ 3259 dwc_otg_timer_stop(sc); 3260 3261 /* set disconnect */ 3262 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3263 DCTL_SFTDISCON); 3264 3265 /* turn off global IRQ */ 3266 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3267 3268 sc->sc_flags.port_enabled = 0; 3269 sc->sc_flags.port_powered = 0; 3270 sc->sc_flags.status_vbus = 0; 3271 sc->sc_flags.status_bus_reset = 0; 3272 sc->sc_flags.status_suspend = 0; 3273 sc->sc_flags.change_suspend = 0; 3274 sc->sc_flags.change_connect = 1; 3275 3276 dwc_otg_pull_down(sc); 3277 dwc_otg_clocks_off(sc); 3278 3279 USB_BUS_UNLOCK(&sc->sc_bus); 3280 3281 usb_callout_drain(&sc->sc_timer); 3282 } 3283 3284 static void 3285 dwc_otg_suspend(struct dwc_otg_softc *sc) 3286 { 3287 return; 3288 } 3289 3290 static void 3291 dwc_otg_resume(struct dwc_otg_softc *sc) 3292 { 3293 return; 3294 } 3295 3296 static void 3297 dwc_otg_do_poll(struct usb_bus *bus) 3298 { 3299 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3300 3301 USB_BUS_LOCK(&sc->sc_bus); 3302 dwc_otg_interrupt_poll(sc); 3303 USB_BUS_UNLOCK(&sc->sc_bus); 3304 } 3305 3306 /*------------------------------------------------------------------------* 3307 * DWC OTG bulk support 3308 * DWC OTG control support 3309 * DWC OTG interrupt support 3310 *------------------------------------------------------------------------*/ 3311 static void 3312 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3313 { 3314 } 3315 3316 static void 3317 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3318 { 3319 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3320 } 3321 3322 static void 3323 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3324 { 3325 } 3326 3327 static void 3328 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3329 { 3330 /* setup TDs */ 3331 dwc_otg_setup_standard_chain(xfer); 3332 dwc_otg_start_standard_chain(xfer); 3333 } 3334 3335 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3336 { 3337 .open = dwc_otg_device_non_isoc_open, 3338 .close = dwc_otg_device_non_isoc_close, 3339 .enter = dwc_otg_device_non_isoc_enter, 3340 .start = dwc_otg_device_non_isoc_start, 3341 }; 3342 3343 /*------------------------------------------------------------------------* 3344 * DWC OTG full speed isochronous support 3345 *------------------------------------------------------------------------*/ 3346 static void 3347 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3348 { 3349 } 3350 3351 static void 3352 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3353 { 3354 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3355 } 3356 3357 static void 3358 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3359 { 3360 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3361 uint32_t temp; 3362 uint32_t nframes; 3363 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3364 3365 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3366 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3367 3368 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3369 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3370 3371 /* get the current frame index */ 3372 nframes = (temp & HFNUM_FRNUM_MASK); 3373 } else { 3374 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3375 3376 /* get the current frame index */ 3377 nframes = DSTS_SOFFN_GET(temp); 3378 } 3379 3380 if (sc->sc_flags.status_high_speed) 3381 nframes /= 8; 3382 3383 nframes &= DWC_OTG_FRAME_MASK; 3384 3385 /* 3386 * check if the frame index is within the window where the frames 3387 * will be inserted 3388 */ 3389 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3390 3391 if ((xfer->endpoint->is_synced == 0) || 3392 (temp < (((xfer->nframes << shift) + 7) / 8))) { 3393 /* 3394 * If there is data underflow or the pipe queue is 3395 * empty we schedule the transfer a few frames ahead 3396 * of the current frame position. Else two isochronous 3397 * transfers might overlap. 3398 */ 3399 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 3400 xfer->endpoint->is_synced = 1; 3401 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3402 } 3403 /* 3404 * compute how many milliseconds the insertion is ahead of the 3405 * current frame position: 3406 */ 3407 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 3408 3409 /* 3410 * pre-compute when the isochronous transfer will be finished: 3411 */ 3412 xfer->isoc_time_complete = 3413 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3414 (((xfer->nframes << shift) + 7) / 8); 3415 3416 /* setup TDs */ 3417 dwc_otg_setup_standard_chain(xfer); 3418 3419 /* compute frame number for next insertion */ 3420 xfer->endpoint->isoc_next += (xfer->nframes << shift); 3421 } 3422 3423 static void 3424 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3425 { 3426 /* start TD chain */ 3427 dwc_otg_start_standard_chain(xfer); 3428 } 3429 3430 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 3431 { 3432 .open = dwc_otg_device_isoc_open, 3433 .close = dwc_otg_device_isoc_close, 3434 .enter = dwc_otg_device_isoc_enter, 3435 .start = dwc_otg_device_isoc_start, 3436 }; 3437 3438 /*------------------------------------------------------------------------* 3439 * DWC OTG root control support 3440 *------------------------------------------------------------------------* 3441 * Simulate a hardware HUB by handling all the necessary requests. 3442 *------------------------------------------------------------------------*/ 3443 3444 static const struct usb_device_descriptor dwc_otg_devd = { 3445 .bLength = sizeof(struct usb_device_descriptor), 3446 .bDescriptorType = UDESC_DEVICE, 3447 .bcdUSB = {0x00, 0x02}, 3448 .bDeviceClass = UDCLASS_HUB, 3449 .bDeviceSubClass = UDSUBCLASS_HUB, 3450 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3451 .bMaxPacketSize = 64, 3452 .bcdDevice = {0x00, 0x01}, 3453 .iManufacturer = 1, 3454 .iProduct = 2, 3455 .bNumConfigurations = 1, 3456 }; 3457 3458 static const struct dwc_otg_config_desc dwc_otg_confd = { 3459 .confd = { 3460 .bLength = sizeof(struct usb_config_descriptor), 3461 .bDescriptorType = UDESC_CONFIG, 3462 .wTotalLength[0] = sizeof(dwc_otg_confd), 3463 .bNumInterface = 1, 3464 .bConfigurationValue = 1, 3465 .iConfiguration = 0, 3466 .bmAttributes = UC_SELF_POWERED, 3467 .bMaxPower = 0, 3468 }, 3469 .ifcd = { 3470 .bLength = sizeof(struct usb_interface_descriptor), 3471 .bDescriptorType = UDESC_INTERFACE, 3472 .bNumEndpoints = 1, 3473 .bInterfaceClass = UICLASS_HUB, 3474 .bInterfaceSubClass = UISUBCLASS_HUB, 3475 .bInterfaceProtocol = 0, 3476 }, 3477 .endpd = { 3478 .bLength = sizeof(struct usb_endpoint_descriptor), 3479 .bDescriptorType = UDESC_ENDPOINT, 3480 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 3481 .bmAttributes = UE_INTERRUPT, 3482 .wMaxPacketSize[0] = 8, 3483 .bInterval = 255, 3484 }, 3485 }; 3486 3487 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3488 3489 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 3490 .bDescLength = sizeof(dwc_otg_hubd), 3491 .bDescriptorType = UDESC_HUB, 3492 .bNbrPorts = 1, 3493 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3494 .bPwrOn2PwrGood = 50, 3495 .bHubContrCurrent = 0, 3496 .DeviceRemovable = {0}, /* port is removable */ 3497 }; 3498 3499 #define STRING_VENDOR \ 3500 "D\0W\0C\0O\0T\0G" 3501 3502 #define STRING_PRODUCT \ 3503 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 3504 3505 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 3506 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 3507 3508 static usb_error_t 3509 dwc_otg_roothub_exec(struct usb_device *udev, 3510 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3511 { 3512 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3513 const void *ptr; 3514 uint16_t len; 3515 uint16_t value; 3516 uint16_t index; 3517 usb_error_t err; 3518 3519 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3520 3521 /* buffer reset */ 3522 ptr = (const void *)&sc->sc_hub_temp; 3523 len = 0; 3524 err = 0; 3525 3526 value = UGETW(req->wValue); 3527 index = UGETW(req->wIndex); 3528 3529 /* demultiplex the control request */ 3530 3531 switch (req->bmRequestType) { 3532 case UT_READ_DEVICE: 3533 switch (req->bRequest) { 3534 case UR_GET_DESCRIPTOR: 3535 goto tr_handle_get_descriptor; 3536 case UR_GET_CONFIG: 3537 goto tr_handle_get_config; 3538 case UR_GET_STATUS: 3539 goto tr_handle_get_status; 3540 default: 3541 goto tr_stalled; 3542 } 3543 break; 3544 3545 case UT_WRITE_DEVICE: 3546 switch (req->bRequest) { 3547 case UR_SET_ADDRESS: 3548 goto tr_handle_set_address; 3549 case UR_SET_CONFIG: 3550 goto tr_handle_set_config; 3551 case UR_CLEAR_FEATURE: 3552 goto tr_valid; /* nop */ 3553 case UR_SET_DESCRIPTOR: 3554 goto tr_valid; /* nop */ 3555 case UR_SET_FEATURE: 3556 default: 3557 goto tr_stalled; 3558 } 3559 break; 3560 3561 case UT_WRITE_ENDPOINT: 3562 switch (req->bRequest) { 3563 case UR_CLEAR_FEATURE: 3564 switch (UGETW(req->wValue)) { 3565 case UF_ENDPOINT_HALT: 3566 goto tr_handle_clear_halt; 3567 case UF_DEVICE_REMOTE_WAKEUP: 3568 goto tr_handle_clear_wakeup; 3569 default: 3570 goto tr_stalled; 3571 } 3572 break; 3573 case UR_SET_FEATURE: 3574 switch (UGETW(req->wValue)) { 3575 case UF_ENDPOINT_HALT: 3576 goto tr_handle_set_halt; 3577 case UF_DEVICE_REMOTE_WAKEUP: 3578 goto tr_handle_set_wakeup; 3579 default: 3580 goto tr_stalled; 3581 } 3582 break; 3583 case UR_SYNCH_FRAME: 3584 goto tr_valid; /* nop */ 3585 default: 3586 goto tr_stalled; 3587 } 3588 break; 3589 3590 case UT_READ_ENDPOINT: 3591 switch (req->bRequest) { 3592 case UR_GET_STATUS: 3593 goto tr_handle_get_ep_status; 3594 default: 3595 goto tr_stalled; 3596 } 3597 break; 3598 3599 case UT_WRITE_INTERFACE: 3600 switch (req->bRequest) { 3601 case UR_SET_INTERFACE: 3602 goto tr_handle_set_interface; 3603 case UR_CLEAR_FEATURE: 3604 goto tr_valid; /* nop */ 3605 case UR_SET_FEATURE: 3606 default: 3607 goto tr_stalled; 3608 } 3609 break; 3610 3611 case UT_READ_INTERFACE: 3612 switch (req->bRequest) { 3613 case UR_GET_INTERFACE: 3614 goto tr_handle_get_interface; 3615 case UR_GET_STATUS: 3616 goto tr_handle_get_iface_status; 3617 default: 3618 goto tr_stalled; 3619 } 3620 break; 3621 3622 case UT_WRITE_CLASS_INTERFACE: 3623 case UT_WRITE_VENDOR_INTERFACE: 3624 /* XXX forward */ 3625 break; 3626 3627 case UT_READ_CLASS_INTERFACE: 3628 case UT_READ_VENDOR_INTERFACE: 3629 /* XXX forward */ 3630 break; 3631 3632 case UT_WRITE_CLASS_DEVICE: 3633 switch (req->bRequest) { 3634 case UR_CLEAR_FEATURE: 3635 goto tr_valid; 3636 case UR_SET_DESCRIPTOR: 3637 case UR_SET_FEATURE: 3638 break; 3639 default: 3640 goto tr_stalled; 3641 } 3642 break; 3643 3644 case UT_WRITE_CLASS_OTHER: 3645 switch (req->bRequest) { 3646 case UR_CLEAR_FEATURE: 3647 goto tr_handle_clear_port_feature; 3648 case UR_SET_FEATURE: 3649 goto tr_handle_set_port_feature; 3650 case UR_CLEAR_TT_BUFFER: 3651 case UR_RESET_TT: 3652 case UR_STOP_TT: 3653 goto tr_valid; 3654 3655 default: 3656 goto tr_stalled; 3657 } 3658 break; 3659 3660 case UT_READ_CLASS_OTHER: 3661 switch (req->bRequest) { 3662 case UR_GET_TT_STATE: 3663 goto tr_handle_get_tt_state; 3664 case UR_GET_STATUS: 3665 goto tr_handle_get_port_status; 3666 default: 3667 goto tr_stalled; 3668 } 3669 break; 3670 3671 case UT_READ_CLASS_DEVICE: 3672 switch (req->bRequest) { 3673 case UR_GET_DESCRIPTOR: 3674 goto tr_handle_get_class_descriptor; 3675 case UR_GET_STATUS: 3676 goto tr_handle_get_class_status; 3677 3678 default: 3679 goto tr_stalled; 3680 } 3681 break; 3682 default: 3683 goto tr_stalled; 3684 } 3685 goto tr_valid; 3686 3687 tr_handle_get_descriptor: 3688 switch (value >> 8) { 3689 case UDESC_DEVICE: 3690 if (value & 0xff) { 3691 goto tr_stalled; 3692 } 3693 len = sizeof(dwc_otg_devd); 3694 ptr = (const void *)&dwc_otg_devd; 3695 goto tr_valid; 3696 case UDESC_CONFIG: 3697 if (value & 0xff) { 3698 goto tr_stalled; 3699 } 3700 len = sizeof(dwc_otg_confd); 3701 ptr = (const void *)&dwc_otg_confd; 3702 goto tr_valid; 3703 case UDESC_STRING: 3704 switch (value & 0xff) { 3705 case 0: /* Language table */ 3706 len = sizeof(usb_string_lang_en); 3707 ptr = (const void *)&usb_string_lang_en; 3708 goto tr_valid; 3709 3710 case 1: /* Vendor */ 3711 len = sizeof(dwc_otg_vendor); 3712 ptr = (const void *)&dwc_otg_vendor; 3713 goto tr_valid; 3714 3715 case 2: /* Product */ 3716 len = sizeof(dwc_otg_product); 3717 ptr = (const void *)&dwc_otg_product; 3718 goto tr_valid; 3719 default: 3720 break; 3721 } 3722 break; 3723 default: 3724 goto tr_stalled; 3725 } 3726 goto tr_stalled; 3727 3728 tr_handle_get_config: 3729 len = 1; 3730 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3731 goto tr_valid; 3732 3733 tr_handle_get_status: 3734 len = 2; 3735 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3736 goto tr_valid; 3737 3738 tr_handle_set_address: 3739 if (value & 0xFF00) { 3740 goto tr_stalled; 3741 } 3742 sc->sc_rt_addr = value; 3743 goto tr_valid; 3744 3745 tr_handle_set_config: 3746 if (value >= 2) { 3747 goto tr_stalled; 3748 } 3749 sc->sc_conf = value; 3750 goto tr_valid; 3751 3752 tr_handle_get_interface: 3753 len = 1; 3754 sc->sc_hub_temp.wValue[0] = 0; 3755 goto tr_valid; 3756 3757 tr_handle_get_tt_state: 3758 tr_handle_get_class_status: 3759 tr_handle_get_iface_status: 3760 tr_handle_get_ep_status: 3761 len = 2; 3762 USETW(sc->sc_hub_temp.wValue, 0); 3763 goto tr_valid; 3764 3765 tr_handle_set_halt: 3766 tr_handle_set_interface: 3767 tr_handle_set_wakeup: 3768 tr_handle_clear_wakeup: 3769 tr_handle_clear_halt: 3770 goto tr_valid; 3771 3772 tr_handle_clear_port_feature: 3773 if (index != 1) 3774 goto tr_stalled; 3775 3776 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3777 3778 switch (value) { 3779 case UHF_PORT_SUSPEND: 3780 dwc_otg_wakeup_peer(sc); 3781 break; 3782 3783 case UHF_PORT_ENABLE: 3784 if (sc->sc_flags.status_device_mode == 0) { 3785 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 3786 sc->sc_hprt_val | HPRT_PRTENA); 3787 } 3788 sc->sc_flags.port_enabled = 0; 3789 break; 3790 3791 case UHF_C_PORT_RESET: 3792 sc->sc_flags.change_reset = 0; 3793 break; 3794 3795 case UHF_C_PORT_ENABLE: 3796 sc->sc_flags.change_enabled = 0; 3797 break; 3798 3799 case UHF_C_PORT_OVER_CURRENT: 3800 sc->sc_flags.change_over_current = 0; 3801 break; 3802 3803 case UHF_PORT_TEST: 3804 case UHF_PORT_INDICATOR: 3805 /* nops */ 3806 break; 3807 3808 case UHF_PORT_POWER: 3809 sc->sc_flags.port_powered = 0; 3810 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3811 sc->sc_hprt_val = 0; 3812 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 3813 } 3814 dwc_otg_pull_down(sc); 3815 dwc_otg_clocks_off(sc); 3816 break; 3817 3818 case UHF_C_PORT_CONNECTION: 3819 /* clear connect change flag */ 3820 sc->sc_flags.change_connect = 0; 3821 break; 3822 3823 case UHF_C_PORT_SUSPEND: 3824 sc->sc_flags.change_suspend = 0; 3825 break; 3826 3827 default: 3828 err = USB_ERR_IOERROR; 3829 goto done; 3830 } 3831 goto tr_valid; 3832 3833 tr_handle_set_port_feature: 3834 if (index != 1) { 3835 goto tr_stalled; 3836 } 3837 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 3838 3839 switch (value) { 3840 case UHF_PORT_ENABLE: 3841 break; 3842 3843 case UHF_PORT_SUSPEND: 3844 if (sc->sc_flags.status_device_mode == 0) { 3845 /* set suspend BIT */ 3846 sc->sc_hprt_val |= HPRT_PRTSUSP; 3847 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3848 3849 /* generate HUB suspend event */ 3850 dwc_otg_suspend_irq(sc); 3851 } 3852 break; 3853 3854 case UHF_PORT_RESET: 3855 if (sc->sc_flags.status_device_mode == 0) { 3856 3857 DPRINTF("PORT RESET\n"); 3858 3859 /* enable PORT reset */ 3860 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 3861 3862 /* Wait 62.5ms for reset to complete */ 3863 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3864 3865 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3866 3867 /* Wait 62.5ms for reset to complete */ 3868 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3869 3870 /* reset FIFOs */ 3871 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 3872 3873 sc->sc_flags.change_reset = 1; 3874 } else { 3875 err = USB_ERR_IOERROR; 3876 } 3877 break; 3878 3879 case UHF_PORT_TEST: 3880 case UHF_PORT_INDICATOR: 3881 /* nops */ 3882 break; 3883 case UHF_PORT_POWER: 3884 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3885 sc->sc_hprt_val |= HPRT_PRTPWR; 3886 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3887 } 3888 sc->sc_flags.port_powered = 1; 3889 break; 3890 default: 3891 err = USB_ERR_IOERROR; 3892 goto done; 3893 } 3894 goto tr_valid; 3895 3896 tr_handle_get_port_status: 3897 3898 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 3899 3900 if (index != 1) 3901 goto tr_stalled; 3902 3903 if (sc->sc_flags.status_vbus) 3904 dwc_otg_clocks_on(sc); 3905 else 3906 dwc_otg_clocks_off(sc); 3907 3908 /* Select Device Side Mode */ 3909 3910 if (sc->sc_flags.status_device_mode) { 3911 value = UPS_PORT_MODE_DEVICE; 3912 dwc_otg_timer_stop(sc); 3913 } else { 3914 value = 0; 3915 dwc_otg_timer_start(sc); 3916 } 3917 3918 if (sc->sc_flags.status_high_speed) 3919 value |= UPS_HIGH_SPEED; 3920 else if (sc->sc_flags.status_low_speed) 3921 value |= UPS_LOW_SPEED; 3922 3923 if (sc->sc_flags.port_powered) 3924 value |= UPS_PORT_POWER; 3925 3926 if (sc->sc_flags.port_enabled) 3927 value |= UPS_PORT_ENABLED; 3928 3929 if (sc->sc_flags.port_over_current) 3930 value |= UPS_OVERCURRENT_INDICATOR; 3931 3932 if (sc->sc_flags.status_vbus && 3933 sc->sc_flags.status_bus_reset) 3934 value |= UPS_CURRENT_CONNECT_STATUS; 3935 3936 if (sc->sc_flags.status_suspend) 3937 value |= UPS_SUSPEND; 3938 3939 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3940 3941 value = 0; 3942 3943 if (sc->sc_flags.change_connect) 3944 value |= UPS_C_CONNECT_STATUS; 3945 if (sc->sc_flags.change_suspend) 3946 value |= UPS_C_SUSPEND; 3947 if (sc->sc_flags.change_reset) 3948 value |= UPS_C_PORT_RESET; 3949 if (sc->sc_flags.change_over_current) 3950 value |= UPS_C_OVERCURRENT_INDICATOR; 3951 3952 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3953 len = sizeof(sc->sc_hub_temp.ps); 3954 goto tr_valid; 3955 3956 tr_handle_get_class_descriptor: 3957 if (value & 0xFF) { 3958 goto tr_stalled; 3959 } 3960 ptr = (const void *)&dwc_otg_hubd; 3961 len = sizeof(dwc_otg_hubd); 3962 goto tr_valid; 3963 3964 tr_stalled: 3965 err = USB_ERR_STALLED; 3966 tr_valid: 3967 done: 3968 *plength = len; 3969 *pptr = ptr; 3970 return (err); 3971 } 3972 3973 static void 3974 dwc_otg_xfer_setup(struct usb_setup_params *parm) 3975 { 3976 struct usb_xfer *xfer; 3977 void *last_obj; 3978 uint32_t ntd; 3979 uint32_t n; 3980 uint8_t ep_no; 3981 3982 xfer = parm->curr_xfer; 3983 3984 /* 3985 * NOTE: This driver does not use any of the parameters that 3986 * are computed from the following values. Just set some 3987 * reasonable dummies: 3988 */ 3989 parm->hc_max_packet_size = 0x500; 3990 parm->hc_max_packet_count = 1; 3991 parm->hc_max_frame_size = 0x500; 3992 3993 usbd_transfer_setup_sub(parm); 3994 3995 /* 3996 * compute maximum number of TDs 3997 */ 3998 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 3999 4000 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4001 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4002 } else { 4003 4004 ntd = xfer->nframes + 1 /* SYNC */ ; 4005 } 4006 4007 /* 4008 * check if "usbd_transfer_setup_sub" set an error 4009 */ 4010 if (parm->err) 4011 return; 4012 4013 /* 4014 * allocate transfer descriptors 4015 */ 4016 last_obj = NULL; 4017 4018 ep_no = xfer->endpointno & UE_ADDR; 4019 4020 /* 4021 * Check for a valid endpoint profile in USB device mode: 4022 */ 4023 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4024 const struct usb_hw_ep_profile *pf; 4025 4026 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4027 4028 if (pf == NULL) { 4029 /* should not happen */ 4030 parm->err = USB_ERR_INVAL; 4031 return; 4032 } 4033 } 4034 4035 /* align data */ 4036 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4037 4038 for (n = 0; n != ntd; n++) { 4039 4040 struct dwc_otg_td *td; 4041 4042 if (parm->buf) { 4043 4044 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4045 4046 /* init TD */ 4047 td->max_packet_size = xfer->max_packet_size; 4048 td->ep_no = ep_no; 4049 td->obj_next = last_obj; 4050 4051 last_obj = td; 4052 } 4053 parm->size[0] += sizeof(*td); 4054 } 4055 4056 xfer->td_start[0] = last_obj; 4057 } 4058 4059 static void 4060 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4061 { 4062 return; 4063 } 4064 4065 static void 4066 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4067 struct usb_endpoint *ep) 4068 { 4069 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4070 4071 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4072 ep, udev->address, 4073 edesc->bEndpointAddress, udev->flags.usb_mode, 4074 sc->sc_rt_addr, udev->device_index); 4075 4076 if (udev->device_index != sc->sc_rt_addr) { 4077 4078 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4079 if (udev->speed != USB_SPEED_FULL && 4080 udev->speed != USB_SPEED_HIGH) { 4081 /* not supported */ 4082 return; 4083 } 4084 } else { 4085 uint16_t mps; 4086 4087 mps = UGETW(edesc->wMaxPacketSize); 4088 4089 /* Apply limitations of our USB host driver */ 4090 4091 switch (udev->speed) { 4092 case USB_SPEED_HIGH: 4093 if (mps > 512) { 4094 DPRINTF("wMaxPacketSize=0x%04x" 4095 "is not supported\n", (int)mps); 4096 /* not supported */ 4097 return; 4098 } 4099 break; 4100 4101 case USB_SPEED_FULL: 4102 case USB_SPEED_LOW: 4103 if (mps > 188) { 4104 DPRINTF("wMaxPacketSize=0x%04x" 4105 "is not supported\n", (int)mps); 4106 /* not supported */ 4107 return; 4108 } 4109 break; 4110 4111 default: 4112 DPRINTF("Invalid device speed\n"); 4113 /* not supported */ 4114 return; 4115 } 4116 } 4117 4118 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4119 ep->methods = &dwc_otg_device_isoc_methods; 4120 else 4121 ep->methods = &dwc_otg_device_non_isoc_methods; 4122 } 4123 } 4124 4125 static void 4126 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4127 { 4128 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4129 4130 switch (state) { 4131 case USB_HW_POWER_SUSPEND: 4132 dwc_otg_suspend(sc); 4133 break; 4134 case USB_HW_POWER_SHUTDOWN: 4135 dwc_otg_uninit(sc); 4136 break; 4137 case USB_HW_POWER_RESUME: 4138 dwc_otg_resume(sc); 4139 break; 4140 default: 4141 break; 4142 } 4143 } 4144 4145 static void 4146 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4147 { 4148 /* DMA delay - wait until any use of memory is finished */ 4149 *pus = (2125); /* microseconds */ 4150 } 4151 4152 static void 4153 dwc_otg_device_resume(struct usb_device *udev) 4154 { 4155 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4156 struct usb_xfer *xfer; 4157 struct dwc_otg_td *td; 4158 4159 DPRINTF("\n"); 4160 4161 /* Enable relevant Host channels before resuming */ 4162 4163 USB_BUS_LOCK(udev->bus); 4164 4165 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4166 4167 if (xfer->xroot->udev == udev) { 4168 4169 td = xfer->td_transfer_cache; 4170 if (td != NULL && 4171 td->channel < DWC_OTG_MAX_CHANNELS) 4172 sc->sc_chan_state[td->channel].suspended = 0; 4173 } 4174 } 4175 4176 USB_BUS_UNLOCK(udev->bus); 4177 4178 /* poll all transfers again to restart resumed ones */ 4179 dwc_otg_do_poll(udev->bus); 4180 } 4181 4182 static void 4183 dwc_otg_device_suspend(struct usb_device *udev) 4184 { 4185 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4186 struct usb_xfer *xfer; 4187 struct dwc_otg_td *td; 4188 4189 DPRINTF("\n"); 4190 4191 /* Disable relevant Host channels before going to suspend */ 4192 4193 USB_BUS_LOCK(udev->bus); 4194 4195 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4196 4197 if (xfer->xroot->udev == udev) { 4198 4199 td = xfer->td_transfer_cache; 4200 if (td != NULL && 4201 td->channel < DWC_OTG_MAX_CHANNELS) 4202 sc->sc_chan_state[td->channel].suspended = 1; 4203 } 4204 } 4205 4206 USB_BUS_UNLOCK(udev->bus); 4207 } 4208 4209 static const struct usb_bus_methods dwc_otg_bus_methods = 4210 { 4211 .endpoint_init = &dwc_otg_ep_init, 4212 .xfer_setup = &dwc_otg_xfer_setup, 4213 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4214 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4215 .xfer_stall = &dwc_otg_xfer_stall, 4216 .set_stall = &dwc_otg_set_stall, 4217 .clear_stall = &dwc_otg_clear_stall, 4218 .roothub_exec = &dwc_otg_roothub_exec, 4219 .xfer_poll = &dwc_otg_do_poll, 4220 .device_state_change = &dwc_otg_device_state_change, 4221 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4222 .get_dma_delay = &dwc_otg_get_dma_delay, 4223 .device_resume = &dwc_otg_device_resume, 4224 .device_suspend = &dwc_otg_device_suspend, 4225 }; 4226