1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the DesignWare series USB 2.0 OTG 29 * Controller. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 #include <dev/usb/controller/dwc_otgreg.h> 85 86 #define DWC_OTG_BUS2SC(bus) \ 87 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 89 90 #define DWC_OTG_PC2SC(pc) \ 91 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 92 93 #define DWC_OTG_MSK_GINT_ENABLED \ 94 (GINTSTS_ENUMDONE | \ 95 GINTSTS_USBRST | \ 96 GINTSTS_USBSUSP | \ 97 GINTSTS_IEPINT | \ 98 GINTSTS_RXFLVL | \ 99 GINTSTS_SESSREQINT | \ 100 GINTMSK_OTGINTMSK | \ 101 GINTMSK_HCHINTMSK | \ 102 GINTSTS_PRTINT) 103 104 static int dwc_otg_use_hsic; 105 106 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 107 108 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD, 109 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 110 111 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 112 113 #ifdef USB_DEBUG 114 static int dwc_otg_debug; 115 116 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 117 &dwc_otg_debug, 0, "DWC OTG debug level"); 118 #endif 119 120 #define DWC_OTG_INTR_ENDPT 1 121 122 /* prototypes */ 123 124 struct usb_bus_methods dwc_otg_bus_methods; 125 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 126 struct usb_pipe_methods dwc_otg_device_isoc_methods; 127 128 static dwc_otg_cmd_t dwc_otg_setup_rx; 129 static dwc_otg_cmd_t dwc_otg_data_rx; 130 static dwc_otg_cmd_t dwc_otg_data_tx; 131 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 132 133 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 134 static dwc_otg_cmd_t dwc_otg_host_data_tx; 135 static dwc_otg_cmd_t dwc_otg_host_data_rx; 136 137 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 138 static void dwc_otg_do_poll(struct usb_bus *); 139 static void dwc_otg_standard_done(struct usb_xfer *); 140 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 141 static void dwc_otg_interrupt_poll(struct dwc_otg_softc *sc); 142 143 /* 144 * Here is a configuration that the chip supports. 145 */ 146 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 147 148 [0] = { 149 .max_in_frame_size = 64,/* fixed */ 150 .max_out_frame_size = 64, /* fixed */ 151 .is_simplex = 1, 152 .support_control = 1, 153 } 154 }; 155 156 static void 157 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 158 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 159 { 160 struct dwc_otg_softc *sc; 161 162 sc = DWC_OTG_BUS2SC(udev->bus); 163 164 if (ep_addr < sc->sc_dev_ep_max) 165 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 166 else 167 *ppf = NULL; 168 } 169 170 static int 171 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 172 { 173 struct dwc_otg_profile *pf; 174 uint32_t fifo_size; 175 uint32_t fifo_regs; 176 uint32_t tx_start; 177 uint8_t x; 178 179 fifo_size = sc->sc_fifo_size; 180 181 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 182 183 if (fifo_size >= fifo_regs) 184 fifo_size -= fifo_regs; 185 else 186 fifo_size = 0; 187 188 /* split equally for IN and OUT */ 189 fifo_size /= 2; 190 191 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 192 193 /* align to 4-bytes */ 194 fifo_size &= ~3; 195 196 tx_start = fifo_size; 197 198 if (fifo_size < 0x40) { 199 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 200 USB_BUS_UNLOCK(&sc->sc_bus); 201 return (EINVAL); 202 } 203 204 if (mode == DWC_MODE_HOST) { 205 206 /* reset active endpoints */ 207 sc->sc_active_rx_ep = 0; 208 209 fifo_size /= 2; 210 211 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 212 ((fifo_size / 4) << 16) | 213 (tx_start / 4)); 214 215 tx_start += fifo_size; 216 217 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 218 ((fifo_size / 4) << 16) | 219 (tx_start / 4)); 220 221 for (x = 0; x != sc->sc_host_ch_max; x++) { 222 /* enable interrupts */ 223 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 224 HCINT_STALL | HCINT_BBLERR | 225 HCINT_XACTERR | 226 HCINT_NAK | HCINT_ACK | HCINT_NYET | 227 HCINT_CHHLTD | HCINT_FRMOVRUN | 228 HCINT_DATATGLERR); 229 } 230 231 /* enable host channel interrupts */ 232 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 233 (1U << sc->sc_host_ch_max) - 1U); 234 } 235 236 if (mode == DWC_MODE_DEVICE) { 237 238 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 239 (0x10 << 16) | (tx_start / 4)); 240 fifo_size -= 0x40; 241 tx_start += 0x40; 242 243 /* setup control endpoint profile */ 244 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 245 246 /* reset active endpoints */ 247 sc->sc_active_rx_ep = 1; 248 249 for (x = 1; x != sc->sc_dev_ep_max; x++) { 250 251 pf = sc->sc_hw_ep_profile + x; 252 253 pf->usb.max_out_frame_size = 1024 * 3; 254 pf->usb.is_simplex = 0; /* assume duplex */ 255 pf->usb.support_bulk = 1; 256 pf->usb.support_interrupt = 1; 257 pf->usb.support_isochronous = 1; 258 pf->usb.support_out = 1; 259 260 if (x < sc->sc_dev_in_ep_max) { 261 uint32_t limit; 262 263 limit = (x == 1) ? DWC_OTG_MAX_TXN : 264 (DWC_OTG_MAX_TXN / 2); 265 266 if (fifo_size >= limit) { 267 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 268 ((limit / 4) << 16) | 269 (tx_start / 4)); 270 tx_start += limit; 271 fifo_size -= limit; 272 pf->usb.max_in_frame_size = 0x200; 273 pf->usb.support_in = 1; 274 pf->max_buffer = limit; 275 276 } else if (fifo_size >= 0x80) { 277 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 278 ((0x80 / 4) << 16) | (tx_start / 4)); 279 tx_start += 0x80; 280 fifo_size -= 0x80; 281 pf->usb.max_in_frame_size = 0x40; 282 pf->usb.support_in = 1; 283 284 } else { 285 pf->usb.is_simplex = 1; 286 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 287 (0x0 << 16) | (tx_start / 4)); 288 } 289 } else { 290 pf->usb.is_simplex = 1; 291 } 292 293 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 294 pf->usb.max_in_frame_size, 295 pf->usb.max_out_frame_size); 296 } 297 } 298 299 /* reset RX FIFO */ 300 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 301 GRSTCTL_RXFFLSH); 302 303 if (mode != DWC_MODE_OTG) { 304 /* reset all TX FIFOs */ 305 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 306 GRSTCTL_TXFIFO(0x10) | 307 GRSTCTL_TXFFLSH); 308 } else { 309 /* reset active endpoints */ 310 sc->sc_active_rx_ep = 0; 311 } 312 return (0); 313 } 314 315 static void 316 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 317 { 318 if (sc->sc_flags.clocks_off && 319 sc->sc_flags.port_powered) { 320 321 DPRINTFN(5, "\n"); 322 323 /* TODO - platform specific */ 324 325 sc->sc_flags.clocks_off = 0; 326 } 327 } 328 329 static void 330 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 331 { 332 if (!sc->sc_flags.clocks_off) { 333 334 DPRINTFN(5, "\n"); 335 336 /* TODO - platform specific */ 337 338 sc->sc_flags.clocks_off = 1; 339 } 340 } 341 342 static void 343 dwc_otg_pull_up(struct dwc_otg_softc *sc) 344 { 345 uint32_t temp; 346 347 /* pullup D+, if possible */ 348 349 if (!sc->sc_flags.d_pulled_up && 350 sc->sc_flags.port_powered) { 351 sc->sc_flags.d_pulled_up = 1; 352 353 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 354 temp &= ~DCTL_SFTDISCON; 355 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 356 } 357 } 358 359 static void 360 dwc_otg_pull_down(struct dwc_otg_softc *sc) 361 { 362 uint32_t temp; 363 364 /* pulldown D+, if possible */ 365 366 if (sc->sc_flags.d_pulled_up) { 367 sc->sc_flags.d_pulled_up = 0; 368 369 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 370 temp |= DCTL_SFTDISCON; 371 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 372 } 373 } 374 375 static void 376 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 377 { 378 if (sc->sc_flags.status_suspend) { 379 /* update status bits */ 380 sc->sc_flags.status_suspend = 0; 381 sc->sc_flags.change_suspend = 1; 382 383 if (sc->sc_flags.status_device_mode) { 384 /* 385 * Disable resume interrupt and enable suspend 386 * interrupt: 387 */ 388 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 389 sc->sc_irq_mask |= GINTSTS_USBSUSP; 390 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 391 } 392 393 /* complete root HUB interrupt endpoint */ 394 dwc_otg_root_intr(sc); 395 } 396 } 397 398 static void 399 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 400 { 401 if (!sc->sc_flags.status_suspend) { 402 /* update status bits */ 403 sc->sc_flags.status_suspend = 1; 404 sc->sc_flags.change_suspend = 1; 405 406 if (sc->sc_flags.status_device_mode) { 407 /* 408 * Disable suspend interrupt and enable resume 409 * interrupt: 410 */ 411 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 412 sc->sc_irq_mask |= GINTSTS_WKUPINT; 413 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 414 } 415 416 /* complete root HUB interrupt endpoint */ 417 dwc_otg_root_intr(sc); 418 } 419 } 420 421 static void 422 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 423 { 424 if (!sc->sc_flags.status_suspend) 425 return; 426 427 DPRINTFN(5, "Remote wakeup\n"); 428 429 if (sc->sc_flags.status_device_mode) { 430 uint32_t temp; 431 432 /* enable remote wakeup signalling */ 433 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 434 temp |= DCTL_RMTWKUPSIG; 435 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 436 437 /* Wait 8ms for remote wakeup to complete. */ 438 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 439 440 temp &= ~DCTL_RMTWKUPSIG; 441 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 442 } else { 443 /* enable USB port */ 444 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 445 446 /* wait 10ms */ 447 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 448 449 /* resume port */ 450 sc->sc_hprt_val |= HPRT_PRTRES; 451 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 452 453 /* Wait 100ms for resume signalling to complete. */ 454 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 455 456 /* clear suspend and resume */ 457 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 458 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 459 460 /* Wait 4ms */ 461 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 462 } 463 464 /* need to fake resume IRQ */ 465 dwc_otg_resume_irq(sc); 466 } 467 468 static void 469 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 470 { 471 uint32_t temp; 472 473 DPRINTFN(5, "addr=%d\n", addr); 474 475 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 476 temp &= ~DCFG_DEVADDR_SET(0x7F); 477 temp |= DCFG_DEVADDR_SET(addr); 478 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 479 } 480 481 static void 482 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 483 { 484 DPRINTFN(5, "RX status clear\n"); 485 486 /* enable RX FIFO level interrupt */ 487 sc->sc_irq_mask |= GINTSTS_RXFLVL; 488 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 489 490 /* clear cached status */ 491 sc->sc_last_rx_status = 0; 492 } 493 494 static void 495 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 496 { 497 uint32_t hcint; 498 499 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 500 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 501 502 /* clear buffered interrupts */ 503 sc->sc_chan_state[x].hcint = 0; 504 } 505 506 static uint8_t 507 dwc_otg_host_channel_wait(struct dwc_otg_td *td) 508 { 509 struct dwc_otg_softc *sc; 510 uint8_t x; 511 512 x = td->channel; 513 514 DPRINTF("CH=%d\n", x); 515 516 /* get pointer to softc */ 517 sc = DWC_OTG_PC2SC(td->pc); 518 519 if (sc->sc_chan_state[x].wait_sof == 0) { 520 dwc_otg_clear_hcint(sc, x); 521 return (1); /* done */ 522 } 523 524 if (x == 0) 525 return (0); /* wait */ 526 527 /* assume NAK-ing is next */ 528 if (sc->sc_chan_state[x].hcint & HCINT_NYET) 529 return (0); /* wait */ 530 531 /* find new disabled channel */ 532 for (x = 1; x != sc->sc_host_ch_max; x++) { 533 534 if (sc->sc_chan_state[x].allocated) 535 continue; 536 if (sc->sc_chan_state[x].wait_sof != 0) 537 continue; 538 539 sc->sc_chan_state[td->channel].allocated = 0; 540 sc->sc_chan_state[x].allocated = 1; 541 542 if (sc->sc_chan_state[td->channel].suspended) { 543 sc->sc_chan_state[td->channel].suspended = 0; 544 sc->sc_chan_state[x].suspended = 1; 545 } 546 547 /* clear interrupts */ 548 dwc_otg_clear_hcint(sc, x); 549 550 DPRINTF("CH=%d HCCHAR=0x%08x " 551 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 552 553 /* ack any pending messages */ 554 if (sc->sc_last_rx_status != 0 && 555 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == td->channel) { 556 /* get rid of message */ 557 dwc_otg_common_rx_ack(sc); 558 } 559 560 /* move active channel */ 561 sc->sc_active_rx_ep &= ~(1 << td->channel); 562 sc->sc_active_rx_ep |= (1 << x); 563 564 /* set channel */ 565 td->channel = x; 566 567 return (1); /* new channel allocated */ 568 } 569 return (0); /* wait */ 570 } 571 572 static uint8_t 573 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 574 { 575 struct dwc_otg_softc *sc; 576 uint8_t x; 577 uint8_t max_channel; 578 579 if (td->channel < DWC_OTG_MAX_CHANNELS) 580 return (0); /* already allocated */ 581 582 /* get pointer to softc */ 583 sc = DWC_OTG_PC2SC(td->pc); 584 585 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 586 max_channel = 1; 587 x = 0; 588 } else { 589 max_channel = sc->sc_host_ch_max; 590 x = 1; 591 } 592 593 for (; x != max_channel; x++) { 594 595 if (sc->sc_chan_state[x].allocated) 596 continue; 597 if (sc->sc_chan_state[x].wait_sof != 0) 598 continue; 599 600 sc->sc_chan_state[x].allocated = 1; 601 602 /* clear interrupts */ 603 dwc_otg_clear_hcint(sc, x); 604 605 DPRINTF("CH=%d HCCHAR=0x%08x " 606 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 607 608 /* set active channel */ 609 sc->sc_active_rx_ep |= (1 << x); 610 611 /* set channel */ 612 td->channel = x; 613 614 return (0); /* allocated */ 615 } 616 return (1); /* busy */ 617 } 618 619 static void 620 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 621 { 622 uint32_t hcchar; 623 if (sc->sc_chan_state[x].wait_sof != 0) 624 return; 625 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 626 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 627 /* disable channel */ 628 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 629 HCCHAR_CHENA | HCCHAR_CHDIS); 630 /* don't re-use channel until next SOF is transmitted */ 631 sc->sc_chan_state[x].wait_sof = 2; 632 /* enable SOF interrupt */ 633 sc->sc_irq_mask |= GINTMSK_SOFMSK; 634 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 635 } 636 } 637 638 static void 639 dwc_otg_host_channel_free(struct dwc_otg_td *td) 640 { 641 struct dwc_otg_softc *sc; 642 uint8_t x; 643 644 if (td->channel >= DWC_OTG_MAX_CHANNELS) 645 return; /* already freed */ 646 647 /* free channel */ 648 x = td->channel; 649 td->channel = DWC_OTG_MAX_CHANNELS; 650 651 DPRINTF("CH=%d\n", x); 652 653 /* get pointer to softc */ 654 sc = DWC_OTG_PC2SC(td->pc); 655 656 dwc_otg_host_channel_disable(sc, x); 657 658 sc->sc_chan_state[x].allocated = 0; 659 sc->sc_chan_state[x].suspended = 0; 660 661 /* ack any pending messages */ 662 if (sc->sc_last_rx_status != 0 && 663 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 664 dwc_otg_common_rx_ack(sc); 665 } 666 667 /* clear active channel */ 668 sc->sc_active_rx_ep &= ~(1 << x); 669 } 670 671 static uint8_t 672 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 673 { 674 struct usb_device_request req __aligned(4); 675 struct dwc_otg_softc *sc; 676 uint32_t hcint; 677 uint32_t hcchar; 678 679 if (dwc_otg_host_channel_alloc(td)) 680 return (1); /* busy */ 681 682 /* get pointer to softc */ 683 sc = DWC_OTG_PC2SC(td->pc); 684 685 hcint = sc->sc_chan_state[td->channel].hcint; 686 687 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 688 td->channel, td->state, hcint, 689 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 690 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 691 692 if (hcint & HCINT_STALL) { 693 DPRINTF("CH=%d STALL\n", td->channel); 694 td->error_stall = 1; 695 td->error_any = 1; 696 return (0); /* complete */ 697 } 698 699 if (hcint & HCINT_ERRORS) { 700 DPRINTF("CH=%d ERROR\n", td->channel); 701 td->errcnt++; 702 if (td->hcsplt != 0 || td->errcnt >= 3) { 703 td->error_any = 1; 704 return (0); /* complete */ 705 } 706 } 707 708 /* channel must be disabled before we can complete the transfer */ 709 710 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 711 HCINT_ACK | HCINT_NYET)) { 712 713 dwc_otg_host_channel_disable(sc, td->channel); 714 715 if (!(hcint & HCINT_ERRORS)) 716 td->errcnt = 0; 717 } 718 719 switch (td->state) { 720 case DWC_CHAN_ST_START: 721 goto send_pkt; 722 723 case DWC_CHAN_ST_WAIT_ANE: 724 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 725 if (!dwc_otg_host_channel_wait(td)) 726 break; 727 td->did_nak = 1; 728 goto send_pkt; 729 } 730 if (hcint & (HCINT_ACK | HCINT_NYET)) { 731 if (!dwc_otg_host_channel_wait(td)) 732 break; 733 td->offset += td->tx_bytes; 734 td->remainder -= td->tx_bytes; 735 td->toggle = 1; 736 return (0); /* complete */ 737 } 738 break; 739 case DWC_CHAN_ST_WAIT_S_ANE: 740 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 741 if (!dwc_otg_host_channel_wait(td)) 742 break; 743 td->did_nak = 1; 744 goto send_pkt; 745 } 746 if (hcint & (HCINT_ACK | HCINT_NYET)) { 747 if (!dwc_otg_host_channel_wait(td)) 748 break; 749 goto send_cpkt; 750 } 751 break; 752 case DWC_CHAN_ST_WAIT_C_ANE: 753 if (hcint & HCINT_NYET) { 754 if (!dwc_otg_host_channel_wait(td)) 755 break; 756 goto send_cpkt; 757 } 758 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 759 if (!dwc_otg_host_channel_wait(td)) 760 break; 761 td->did_nak = 1; 762 goto send_pkt; 763 } 764 if (hcint & HCINT_ACK) { 765 if (!dwc_otg_host_channel_wait(td)) 766 break; 767 td->offset += td->tx_bytes; 768 td->remainder -= td->tx_bytes; 769 td->toggle = 1; 770 return (0); /* complete */ 771 } 772 break; 773 default: 774 break; 775 } 776 return (1); /* busy */ 777 778 send_pkt: 779 if (sizeof(req) != td->remainder) { 780 td->error_any = 1; 781 return (0); /* complete */ 782 } 783 784 if (td->hcsplt != 0) { 785 td->hcsplt &= ~HCSPLT_COMPSPLT; 786 td->state = DWC_CHAN_ST_WAIT_S_ANE; 787 } else { 788 td->state = DWC_CHAN_ST_WAIT_ANE; 789 } 790 791 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 792 793 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 794 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 795 (1 << HCTSIZ_PKTCNT_SHIFT) | 796 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 797 798 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 799 800 hcchar = td->hcchar; 801 hcchar &= ~HCCHAR_EPDIR_IN; 802 803 /* must enable channel before writing data to FIFO */ 804 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 805 806 /* transfer data into FIFO */ 807 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 808 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 809 810 /* store number of bytes transmitted */ 811 td->tx_bytes = sizeof(req); 812 813 return (1); /* busy */ 814 815 send_cpkt: 816 td->hcsplt |= HCSPLT_COMPSPLT; 817 td->state = DWC_CHAN_ST_WAIT_C_ANE; 818 819 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 820 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 821 822 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 823 824 hcchar = td->hcchar; 825 hcchar &= ~HCCHAR_EPDIR_IN; 826 827 /* must enable channel before writing data to FIFO */ 828 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 829 830 return (1); /* busy */ 831 } 832 833 static uint8_t 834 dwc_otg_setup_rx(struct dwc_otg_td *td) 835 { 836 struct dwc_otg_softc *sc; 837 struct usb_device_request req __aligned(4); 838 uint32_t temp; 839 uint16_t count; 840 841 /* get pointer to softc */ 842 sc = DWC_OTG_PC2SC(td->pc); 843 844 /* check endpoint status */ 845 846 if (sc->sc_last_rx_status == 0) 847 goto not_complete; 848 849 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 850 goto not_complete; 851 852 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 853 GRXSTSRD_DPID_DATA0) { 854 /* release FIFO */ 855 dwc_otg_common_rx_ack(sc); 856 goto not_complete; 857 } 858 859 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 860 GRXSTSRD_STP_DATA) { 861 /* release FIFO */ 862 dwc_otg_common_rx_ack(sc); 863 goto not_complete; 864 } 865 866 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 867 868 /* clear did stall */ 869 td->did_stall = 0; 870 871 /* get the packet byte count */ 872 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 873 874 /* verify data length */ 875 if (count != td->remainder) { 876 DPRINTFN(0, "Invalid SETUP packet " 877 "length, %d bytes\n", count); 878 /* release FIFO */ 879 dwc_otg_common_rx_ack(sc); 880 goto not_complete; 881 } 882 if (count != sizeof(req)) { 883 DPRINTFN(0, "Unsupported SETUP packet " 884 "length, %d bytes\n", count); 885 /* release FIFO */ 886 dwc_otg_common_rx_ack(sc); 887 goto not_complete; 888 } 889 890 /* copy in control request */ 891 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 892 893 /* copy data into real buffer */ 894 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 895 896 td->offset = sizeof(req); 897 td->remainder = 0; 898 899 /* sneak peek the set address */ 900 if ((req.bmRequestType == UT_WRITE_DEVICE) && 901 (req.bRequest == UR_SET_ADDRESS)) { 902 /* must write address before ZLP */ 903 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 904 } 905 906 /* don't send any data by default */ 907 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 908 DXEPTSIZ_SET_NPKT(0) | 909 DXEPTSIZ_SET_NBYTES(0)); 910 911 temp = sc->sc_in_ctl[0]; 912 913 /* enable IN endpoint */ 914 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 915 temp | DIEPCTL_EPENA); 916 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 917 temp | DIEPCTL_SNAK); 918 919 /* reset IN endpoint buffer */ 920 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 921 GRSTCTL_TXFIFO(0) | 922 GRSTCTL_TXFFLSH); 923 924 /* acknowledge RX status */ 925 dwc_otg_common_rx_ack(sc); 926 return (0); /* complete */ 927 928 not_complete: 929 /* abort any ongoing transfer, before enabling again */ 930 931 temp = sc->sc_out_ctl[0]; 932 933 temp |= DOEPCTL_EPENA | 934 DOEPCTL_SNAK; 935 936 /* enable OUT endpoint */ 937 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 938 939 if (!td->did_stall) { 940 td->did_stall = 1; 941 942 DPRINTFN(5, "stalling IN and OUT direction\n"); 943 944 /* set stall after enabling endpoint */ 945 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 946 temp | DOEPCTL_STALL); 947 948 temp = sc->sc_in_ctl[0]; 949 950 /* set stall assuming endpoint is enabled */ 951 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 952 temp | DIEPCTL_STALL); 953 } 954 955 /* setup number of buffers to receive */ 956 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 957 DXEPTSIZ_SET_MULTI(3) | 958 DXEPTSIZ_SET_NPKT(1) | 959 DXEPTSIZ_SET_NBYTES(sizeof(req))); 960 961 return (1); /* not complete */ 962 } 963 964 static uint8_t 965 dwc_otg_host_rate_check(struct dwc_otg_td *td, 966 uint8_t do_inc) 967 { 968 struct dwc_otg_softc *sc; 969 uint8_t ep_type; 970 971 /* get pointer to softc */ 972 sc = DWC_OTG_PC2SC(td->pc); 973 974 ep_type = ((td->hcchar & 975 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 976 977 if (sc->sc_chan_state[td->channel].suspended) 978 goto busy; 979 980 if (ep_type == UE_ISOCHRONOUS) { 981 if (td->tmr_val & 1) 982 td->hcchar |= HCCHAR_ODDFRM; 983 else 984 td->hcchar &= ~HCCHAR_ODDFRM; 985 if (do_inc) 986 td->tmr_val += td->tmr_res; 987 } else if (ep_type == UE_INTERRUPT) { 988 if ((sc->sc_tmr_val & 0xFF) != td->tmr_val) 989 goto busy; 990 if (do_inc) 991 td->tmr_val += td->tmr_res; 992 } else if (td->did_nak != 0) { 993 goto busy; 994 } 995 996 if (ep_type == UE_ISOCHRONOUS) { 997 td->toggle = 0; 998 } else if (td->set_toggle) { 999 td->set_toggle = 0; 1000 td->toggle = 1; 1001 } 1002 return (0); 1003 busy: 1004 return (1); 1005 } 1006 1007 static uint8_t 1008 dwc_otg_host_data_rx(struct dwc_otg_td *td) 1009 { 1010 struct dwc_otg_softc *sc; 1011 uint32_t hcint; 1012 uint32_t hcchar; 1013 uint32_t count; 1014 1015 if (dwc_otg_host_channel_alloc(td)) 1016 return (1); /* busy */ 1017 1018 /* get pointer to softc */ 1019 sc = DWC_OTG_PC2SC(td->pc); 1020 1021 hcint = sc->sc_chan_state[td->channel].hcint; 1022 1023 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1024 td->channel, td->state, hcint, 1025 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1026 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1027 1028 /* check interrupt bits */ 1029 1030 if (hcint & HCINT_STALL) { 1031 DPRINTF("CH=%d STALL\n", td->channel); 1032 td->error_stall = 1; 1033 td->error_any = 1; 1034 return (0); /* complete */ 1035 } 1036 1037 if (hcint & HCINT_ERRORS) { 1038 DPRINTF("CH=%d ERROR\n", td->channel); 1039 td->errcnt++; 1040 if (td->hcsplt != 0 || td->errcnt >= 3) { 1041 td->error_any = 1; 1042 return (0); /* complete */ 1043 } 1044 } 1045 1046 /* channel must be disabled before we can complete the transfer */ 1047 1048 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1049 HCINT_ACK | HCINT_NYET)) { 1050 1051 dwc_otg_host_channel_disable(sc, td->channel); 1052 1053 if (!(hcint & HCINT_ERRORS)) 1054 td->errcnt = 0; 1055 } 1056 1057 /* check endpoint status */ 1058 if (sc->sc_last_rx_status == 0) 1059 goto check_state; 1060 1061 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 1062 goto check_state; 1063 1064 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1065 case GRXSTSRH_IN_DATA: 1066 1067 DPRINTF("DATA\n"); 1068 1069 td->toggle ^= 1; 1070 1071 /* get the packet byte count */ 1072 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1073 1074 /* verify the packet byte count */ 1075 if (count != td->max_packet_size) { 1076 if (count < td->max_packet_size) { 1077 /* we have a short packet */ 1078 td->short_pkt = 1; 1079 td->got_short = 1; 1080 } else { 1081 /* invalid USB packet */ 1082 td->error_any = 1; 1083 1084 /* release FIFO */ 1085 dwc_otg_common_rx_ack(sc); 1086 return (0); /* we are complete */ 1087 } 1088 } 1089 1090 /* verify the packet byte count */ 1091 if (count > td->remainder) { 1092 /* invalid USB packet */ 1093 td->error_any = 1; 1094 1095 /* release FIFO */ 1096 dwc_otg_common_rx_ack(sc); 1097 return (0); /* we are complete */ 1098 } 1099 1100 usbd_copy_in(td->pc, td->offset, 1101 sc->sc_rx_bounce_buffer, count); 1102 1103 td->remainder -= count; 1104 td->offset += count; 1105 hcint |= HCINT_SOFTWARE_ONLY | HCINT_ACK; 1106 sc->sc_chan_state[td->channel].hcint = hcint; 1107 break; 1108 1109 default: 1110 DPRINTF("OTHER\n"); 1111 break; 1112 } 1113 /* release FIFO */ 1114 dwc_otg_common_rx_ack(sc); 1115 1116 check_state: 1117 switch (td->state) { 1118 case DWC_CHAN_ST_START: 1119 if (td->hcsplt != 0) 1120 goto receive_spkt; 1121 else 1122 goto receive_pkt; 1123 1124 case DWC_CHAN_ST_WAIT_ANE: 1125 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1126 if (!dwc_otg_host_channel_wait(td)) 1127 break; 1128 1129 td->did_nak = 1; 1130 if (td->hcsplt != 0) 1131 goto receive_spkt; 1132 else 1133 goto receive_pkt; 1134 } 1135 if (hcint & HCINT_NYET) { 1136 if (td->hcsplt != 0) 1137 goto receive_pkt; 1138 } 1139 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1140 break; 1141 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1142 if (!dwc_otg_host_channel_wait(td)) 1143 break; 1144 1145 /* check if we are complete */ 1146 if ((td->remainder == 0) || (td->got_short != 0)) { 1147 if (td->short_pkt) 1148 return (0); /* complete */ 1149 1150 /* 1151 * Else need to receive a zero length 1152 * packet. 1153 */ 1154 } 1155 if (td->hcsplt != 0) 1156 goto receive_spkt; 1157 else 1158 goto receive_pkt; 1159 } 1160 break; 1161 1162 case DWC_CHAN_ST_WAIT_S_ANE: 1163 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1164 if (!dwc_otg_host_channel_wait(td)) 1165 break; 1166 1167 td->did_nak = 1; 1168 goto receive_spkt; 1169 } 1170 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1171 if (!dwc_otg_host_channel_wait(td)) 1172 break; 1173 goto receive_pkt; 1174 } 1175 break; 1176 1177 case DWC_CHAN_ST_RX_PKT: 1178 goto receive_pkt; 1179 1180 case DWC_CHAN_ST_RX_SPKT: 1181 goto receive_spkt; 1182 1183 default: 1184 break; 1185 } 1186 goto busy; 1187 1188 receive_pkt: 1189 if (dwc_otg_host_rate_check(td, 1)) { 1190 td->state = DWC_CHAN_ST_RX_PKT; 1191 dwc_otg_host_channel_free(td); 1192 goto busy; 1193 } 1194 1195 if (td->hcsplt != 0) 1196 td->hcsplt |= HCSPLT_COMPSPLT; 1197 td->state = DWC_CHAN_ST_WAIT_ANE; 1198 1199 /* receive one packet */ 1200 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1201 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1202 (1 << HCTSIZ_PKTCNT_SHIFT) | 1203 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1204 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1205 1206 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1207 1208 hcchar = td->hcchar; 1209 hcchar |= HCCHAR_EPDIR_IN; 1210 1211 /* must enable channel before data can be received */ 1212 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1213 1214 goto busy; 1215 1216 receive_spkt: 1217 if (dwc_otg_host_rate_check(td, 0)) { 1218 td->state = DWC_CHAN_ST_RX_SPKT; 1219 dwc_otg_host_channel_free(td); 1220 goto busy; 1221 } 1222 1223 td->hcsplt &= ~HCSPLT_COMPSPLT; 1224 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1225 1226 /* receive one packet */ 1227 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1228 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1229 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1230 1231 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1232 1233 hcchar = td->hcchar; 1234 hcchar |= HCCHAR_EPDIR_IN; 1235 1236 /* must enable channel before data can be received */ 1237 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1238 1239 busy: 1240 return (1); /* busy */ 1241 } 1242 1243 static uint8_t 1244 dwc_otg_data_rx(struct dwc_otg_td *td) 1245 { 1246 struct dwc_otg_softc *sc; 1247 uint32_t temp; 1248 uint16_t count; 1249 uint8_t got_short; 1250 1251 got_short = 0; 1252 1253 /* get pointer to softc */ 1254 sc = DWC_OTG_PC2SC(td->pc); 1255 1256 /* check endpoint status */ 1257 if (sc->sc_last_rx_status == 0) 1258 goto not_complete; 1259 1260 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1261 goto not_complete; 1262 1263 /* check for SETUP packet */ 1264 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1265 GRXSTSRD_STP_DATA) { 1266 if (td->remainder == 0) { 1267 /* 1268 * We are actually complete and have 1269 * received the next SETUP 1270 */ 1271 DPRINTFN(5, "faking complete\n"); 1272 return (0); /* complete */ 1273 } 1274 /* 1275 * USB Host Aborted the transfer. 1276 */ 1277 td->error_any = 1; 1278 return (0); /* complete */ 1279 } 1280 1281 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1282 GRXSTSRD_OUT_DATA) { 1283 /* release FIFO */ 1284 dwc_otg_common_rx_ack(sc); 1285 goto not_complete; 1286 } 1287 1288 /* get the packet byte count */ 1289 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1290 1291 /* verify the packet byte count */ 1292 if (count != td->max_packet_size) { 1293 if (count < td->max_packet_size) { 1294 /* we have a short packet */ 1295 td->short_pkt = 1; 1296 got_short = 1; 1297 } else { 1298 /* invalid USB packet */ 1299 td->error_any = 1; 1300 1301 /* release FIFO */ 1302 dwc_otg_common_rx_ack(sc); 1303 return (0); /* we are complete */ 1304 } 1305 } 1306 /* verify the packet byte count */ 1307 if (count > td->remainder) { 1308 /* invalid USB packet */ 1309 td->error_any = 1; 1310 1311 /* release FIFO */ 1312 dwc_otg_common_rx_ack(sc); 1313 return (0); /* we are complete */ 1314 } 1315 1316 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1317 td->remainder -= count; 1318 td->offset += count; 1319 1320 /* release FIFO */ 1321 dwc_otg_common_rx_ack(sc); 1322 1323 /* check if we are complete */ 1324 if ((td->remainder == 0) || got_short) { 1325 if (td->short_pkt) { 1326 /* we are complete */ 1327 return (0); 1328 } 1329 /* else need to receive a zero length packet */ 1330 } 1331 1332 not_complete: 1333 1334 temp = sc->sc_out_ctl[td->ep_no]; 1335 1336 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1337 1338 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1339 1340 /* enable SETUP and transfer complete interrupt */ 1341 if (td->ep_no == 0) { 1342 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1343 DXEPTSIZ_SET_NPKT(1) | 1344 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1345 } else { 1346 /* allow reception of multiple packets */ 1347 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1348 DXEPTSIZ_SET_MULTI(1) | 1349 DXEPTSIZ_SET_NPKT(4) | 1350 DXEPTSIZ_SET_NBYTES(4 * 1351 ((td->max_packet_size + 3) & ~3))); 1352 } 1353 return (1); /* not complete */ 1354 } 1355 1356 static uint8_t 1357 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1358 { 1359 struct dwc_otg_softc *sc; 1360 uint32_t count; 1361 uint32_t hcint; 1362 uint32_t hcchar; 1363 uint8_t ep_type; 1364 1365 if (dwc_otg_host_channel_alloc(td)) 1366 return (1); /* busy */ 1367 1368 /* get pointer to softc */ 1369 sc = DWC_OTG_PC2SC(td->pc); 1370 1371 ep_type = ((td->hcchar & 1372 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1373 1374 hcint = sc->sc_chan_state[td->channel].hcint; 1375 1376 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1377 td->channel, td->state, hcint, 1378 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1379 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1380 1381 if (hcint & HCINT_STALL) { 1382 DPRINTF("CH=%d STALL\n", td->channel); 1383 td->error_stall = 1; 1384 td->error_any = 1; 1385 return (0); /* complete */ 1386 } 1387 1388 if (hcint & HCINT_ERRORS) { 1389 DPRINTF("CH=%d ERROR\n", td->channel); 1390 td->errcnt++; 1391 if (td->hcsplt != 0 || td->errcnt >= 3) { 1392 td->error_any = 1; 1393 return (0); /* complete */ 1394 } 1395 } 1396 1397 /* channel must be disabled before we can complete the transfer */ 1398 1399 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1400 HCINT_ACK | HCINT_NYET)) { 1401 1402 dwc_otg_host_channel_disable(sc, td->channel); 1403 1404 if (!(hcint & HCINT_ERRORS)) 1405 td->errcnt = 0; 1406 } 1407 1408 switch (td->state) { 1409 case DWC_CHAN_ST_START: 1410 goto send_pkt; 1411 1412 case DWC_CHAN_ST_WAIT_ANE: 1413 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1414 if (!dwc_otg_host_channel_wait(td)) 1415 break; 1416 td->did_nak = 1; 1417 goto send_pkt; 1418 } 1419 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1420 if (!dwc_otg_host_channel_wait(td)) 1421 break; 1422 1423 td->offset += td->tx_bytes; 1424 td->remainder -= td->tx_bytes; 1425 td->toggle ^= 1; 1426 1427 /* check remainder */ 1428 if (td->remainder == 0) { 1429 if (td->short_pkt) 1430 return (0); /* complete */ 1431 1432 /* 1433 * Else we need to transmit a short 1434 * packet: 1435 */ 1436 } 1437 goto send_pkt; 1438 } 1439 break; 1440 case DWC_CHAN_ST_WAIT_S_ANE: 1441 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1442 if (!dwc_otg_host_channel_wait(td)) 1443 break; 1444 td->did_nak = 1; 1445 goto send_pkt; 1446 } 1447 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1448 if (!dwc_otg_host_channel_wait(td)) 1449 break; 1450 goto send_cpkt; 1451 } 1452 break; 1453 case DWC_CHAN_ST_WAIT_C_ANE: 1454 if (hcint & HCINT_NYET) { 1455 if (!dwc_otg_host_channel_wait(td)) 1456 break; 1457 goto send_cpkt; 1458 } 1459 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1460 if (!dwc_otg_host_channel_wait(td)) 1461 break; 1462 td->did_nak = 1; 1463 goto send_pkt; 1464 } 1465 if (hcint & HCINT_ACK) { 1466 if (!dwc_otg_host_channel_wait(td)) 1467 break; 1468 td->offset += td->tx_bytes; 1469 td->remainder -= td->tx_bytes; 1470 td->toggle ^= 1; 1471 1472 /* check remainder */ 1473 if (td->remainder == 0) { 1474 if (td->short_pkt) 1475 return (0); /* complete */ 1476 1477 /* else we need to transmit a short packet */ 1478 } 1479 goto send_pkt; 1480 } 1481 break; 1482 1483 case DWC_CHAN_ST_TX_PKT: 1484 goto send_pkt; 1485 1486 case DWC_CHAN_ST_TX_CPKT: 1487 goto send_cpkt; 1488 1489 default: 1490 break; 1491 } 1492 goto busy; 1493 1494 send_pkt: 1495 if (dwc_otg_host_rate_check(td, 1)) { 1496 td->state = DWC_CHAN_ST_TX_PKT; 1497 dwc_otg_host_channel_free(td); 1498 goto busy; 1499 } 1500 1501 if (td->hcsplt != 0) { 1502 td->hcsplt &= ~HCSPLT_COMPSPLT; 1503 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1504 } else { 1505 td->state = DWC_CHAN_ST_WAIT_ANE; 1506 } 1507 1508 /* send one packet at a time */ 1509 count = td->max_packet_size; 1510 if (td->remainder < count) { 1511 /* we have a short packet */ 1512 td->short_pkt = 1; 1513 count = td->remainder; 1514 } 1515 1516 /* TODO: HCTSIZ_DOPNG */ 1517 1518 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1519 (count << HCTSIZ_XFERSIZE_SHIFT) | 1520 (1 << HCTSIZ_PKTCNT_SHIFT) | 1521 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1522 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1523 1524 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1525 1526 hcchar = td->hcchar; 1527 hcchar &= ~HCCHAR_EPDIR_IN; 1528 1529 /* must enable before writing data to FIFO */ 1530 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1531 1532 if (count != 0) { 1533 1534 /* clear topmost word before copy */ 1535 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1536 1537 /* copy out data */ 1538 usbd_copy_out(td->pc, td->offset, 1539 sc->sc_tx_bounce_buffer, count); 1540 1541 /* transfer data into FIFO */ 1542 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1543 DOTG_DFIFO(td->channel), 1544 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1545 } 1546 1547 /* store number of bytes transmitted */ 1548 td->tx_bytes = count; 1549 1550 goto busy; 1551 1552 send_cpkt: 1553 td->hcsplt |= HCSPLT_COMPSPLT; 1554 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1555 1556 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1557 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1558 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1559 1560 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1561 1562 hcchar = td->hcchar; 1563 hcchar &= ~HCCHAR_EPDIR_IN; 1564 1565 /* must enable channel before writing data to FIFO */ 1566 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1567 1568 busy: 1569 return (1); /* busy */ 1570 } 1571 1572 static uint8_t 1573 dwc_otg_data_tx(struct dwc_otg_td *td) 1574 { 1575 struct dwc_otg_softc *sc; 1576 uint32_t max_buffer; 1577 uint32_t count; 1578 uint32_t fifo_left; 1579 uint32_t mpkt; 1580 uint32_t temp; 1581 uint8_t to; 1582 1583 to = 3; /* don't loop forever! */ 1584 1585 /* get pointer to softc */ 1586 sc = DWC_OTG_PC2SC(td->pc); 1587 1588 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1589 1590 repeat: 1591 /* check for for endpoint 0 data */ 1592 1593 temp = sc->sc_last_rx_status; 1594 1595 if ((td->ep_no == 0) && (temp != 0) && 1596 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1597 1598 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1599 GRXSTSRD_STP_DATA) { 1600 1601 /* dump data - wrong direction */ 1602 dwc_otg_common_rx_ack(sc); 1603 } else { 1604 /* 1605 * The current transfer was cancelled 1606 * by the USB Host: 1607 */ 1608 td->error_any = 1; 1609 return (0); /* complete */ 1610 } 1611 } 1612 1613 /* fill in more TX data, if possible */ 1614 if (td->tx_bytes != 0) { 1615 1616 uint16_t cpkt; 1617 1618 /* check if packets have been transferred */ 1619 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1620 1621 /* get current packet number */ 1622 cpkt = DXEPTSIZ_GET_NPKT(temp); 1623 1624 if (cpkt >= td->npkt) { 1625 fifo_left = 0; 1626 } else { 1627 if (max_buffer != 0) { 1628 fifo_left = (td->npkt - cpkt) * 1629 td->max_packet_size; 1630 1631 if (fifo_left > max_buffer) 1632 fifo_left = max_buffer; 1633 } else { 1634 fifo_left = td->max_packet_size; 1635 } 1636 } 1637 1638 count = td->tx_bytes; 1639 if (count > fifo_left) 1640 count = fifo_left; 1641 1642 if (count != 0) { 1643 1644 /* clear topmost word before copy */ 1645 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1646 1647 /* copy out data */ 1648 usbd_copy_out(td->pc, td->offset, 1649 sc->sc_tx_bounce_buffer, count); 1650 1651 /* transfer data into FIFO */ 1652 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1653 DOTG_DFIFO(td->ep_no), 1654 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1655 1656 td->tx_bytes -= count; 1657 td->remainder -= count; 1658 td->offset += count; 1659 td->npkt = cpkt; 1660 } 1661 if (td->tx_bytes != 0) 1662 goto not_complete; 1663 1664 /* check remainder */ 1665 if (td->remainder == 0) { 1666 if (td->short_pkt) 1667 return (0); /* complete */ 1668 1669 /* else we need to transmit a short packet */ 1670 } 1671 } 1672 1673 if (!to--) 1674 goto not_complete; 1675 1676 /* check if not all packets have been transferred */ 1677 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1678 1679 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1680 1681 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 1682 "DIEPCTL=0x%08x\n", td->ep_no, 1683 DXEPTSIZ_GET_NPKT(temp), 1684 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 1685 1686 goto not_complete; 1687 } 1688 1689 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 1690 1691 /* try to optimise by sending more data */ 1692 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 1693 1694 /* send multiple packets at the same time */ 1695 mpkt = max_buffer / td->max_packet_size; 1696 1697 if (mpkt > 0x3FE) 1698 mpkt = 0x3FE; 1699 1700 count = td->remainder; 1701 if (count > 0x7FFFFF) 1702 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 1703 1704 td->npkt = count / td->max_packet_size; 1705 1706 /* 1707 * NOTE: We could use 0x3FE instead of "mpkt" in the 1708 * check below to get more throughput, but then we 1709 * have a dependency towards non-generic chip features 1710 * to disable the TX-FIFO-EMPTY interrupts on a per 1711 * endpoint basis. Increase the maximum buffer size of 1712 * the IN endpoint to increase the performance. 1713 */ 1714 if (td->npkt > mpkt) { 1715 td->npkt = mpkt; 1716 count = td->max_packet_size * mpkt; 1717 } else if ((count == 0) || (count % td->max_packet_size)) { 1718 /* we are transmitting a short packet */ 1719 td->npkt++; 1720 td->short_pkt = 1; 1721 } 1722 } else { 1723 /* send one packet at a time */ 1724 mpkt = 1; 1725 count = td->max_packet_size; 1726 if (td->remainder < count) { 1727 /* we have a short packet */ 1728 td->short_pkt = 1; 1729 count = td->remainder; 1730 } 1731 td->npkt = 1; 1732 } 1733 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 1734 DXEPTSIZ_SET_MULTI(1) | 1735 DXEPTSIZ_SET_NPKT(td->npkt) | 1736 DXEPTSIZ_SET_NBYTES(count)); 1737 1738 /* make room for buffering */ 1739 td->npkt += mpkt; 1740 1741 temp = sc->sc_in_ctl[td->ep_no]; 1742 1743 /* must enable before writing data to FIFO */ 1744 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 1745 DIEPCTL_EPENA | 1746 DIEPCTL_CNAK); 1747 1748 td->tx_bytes = count; 1749 1750 /* check remainder */ 1751 if (td->tx_bytes == 0 && 1752 td->remainder == 0) { 1753 if (td->short_pkt) 1754 return (0); /* complete */ 1755 1756 /* else we need to transmit a short packet */ 1757 } 1758 goto repeat; 1759 1760 not_complete: 1761 return (1); /* not complete */ 1762 } 1763 1764 static uint8_t 1765 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 1766 { 1767 struct dwc_otg_softc *sc; 1768 uint32_t temp; 1769 1770 /* get pointer to softc */ 1771 sc = DWC_OTG_PC2SC(td->pc); 1772 1773 /* 1774 * If all packets are transferred we are complete: 1775 */ 1776 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1777 1778 /* check that all packets have been transferred */ 1779 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1780 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 1781 goto not_complete; 1782 } 1783 return (0); 1784 1785 not_complete: 1786 1787 /* we only want to know if there is a SETUP packet or free IN packet */ 1788 1789 temp = sc->sc_last_rx_status; 1790 1791 if ((td->ep_no == 0) && (temp != 0) && 1792 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1793 1794 if ((temp & GRXSTSRD_PKTSTS_MASK) == 1795 GRXSTSRD_STP_DATA) { 1796 DPRINTFN(5, "faking complete\n"); 1797 /* 1798 * Race condition: We are complete! 1799 */ 1800 return (0); 1801 } else { 1802 /* dump data - wrong direction */ 1803 dwc_otg_common_rx_ack(sc); 1804 } 1805 } 1806 return (1); /* not complete */ 1807 } 1808 1809 static uint8_t 1810 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 1811 { 1812 struct dwc_otg_td *td; 1813 uint8_t toggle; 1814 uint8_t channel; 1815 uint8_t tmr_val; 1816 uint8_t tmr_res; 1817 1818 DPRINTFN(9, "\n"); 1819 1820 td = xfer->td_transfer_cache; 1821 1822 /* 1823 * If we are suspended in host mode and no channel is 1824 * allocated, simply return: 1825 */ 1826 if (xfer->xroot->udev->flags.self_suspended != 0 && 1827 xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST && 1828 td->channel >= DWC_OTG_MAX_CHANNELS) { 1829 return (1); /* not complete */ 1830 } 1831 while (1) { 1832 if ((td->func) (td)) { 1833 /* operation in progress */ 1834 break; 1835 } 1836 if (((void *)td) == xfer->td_transfer_last) { 1837 goto done; 1838 } 1839 if (td->error_any) { 1840 goto done; 1841 } else if (td->remainder > 0) { 1842 /* 1843 * We had a short transfer. If there is no alternate 1844 * next, stop processing ! 1845 */ 1846 if (!td->alt_next) 1847 goto done; 1848 } 1849 1850 /* 1851 * Fetch the next transfer descriptor and transfer 1852 * some flags to the next transfer descriptor 1853 */ 1854 tmr_res = td->tmr_res; 1855 tmr_val = td->tmr_val; 1856 toggle = td->toggle; 1857 channel = td->channel; 1858 td = td->obj_next; 1859 xfer->td_transfer_cache = td; 1860 td->toggle = toggle; /* transfer toggle */ 1861 td->channel = channel; /* transfer channel */ 1862 td->tmr_res = tmr_res; 1863 td->tmr_val = tmr_val; 1864 } 1865 return (1); /* not complete */ 1866 1867 done: 1868 /* compute all actual lengths */ 1869 1870 dwc_otg_standard_done(xfer); 1871 return (0); /* complete */ 1872 } 1873 1874 static void 1875 dwc_otg_timer(void *_sc) 1876 { 1877 struct dwc_otg_softc *sc = _sc; 1878 struct usb_xfer *xfer; 1879 struct dwc_otg_td *td; 1880 1881 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1882 1883 DPRINTF("\n"); 1884 1885 /* increment timer value */ 1886 sc->sc_tmr_val++; 1887 1888 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1889 td = xfer->td_transfer_cache; 1890 if (td != NULL) 1891 td->did_nak = 0; 1892 } 1893 1894 /* poll jobs */ 1895 dwc_otg_interrupt_poll(sc); 1896 1897 if (sc->sc_timer_active) { 1898 /* restart timer */ 1899 usb_callout_reset(&sc->sc_timer, 1900 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 1901 &dwc_otg_timer, sc); 1902 } 1903 } 1904 1905 static void 1906 dwc_otg_timer_start(struct dwc_otg_softc *sc) 1907 { 1908 if (sc->sc_timer_active != 0) 1909 return; 1910 1911 sc->sc_timer_active = 1; 1912 1913 /* restart timer */ 1914 usb_callout_reset(&sc->sc_timer, 1915 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 1916 &dwc_otg_timer, sc); 1917 } 1918 1919 static void 1920 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 1921 { 1922 if (sc->sc_timer_active == 0) 1923 return; 1924 1925 sc->sc_timer_active = 0; 1926 1927 /* stop timer */ 1928 usb_callout_stop(&sc->sc_timer); 1929 } 1930 1931 static void 1932 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 1933 { 1934 struct usb_xfer *xfer; 1935 uint32_t temp; 1936 uint8_t got_rx_status; 1937 uint8_t x; 1938 1939 repeat: 1940 /* get all channel interrupts */ 1941 for (x = 0; x != sc->sc_host_ch_max; x++) { 1942 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 1943 if (temp != 0) { 1944 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 1945 temp &= ~HCINT_SOFTWARE_ONLY; 1946 sc->sc_chan_state[x].hcint |= temp; 1947 } 1948 } 1949 1950 if (sc->sc_last_rx_status == 0) { 1951 1952 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 1953 if (temp & GINTSTS_RXFLVL) { 1954 /* pop current status */ 1955 sc->sc_last_rx_status = 1956 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 1957 } 1958 1959 if (sc->sc_last_rx_status != 0) { 1960 1961 uint8_t ep_no; 1962 1963 temp = sc->sc_last_rx_status & 1964 GRXSTSRD_PKTSTS_MASK; 1965 1966 /* non-data messages we simply skip */ 1967 if (temp != GRXSTSRD_STP_DATA && 1968 temp != GRXSTSRD_OUT_DATA) { 1969 dwc_otg_common_rx_ack(sc); 1970 goto repeat; 1971 } 1972 1973 temp = GRXSTSRD_BCNT_GET( 1974 sc->sc_last_rx_status); 1975 ep_no = GRXSTSRD_CHNUM_GET( 1976 sc->sc_last_rx_status); 1977 1978 /* receive data, if any */ 1979 if (temp != 0) { 1980 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 1981 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1982 DOTG_DFIFO(ep_no), 1983 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 1984 } 1985 1986 /* check if we should dump the data */ 1987 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 1988 dwc_otg_common_rx_ack(sc); 1989 goto repeat; 1990 } 1991 1992 got_rx_status = 1; 1993 1994 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 1995 sc->sc_last_rx_status, ep_no, 1996 (sc->sc_last_rx_status >> 15) & 3, 1997 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 1998 (sc->sc_last_rx_status >> 17) & 15); 1999 } else { 2000 got_rx_status = 0; 2001 } 2002 } else { 2003 uint8_t ep_no; 2004 2005 ep_no = GRXSTSRD_CHNUM_GET( 2006 sc->sc_last_rx_status); 2007 2008 /* check if we should dump the data */ 2009 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2010 dwc_otg_common_rx_ack(sc); 2011 goto repeat; 2012 } 2013 2014 got_rx_status = 1; 2015 } 2016 2017 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2018 if (!dwc_otg_xfer_do_fifo(xfer)) { 2019 /* queue has been modified */ 2020 goto repeat; 2021 } 2022 } 2023 2024 if (got_rx_status) { 2025 /* check if data was consumed */ 2026 if (sc->sc_last_rx_status == 0) 2027 goto repeat; 2028 2029 /* disable RX FIFO level interrupt */ 2030 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 2031 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2032 } 2033 } 2034 2035 static void 2036 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2037 { 2038 DPRINTFN(5, "vbus = %u\n", is_on); 2039 2040 if (is_on) { 2041 if (!sc->sc_flags.status_vbus) { 2042 sc->sc_flags.status_vbus = 1; 2043 2044 /* complete root HUB interrupt endpoint */ 2045 2046 dwc_otg_root_intr(sc); 2047 } 2048 } else { 2049 if (sc->sc_flags.status_vbus) { 2050 sc->sc_flags.status_vbus = 0; 2051 sc->sc_flags.status_bus_reset = 0; 2052 sc->sc_flags.status_suspend = 0; 2053 sc->sc_flags.change_suspend = 0; 2054 sc->sc_flags.change_connect = 1; 2055 2056 /* complete root HUB interrupt endpoint */ 2057 2058 dwc_otg_root_intr(sc); 2059 } 2060 } 2061 } 2062 2063 void 2064 dwc_otg_interrupt(struct dwc_otg_softc *sc) 2065 { 2066 uint32_t status; 2067 2068 USB_BUS_LOCK(&sc->sc_bus); 2069 2070 /* read and clear interrupt status */ 2071 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2072 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 2073 2074 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2075 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2076 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2077 2078 if (status & GINTSTS_USBRST) { 2079 2080 /* set correct state */ 2081 sc->sc_flags.status_device_mode = 1; 2082 sc->sc_flags.status_bus_reset = 0; 2083 sc->sc_flags.status_suspend = 0; 2084 sc->sc_flags.change_suspend = 0; 2085 sc->sc_flags.change_connect = 1; 2086 2087 /* complete root HUB interrupt endpoint */ 2088 dwc_otg_root_intr(sc); 2089 } 2090 2091 /* check for any bus state change interrupts */ 2092 if (status & GINTSTS_ENUMDONE) { 2093 2094 uint32_t temp; 2095 2096 DPRINTFN(5, "end of reset\n"); 2097 2098 /* set correct state */ 2099 sc->sc_flags.status_device_mode = 1; 2100 sc->sc_flags.status_bus_reset = 1; 2101 sc->sc_flags.status_suspend = 0; 2102 sc->sc_flags.change_suspend = 0; 2103 sc->sc_flags.change_connect = 1; 2104 sc->sc_flags.status_low_speed = 0; 2105 sc->sc_flags.port_enabled = 1; 2106 2107 /* reset FIFOs */ 2108 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2109 2110 /* reset function address */ 2111 dwc_otg_set_address(sc, 0); 2112 2113 /* figure out enumeration speed */ 2114 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2115 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2116 sc->sc_flags.status_high_speed = 1; 2117 else 2118 sc->sc_flags.status_high_speed = 0; 2119 2120 /* disable resume interrupt and enable suspend interrupt */ 2121 2122 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 2123 sc->sc_irq_mask |= GINTSTS_USBSUSP; 2124 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2125 2126 /* complete root HUB interrupt endpoint */ 2127 dwc_otg_root_intr(sc); 2128 } 2129 2130 if (status & GINTSTS_PRTINT) { 2131 uint32_t hprt; 2132 2133 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2134 2135 /* clear change bits */ 2136 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2137 HPRT_PRTPWR | HPRT_PRTENCHNG | 2138 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2139 sc->sc_hprt_val); 2140 2141 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2142 2143 sc->sc_flags.status_device_mode = 0; 2144 2145 if (hprt & HPRT_PRTCONNSTS) 2146 sc->sc_flags.status_bus_reset = 1; 2147 else 2148 sc->sc_flags.status_bus_reset = 0; 2149 2150 if (hprt & HPRT_PRTENCHNG) 2151 sc->sc_flags.change_enabled = 1; 2152 2153 if (hprt & HPRT_PRTENA) 2154 sc->sc_flags.port_enabled = 1; 2155 else 2156 sc->sc_flags.port_enabled = 0; 2157 2158 if (hprt & HPRT_PRTOVRCURRCHNG) 2159 sc->sc_flags.change_over_current = 1; 2160 2161 if (hprt & HPRT_PRTOVRCURRACT) 2162 sc->sc_flags.port_over_current = 1; 2163 else 2164 sc->sc_flags.port_over_current = 0; 2165 2166 if (hprt & HPRT_PRTPWR) 2167 sc->sc_flags.port_powered = 1; 2168 else 2169 sc->sc_flags.port_powered = 0; 2170 2171 if (((hprt & HPRT_PRTSPD_MASK) 2172 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2173 sc->sc_flags.status_low_speed = 1; 2174 else 2175 sc->sc_flags.status_low_speed = 0; 2176 2177 if (((hprt & HPRT_PRTSPD_MASK) 2178 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2179 sc->sc_flags.status_high_speed = 1; 2180 else 2181 sc->sc_flags.status_high_speed = 0; 2182 2183 if (hprt & HPRT_PRTCONNDET) 2184 sc->sc_flags.change_connect = 1; 2185 2186 if (hprt & HPRT_PRTSUSP) 2187 dwc_otg_suspend_irq(sc); 2188 else 2189 dwc_otg_resume_irq(sc); 2190 2191 /* complete root HUB interrupt endpoint */ 2192 dwc_otg_root_intr(sc); 2193 } 2194 2195 /* 2196 * If resume and suspend is set at the same time we interpret 2197 * that like RESUME. Resume is set when there is at least 3 2198 * milliseconds of inactivity on the USB BUS. 2199 */ 2200 if (status & GINTSTS_WKUPINT) { 2201 2202 DPRINTFN(5, "resume interrupt\n"); 2203 2204 dwc_otg_resume_irq(sc); 2205 2206 } else if (status & GINTSTS_USBSUSP) { 2207 2208 DPRINTFN(5, "suspend interrupt\n"); 2209 2210 dwc_otg_suspend_irq(sc); 2211 } 2212 /* check VBUS */ 2213 if (status & (GINTSTS_USBSUSP | 2214 GINTSTS_USBRST | 2215 GINTMSK_OTGINTMSK | 2216 GINTSTS_SESSREQINT)) { 2217 uint32_t temp; 2218 2219 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2220 2221 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2222 2223 dwc_otg_vbus_interrupt(sc, 2224 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2225 } 2226 2227 /* clear all IN endpoint interrupts */ 2228 if (status & GINTSTS_IEPINT) { 2229 uint32_t temp; 2230 uint8_t x; 2231 2232 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2233 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2234 if (temp & DIEPMSK_XFERCOMPLMSK) { 2235 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2236 DIEPMSK_XFERCOMPLMSK); 2237 } 2238 } 2239 } 2240 2241 /* check for SOF interrupt */ 2242 if (status & GINTSTS_SOF) { 2243 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2244 uint8_t x; 2245 uint8_t y; 2246 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 2247 if (sc->sc_chan_state[x].wait_sof != 0) { 2248 if (--(sc->sc_chan_state[x].wait_sof) != 0) 2249 y = 1; 2250 } 2251 } 2252 if (y == 0) { 2253 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2254 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2255 } 2256 } 2257 } 2258 2259 /* poll FIFO(s) */ 2260 dwc_otg_interrupt_poll(sc); 2261 2262 USB_BUS_UNLOCK(&sc->sc_bus); 2263 } 2264 2265 static void 2266 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2267 { 2268 struct dwc_otg_td *td; 2269 2270 /* get current Transfer Descriptor */ 2271 td = temp->td_next; 2272 temp->td = td; 2273 2274 /* prepare for next TD */ 2275 temp->td_next = td->obj_next; 2276 2277 /* fill out the Transfer Descriptor */ 2278 td->func = temp->func; 2279 td->pc = temp->pc; 2280 td->offset = temp->offset; 2281 td->remainder = temp->len; 2282 td->tx_bytes = 0; 2283 td->error_any = 0; 2284 td->npkt = 0; 2285 td->did_stall = temp->did_stall; 2286 td->short_pkt = temp->short_pkt; 2287 td->alt_next = temp->setup_alt_next; 2288 td->set_toggle = 0; 2289 td->got_short = 0; 2290 td->did_nak = 0; 2291 td->channel = DWC_OTG_MAX_CHANNELS; 2292 td->state = 0; 2293 td->errcnt = 0; 2294 } 2295 2296 static void 2297 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2298 { 2299 struct dwc_otg_std_temp temp; 2300 struct dwc_otg_td *td; 2301 uint32_t x; 2302 uint8_t need_sync; 2303 uint8_t is_host; 2304 2305 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2306 xfer->address, UE_GET_ADDR(xfer->endpointno), 2307 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2308 2309 temp.max_frame_size = xfer->max_frame_size; 2310 2311 td = xfer->td_start[0]; 2312 xfer->td_transfer_first = td; 2313 xfer->td_transfer_cache = td; 2314 2315 /* setup temp */ 2316 2317 temp.pc = NULL; 2318 temp.td = NULL; 2319 temp.td_next = xfer->td_start[0]; 2320 temp.offset = 0; 2321 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2322 temp.did_stall = !xfer->flags_int.control_stall; 2323 2324 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2325 2326 /* check if we should prepend a setup message */ 2327 2328 if (xfer->flags_int.control_xfr) { 2329 if (xfer->flags_int.control_hdr) { 2330 2331 if (is_host) 2332 temp.func = &dwc_otg_host_setup_tx; 2333 else 2334 temp.func = &dwc_otg_setup_rx; 2335 2336 temp.len = xfer->frlengths[0]; 2337 temp.pc = xfer->frbuffers + 0; 2338 temp.short_pkt = temp.len ? 1 : 0; 2339 2340 /* check for last frame */ 2341 if (xfer->nframes == 1) { 2342 /* no STATUS stage yet, SETUP is last */ 2343 if (xfer->flags_int.control_act) 2344 temp.setup_alt_next = 0; 2345 } 2346 2347 dwc_otg_setup_standard_chain_sub(&temp); 2348 } 2349 x = 1; 2350 } else { 2351 x = 0; 2352 } 2353 2354 if (x != xfer->nframes) { 2355 if (xfer->endpointno & UE_DIR_IN) { 2356 if (is_host) { 2357 temp.func = &dwc_otg_host_data_rx; 2358 need_sync = 0; 2359 } else { 2360 temp.func = &dwc_otg_data_tx; 2361 need_sync = 1; 2362 } 2363 } else { 2364 if (is_host) { 2365 temp.func = &dwc_otg_host_data_tx; 2366 need_sync = 0; 2367 } else { 2368 temp.func = &dwc_otg_data_rx; 2369 need_sync = 0; 2370 } 2371 } 2372 2373 /* setup "pc" pointer */ 2374 temp.pc = xfer->frbuffers + x; 2375 } else { 2376 need_sync = 0; 2377 } 2378 while (x != xfer->nframes) { 2379 2380 /* DATA0 / DATA1 message */ 2381 2382 temp.len = xfer->frlengths[x]; 2383 2384 x++; 2385 2386 if (x == xfer->nframes) { 2387 if (xfer->flags_int.control_xfr) { 2388 if (xfer->flags_int.control_act) { 2389 temp.setup_alt_next = 0; 2390 } 2391 } else { 2392 temp.setup_alt_next = 0; 2393 } 2394 } 2395 if (temp.len == 0) { 2396 2397 /* make sure that we send an USB packet */ 2398 2399 temp.short_pkt = 0; 2400 2401 } else { 2402 2403 /* regular data transfer */ 2404 2405 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2406 } 2407 2408 dwc_otg_setup_standard_chain_sub(&temp); 2409 2410 if (xfer->flags_int.isochronous_xfr) { 2411 temp.offset += temp.len; 2412 } else { 2413 /* get next Page Cache pointer */ 2414 temp.pc = xfer->frbuffers + x; 2415 } 2416 } 2417 2418 if (xfer->flags_int.control_xfr) { 2419 2420 /* always setup a valid "pc" pointer for status and sync */ 2421 temp.pc = xfer->frbuffers + 0; 2422 temp.len = 0; 2423 temp.short_pkt = 0; 2424 temp.setup_alt_next = 0; 2425 2426 /* check if we need to sync */ 2427 if (need_sync) { 2428 /* we need a SYNC point after TX */ 2429 temp.func = &dwc_otg_data_tx_sync; 2430 dwc_otg_setup_standard_chain_sub(&temp); 2431 } 2432 2433 /* check if we should append a status stage */ 2434 if (!xfer->flags_int.control_act) { 2435 2436 /* 2437 * Send a DATA1 message and invert the current 2438 * endpoint direction. 2439 */ 2440 if (xfer->endpointno & UE_DIR_IN) { 2441 if (is_host) { 2442 temp.func = &dwc_otg_host_data_tx; 2443 need_sync = 0; 2444 } else { 2445 temp.func = &dwc_otg_data_rx; 2446 need_sync = 0; 2447 } 2448 } else { 2449 if (is_host) { 2450 temp.func = &dwc_otg_host_data_rx; 2451 need_sync = 0; 2452 } else { 2453 temp.func = &dwc_otg_data_tx; 2454 need_sync = 1; 2455 } 2456 } 2457 2458 dwc_otg_setup_standard_chain_sub(&temp); 2459 2460 /* data toggle should be DATA1 */ 2461 td = temp.td; 2462 td->set_toggle = 1; 2463 2464 if (need_sync) { 2465 /* we need a SYNC point after TX */ 2466 temp.func = &dwc_otg_data_tx_sync; 2467 dwc_otg_setup_standard_chain_sub(&temp); 2468 } 2469 } 2470 } else { 2471 /* check if we need to sync */ 2472 if (need_sync) { 2473 2474 temp.pc = xfer->frbuffers + 0; 2475 temp.len = 0; 2476 temp.short_pkt = 0; 2477 temp.setup_alt_next = 0; 2478 2479 /* we need a SYNC point after TX */ 2480 temp.func = &dwc_otg_data_tx_sync; 2481 dwc_otg_setup_standard_chain_sub(&temp); 2482 } 2483 } 2484 2485 /* must have at least one frame! */ 2486 td = temp.td; 2487 xfer->td_transfer_last = td; 2488 2489 if (is_host) { 2490 2491 struct dwc_otg_softc *sc; 2492 uint32_t hcchar; 2493 uint32_t hcsplt; 2494 uint8_t xfer_type; 2495 2496 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2497 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2498 2499 /* get first again */ 2500 td = xfer->td_transfer_first; 2501 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 2502 2503 hcchar = 2504 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 2505 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 2506 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 2507 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 2508 HCCHAR_CHENA; 2509 2510 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 2511 hcchar |= HCCHAR_LSPDDEV; 2512 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2513 hcchar |= HCCHAR_EPDIR_IN; 2514 2515 switch (xfer->xroot->udev->speed) { 2516 case USB_SPEED_FULL: 2517 case USB_SPEED_LOW: 2518 /* check if root HUB port is running High Speed */ 2519 if (sc->sc_flags.status_high_speed != 0) { 2520 hcsplt = HCSPLT_SPLTENA | 2521 (xfer->xroot->udev->hs_port_no << 2522 HCSPLT_PRTADDR_SHIFT) | 2523 (xfer->xroot->udev->hs_hub_addr << 2524 HCSPLT_HUBADDR_SHIFT); 2525 if (xfer_type == UE_ISOCHRONOUS) /* XXX */ 2526 hcsplt |= (3 << HCSPLT_XACTPOS_SHIFT); 2527 } else { 2528 hcsplt = 0; 2529 } 2530 if (xfer_type == UE_INTERRUPT) { 2531 uint32_t ival; 2532 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2533 if (ival == 0) 2534 ival = 1; 2535 else if (ival > 255) 2536 ival = 255; 2537 td->tmr_val = sc->sc_tmr_val + ival; 2538 td->tmr_res = ival; 2539 } 2540 break; 2541 case USB_SPEED_HIGH: 2542 hcsplt = 0; 2543 if (xfer_type == UE_ISOCHRONOUS || 2544 xfer_type == UE_INTERRUPT) { 2545 hcchar |= ((xfer->max_packet_count & 3) 2546 << HCCHAR_MC_SHIFT); 2547 } 2548 if (xfer_type == UE_INTERRUPT) { 2549 uint32_t ival; 2550 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2551 if (ival == 0) 2552 ival = 1; 2553 else if (ival > 255) 2554 ival = 255; 2555 td->tmr_val = sc->sc_tmr_val + ival; 2556 td->tmr_res = ival; 2557 } 2558 break; 2559 default: 2560 hcsplt = 0; 2561 break; 2562 } 2563 2564 if (xfer_type == UE_ISOCHRONOUS) { 2565 td->tmr_val = xfer->endpoint->isoc_next & 0xFF; 2566 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 2567 } else if (xfer_type != UE_INTERRUPT) { 2568 td->tmr_val = 0; 2569 td->tmr_res = 0; 2570 } 2571 2572 /* store configuration in all TD's */ 2573 while (1) { 2574 td->hcchar = hcchar; 2575 td->hcsplt = hcsplt; 2576 2577 if (((void *)td) == xfer->td_transfer_last) 2578 break; 2579 2580 td = td->obj_next; 2581 } 2582 } 2583 } 2584 2585 static void 2586 dwc_otg_timeout(void *arg) 2587 { 2588 struct usb_xfer *xfer = arg; 2589 2590 DPRINTF("xfer=%p\n", xfer); 2591 2592 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2593 2594 /* transfer is transferred */ 2595 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 2596 } 2597 2598 static void 2599 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 2600 { 2601 DPRINTFN(9, "\n"); 2602 2603 /* poll one time - will turn on interrupts */ 2604 if (dwc_otg_xfer_do_fifo(xfer)) { 2605 2606 /* put transfer on interrupt queue */ 2607 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2608 2609 /* start timeout, if any */ 2610 if (xfer->timeout != 0) { 2611 usbd_transfer_timeout_ms(xfer, 2612 &dwc_otg_timeout, xfer->timeout); 2613 } 2614 } 2615 } 2616 2617 static void 2618 dwc_otg_root_intr(struct dwc_otg_softc *sc) 2619 { 2620 DPRINTFN(9, "\n"); 2621 2622 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2623 2624 /* set port bit */ 2625 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2626 2627 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2628 sizeof(sc->sc_hub_idata)); 2629 } 2630 2631 static usb_error_t 2632 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 2633 { 2634 struct dwc_otg_td *td; 2635 uint32_t len; 2636 usb_error_t error; 2637 2638 DPRINTFN(9, "\n"); 2639 2640 td = xfer->td_transfer_cache; 2641 2642 do { 2643 len = td->remainder; 2644 2645 /* store last data toggle */ 2646 xfer->endpoint->toggle_next = td->toggle; 2647 2648 if (xfer->aframes != xfer->nframes) { 2649 /* 2650 * Verify the length and subtract 2651 * the remainder from "frlengths[]": 2652 */ 2653 if (len > xfer->frlengths[xfer->aframes]) { 2654 td->error_any = 1; 2655 } else { 2656 xfer->frlengths[xfer->aframes] -= len; 2657 } 2658 } 2659 /* Check for transfer error */ 2660 if (td->error_any) { 2661 /* the transfer is finished */ 2662 error = (td->error_stall ? 2663 USB_ERR_STALLED : USB_ERR_IOERROR); 2664 td = NULL; 2665 break; 2666 } 2667 /* Check for short transfer */ 2668 if (len > 0) { 2669 if (xfer->flags_int.short_frames_ok) { 2670 /* follow alt next */ 2671 if (td->alt_next) { 2672 td = td->obj_next; 2673 } else { 2674 td = NULL; 2675 } 2676 } else { 2677 /* the transfer is finished */ 2678 td = NULL; 2679 } 2680 error = 0; 2681 break; 2682 } 2683 td = td->obj_next; 2684 2685 /* this USB frame is complete */ 2686 error = 0; 2687 break; 2688 2689 } while (0); 2690 2691 /* update transfer cache */ 2692 2693 xfer->td_transfer_cache = td; 2694 2695 return (error); 2696 } 2697 2698 static void 2699 dwc_otg_standard_done(struct usb_xfer *xfer) 2700 { 2701 usb_error_t err = 0; 2702 2703 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2704 xfer, xfer->endpoint); 2705 2706 /* reset scanner */ 2707 2708 xfer->td_transfer_cache = xfer->td_transfer_first; 2709 2710 if (xfer->flags_int.control_xfr) { 2711 2712 if (xfer->flags_int.control_hdr) { 2713 2714 err = dwc_otg_standard_done_sub(xfer); 2715 } 2716 xfer->aframes = 1; 2717 2718 if (xfer->td_transfer_cache == NULL) { 2719 goto done; 2720 } 2721 } 2722 while (xfer->aframes != xfer->nframes) { 2723 2724 err = dwc_otg_standard_done_sub(xfer); 2725 xfer->aframes++; 2726 2727 if (xfer->td_transfer_cache == NULL) { 2728 goto done; 2729 } 2730 } 2731 2732 if (xfer->flags_int.control_xfr && 2733 !xfer->flags_int.control_act) { 2734 2735 err = dwc_otg_standard_done_sub(xfer); 2736 } 2737 done: 2738 dwc_otg_device_done(xfer, err); 2739 } 2740 2741 /*------------------------------------------------------------------------* 2742 * dwc_otg_device_done 2743 * 2744 * NOTE: this function can be called more than one time on the 2745 * same USB transfer! 2746 *------------------------------------------------------------------------*/ 2747 static void 2748 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 2749 { 2750 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 2751 xfer, xfer->endpoint, error); 2752 2753 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 2754 DPRINTFN(15, "disabled interrupts!\n"); 2755 } else { 2756 struct dwc_otg_td *td; 2757 2758 td = xfer->td_transfer_first; 2759 2760 if (td != NULL) 2761 dwc_otg_host_channel_free(td); 2762 } 2763 /* dequeue transfer and start next transfer */ 2764 usbd_transfer_done(xfer, error); 2765 } 2766 2767 static void 2768 dwc_otg_xfer_stall(struct usb_xfer *xfer) 2769 { 2770 dwc_otg_device_done(xfer, USB_ERR_STALLED); 2771 } 2772 2773 static void 2774 dwc_otg_set_stall(struct usb_device *udev, 2775 struct usb_endpoint *ep, uint8_t *did_stall) 2776 { 2777 struct dwc_otg_softc *sc; 2778 uint32_t temp; 2779 uint32_t reg; 2780 uint8_t ep_no; 2781 2782 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2783 2784 /* check mode */ 2785 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2786 /* not supported */ 2787 return; 2788 } 2789 2790 sc = DWC_OTG_BUS2SC(udev->bus); 2791 2792 /* get endpoint address */ 2793 ep_no = ep->edesc->bEndpointAddress; 2794 2795 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 2796 2797 if (ep_no & UE_DIR_IN) { 2798 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 2799 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 2800 } else { 2801 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 2802 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 2803 } 2804 2805 /* disable and stall endpoint */ 2806 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2807 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 2808 2809 /* clear active OUT ep */ 2810 if (!(ep_no & UE_DIR_IN)) { 2811 2812 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 2813 2814 if (sc->sc_last_rx_status != 0 && 2815 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 2816 sc->sc_last_rx_status)) { 2817 /* dump data */ 2818 dwc_otg_common_rx_ack(sc); 2819 /* poll interrupt */ 2820 dwc_otg_interrupt_poll(sc); 2821 } 2822 } 2823 } 2824 2825 static void 2826 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 2827 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2828 { 2829 uint32_t reg; 2830 uint32_t temp; 2831 2832 if (ep_type == UE_CONTROL) { 2833 /* clearing stall is not needed */ 2834 return; 2835 } 2836 2837 if (ep_dir) { 2838 reg = DOTG_DIEPCTL(ep_no); 2839 } else { 2840 reg = DOTG_DOEPCTL(ep_no); 2841 sc->sc_active_rx_ep |= (1U << ep_no); 2842 } 2843 2844 /* round up and mask away the multiplier count */ 2845 mps = (mps + 3) & 0x7FC; 2846 2847 if (ep_type == UE_BULK) { 2848 temp = DIEPCTL_EPTYPE_SET( 2849 DIEPCTL_EPTYPE_BULK) | 2850 DIEPCTL_USBACTEP; 2851 } else if (ep_type == UE_INTERRUPT) { 2852 temp = DIEPCTL_EPTYPE_SET( 2853 DIEPCTL_EPTYPE_INTERRUPT) | 2854 DIEPCTL_USBACTEP; 2855 } else { 2856 temp = DIEPCTL_EPTYPE_SET( 2857 DIEPCTL_EPTYPE_ISOC) | 2858 DIEPCTL_USBACTEP; 2859 } 2860 2861 temp |= DIEPCTL_MPS_SET(mps); 2862 temp |= DIEPCTL_TXFNUM_SET(ep_no); 2863 2864 if (ep_dir) 2865 sc->sc_in_ctl[ep_no] = temp; 2866 else 2867 sc->sc_out_ctl[ep_no] = temp; 2868 2869 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2870 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 2871 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 2872 2873 /* we only reset the transmit FIFO */ 2874 if (ep_dir) { 2875 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2876 GRSTCTL_TXFIFO(ep_no) | 2877 GRSTCTL_TXFFLSH); 2878 2879 DWC_OTG_WRITE_4(sc, 2880 DOTG_DIEPTSIZ(ep_no), 0); 2881 } 2882 2883 /* poll interrupt */ 2884 dwc_otg_interrupt_poll(sc); 2885 } 2886 2887 static void 2888 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 2889 { 2890 struct dwc_otg_softc *sc; 2891 struct usb_endpoint_descriptor *ed; 2892 2893 DPRINTFN(5, "endpoint=%p\n", ep); 2894 2895 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2896 2897 /* check mode */ 2898 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2899 /* not supported */ 2900 return; 2901 } 2902 /* get softc */ 2903 sc = DWC_OTG_BUS2SC(udev->bus); 2904 2905 /* get endpoint descriptor */ 2906 ed = ep->edesc; 2907 2908 /* reset endpoint */ 2909 dwc_otg_clear_stall_sub(sc, 2910 UGETW(ed->wMaxPacketSize), 2911 (ed->bEndpointAddress & UE_ADDR), 2912 (ed->bmAttributes & UE_XFERTYPE), 2913 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 2914 } 2915 2916 static void 2917 dwc_otg_device_state_change(struct usb_device *udev) 2918 { 2919 struct dwc_otg_softc *sc; 2920 uint8_t x; 2921 2922 /* check mode */ 2923 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2924 /* not supported */ 2925 return; 2926 } 2927 2928 /* get softc */ 2929 sc = DWC_OTG_BUS2SC(udev->bus); 2930 2931 /* deactivate all other endpoint but the control endpoint */ 2932 if (udev->state == USB_STATE_CONFIGURED || 2933 udev->state == USB_STATE_ADDRESSED) { 2934 2935 USB_BUS_LOCK(&sc->sc_bus); 2936 2937 for (x = 1; x != sc->sc_dev_ep_max; x++) { 2938 2939 if (x < sc->sc_dev_in_ep_max) { 2940 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 2941 DIEPCTL_EPDIS); 2942 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 2943 } 2944 2945 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 2946 DOEPCTL_EPDIS); 2947 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 2948 } 2949 USB_BUS_UNLOCK(&sc->sc_bus); 2950 } 2951 } 2952 2953 int 2954 dwc_otg_init(struct dwc_otg_softc *sc) 2955 { 2956 uint32_t temp; 2957 2958 DPRINTF("start\n"); 2959 2960 /* set up the bus structure */ 2961 sc->sc_bus.usbrev = USB_REV_2_0; 2962 sc->sc_bus.methods = &dwc_otg_bus_methods; 2963 2964 usb_callout_init_mtx(&sc->sc_timer, 2965 &sc->sc_bus.bus_mtx, 0); 2966 2967 USB_BUS_LOCK(&sc->sc_bus); 2968 2969 /* turn on clocks */ 2970 dwc_otg_clocks_on(sc); 2971 2972 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 2973 DPRINTF("Version = 0x%08x\n", temp); 2974 2975 /* disconnect */ 2976 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 2977 DCTL_SFTDISCON); 2978 2979 /* wait for host to detect disconnect */ 2980 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 2981 2982 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2983 GRSTCTL_CSFTRST); 2984 2985 /* wait a little bit for block to reset */ 2986 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 2987 2988 switch (sc->sc_mode) { 2989 case DWC_MODE_DEVICE: 2990 temp = GUSBCFG_FORCEDEVMODE; 2991 break; 2992 case DWC_MODE_HOST: 2993 temp = GUSBCFG_FORCEHOSTMODE; 2994 break; 2995 default: 2996 temp = 0; 2997 break; 2998 } 2999 3000 /* select HSIC or non-HSIC mode */ 3001 if (dwc_otg_use_hsic) { 3002 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3003 GUSBCFG_PHYIF | 3004 GUSBCFG_TRD_TIM_SET(5) | temp); 3005 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3006 0x000000EC); 3007 3008 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3009 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3010 temp & ~GLPMCFG_HSIC_CONN); 3011 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3012 temp | GLPMCFG_HSIC_CONN); 3013 } else { 3014 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3015 GUSBCFG_ULPI_UTMI_SEL | 3016 GUSBCFG_TRD_TIM_SET(5) | temp); 3017 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3018 3019 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3020 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3021 temp & ~GLPMCFG_HSIC_CONN); 3022 } 3023 3024 /* clear global nak */ 3025 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3026 DCTL_CGOUTNAK | 3027 DCTL_CGNPINNAK); 3028 3029 /* disable USB port */ 3030 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3031 3032 /* wait 10ms */ 3033 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3034 3035 /* enable USB port */ 3036 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3037 3038 /* wait 10ms */ 3039 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3040 3041 /* pull up D+ */ 3042 dwc_otg_pull_up(sc); 3043 3044 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3045 3046 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3047 3048 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3049 3050 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3051 3052 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3053 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3054 3055 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3056 3057 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3058 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3059 3060 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3061 3062 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3063 3064 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3065 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3066 sc->sc_host_ch_max); 3067 3068 /* setup FIFO */ 3069 if (dwc_otg_init_fifo(sc, DWC_MODE_OTG)) 3070 return (EINVAL); 3071 3072 /* enable interrupts */ 3073 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3074 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3075 3076 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3077 3078 /* enable all endpoint interrupts */ 3079 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3080 if (temp & GHWCFG2_MPI) { 3081 uint8_t x; 3082 3083 DPRINTF("Multi Process Interrupts\n"); 3084 3085 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3086 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3087 DIEPMSK_XFERCOMPLMSK); 3088 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3089 } 3090 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3091 } else { 3092 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3093 DIEPMSK_XFERCOMPLMSK); 3094 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3095 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3096 } 3097 } 3098 3099 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3100 /* setup clocks */ 3101 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3102 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3103 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3104 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3105 } 3106 3107 /* only enable global IRQ */ 3108 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3109 GAHBCFG_GLBLINTRMSK); 3110 3111 /* turn off clocks */ 3112 dwc_otg_clocks_off(sc); 3113 3114 /* read initial VBUS state */ 3115 3116 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3117 3118 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3119 3120 dwc_otg_vbus_interrupt(sc, 3121 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3122 3123 USB_BUS_UNLOCK(&sc->sc_bus); 3124 3125 /* catch any lost interrupts */ 3126 3127 dwc_otg_do_poll(&sc->sc_bus); 3128 3129 return (0); /* success */ 3130 } 3131 3132 void 3133 dwc_otg_uninit(struct dwc_otg_softc *sc) 3134 { 3135 USB_BUS_LOCK(&sc->sc_bus); 3136 3137 /* stop host timer */ 3138 dwc_otg_timer_stop(sc); 3139 3140 /* set disconnect */ 3141 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3142 DCTL_SFTDISCON); 3143 3144 /* turn off global IRQ */ 3145 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3146 3147 sc->sc_flags.port_enabled = 0; 3148 sc->sc_flags.port_powered = 0; 3149 sc->sc_flags.status_vbus = 0; 3150 sc->sc_flags.status_bus_reset = 0; 3151 sc->sc_flags.status_suspend = 0; 3152 sc->sc_flags.change_suspend = 0; 3153 sc->sc_flags.change_connect = 1; 3154 3155 dwc_otg_pull_down(sc); 3156 dwc_otg_clocks_off(sc); 3157 3158 USB_BUS_UNLOCK(&sc->sc_bus); 3159 3160 usb_callout_drain(&sc->sc_timer); 3161 } 3162 3163 static void 3164 dwc_otg_suspend(struct dwc_otg_softc *sc) 3165 { 3166 return; 3167 } 3168 3169 static void 3170 dwc_otg_resume(struct dwc_otg_softc *sc) 3171 { 3172 return; 3173 } 3174 3175 static void 3176 dwc_otg_do_poll(struct usb_bus *bus) 3177 { 3178 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3179 3180 USB_BUS_LOCK(&sc->sc_bus); 3181 dwc_otg_interrupt_poll(sc); 3182 USB_BUS_UNLOCK(&sc->sc_bus); 3183 } 3184 3185 /*------------------------------------------------------------------------* 3186 * DWC OTG bulk support 3187 * DWC OTG control support 3188 * DWC OTG interrupt support 3189 *------------------------------------------------------------------------*/ 3190 static void 3191 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3192 { 3193 } 3194 3195 static void 3196 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3197 { 3198 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3199 } 3200 3201 static void 3202 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3203 { 3204 } 3205 3206 static void 3207 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3208 { 3209 /* setup TDs */ 3210 dwc_otg_setup_standard_chain(xfer); 3211 dwc_otg_start_standard_chain(xfer); 3212 } 3213 3214 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3215 { 3216 .open = dwc_otg_device_non_isoc_open, 3217 .close = dwc_otg_device_non_isoc_close, 3218 .enter = dwc_otg_device_non_isoc_enter, 3219 .start = dwc_otg_device_non_isoc_start, 3220 }; 3221 3222 /*------------------------------------------------------------------------* 3223 * DWC OTG full speed isochronous support 3224 *------------------------------------------------------------------------*/ 3225 static void 3226 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3227 { 3228 } 3229 3230 static void 3231 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3232 { 3233 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3234 } 3235 3236 static void 3237 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3238 { 3239 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3240 uint32_t temp; 3241 uint32_t nframes; 3242 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3243 3244 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3245 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3246 3247 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3248 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3249 3250 /* get the current frame index */ 3251 nframes = (temp & HFNUM_FRNUM_MASK); 3252 } else { 3253 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3254 3255 /* get the current frame index */ 3256 nframes = DSTS_SOFFN_GET(temp); 3257 } 3258 3259 if (sc->sc_flags.status_high_speed) 3260 nframes /= 8; 3261 3262 nframes &= DWC_OTG_FRAME_MASK; 3263 3264 /* 3265 * check if the frame index is within the window where the frames 3266 * will be inserted 3267 */ 3268 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3269 3270 if ((xfer->endpoint->is_synced == 0) || 3271 (temp < (((xfer->nframes << shift) + 7) / 8))) { 3272 /* 3273 * If there is data underflow or the pipe queue is 3274 * empty we schedule the transfer a few frames ahead 3275 * of the current frame position. Else two isochronous 3276 * transfers might overlap. 3277 */ 3278 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 3279 xfer->endpoint->is_synced = 1; 3280 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3281 } 3282 /* 3283 * compute how many milliseconds the insertion is ahead of the 3284 * current frame position: 3285 */ 3286 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 3287 3288 /* 3289 * pre-compute when the isochronous transfer will be finished: 3290 */ 3291 xfer->isoc_time_complete = 3292 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3293 (((xfer->nframes << shift) + 7) / 8); 3294 3295 /* setup TDs */ 3296 dwc_otg_setup_standard_chain(xfer); 3297 3298 /* compute frame number for next insertion */ 3299 xfer->endpoint->isoc_next += (xfer->nframes << shift); 3300 } 3301 3302 static void 3303 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3304 { 3305 /* start TD chain */ 3306 dwc_otg_start_standard_chain(xfer); 3307 } 3308 3309 struct usb_pipe_methods dwc_otg_device_isoc_methods = 3310 { 3311 .open = dwc_otg_device_isoc_open, 3312 .close = dwc_otg_device_isoc_close, 3313 .enter = dwc_otg_device_isoc_enter, 3314 .start = dwc_otg_device_isoc_start, 3315 }; 3316 3317 /*------------------------------------------------------------------------* 3318 * DWC OTG root control support 3319 *------------------------------------------------------------------------* 3320 * Simulate a hardware HUB by handling all the necessary requests. 3321 *------------------------------------------------------------------------*/ 3322 3323 static const struct usb_device_descriptor dwc_otg_devd = { 3324 .bLength = sizeof(struct usb_device_descriptor), 3325 .bDescriptorType = UDESC_DEVICE, 3326 .bcdUSB = {0x00, 0x02}, 3327 .bDeviceClass = UDCLASS_HUB, 3328 .bDeviceSubClass = UDSUBCLASS_HUB, 3329 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3330 .bMaxPacketSize = 64, 3331 .bcdDevice = {0x00, 0x01}, 3332 .iManufacturer = 1, 3333 .iProduct = 2, 3334 .bNumConfigurations = 1, 3335 }; 3336 3337 static const struct dwc_otg_config_desc dwc_otg_confd = { 3338 .confd = { 3339 .bLength = sizeof(struct usb_config_descriptor), 3340 .bDescriptorType = UDESC_CONFIG, 3341 .wTotalLength[0] = sizeof(dwc_otg_confd), 3342 .bNumInterface = 1, 3343 .bConfigurationValue = 1, 3344 .iConfiguration = 0, 3345 .bmAttributes = UC_SELF_POWERED, 3346 .bMaxPower = 0, 3347 }, 3348 .ifcd = { 3349 .bLength = sizeof(struct usb_interface_descriptor), 3350 .bDescriptorType = UDESC_INTERFACE, 3351 .bNumEndpoints = 1, 3352 .bInterfaceClass = UICLASS_HUB, 3353 .bInterfaceSubClass = UISUBCLASS_HUB, 3354 .bInterfaceProtocol = 0, 3355 }, 3356 .endpd = { 3357 .bLength = sizeof(struct usb_endpoint_descriptor), 3358 .bDescriptorType = UDESC_ENDPOINT, 3359 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 3360 .bmAttributes = UE_INTERRUPT, 3361 .wMaxPacketSize[0] = 8, 3362 .bInterval = 255, 3363 }, 3364 }; 3365 3366 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3367 3368 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 3369 .bDescLength = sizeof(dwc_otg_hubd), 3370 .bDescriptorType = UDESC_HUB, 3371 .bNbrPorts = 1, 3372 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3373 .bPwrOn2PwrGood = 50, 3374 .bHubContrCurrent = 0, 3375 .DeviceRemovable = {0}, /* port is removable */ 3376 }; 3377 3378 #define STRING_LANG \ 3379 0x09, 0x04, /* American English */ 3380 3381 #define STRING_VENDOR \ 3382 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 3383 3384 #define STRING_PRODUCT \ 3385 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 3386 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 3387 'U', 0, 'B', 0, 3388 3389 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 3390 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 3391 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 3392 3393 static usb_error_t 3394 dwc_otg_roothub_exec(struct usb_device *udev, 3395 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3396 { 3397 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3398 const void *ptr; 3399 uint16_t len; 3400 uint16_t value; 3401 uint16_t index; 3402 usb_error_t err; 3403 3404 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3405 3406 /* buffer reset */ 3407 ptr = (const void *)&sc->sc_hub_temp; 3408 len = 0; 3409 err = 0; 3410 3411 value = UGETW(req->wValue); 3412 index = UGETW(req->wIndex); 3413 3414 /* demultiplex the control request */ 3415 3416 switch (req->bmRequestType) { 3417 case UT_READ_DEVICE: 3418 switch (req->bRequest) { 3419 case UR_GET_DESCRIPTOR: 3420 goto tr_handle_get_descriptor; 3421 case UR_GET_CONFIG: 3422 goto tr_handle_get_config; 3423 case UR_GET_STATUS: 3424 goto tr_handle_get_status; 3425 default: 3426 goto tr_stalled; 3427 } 3428 break; 3429 3430 case UT_WRITE_DEVICE: 3431 switch (req->bRequest) { 3432 case UR_SET_ADDRESS: 3433 goto tr_handle_set_address; 3434 case UR_SET_CONFIG: 3435 goto tr_handle_set_config; 3436 case UR_CLEAR_FEATURE: 3437 goto tr_valid; /* nop */ 3438 case UR_SET_DESCRIPTOR: 3439 goto tr_valid; /* nop */ 3440 case UR_SET_FEATURE: 3441 default: 3442 goto tr_stalled; 3443 } 3444 break; 3445 3446 case UT_WRITE_ENDPOINT: 3447 switch (req->bRequest) { 3448 case UR_CLEAR_FEATURE: 3449 switch (UGETW(req->wValue)) { 3450 case UF_ENDPOINT_HALT: 3451 goto tr_handle_clear_halt; 3452 case UF_DEVICE_REMOTE_WAKEUP: 3453 goto tr_handle_clear_wakeup; 3454 default: 3455 goto tr_stalled; 3456 } 3457 break; 3458 case UR_SET_FEATURE: 3459 switch (UGETW(req->wValue)) { 3460 case UF_ENDPOINT_HALT: 3461 goto tr_handle_set_halt; 3462 case UF_DEVICE_REMOTE_WAKEUP: 3463 goto tr_handle_set_wakeup; 3464 default: 3465 goto tr_stalled; 3466 } 3467 break; 3468 case UR_SYNCH_FRAME: 3469 goto tr_valid; /* nop */ 3470 default: 3471 goto tr_stalled; 3472 } 3473 break; 3474 3475 case UT_READ_ENDPOINT: 3476 switch (req->bRequest) { 3477 case UR_GET_STATUS: 3478 goto tr_handle_get_ep_status; 3479 default: 3480 goto tr_stalled; 3481 } 3482 break; 3483 3484 case UT_WRITE_INTERFACE: 3485 switch (req->bRequest) { 3486 case UR_SET_INTERFACE: 3487 goto tr_handle_set_interface; 3488 case UR_CLEAR_FEATURE: 3489 goto tr_valid; /* nop */ 3490 case UR_SET_FEATURE: 3491 default: 3492 goto tr_stalled; 3493 } 3494 break; 3495 3496 case UT_READ_INTERFACE: 3497 switch (req->bRequest) { 3498 case UR_GET_INTERFACE: 3499 goto tr_handle_get_interface; 3500 case UR_GET_STATUS: 3501 goto tr_handle_get_iface_status; 3502 default: 3503 goto tr_stalled; 3504 } 3505 break; 3506 3507 case UT_WRITE_CLASS_INTERFACE: 3508 case UT_WRITE_VENDOR_INTERFACE: 3509 /* XXX forward */ 3510 break; 3511 3512 case UT_READ_CLASS_INTERFACE: 3513 case UT_READ_VENDOR_INTERFACE: 3514 /* XXX forward */ 3515 break; 3516 3517 case UT_WRITE_CLASS_DEVICE: 3518 switch (req->bRequest) { 3519 case UR_CLEAR_FEATURE: 3520 goto tr_valid; 3521 case UR_SET_DESCRIPTOR: 3522 case UR_SET_FEATURE: 3523 break; 3524 default: 3525 goto tr_stalled; 3526 } 3527 break; 3528 3529 case UT_WRITE_CLASS_OTHER: 3530 switch (req->bRequest) { 3531 case UR_CLEAR_FEATURE: 3532 goto tr_handle_clear_port_feature; 3533 case UR_SET_FEATURE: 3534 goto tr_handle_set_port_feature; 3535 case UR_CLEAR_TT_BUFFER: 3536 case UR_RESET_TT: 3537 case UR_STOP_TT: 3538 goto tr_valid; 3539 3540 default: 3541 goto tr_stalled; 3542 } 3543 break; 3544 3545 case UT_READ_CLASS_OTHER: 3546 switch (req->bRequest) { 3547 case UR_GET_TT_STATE: 3548 goto tr_handle_get_tt_state; 3549 case UR_GET_STATUS: 3550 goto tr_handle_get_port_status; 3551 default: 3552 goto tr_stalled; 3553 } 3554 break; 3555 3556 case UT_READ_CLASS_DEVICE: 3557 switch (req->bRequest) { 3558 case UR_GET_DESCRIPTOR: 3559 goto tr_handle_get_class_descriptor; 3560 case UR_GET_STATUS: 3561 goto tr_handle_get_class_status; 3562 3563 default: 3564 goto tr_stalled; 3565 } 3566 break; 3567 default: 3568 goto tr_stalled; 3569 } 3570 goto tr_valid; 3571 3572 tr_handle_get_descriptor: 3573 switch (value >> 8) { 3574 case UDESC_DEVICE: 3575 if (value & 0xff) { 3576 goto tr_stalled; 3577 } 3578 len = sizeof(dwc_otg_devd); 3579 ptr = (const void *)&dwc_otg_devd; 3580 goto tr_valid; 3581 case UDESC_CONFIG: 3582 if (value & 0xff) { 3583 goto tr_stalled; 3584 } 3585 len = sizeof(dwc_otg_confd); 3586 ptr = (const void *)&dwc_otg_confd; 3587 goto tr_valid; 3588 case UDESC_STRING: 3589 switch (value & 0xff) { 3590 case 0: /* Language table */ 3591 len = sizeof(dwc_otg_langtab); 3592 ptr = (const void *)&dwc_otg_langtab; 3593 goto tr_valid; 3594 3595 case 1: /* Vendor */ 3596 len = sizeof(dwc_otg_vendor); 3597 ptr = (const void *)&dwc_otg_vendor; 3598 goto tr_valid; 3599 3600 case 2: /* Product */ 3601 len = sizeof(dwc_otg_product); 3602 ptr = (const void *)&dwc_otg_product; 3603 goto tr_valid; 3604 default: 3605 break; 3606 } 3607 break; 3608 default: 3609 goto tr_stalled; 3610 } 3611 goto tr_stalled; 3612 3613 tr_handle_get_config: 3614 len = 1; 3615 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3616 goto tr_valid; 3617 3618 tr_handle_get_status: 3619 len = 2; 3620 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3621 goto tr_valid; 3622 3623 tr_handle_set_address: 3624 if (value & 0xFF00) { 3625 goto tr_stalled; 3626 } 3627 sc->sc_rt_addr = value; 3628 goto tr_valid; 3629 3630 tr_handle_set_config: 3631 if (value >= 2) { 3632 goto tr_stalled; 3633 } 3634 sc->sc_conf = value; 3635 goto tr_valid; 3636 3637 tr_handle_get_interface: 3638 len = 1; 3639 sc->sc_hub_temp.wValue[0] = 0; 3640 goto tr_valid; 3641 3642 tr_handle_get_tt_state: 3643 tr_handle_get_class_status: 3644 tr_handle_get_iface_status: 3645 tr_handle_get_ep_status: 3646 len = 2; 3647 USETW(sc->sc_hub_temp.wValue, 0); 3648 goto tr_valid; 3649 3650 tr_handle_set_halt: 3651 tr_handle_set_interface: 3652 tr_handle_set_wakeup: 3653 tr_handle_clear_wakeup: 3654 tr_handle_clear_halt: 3655 goto tr_valid; 3656 3657 tr_handle_clear_port_feature: 3658 if (index != 1) 3659 goto tr_stalled; 3660 3661 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3662 3663 switch (value) { 3664 case UHF_PORT_SUSPEND: 3665 dwc_otg_wakeup_peer(sc); 3666 break; 3667 3668 case UHF_PORT_ENABLE: 3669 if (sc->sc_flags.status_device_mode == 0) { 3670 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 3671 sc->sc_hprt_val | HPRT_PRTENA); 3672 } 3673 sc->sc_flags.port_enabled = 0; 3674 break; 3675 3676 case UHF_C_PORT_RESET: 3677 sc->sc_flags.change_reset = 0; 3678 break; 3679 3680 case UHF_C_PORT_ENABLE: 3681 sc->sc_flags.change_enabled = 0; 3682 break; 3683 3684 case UHF_C_PORT_OVER_CURRENT: 3685 sc->sc_flags.change_over_current = 0; 3686 break; 3687 3688 case UHF_PORT_TEST: 3689 case UHF_PORT_INDICATOR: 3690 /* nops */ 3691 break; 3692 3693 case UHF_PORT_POWER: 3694 sc->sc_flags.port_powered = 0; 3695 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3696 sc->sc_hprt_val = 0; 3697 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 3698 } 3699 dwc_otg_pull_down(sc); 3700 dwc_otg_clocks_off(sc); 3701 break; 3702 3703 case UHF_C_PORT_CONNECTION: 3704 /* clear connect change flag */ 3705 sc->sc_flags.change_connect = 0; 3706 break; 3707 3708 case UHF_C_PORT_SUSPEND: 3709 sc->sc_flags.change_suspend = 0; 3710 break; 3711 3712 default: 3713 err = USB_ERR_IOERROR; 3714 goto done; 3715 } 3716 goto tr_valid; 3717 3718 tr_handle_set_port_feature: 3719 if (index != 1) { 3720 goto tr_stalled; 3721 } 3722 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 3723 3724 switch (value) { 3725 case UHF_PORT_ENABLE: 3726 break; 3727 3728 case UHF_PORT_SUSPEND: 3729 if (sc->sc_flags.status_device_mode == 0) { 3730 /* set suspend BIT */ 3731 sc->sc_hprt_val |= HPRT_PRTSUSP; 3732 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3733 3734 /* generate HUB suspend event */ 3735 dwc_otg_suspend_irq(sc); 3736 } 3737 break; 3738 3739 case UHF_PORT_RESET: 3740 if (sc->sc_flags.status_device_mode == 0) { 3741 3742 DPRINTF("PORT RESET\n"); 3743 3744 /* enable PORT reset */ 3745 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 3746 3747 /* Wait 62.5ms for reset to complete */ 3748 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3749 3750 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3751 3752 /* Wait 62.5ms for reset to complete */ 3753 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3754 3755 /* reset FIFOs */ 3756 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 3757 3758 sc->sc_flags.change_reset = 1; 3759 } else { 3760 err = USB_ERR_IOERROR; 3761 } 3762 break; 3763 3764 case UHF_PORT_TEST: 3765 case UHF_PORT_INDICATOR: 3766 /* nops */ 3767 break; 3768 case UHF_PORT_POWER: 3769 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3770 sc->sc_hprt_val |= HPRT_PRTPWR; 3771 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3772 } 3773 sc->sc_flags.port_powered = 1; 3774 break; 3775 default: 3776 err = USB_ERR_IOERROR; 3777 goto done; 3778 } 3779 goto tr_valid; 3780 3781 tr_handle_get_port_status: 3782 3783 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 3784 3785 if (index != 1) 3786 goto tr_stalled; 3787 3788 if (sc->sc_flags.status_vbus) 3789 dwc_otg_clocks_on(sc); 3790 else 3791 dwc_otg_clocks_off(sc); 3792 3793 /* Select Device Side Mode */ 3794 3795 if (sc->sc_flags.status_device_mode) { 3796 value = UPS_PORT_MODE_DEVICE; 3797 dwc_otg_timer_stop(sc); 3798 } else { 3799 value = 0; 3800 dwc_otg_timer_start(sc); 3801 } 3802 3803 if (sc->sc_flags.status_high_speed) 3804 value |= UPS_HIGH_SPEED; 3805 else if (sc->sc_flags.status_low_speed) 3806 value |= UPS_LOW_SPEED; 3807 3808 if (sc->sc_flags.port_powered) 3809 value |= UPS_PORT_POWER; 3810 3811 if (sc->sc_flags.port_enabled) 3812 value |= UPS_PORT_ENABLED; 3813 3814 if (sc->sc_flags.port_over_current) 3815 value |= UPS_OVERCURRENT_INDICATOR; 3816 3817 if (sc->sc_flags.status_vbus && 3818 sc->sc_flags.status_bus_reset) 3819 value |= UPS_CURRENT_CONNECT_STATUS; 3820 3821 if (sc->sc_flags.status_suspend) 3822 value |= UPS_SUSPEND; 3823 3824 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3825 3826 value = 0; 3827 3828 if (sc->sc_flags.change_connect) 3829 value |= UPS_C_CONNECT_STATUS; 3830 if (sc->sc_flags.change_suspend) 3831 value |= UPS_C_SUSPEND; 3832 if (sc->sc_flags.change_reset) 3833 value |= UPS_C_PORT_RESET; 3834 if (sc->sc_flags.change_over_current) 3835 value |= UPS_C_OVERCURRENT_INDICATOR; 3836 3837 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3838 len = sizeof(sc->sc_hub_temp.ps); 3839 goto tr_valid; 3840 3841 tr_handle_get_class_descriptor: 3842 if (value & 0xFF) { 3843 goto tr_stalled; 3844 } 3845 ptr = (const void *)&dwc_otg_hubd; 3846 len = sizeof(dwc_otg_hubd); 3847 goto tr_valid; 3848 3849 tr_stalled: 3850 err = USB_ERR_STALLED; 3851 tr_valid: 3852 done: 3853 *plength = len; 3854 *pptr = ptr; 3855 return (err); 3856 } 3857 3858 static void 3859 dwc_otg_xfer_setup(struct usb_setup_params *parm) 3860 { 3861 const struct usb_hw_ep_profile *pf; 3862 struct usb_xfer *xfer; 3863 void *last_obj; 3864 uint32_t ntd; 3865 uint32_t n; 3866 uint8_t ep_no; 3867 3868 xfer = parm->curr_xfer; 3869 3870 /* 3871 * NOTE: This driver does not use any of the parameters that 3872 * are computed from the following values. Just set some 3873 * reasonable dummies: 3874 */ 3875 parm->hc_max_packet_size = 0x500; 3876 parm->hc_max_packet_count = 1; 3877 parm->hc_max_frame_size = 0x500; 3878 3879 usbd_transfer_setup_sub(parm); 3880 3881 /* 3882 * compute maximum number of TDs 3883 */ 3884 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 3885 3886 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 3887 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 3888 } else { 3889 3890 ntd = xfer->nframes + 1 /* SYNC */ ; 3891 } 3892 3893 /* 3894 * check if "usbd_transfer_setup_sub" set an error 3895 */ 3896 if (parm->err) 3897 return; 3898 3899 /* 3900 * allocate transfer descriptors 3901 */ 3902 last_obj = NULL; 3903 3904 /* 3905 * get profile stuff 3906 */ 3907 ep_no = xfer->endpointno & UE_ADDR; 3908 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 3909 3910 if (pf == NULL) { 3911 /* should not happen */ 3912 parm->err = USB_ERR_INVAL; 3913 return; 3914 } 3915 3916 /* align data */ 3917 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 3918 3919 for (n = 0; n != ntd; n++) { 3920 3921 struct dwc_otg_td *td; 3922 3923 if (parm->buf) { 3924 3925 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 3926 3927 /* init TD */ 3928 td->max_packet_size = xfer->max_packet_size; 3929 td->ep_no = ep_no; 3930 td->obj_next = last_obj; 3931 3932 last_obj = td; 3933 } 3934 parm->size[0] += sizeof(*td); 3935 } 3936 3937 xfer->td_start[0] = last_obj; 3938 } 3939 3940 static void 3941 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 3942 { 3943 return; 3944 } 3945 3946 static void 3947 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3948 struct usb_endpoint *ep) 3949 { 3950 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3951 3952 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 3953 ep, udev->address, 3954 edesc->bEndpointAddress, udev->flags.usb_mode, 3955 sc->sc_rt_addr, udev->device_index); 3956 3957 if (udev->device_index != sc->sc_rt_addr) { 3958 3959 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 3960 if (udev->speed != USB_SPEED_FULL && 3961 udev->speed != USB_SPEED_HIGH) { 3962 /* not supported */ 3963 return; 3964 } 3965 } else { 3966 uint16_t mps; 3967 3968 mps = UGETW(edesc->wMaxPacketSize); 3969 3970 /* Apply limitations of our USB host driver */ 3971 3972 switch (udev->speed) { 3973 case USB_SPEED_HIGH: 3974 if (mps > 512) { 3975 DPRINTF("wMaxPacketSize=0x%04x" 3976 "is not supported\n", (int)mps); 3977 /* not supported */ 3978 return; 3979 } 3980 break; 3981 3982 case USB_SPEED_FULL: 3983 case USB_SPEED_LOW: 3984 if (mps > 188) { 3985 DPRINTF("wMaxPacketSize=0x%04x" 3986 "is not supported\n", (int)mps); 3987 /* not supported */ 3988 return; 3989 } 3990 break; 3991 3992 default: 3993 DPRINTF("Invalid device speed\n"); 3994 /* not supported */ 3995 return; 3996 } 3997 } 3998 3999 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4000 ep->methods = &dwc_otg_device_isoc_methods; 4001 else 4002 ep->methods = &dwc_otg_device_non_isoc_methods; 4003 } 4004 } 4005 4006 static void 4007 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4008 { 4009 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4010 4011 switch (state) { 4012 case USB_HW_POWER_SUSPEND: 4013 dwc_otg_suspend(sc); 4014 break; 4015 case USB_HW_POWER_SHUTDOWN: 4016 dwc_otg_uninit(sc); 4017 break; 4018 case USB_HW_POWER_RESUME: 4019 dwc_otg_resume(sc); 4020 break; 4021 default: 4022 break; 4023 } 4024 } 4025 4026 static void 4027 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4028 { 4029 /* DMA delay - wait until any use of memory is finished */ 4030 *pus = (2125); /* microseconds */ 4031 } 4032 4033 static void 4034 dwc_otg_device_resume(struct usb_device *udev) 4035 { 4036 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4037 struct usb_xfer *xfer; 4038 struct dwc_otg_td *td; 4039 4040 DPRINTF("\n"); 4041 4042 /* Enable relevant Host channels before resuming */ 4043 4044 USB_BUS_LOCK(udev->bus); 4045 4046 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4047 4048 if (xfer->xroot->udev == udev) { 4049 4050 td = xfer->td_transfer_cache; 4051 if (td != NULL && 4052 td->channel < DWC_OTG_MAX_CHANNELS) 4053 sc->sc_chan_state[td->channel].suspended = 0; 4054 } 4055 } 4056 4057 USB_BUS_UNLOCK(udev->bus); 4058 4059 /* poll all transfers again to restart resumed ones */ 4060 dwc_otg_do_poll(udev->bus); 4061 } 4062 4063 static void 4064 dwc_otg_device_suspend(struct usb_device *udev) 4065 { 4066 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4067 struct usb_xfer *xfer; 4068 struct dwc_otg_td *td; 4069 4070 DPRINTF("\n"); 4071 4072 /* Disable relevant Host channels before going to suspend */ 4073 4074 USB_BUS_LOCK(udev->bus); 4075 4076 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4077 4078 if (xfer->xroot->udev == udev) { 4079 4080 td = xfer->td_transfer_cache; 4081 if (td != NULL && 4082 td->channel < DWC_OTG_MAX_CHANNELS) 4083 sc->sc_chan_state[td->channel].suspended = 1; 4084 } 4085 } 4086 4087 USB_BUS_UNLOCK(udev->bus); 4088 } 4089 4090 struct usb_bus_methods dwc_otg_bus_methods = 4091 { 4092 .endpoint_init = &dwc_otg_ep_init, 4093 .xfer_setup = &dwc_otg_xfer_setup, 4094 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4095 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4096 .xfer_stall = &dwc_otg_xfer_stall, 4097 .set_stall = &dwc_otg_set_stall, 4098 .clear_stall = &dwc_otg_clear_stall, 4099 .roothub_exec = &dwc_otg_roothub_exec, 4100 .xfer_poll = &dwc_otg_do_poll, 4101 .device_state_change = &dwc_otg_device_state_change, 4102 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4103 .get_dma_delay = &dwc_otg_get_dma_delay, 4104 .device_resume = &dwc_otg_device_resume, 4105 .device_suspend = &dwc_otg_device_suspend, 4106 }; 4107