1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2UDEV(pc) \ 93 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_RXFLVLMSK | \ 102 GINTMSK_HCHINTMSK | \ 103 GINTMSK_OTGINTMSK | \ 104 GINTMSK_PRTINTMSK) 105 106 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 107 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 108 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 109 GINTSTS_SESSREQINT) 110 111 static int dwc_otg_use_hsic; 112 113 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 114 115 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 116 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 117 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 118 119 #ifdef USB_DEBUG 120 static int dwc_otg_debug; 121 122 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 123 &dwc_otg_debug, 0, "DWC OTG debug level"); 124 #endif 125 126 #define DWC_OTG_INTR_ENDPT 1 127 128 /* prototypes */ 129 130 static const struct usb_bus_methods dwc_otg_bus_methods; 131 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 132 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 133 134 static dwc_otg_cmd_t dwc_otg_setup_rx; 135 static dwc_otg_cmd_t dwc_otg_data_rx; 136 static dwc_otg_cmd_t dwc_otg_data_tx; 137 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 138 139 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 140 static dwc_otg_cmd_t dwc_otg_host_data_tx; 141 static dwc_otg_cmd_t dwc_otg_host_data_rx; 142 143 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 144 static void dwc_otg_do_poll(struct usb_bus *); 145 static void dwc_otg_standard_done(struct usb_xfer *); 146 static void dwc_otg_root_intr(struct dwc_otg_softc *); 147 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 148 static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); 149 150 /* 151 * Here is a configuration that the chip supports. 152 */ 153 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 154 155 [0] = { 156 .max_in_frame_size = 64,/* fixed */ 157 .max_out_frame_size = 64, /* fixed */ 158 .is_simplex = 1, 159 .support_control = 1, 160 } 161 }; 162 163 static void 164 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 165 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 166 { 167 struct dwc_otg_softc *sc; 168 169 sc = DWC_OTG_BUS2SC(udev->bus); 170 171 if (ep_addr < sc->sc_dev_ep_max) 172 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 173 else 174 *ppf = NULL; 175 } 176 177 static int 178 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 179 { 180 struct dwc_otg_profile *pf; 181 uint32_t fifo_size; 182 uint32_t fifo_regs; 183 uint32_t tx_start; 184 uint8_t x; 185 186 fifo_size = sc->sc_fifo_size; 187 188 /* 189 * NOTE: Reserved fixed size area at end of RAM, which must 190 * not be allocated to the FIFOs: 191 */ 192 fifo_regs = 4 * 16; 193 194 if (fifo_size < fifo_regs) { 195 DPRINTF("Too little FIFO\n"); 196 return (EINVAL); 197 } 198 199 /* subtract FIFO regs from total once */ 200 fifo_size -= fifo_regs; 201 202 /* split equally for IN and OUT */ 203 fifo_size /= 2; 204 205 /* align to 4 bytes boundary */ 206 fifo_size &= ~3; 207 208 /* set global receive FIFO size */ 209 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 210 211 tx_start = fifo_size; 212 213 if (fifo_size < 64) { 214 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 215 return (EINVAL); 216 } 217 218 /* disable any leftover host channels */ 219 for (x = 0; x != sc->sc_host_ch_max; x++) { 220 if (sc->sc_chan_state[x].wait_sof == 0) 221 continue; 222 dwc_otg_host_channel_disable(sc, x); 223 } 224 225 if (mode == DWC_MODE_HOST) { 226 227 /* reset active endpoints */ 228 sc->sc_active_rx_ep = 0; 229 230 /* split equally for periodic and non-periodic */ 231 fifo_size /= 2; 232 233 /* align to 4 bytes boundary */ 234 fifo_size &= ~3; 235 236 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 237 ((fifo_size / 4) << 16) | 238 (tx_start / 4)); 239 240 tx_start += fifo_size; 241 242 for (x = 0; x != sc->sc_host_ch_max; x++) { 243 /* disable all host interrupts */ 244 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 245 HCINT_DEFAULT_MASK); 246 } 247 248 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 249 ((fifo_size / 4) << 16) | 250 (tx_start / 4)); 251 252 /* reset host channel state */ 253 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 254 255 /* reset FIFO TX levels */ 256 sc->sc_tx_cur_p_level = 0; 257 sc->sc_tx_cur_np_level = 0; 258 259 /* store maximum periodic and non-periodic FIFO TX size */ 260 sc->sc_tx_max_size = fifo_size; 261 262 /* enable all host channel interrupts */ 263 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 264 (1U << sc->sc_host_ch_max) - 1U); 265 } 266 267 if (mode == DWC_MODE_DEVICE) { 268 269 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 270 (0x10 << 16) | (tx_start / 4)); 271 fifo_size -= 0x40; 272 tx_start += 0x40; 273 274 /* setup control endpoint profile */ 275 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 276 277 /* reset active endpoints */ 278 sc->sc_active_rx_ep = 1; 279 280 for (x = 1; x != sc->sc_dev_ep_max; x++) { 281 282 pf = sc->sc_hw_ep_profile + x; 283 284 pf->usb.max_out_frame_size = 1024 * 3; 285 pf->usb.is_simplex = 0; /* assume duplex */ 286 pf->usb.support_bulk = 1; 287 pf->usb.support_interrupt = 1; 288 pf->usb.support_isochronous = 1; 289 pf->usb.support_out = 1; 290 291 if (x < sc->sc_dev_in_ep_max) { 292 uint32_t limit; 293 294 limit = (x == 1) ? DWC_OTG_MAX_TXN : 295 (DWC_OTG_MAX_TXN / 2); 296 297 if (fifo_size >= limit) { 298 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 299 ((limit / 4) << 16) | 300 (tx_start / 4)); 301 tx_start += limit; 302 fifo_size -= limit; 303 pf->usb.max_in_frame_size = 0x200; 304 pf->usb.support_in = 1; 305 pf->max_buffer = limit; 306 307 } else if (fifo_size >= 0x80) { 308 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 309 ((0x80 / 4) << 16) | (tx_start / 4)); 310 tx_start += 0x80; 311 fifo_size -= 0x80; 312 pf->usb.max_in_frame_size = 0x40; 313 pf->usb.support_in = 1; 314 315 } else { 316 pf->usb.is_simplex = 1; 317 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 318 (0x0 << 16) | (tx_start / 4)); 319 } 320 } else { 321 pf->usb.is_simplex = 1; 322 } 323 324 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 325 pf->usb.max_in_frame_size, 326 pf->usb.max_out_frame_size); 327 } 328 } 329 330 /* reset RX FIFO */ 331 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 332 GRSTCTL_RXFFLSH); 333 334 if (mode != DWC_MODE_OTG) { 335 /* reset all TX FIFOs */ 336 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 337 GRSTCTL_TXFIFO(0x10) | 338 GRSTCTL_TXFFLSH); 339 } else { 340 /* reset active endpoints */ 341 sc->sc_active_rx_ep = 0; 342 343 /* reset periodic and non-periodic FIFO TX size */ 344 sc->sc_tx_max_size = fifo_size; 345 346 /* reset host channel state */ 347 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 348 349 /* reset FIFO TX levels */ 350 sc->sc_tx_cur_p_level = 0; 351 sc->sc_tx_cur_np_level = 0; 352 } 353 return (0); 354 } 355 356 static void 357 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 358 { 359 360 /* 361 * Disabled until further. Assuming that the register is already 362 * programmed correctly by the boot loader. 363 */ 364 #if 0 365 uint32_t temp; 366 367 /* setup HOST frame interval register, based on existing value */ 368 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 369 if (temp >= 10000) 370 temp /= 1000; 371 else 372 temp /= 125; 373 374 /* figure out nearest X-tal value */ 375 if (temp >= 54) 376 temp = 60; /* MHz */ 377 else if (temp >= 39) 378 temp = 48; /* MHz */ 379 else 380 temp = 30; /* MHz */ 381 382 if (sc->sc_flags.status_high_speed) 383 temp *= 125; 384 else 385 temp *= 1000; 386 387 DPRINTF("HFIR=0x%08x\n", temp); 388 389 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 390 #endif 391 } 392 393 static void 394 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 395 { 396 if (sc->sc_flags.clocks_off && 397 sc->sc_flags.port_powered) { 398 399 DPRINTFN(5, "\n"); 400 401 /* TODO - platform specific */ 402 403 sc->sc_flags.clocks_off = 0; 404 } 405 } 406 407 static void 408 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 409 { 410 if (!sc->sc_flags.clocks_off) { 411 412 DPRINTFN(5, "\n"); 413 414 /* TODO - platform specific */ 415 416 sc->sc_flags.clocks_off = 1; 417 } 418 } 419 420 static void 421 dwc_otg_pull_up(struct dwc_otg_softc *sc) 422 { 423 uint32_t temp; 424 425 /* pullup D+, if possible */ 426 427 if (!sc->sc_flags.d_pulled_up && 428 sc->sc_flags.port_powered) { 429 sc->sc_flags.d_pulled_up = 1; 430 431 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 432 temp &= ~DCTL_SFTDISCON; 433 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 434 } 435 } 436 437 static void 438 dwc_otg_pull_down(struct dwc_otg_softc *sc) 439 { 440 uint32_t temp; 441 442 /* pulldown D+, if possible */ 443 444 if (sc->sc_flags.d_pulled_up) { 445 sc->sc_flags.d_pulled_up = 0; 446 447 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 448 temp |= DCTL_SFTDISCON; 449 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 450 } 451 } 452 453 static void 454 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 455 { 456 /* In device mode we don't use the SOF interrupt */ 457 if (sc->sc_flags.status_device_mode != 0 || 458 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 459 return; 460 sc->sc_irq_mask |= GINTMSK_SOFMSK; 461 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 462 } 463 464 static void 465 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 466 { 467 if (sc->sc_flags.status_suspend) { 468 /* update status bits */ 469 sc->sc_flags.status_suspend = 0; 470 sc->sc_flags.change_suspend = 1; 471 472 if (sc->sc_flags.status_device_mode) { 473 /* 474 * Disable resume interrupt and enable suspend 475 * interrupt: 476 */ 477 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 478 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 479 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 480 } 481 482 /* complete root HUB interrupt endpoint */ 483 dwc_otg_root_intr(sc); 484 } 485 } 486 487 static void 488 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 489 { 490 if (!sc->sc_flags.status_suspend) { 491 /* update status bits */ 492 sc->sc_flags.status_suspend = 1; 493 sc->sc_flags.change_suspend = 1; 494 495 if (sc->sc_flags.status_device_mode) { 496 /* 497 * Disable suspend interrupt and enable resume 498 * interrupt: 499 */ 500 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 501 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 502 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 503 } 504 505 /* complete root HUB interrupt endpoint */ 506 dwc_otg_root_intr(sc); 507 } 508 } 509 510 static void 511 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 512 { 513 if (!sc->sc_flags.status_suspend) 514 return; 515 516 DPRINTFN(5, "Remote wakeup\n"); 517 518 if (sc->sc_flags.status_device_mode) { 519 uint32_t temp; 520 521 /* enable remote wakeup signalling */ 522 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 523 temp |= DCTL_RMTWKUPSIG; 524 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 525 526 /* Wait 8ms for remote wakeup to complete. */ 527 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 528 529 temp &= ~DCTL_RMTWKUPSIG; 530 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 531 } else { 532 /* enable USB port */ 533 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 534 535 /* wait 10ms */ 536 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 537 538 /* resume port */ 539 sc->sc_hprt_val |= HPRT_PRTRES; 540 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 541 542 /* Wait 100ms for resume signalling to complete. */ 543 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 544 545 /* clear suspend and resume */ 546 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 547 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 548 549 /* Wait 4ms */ 550 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 551 } 552 553 /* need to fake resume IRQ */ 554 dwc_otg_resume_irq(sc); 555 } 556 557 static void 558 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 559 { 560 uint32_t temp; 561 562 DPRINTFN(5, "addr=%d\n", addr); 563 564 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 565 temp &= ~DCFG_DEVADDR_SET(0x7F); 566 temp |= DCFG_DEVADDR_SET(addr); 567 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 568 } 569 570 static void 571 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 572 { 573 DPRINTFN(5, "RX status clear\n"); 574 575 /* enable RX FIFO level interrupt */ 576 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 577 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 578 579 /* clear cached status */ 580 sc->sc_last_rx_status = 0; 581 } 582 583 static void 584 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 585 { 586 uint32_t hcint; 587 588 /* clear all pending interrupts */ 589 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 590 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 591 592 /* clear buffered interrupts */ 593 sc->sc_chan_state[x].hcint = 0; 594 } 595 596 static uint8_t 597 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) 598 { 599 uint32_t tx_p_size; 600 uint32_t tx_np_size; 601 uint8_t x; 602 603 if (td->channel < DWC_OTG_MAX_CHANNELS) 604 return (0); /* already allocated */ 605 606 /* check if device is suspended */ 607 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 608 return (1); /* busy - cannot transfer data */ 609 610 /* compute needed TX FIFO size */ 611 if (is_out != 0) { 612 if (td->ep_type == UE_ISOCHRONOUS) { 613 tx_p_size = td->max_packet_size; 614 tx_np_size = 0; 615 if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) 616 tx_p_size = HCSPLT_XACTLEN_BURST; 617 if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { 618 DPRINTF("Too little FIFO space\n"); 619 return (1); /* too little FIFO */ 620 } 621 } else { 622 tx_p_size = 0; 623 tx_np_size = td->max_packet_size; 624 if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) 625 tx_np_size = HCSPLT_XACTLEN_BURST; 626 if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { 627 DPRINTF("Too little FIFO space\n"); 628 return (1); /* too little FIFO */ 629 } 630 } 631 } else { 632 /* not a TX transaction */ 633 tx_p_size = 0; 634 tx_np_size = 0; 635 } 636 637 for (x = 0; x != sc->sc_host_ch_max; x++) { 638 if (sc->sc_chan_state[x].allocated != 0) 639 continue; 640 /* check if channel is still enabled */ 641 if (sc->sc_chan_state[x].wait_sof != 0) 642 continue; 643 644 sc->sc_chan_state[x].allocated = 1; 645 sc->sc_chan_state[x].tx_p_size = tx_p_size; 646 sc->sc_chan_state[x].tx_np_size = tx_np_size; 647 648 /* keep track of used TX FIFO, if any */ 649 sc->sc_tx_cur_p_level += tx_p_size; 650 sc->sc_tx_cur_np_level += tx_np_size; 651 652 /* clear interrupts */ 653 dwc_otg_clear_hcint(sc, x); 654 655 DPRINTF("CH=%d HCCHAR=0x%08x " 656 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 657 658 /* set active channel */ 659 sc->sc_active_rx_ep |= (1 << x); 660 661 /* set channel */ 662 td->channel = x; 663 664 return (0); /* allocated */ 665 } 666 /* wait a bit */ 667 dwc_otg_enable_sof_irq(sc); 668 return (1); /* busy */ 669 } 670 671 static void 672 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 673 { 674 uint8_t x; 675 676 if (td->channel >= DWC_OTG_MAX_CHANNELS) 677 return; /* already freed */ 678 679 /* free channel */ 680 x = td->channel; 681 td->channel = DWC_OTG_MAX_CHANNELS; 682 683 DPRINTF("CH=%d\n", x); 684 685 /* 686 * We need to let programmed host channels run till complete 687 * else the host channel will stop functioning. Assume that 688 * after a fixed given amount of time the host channel is no 689 * longer doing any USB traffic: 690 */ 691 if (td->ep_type == UE_ISOCHRONOUS) { 692 /* double buffered */ 693 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; 694 } else { 695 /* single buffered */ 696 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; 697 } 698 699 sc->sc_chan_state[x].allocated = 0; 700 701 /* ack any pending messages */ 702 if (sc->sc_last_rx_status != 0 && 703 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 704 dwc_otg_common_rx_ack(sc); 705 } 706 707 /* clear active channel */ 708 sc->sc_active_rx_ep &= ~(1 << x); 709 } 710 711 static void 712 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 713 { 714 /* dump any pending messages */ 715 if (sc->sc_last_rx_status != 0) { 716 if (td->channel < DWC_OTG_MAX_CHANNELS && 717 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 718 dwc_otg_common_rx_ack(sc); 719 } 720 } 721 } 722 723 static uint8_t 724 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 725 { 726 struct usb_device_request req __aligned(4); 727 uint32_t hcint; 728 uint32_t hcchar; 729 uint8_t delta; 730 731 dwc_otg_host_dump_rx(sc, td); 732 733 if (td->channel < DWC_OTG_MAX_CHANNELS) { 734 hcint = sc->sc_chan_state[td->channel].hcint; 735 736 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 737 td->channel, td->state, hcint, 738 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 739 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 740 } else { 741 hcint = 0; 742 goto check_state; 743 } 744 745 if (hcint & (HCINT_RETRY | 746 HCINT_ACK | HCINT_NYET)) { 747 /* give success bits priority over failure bits */ 748 } else if (hcint & HCINT_STALL) { 749 DPRINTF("CH=%d STALL\n", td->channel); 750 td->error_stall = 1; 751 td->error_any = 1; 752 goto complete; 753 } else if (hcint & HCINT_ERRORS) { 754 DPRINTF("CH=%d ERROR\n", td->channel); 755 td->errcnt++; 756 if (td->hcsplt != 0 || td->errcnt >= 3) { 757 td->error_any = 1; 758 goto complete; 759 } 760 } 761 762 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 763 HCINT_ACK | HCINT_NYET)) { 764 if (!(hcint & HCINT_ERRORS)) 765 td->errcnt = 0; 766 } 767 768 check_state: 769 switch (td->state) { 770 case DWC_CHAN_ST_START: 771 goto send_pkt; 772 773 case DWC_CHAN_ST_WAIT_ANE: 774 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 775 td->did_nak++; 776 td->tt_scheduled = 0; 777 goto send_pkt; 778 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 779 td->offset += td->tx_bytes; 780 td->remainder -= td->tx_bytes; 781 td->toggle = 1; 782 td->tt_scheduled = 0; 783 goto complete; 784 } 785 break; 786 787 case DWC_CHAN_ST_WAIT_S_ANE: 788 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 789 td->did_nak++; 790 td->tt_scheduled = 0; 791 goto send_pkt; 792 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 793 goto send_cpkt; 794 } 795 break; 796 797 case DWC_CHAN_ST_WAIT_C_ANE: 798 if (hcint & HCINT_NYET) { 799 goto send_cpkt; 800 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 801 td->did_nak++; 802 td->tt_scheduled = 0; 803 goto send_pkt; 804 } else if (hcint & HCINT_ACK) { 805 td->offset += td->tx_bytes; 806 td->remainder -= td->tx_bytes; 807 td->toggle = 1; 808 goto complete; 809 } 810 break; 811 812 case DWC_CHAN_ST_WAIT_C_PKT: 813 goto send_cpkt; 814 815 default: 816 break; 817 } 818 goto busy; 819 820 send_pkt: 821 /* free existing channel, if any */ 822 dwc_otg_host_channel_free(sc, td); 823 824 if (sizeof(req) != td->remainder) { 825 td->error_any = 1; 826 goto complete; 827 } 828 829 if (td->hcsplt != 0) { 830 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 831 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 832 td->state = DWC_CHAN_ST_START; 833 goto busy; 834 } 835 delta = sc->sc_last_frame_num - td->tt_start_slot; 836 if (delta > 5) { 837 /* missed it */ 838 td->tt_scheduled = 0; 839 td->state = DWC_CHAN_ST_START; 840 goto busy; 841 } 842 } 843 844 /* allocate a new channel */ 845 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 846 td->state = DWC_CHAN_ST_START; 847 goto busy; 848 } 849 850 if (td->hcsplt != 0) { 851 td->hcsplt &= ~HCSPLT_COMPSPLT; 852 td->state = DWC_CHAN_ST_WAIT_S_ANE; 853 } else { 854 td->state = DWC_CHAN_ST_WAIT_ANE; 855 } 856 857 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 858 859 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 860 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 861 (1 << HCTSIZ_PKTCNT_SHIFT) | 862 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 863 864 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 865 866 hcchar = td->hcchar; 867 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 868 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 869 870 /* must enable channel before writing data to FIFO */ 871 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 872 873 /* transfer data into FIFO */ 874 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 875 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 876 877 /* wait until next slot before trying complete split */ 878 td->tt_complete_slot = sc->sc_last_frame_num + 1; 879 880 /* store number of bytes transmitted */ 881 td->tx_bytes = sizeof(req); 882 goto busy; 883 884 send_cpkt: 885 /* free existing channel, if any */ 886 dwc_otg_host_channel_free(sc, td); 887 888 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 889 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 890 td->state = DWC_CHAN_ST_WAIT_C_PKT; 891 goto busy; 892 } 893 delta = sc->sc_last_frame_num - td->tt_start_slot; 894 if (delta > DWC_OTG_TT_SLOT_MAX) { 895 /* we missed the service interval */ 896 if (td->ep_type != UE_ISOCHRONOUS) 897 td->error_any = 1; 898 goto complete; 899 } 900 /* allocate a new channel */ 901 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 902 td->state = DWC_CHAN_ST_WAIT_C_PKT; 903 goto busy; 904 } 905 906 /* wait until next slot before trying complete split */ 907 td->tt_complete_slot = sc->sc_last_frame_num + 1; 908 909 td->hcsplt |= HCSPLT_COMPSPLT; 910 td->state = DWC_CHAN_ST_WAIT_C_ANE; 911 912 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 913 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 914 915 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 916 917 hcchar = td->hcchar; 918 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 919 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 920 921 /* must enable channel before writing data to FIFO */ 922 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 923 924 busy: 925 return (1); /* busy */ 926 927 complete: 928 dwc_otg_host_channel_free(sc, td); 929 return (0); /* complete */ 930 } 931 932 static uint8_t 933 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 934 { 935 struct usb_device_request req __aligned(4); 936 uint32_t temp; 937 uint16_t count; 938 939 /* check endpoint status */ 940 941 if (sc->sc_last_rx_status == 0) 942 goto not_complete; 943 944 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 945 goto not_complete; 946 947 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 948 GRXSTSRD_DPID_DATA0) { 949 /* release FIFO */ 950 dwc_otg_common_rx_ack(sc); 951 goto not_complete; 952 } 953 954 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 955 GRXSTSRD_STP_DATA) { 956 /* release FIFO */ 957 dwc_otg_common_rx_ack(sc); 958 goto not_complete; 959 } 960 961 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 962 963 /* clear did stall */ 964 td->did_stall = 0; 965 966 /* get the packet byte count */ 967 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 968 969 /* verify data length */ 970 if (count != td->remainder) { 971 DPRINTFN(0, "Invalid SETUP packet " 972 "length, %d bytes\n", count); 973 /* release FIFO */ 974 dwc_otg_common_rx_ack(sc); 975 goto not_complete; 976 } 977 if (count != sizeof(req)) { 978 DPRINTFN(0, "Unsupported SETUP packet " 979 "length, %d bytes\n", count); 980 /* release FIFO */ 981 dwc_otg_common_rx_ack(sc); 982 goto not_complete; 983 } 984 985 /* copy in control request */ 986 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 987 988 /* copy data into real buffer */ 989 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 990 991 td->offset = sizeof(req); 992 td->remainder = 0; 993 994 /* sneak peek the set address */ 995 if ((req.bmRequestType == UT_WRITE_DEVICE) && 996 (req.bRequest == UR_SET_ADDRESS)) { 997 /* must write address before ZLP */ 998 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 999 } 1000 1001 /* don't send any data by default */ 1002 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 1003 DXEPTSIZ_SET_NPKT(0) | 1004 DXEPTSIZ_SET_NBYTES(0)); 1005 1006 temp = sc->sc_in_ctl[0]; 1007 1008 /* enable IN endpoint */ 1009 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1010 temp | DIEPCTL_EPENA); 1011 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1012 temp | DIEPCTL_SNAK); 1013 1014 /* reset IN endpoint buffer */ 1015 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1016 GRSTCTL_TXFIFO(0) | 1017 GRSTCTL_TXFFLSH); 1018 1019 /* acknowledge RX status */ 1020 dwc_otg_common_rx_ack(sc); 1021 return (0); /* complete */ 1022 1023 not_complete: 1024 /* abort any ongoing transfer, before enabling again */ 1025 1026 temp = sc->sc_out_ctl[0]; 1027 1028 temp |= DOEPCTL_EPENA | 1029 DOEPCTL_SNAK; 1030 1031 /* enable OUT endpoint */ 1032 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1033 1034 if (!td->did_stall) { 1035 td->did_stall = 1; 1036 1037 DPRINTFN(5, "stalling IN and OUT direction\n"); 1038 1039 /* set stall after enabling endpoint */ 1040 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1041 temp | DOEPCTL_STALL); 1042 1043 temp = sc->sc_in_ctl[0]; 1044 1045 /* set stall assuming endpoint is enabled */ 1046 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1047 temp | DIEPCTL_STALL); 1048 } 1049 1050 /* setup number of buffers to receive */ 1051 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1052 DXEPTSIZ_SET_MULTI(3) | 1053 DXEPTSIZ_SET_NPKT(1) | 1054 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1055 1056 return (1); /* not complete */ 1057 } 1058 1059 static uint8_t 1060 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1061 { 1062 uint8_t delta; 1063 1064 delta = sc->sc_tmr_val - td->tmr_val; 1065 if (delta >= 128) 1066 return (1); /* busy */ 1067 1068 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1069 1070 /* set toggle, if any */ 1071 if (td->set_toggle) { 1072 td->set_toggle = 0; 1073 td->toggle = 1; 1074 } 1075 return (0); 1076 } 1077 1078 static uint8_t 1079 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1080 { 1081 if (td->ep_type == UE_ISOCHRONOUS) { 1082 /* non TT isochronous traffic */ 1083 if ((td->tmr_val != 0) || 1084 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1085 goto busy; 1086 } 1087 td->tmr_val = 1; /* executed */ 1088 td->toggle = 0; 1089 1090 } else if (td->ep_type == UE_INTERRUPT) { 1091 if (!td->tt_scheduled) 1092 goto busy; 1093 td->tt_scheduled = 0; 1094 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1095 goto busy; 1096 } else if (td->set_toggle) { 1097 td->set_toggle = 0; 1098 td->toggle = 1; 1099 } 1100 return (0); 1101 busy: 1102 return (1); 1103 } 1104 1105 static uint8_t 1106 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1107 { 1108 uint32_t count; 1109 uint8_t channel; 1110 1111 /* check endpoint status */ 1112 if (sc->sc_last_rx_status == 0) 1113 goto busy; 1114 1115 channel = td->channel; 1116 if (channel >= DWC_OTG_MAX_CHANNELS) 1117 goto busy; 1118 1119 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1120 goto busy; 1121 1122 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1123 case GRXSTSRH_IN_DATA: 1124 1125 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1126 (int)td->state, (int)sc->sc_last_rx_status); 1127 1128 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1129 /* 1130 * When using SPLIT transactions on interrupt 1131 * endpoints, sometimes data occurs twice. 1132 */ 1133 DPRINTF("Data already received\n"); 1134 break; 1135 } 1136 1137 /* get the packet byte count */ 1138 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1139 1140 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1141 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1142 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1143 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1144 } else { 1145 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1146 1147 /* verify the packet byte count */ 1148 if (count < td->max_packet_size) { 1149 /* we have a short packet */ 1150 td->short_pkt = 1; 1151 td->got_short = 1; 1152 } 1153 } 1154 td->toggle = 0; 1155 } else { 1156 /* verify the packet byte count */ 1157 if (count != td->max_packet_size) { 1158 if (count < td->max_packet_size) { 1159 /* we have a short packet */ 1160 td->short_pkt = 1; 1161 td->got_short = 1; 1162 } else { 1163 /* invalid USB packet */ 1164 td->error_any = 1; 1165 1166 /* release FIFO */ 1167 dwc_otg_common_rx_ack(sc); 1168 goto complete; 1169 } 1170 } 1171 td->toggle ^= 1; 1172 td->tt_scheduled = 0; 1173 } 1174 1175 /* verify the packet byte count */ 1176 if (count > td->remainder) { 1177 /* invalid USB packet */ 1178 td->error_any = 1; 1179 1180 /* release FIFO */ 1181 dwc_otg_common_rx_ack(sc); 1182 goto complete; 1183 } 1184 1185 usbd_copy_in(td->pc, td->offset, 1186 sc->sc_rx_bounce_buffer, count); 1187 1188 td->remainder -= count; 1189 td->offset += count; 1190 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1191 break; 1192 default: 1193 break; 1194 } 1195 /* release FIFO */ 1196 dwc_otg_common_rx_ack(sc); 1197 busy: 1198 return (0); 1199 complete: 1200 return (1); 1201 } 1202 1203 static uint8_t 1204 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1205 { 1206 uint32_t hcint; 1207 uint32_t hcchar; 1208 uint8_t delta; 1209 uint8_t channel; 1210 1211 channel = td->channel; 1212 1213 if (channel < DWC_OTG_MAX_CHANNELS) { 1214 hcint = sc->sc_chan_state[channel].hcint; 1215 1216 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1217 channel, td->state, hcint, 1218 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1219 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1220 1221 /* check interrupt bits */ 1222 if (hcint & (HCINT_RETRY | 1223 HCINT_ACK | HCINT_NYET)) { 1224 /* give success bits priority over failure bits */ 1225 } else if (hcint & HCINT_STALL) { 1226 DPRINTF("CH=%d STALL\n", channel); 1227 td->error_stall = 1; 1228 td->error_any = 1; 1229 goto complete; 1230 } else if (hcint & HCINT_ERRORS) { 1231 DPRINTF("CH=%d ERROR\n", channel); 1232 td->errcnt++; 1233 if (td->hcsplt != 0 || td->errcnt >= 3) { 1234 if (td->ep_type != UE_ISOCHRONOUS) { 1235 td->error_any = 1; 1236 goto complete; 1237 } 1238 } 1239 } 1240 1241 /* check channels for data, if any */ 1242 if (dwc_otg_host_data_rx_sub(sc, td)) 1243 goto complete; 1244 1245 /* refresh interrupt status */ 1246 hcint = sc->sc_chan_state[channel].hcint; 1247 1248 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1249 HCINT_ACK | HCINT_NYET)) { 1250 if (!(hcint & HCINT_ERRORS)) 1251 td->errcnt = 0; 1252 } 1253 } else { 1254 hcint = 0; 1255 } 1256 1257 switch (td->state) { 1258 case DWC_CHAN_ST_START: 1259 if (td->hcsplt != 0) 1260 goto receive_spkt; 1261 else 1262 goto receive_pkt; 1263 1264 case DWC_CHAN_ST_WAIT_ANE: 1265 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1266 if (td->ep_type == UE_INTERRUPT) { 1267 /* 1268 * The USB specification does not 1269 * mandate a particular data toggle 1270 * value for USB INTERRUPT 1271 * transfers. Switch the data toggle 1272 * value to receive the packet 1273 * correctly: 1274 */ 1275 if (hcint & HCINT_DATATGLERR) { 1276 DPRINTF("Retrying packet due to " 1277 "data toggle error\n"); 1278 td->toggle ^= 1; 1279 goto receive_pkt; 1280 } 1281 } 1282 td->did_nak++; 1283 td->tt_scheduled = 0; 1284 if (td->hcsplt != 0) 1285 goto receive_spkt; 1286 else 1287 goto receive_pkt; 1288 } else if (hcint & HCINT_NYET) { 1289 if (td->hcsplt != 0) { 1290 /* try again */ 1291 goto receive_pkt; 1292 } else { 1293 /* not a valid token for IN endpoints */ 1294 td->error_any = 1; 1295 goto complete; 1296 } 1297 } else if (hcint & HCINT_ACK) { 1298 /* wait for data - ACK arrived first */ 1299 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1300 goto busy; 1301 1302 if (td->ep_type == UE_ISOCHRONOUS) { 1303 /* check if we are complete */ 1304 if ((td->remainder == 0) || 1305 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1306 goto complete; 1307 } 1308 /* get another packet */ 1309 goto receive_pkt; 1310 } else { 1311 /* check if we are complete */ 1312 if ((td->remainder == 0) || (td->got_short != 0)) { 1313 if (td->short_pkt) 1314 goto complete; 1315 1316 /* 1317 * Else need to receive a zero length 1318 * packet. 1319 */ 1320 } 1321 td->tt_scheduled = 0; 1322 td->did_nak = 0; 1323 if (td->hcsplt != 0) 1324 goto receive_spkt; 1325 else 1326 goto receive_pkt; 1327 } 1328 } 1329 break; 1330 1331 case DWC_CHAN_ST_WAIT_S_ANE: 1332 /* 1333 * NOTE: The DWC OTG hardware provides a fake ACK in 1334 * case of interrupt and isochronous transfers: 1335 */ 1336 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1337 td->did_nak++; 1338 td->tt_scheduled = 0; 1339 goto receive_spkt; 1340 } else if (hcint & HCINT_NYET) { 1341 td->tt_scheduled = 0; 1342 goto receive_spkt; 1343 } else if (hcint & HCINT_ACK) { 1344 td->did_nak = 0; 1345 goto receive_pkt; 1346 } 1347 break; 1348 1349 case DWC_CHAN_ST_WAIT_C_PKT: 1350 goto receive_pkt; 1351 1352 default: 1353 break; 1354 } 1355 goto busy; 1356 1357 receive_pkt: 1358 /* free existing channel, if any */ 1359 dwc_otg_host_channel_free(sc, td); 1360 1361 if (td->hcsplt != 0) { 1362 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1363 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1364 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1365 goto busy; 1366 } 1367 delta = sc->sc_last_frame_num - td->tt_start_slot; 1368 if (delta > DWC_OTG_TT_SLOT_MAX) { 1369 if (td->ep_type != UE_ISOCHRONOUS) { 1370 /* we missed the service interval */ 1371 td->error_any = 1; 1372 } 1373 goto complete; 1374 } 1375 /* complete split */ 1376 td->hcsplt |= HCSPLT_COMPSPLT; 1377 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1378 dwc_otg_host_rate_check(sc, td)) { 1379 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1380 goto busy; 1381 } 1382 1383 /* allocate a new channel */ 1384 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1385 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1386 goto busy; 1387 } 1388 1389 channel = td->channel; 1390 1391 /* set toggle, if any */ 1392 if (td->set_toggle) { 1393 td->set_toggle = 0; 1394 td->toggle = 1; 1395 } 1396 1397 td->state = DWC_CHAN_ST_WAIT_ANE; 1398 1399 /* receive one packet */ 1400 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1401 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1402 (1 << HCTSIZ_PKTCNT_SHIFT) | 1403 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1404 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1405 1406 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1407 1408 hcchar = td->hcchar; 1409 hcchar |= HCCHAR_EPDIR_IN; 1410 1411 /* receive complete split ASAP */ 1412 if ((sc->sc_last_frame_num & 1) != 0) 1413 hcchar |= HCCHAR_ODDFRM; 1414 else 1415 hcchar &= ~HCCHAR_ODDFRM; 1416 1417 /* must enable channel before data can be received */ 1418 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1419 1420 /* wait until next slot before trying complete split */ 1421 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1422 1423 goto busy; 1424 1425 receive_spkt: 1426 /* free existing channel(s), if any */ 1427 dwc_otg_host_channel_free(sc, td); 1428 1429 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1430 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1431 td->state = DWC_CHAN_ST_START; 1432 goto busy; 1433 } 1434 delta = sc->sc_last_frame_num - td->tt_start_slot; 1435 if (delta > 5) { 1436 /* missed it */ 1437 td->tt_scheduled = 0; 1438 td->state = DWC_CHAN_ST_START; 1439 goto busy; 1440 } 1441 1442 /* allocate a new channel */ 1443 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1444 td->state = DWC_CHAN_ST_START; 1445 goto busy; 1446 } 1447 1448 channel = td->channel; 1449 1450 td->hcsplt &= ~HCSPLT_COMPSPLT; 1451 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1452 1453 /* receive one packet */ 1454 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1455 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1456 1457 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1458 1459 /* send after next SOF event */ 1460 if ((sc->sc_last_frame_num & 1) == 0) 1461 td->hcchar |= HCCHAR_ODDFRM; 1462 else 1463 td->hcchar &= ~HCCHAR_ODDFRM; 1464 1465 hcchar = td->hcchar; 1466 hcchar |= HCCHAR_EPDIR_IN; 1467 1468 /* wait until next slot before trying complete split */ 1469 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1470 1471 /* must enable channel before data can be received */ 1472 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1473 busy: 1474 return (1); /* busy */ 1475 1476 complete: 1477 dwc_otg_host_channel_free(sc, td); 1478 return (0); /* complete */ 1479 } 1480 1481 static uint8_t 1482 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1483 { 1484 uint32_t temp; 1485 uint16_t count; 1486 uint8_t got_short; 1487 1488 got_short = 0; 1489 1490 /* check endpoint status */ 1491 if (sc->sc_last_rx_status == 0) 1492 goto not_complete; 1493 1494 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1495 goto not_complete; 1496 1497 /* check for SETUP packet */ 1498 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1499 GRXSTSRD_STP_DATA) { 1500 if (td->remainder == 0) { 1501 /* 1502 * We are actually complete and have 1503 * received the next SETUP 1504 */ 1505 DPRINTFN(5, "faking complete\n"); 1506 return (0); /* complete */ 1507 } 1508 /* 1509 * USB Host Aborted the transfer. 1510 */ 1511 td->error_any = 1; 1512 return (0); /* complete */ 1513 } 1514 1515 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1516 GRXSTSRD_OUT_DATA) { 1517 /* release FIFO */ 1518 dwc_otg_common_rx_ack(sc); 1519 goto not_complete; 1520 } 1521 1522 /* get the packet byte count */ 1523 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1524 1525 /* verify the packet byte count */ 1526 if (count != td->max_packet_size) { 1527 if (count < td->max_packet_size) { 1528 /* we have a short packet */ 1529 td->short_pkt = 1; 1530 got_short = 1; 1531 } else { 1532 /* invalid USB packet */ 1533 td->error_any = 1; 1534 1535 /* release FIFO */ 1536 dwc_otg_common_rx_ack(sc); 1537 return (0); /* we are complete */ 1538 } 1539 } 1540 /* verify the packet byte count */ 1541 if (count > td->remainder) { 1542 /* invalid USB packet */ 1543 td->error_any = 1; 1544 1545 /* release FIFO */ 1546 dwc_otg_common_rx_ack(sc); 1547 return (0); /* we are complete */ 1548 } 1549 1550 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1551 td->remainder -= count; 1552 td->offset += count; 1553 1554 /* release FIFO */ 1555 dwc_otg_common_rx_ack(sc); 1556 1557 /* check if we are complete */ 1558 if ((td->remainder == 0) || got_short) { 1559 if (td->short_pkt) { 1560 /* we are complete */ 1561 return (0); 1562 } 1563 /* else need to receive a zero length packet */ 1564 } 1565 1566 not_complete: 1567 1568 temp = sc->sc_out_ctl[td->ep_no]; 1569 1570 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1571 1572 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1573 1574 /* enable SETUP and transfer complete interrupt */ 1575 if (td->ep_no == 0) { 1576 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1577 DXEPTSIZ_SET_NPKT(1) | 1578 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1579 } else { 1580 /* allow reception of multiple packets */ 1581 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1582 DXEPTSIZ_SET_MULTI(1) | 1583 DXEPTSIZ_SET_NPKT(4) | 1584 DXEPTSIZ_SET_NBYTES(4 * 1585 ((td->max_packet_size + 3) & ~3))); 1586 } 1587 return (1); /* not complete */ 1588 } 1589 1590 static uint8_t 1591 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1592 { 1593 uint32_t count; 1594 uint32_t hcint; 1595 uint32_t hcchar; 1596 uint8_t delta; 1597 uint8_t channel; 1598 1599 dwc_otg_host_dump_rx(sc, td); 1600 1601 channel = td->channel; 1602 1603 if (channel < DWC_OTG_MAX_CHANNELS) { 1604 hcint = sc->sc_chan_state[channel].hcint; 1605 1606 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1607 channel, td->state, hcint, 1608 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1609 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1610 1611 if (hcint & (HCINT_RETRY | 1612 HCINT_ACK | HCINT_NYET)) { 1613 /* give success bits priority over failure bits */ 1614 } else if (hcint & HCINT_STALL) { 1615 DPRINTF("CH=%d STALL\n", channel); 1616 td->error_stall = 1; 1617 td->error_any = 1; 1618 goto complete; 1619 } else if (hcint & HCINT_ERRORS) { 1620 DPRINTF("CH=%d ERROR\n", channel); 1621 td->errcnt++; 1622 if (td->hcsplt != 0 || td->errcnt >= 3) { 1623 td->error_any = 1; 1624 goto complete; 1625 } 1626 } 1627 1628 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1629 HCINT_ACK | HCINT_NYET)) { 1630 1631 if (!(hcint & HCINT_ERRORS)) 1632 td->errcnt = 0; 1633 } 1634 } else { 1635 hcint = 0; 1636 } 1637 1638 switch (td->state) { 1639 case DWC_CHAN_ST_START: 1640 goto send_pkt; 1641 1642 case DWC_CHAN_ST_WAIT_ANE: 1643 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1644 td->did_nak++; 1645 td->tt_scheduled = 0; 1646 goto send_pkt; 1647 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1648 td->offset += td->tx_bytes; 1649 td->remainder -= td->tx_bytes; 1650 td->toggle ^= 1; 1651 td->did_nak = 0; 1652 td->tt_scheduled = 0; 1653 1654 /* check remainder */ 1655 if (td->remainder == 0) { 1656 if (td->short_pkt) 1657 goto complete; 1658 1659 /* 1660 * Else we need to transmit a short 1661 * packet: 1662 */ 1663 } 1664 goto send_pkt; 1665 } 1666 break; 1667 1668 case DWC_CHAN_ST_WAIT_S_ANE: 1669 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1670 td->did_nak++; 1671 td->tt_scheduled = 0; 1672 goto send_pkt; 1673 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1674 td->did_nak = 0; 1675 goto send_cpkt; 1676 } 1677 break; 1678 1679 case DWC_CHAN_ST_WAIT_C_ANE: 1680 if (hcint & HCINT_NYET) { 1681 goto send_cpkt; 1682 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1683 td->did_nak++; 1684 td->tt_scheduled = 0; 1685 goto send_pkt; 1686 } else if (hcint & HCINT_ACK) { 1687 td->offset += td->tx_bytes; 1688 td->remainder -= td->tx_bytes; 1689 td->toggle ^= 1; 1690 td->did_nak = 0; 1691 td->tt_scheduled = 0; 1692 1693 /* check remainder */ 1694 if (td->remainder == 0) { 1695 if (td->short_pkt) 1696 goto complete; 1697 1698 /* else we need to transmit a short packet */ 1699 } 1700 goto send_pkt; 1701 } 1702 break; 1703 1704 case DWC_CHAN_ST_WAIT_C_PKT: 1705 goto send_cpkt; 1706 1707 case DWC_CHAN_ST_TX_WAIT_ISOC: 1708 1709 /* Check if isochronous OUT traffic is complete */ 1710 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1711 break; 1712 1713 td->offset += td->tx_bytes; 1714 td->remainder -= td->tx_bytes; 1715 1716 if (td->hcsplt != 0 || td->remainder == 0) 1717 goto complete; 1718 1719 /* check for next packet */ 1720 if (td->max_packet_count > 1) 1721 td->tt_xactpos++; 1722 1723 /* free existing channel, if any */ 1724 dwc_otg_host_channel_free(sc, td); 1725 1726 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1727 1728 /* FALLTHROUGH */ 1729 1730 case DWC_CHAN_ST_TX_PKT_ISOC: 1731 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1732 break; 1733 channel = td->channel; 1734 goto send_isoc_pkt; 1735 default: 1736 break; 1737 } 1738 goto busy; 1739 1740 send_pkt: 1741 /* free existing channel(s), if any */ 1742 dwc_otg_host_channel_free(sc, td); 1743 1744 if (td->hcsplt != 0) { 1745 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1746 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1747 td->state = DWC_CHAN_ST_START; 1748 goto busy; 1749 } 1750 delta = sc->sc_last_frame_num - td->tt_start_slot; 1751 if (delta > 5) { 1752 /* missed it */ 1753 td->tt_scheduled = 0; 1754 td->state = DWC_CHAN_ST_START; 1755 goto busy; 1756 } 1757 } else if (dwc_otg_host_rate_check(sc, td)) { 1758 td->state = DWC_CHAN_ST_START; 1759 goto busy; 1760 } 1761 1762 /* allocate a new channel */ 1763 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1764 td->state = DWC_CHAN_ST_START; 1765 goto busy; 1766 } 1767 1768 channel = td->channel; 1769 1770 /* set toggle, if any */ 1771 if (td->set_toggle) { 1772 td->set_toggle = 0; 1773 td->toggle = 1; 1774 } 1775 1776 if (td->ep_type == UE_ISOCHRONOUS) { 1777 send_isoc_pkt: 1778 /* Isochronous OUT transfers don't have any ACKs */ 1779 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1780 td->hcsplt &= ~HCSPLT_COMPSPLT; 1781 if (td->hcsplt != 0) { 1782 /* get maximum transfer length */ 1783 count = td->remainder; 1784 if (count > HCSPLT_XACTLEN_BURST) { 1785 DPRINTF("TT overflow\n"); 1786 td->error_any = 1; 1787 goto complete; 1788 } 1789 /* Update transaction position */ 1790 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1791 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1792 } else { 1793 /* send one packet at a time */ 1794 count = td->max_packet_size; 1795 if (td->remainder < count) { 1796 /* we have a short packet */ 1797 td->short_pkt = 1; 1798 count = td->remainder; 1799 } 1800 } 1801 } else if (td->hcsplt != 0) { 1802 1803 td->hcsplt &= ~HCSPLT_COMPSPLT; 1804 1805 /* Wait for ACK/NAK/ERR from TT */ 1806 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1807 1808 /* send one packet at a time */ 1809 count = td->max_packet_size; 1810 if (td->remainder < count) { 1811 /* we have a short packet */ 1812 td->short_pkt = 1; 1813 count = td->remainder; 1814 } 1815 } else { 1816 /* Wait for ACK/NAK/STALL from device */ 1817 td->state = DWC_CHAN_ST_WAIT_ANE; 1818 1819 /* send one packet at a time */ 1820 count = td->max_packet_size; 1821 if (td->remainder < count) { 1822 /* we have a short packet */ 1823 td->short_pkt = 1; 1824 count = td->remainder; 1825 } 1826 } 1827 1828 /* check for High-Speed multi-packets */ 1829 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1830 if (td->npkt == 0) { 1831 if (td->remainder >= (3 * td->max_packet_size)) 1832 td->npkt = 3; 1833 else if (td->remainder >= (2 * td->max_packet_size)) 1834 td->npkt = 2; 1835 else 1836 td->npkt = 1; 1837 1838 if (td->npkt > td->max_packet_count) 1839 td->npkt = td->max_packet_count; 1840 1841 td->tt_xactpos = 1; /* overload */ 1842 } 1843 if (td->tt_xactpos == td->npkt) { 1844 if (td->npkt == 1) { 1845 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1846 (count << HCTSIZ_XFERSIZE_SHIFT) | 1847 (1 << HCTSIZ_PKTCNT_SHIFT) | 1848 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1849 } else if (td->npkt == 2) { 1850 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1851 (count << HCTSIZ_XFERSIZE_SHIFT) | 1852 (1 << HCTSIZ_PKTCNT_SHIFT) | 1853 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1854 } else { 1855 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1856 (count << HCTSIZ_XFERSIZE_SHIFT) | 1857 (1 << HCTSIZ_PKTCNT_SHIFT) | 1858 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1859 } 1860 td->npkt = 0; 1861 } else { 1862 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1863 (count << HCTSIZ_XFERSIZE_SHIFT) | 1864 (1 << HCTSIZ_PKTCNT_SHIFT) | 1865 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1866 } 1867 } else { 1868 /* TODO: HCTSIZ_DOPNG */ 1869 1870 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1871 (count << HCTSIZ_XFERSIZE_SHIFT) | 1872 (1 << HCTSIZ_PKTCNT_SHIFT) | 1873 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1874 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1875 } 1876 1877 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1878 1879 hcchar = td->hcchar; 1880 hcchar &= ~HCCHAR_EPDIR_IN; 1881 1882 /* send after next SOF event */ 1883 if ((sc->sc_last_frame_num & 1) == 0) 1884 hcchar |= HCCHAR_ODDFRM; 1885 else 1886 hcchar &= ~HCCHAR_ODDFRM; 1887 1888 /* must enable before writing data to FIFO */ 1889 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1890 1891 if (count != 0) { 1892 1893 /* clear topmost word before copy */ 1894 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1895 1896 /* copy out data */ 1897 usbd_copy_out(td->pc, td->offset, 1898 sc->sc_tx_bounce_buffer, count); 1899 1900 /* transfer data into FIFO */ 1901 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1902 DOTG_DFIFO(channel), 1903 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1904 } 1905 1906 /* store number of bytes transmitted */ 1907 td->tx_bytes = count; 1908 goto busy; 1909 1910 send_cpkt: 1911 /* free existing channel, if any */ 1912 dwc_otg_host_channel_free(sc, td); 1913 1914 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1915 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1916 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1917 goto busy; 1918 } 1919 delta = sc->sc_last_frame_num - td->tt_start_slot; 1920 if (delta > DWC_OTG_TT_SLOT_MAX) { 1921 /* we missed the service interval */ 1922 if (td->ep_type != UE_ISOCHRONOUS) 1923 td->error_any = 1; 1924 goto complete; 1925 } 1926 1927 /* allocate a new channel */ 1928 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1929 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1930 goto busy; 1931 } 1932 1933 channel = td->channel; 1934 1935 td->hcsplt |= HCSPLT_COMPSPLT; 1936 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1937 1938 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1939 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1940 1941 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1942 1943 hcchar = td->hcchar; 1944 hcchar &= ~HCCHAR_EPDIR_IN; 1945 1946 /* receive complete split ASAP */ 1947 if ((sc->sc_last_frame_num & 1) != 0) 1948 hcchar |= HCCHAR_ODDFRM; 1949 else 1950 hcchar &= ~HCCHAR_ODDFRM; 1951 1952 /* must enable channel before data can be received */ 1953 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1954 1955 /* wait until next slot before trying complete split */ 1956 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1957 busy: 1958 return (1); /* busy */ 1959 1960 complete: 1961 dwc_otg_host_channel_free(sc, td); 1962 return (0); /* complete */ 1963 } 1964 1965 static uint8_t 1966 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1967 { 1968 uint32_t max_buffer; 1969 uint32_t count; 1970 uint32_t fifo_left; 1971 uint32_t mpkt; 1972 uint32_t temp; 1973 uint8_t to; 1974 1975 to = 3; /* don't loop forever! */ 1976 1977 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1978 1979 repeat: 1980 /* check for for endpoint 0 data */ 1981 1982 temp = sc->sc_last_rx_status; 1983 1984 if ((td->ep_no == 0) && (temp != 0) && 1985 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1986 1987 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1988 GRXSTSRD_STP_DATA) { 1989 1990 /* dump data - wrong direction */ 1991 dwc_otg_common_rx_ack(sc); 1992 } else { 1993 /* 1994 * The current transfer was cancelled 1995 * by the USB Host: 1996 */ 1997 td->error_any = 1; 1998 return (0); /* complete */ 1999 } 2000 } 2001 2002 /* fill in more TX data, if possible */ 2003 if (td->tx_bytes != 0) { 2004 2005 uint16_t cpkt; 2006 2007 /* check if packets have been transferred */ 2008 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2009 2010 /* get current packet number */ 2011 cpkt = DXEPTSIZ_GET_NPKT(temp); 2012 2013 if (cpkt >= td->npkt) { 2014 fifo_left = 0; 2015 } else { 2016 if (max_buffer != 0) { 2017 fifo_left = (td->npkt - cpkt) * 2018 td->max_packet_size; 2019 2020 if (fifo_left > max_buffer) 2021 fifo_left = max_buffer; 2022 } else { 2023 fifo_left = td->max_packet_size; 2024 } 2025 } 2026 2027 count = td->tx_bytes; 2028 if (count > fifo_left) 2029 count = fifo_left; 2030 2031 if (count != 0) { 2032 2033 /* clear topmost word before copy */ 2034 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2035 2036 /* copy out data */ 2037 usbd_copy_out(td->pc, td->offset, 2038 sc->sc_tx_bounce_buffer, count); 2039 2040 /* transfer data into FIFO */ 2041 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2042 DOTG_DFIFO(td->ep_no), 2043 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2044 2045 td->tx_bytes -= count; 2046 td->remainder -= count; 2047 td->offset += count; 2048 td->npkt = cpkt; 2049 } 2050 if (td->tx_bytes != 0) 2051 goto not_complete; 2052 2053 /* check remainder */ 2054 if (td->remainder == 0) { 2055 if (td->short_pkt) 2056 return (0); /* complete */ 2057 2058 /* else we need to transmit a short packet */ 2059 } 2060 } 2061 2062 if (!to--) 2063 goto not_complete; 2064 2065 /* check if not all packets have been transferred */ 2066 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2067 2068 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2069 2070 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2071 "DIEPCTL=0x%08x\n", td->ep_no, 2072 DXEPTSIZ_GET_NPKT(temp), 2073 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2074 2075 goto not_complete; 2076 } 2077 2078 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2079 2080 /* try to optimise by sending more data */ 2081 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2082 2083 /* send multiple packets at the same time */ 2084 mpkt = max_buffer / td->max_packet_size; 2085 2086 if (mpkt > 0x3FE) 2087 mpkt = 0x3FE; 2088 2089 count = td->remainder; 2090 if (count > 0x7FFFFF) 2091 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2092 2093 td->npkt = count / td->max_packet_size; 2094 2095 /* 2096 * NOTE: We could use 0x3FE instead of "mpkt" in the 2097 * check below to get more throughput, but then we 2098 * have a dependency towards non-generic chip features 2099 * to disable the TX-FIFO-EMPTY interrupts on a per 2100 * endpoint basis. Increase the maximum buffer size of 2101 * the IN endpoint to increase the performance. 2102 */ 2103 if (td->npkt > mpkt) { 2104 td->npkt = mpkt; 2105 count = td->max_packet_size * mpkt; 2106 } else if ((count == 0) || (count % td->max_packet_size)) { 2107 /* we are transmitting a short packet */ 2108 td->npkt++; 2109 td->short_pkt = 1; 2110 } 2111 } else { 2112 /* send one packet at a time */ 2113 mpkt = 1; 2114 count = td->max_packet_size; 2115 if (td->remainder < count) { 2116 /* we have a short packet */ 2117 td->short_pkt = 1; 2118 count = td->remainder; 2119 } 2120 td->npkt = 1; 2121 } 2122 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2123 DXEPTSIZ_SET_MULTI(1) | 2124 DXEPTSIZ_SET_NPKT(td->npkt) | 2125 DXEPTSIZ_SET_NBYTES(count)); 2126 2127 /* make room for buffering */ 2128 td->npkt += mpkt; 2129 2130 temp = sc->sc_in_ctl[td->ep_no]; 2131 2132 /* must enable before writing data to FIFO */ 2133 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2134 DIEPCTL_EPENA | 2135 DIEPCTL_CNAK); 2136 2137 td->tx_bytes = count; 2138 2139 /* check remainder */ 2140 if (td->tx_bytes == 0 && 2141 td->remainder == 0) { 2142 if (td->short_pkt) 2143 return (0); /* complete */ 2144 2145 /* else we need to transmit a short packet */ 2146 } 2147 goto repeat; 2148 2149 not_complete: 2150 return (1); /* not complete */ 2151 } 2152 2153 static uint8_t 2154 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2155 { 2156 uint32_t temp; 2157 2158 /* 2159 * If all packets are transferred we are complete: 2160 */ 2161 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2162 2163 /* check that all packets have been transferred */ 2164 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2165 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2166 goto not_complete; 2167 } 2168 return (0); 2169 2170 not_complete: 2171 2172 /* we only want to know if there is a SETUP packet or free IN packet */ 2173 2174 temp = sc->sc_last_rx_status; 2175 2176 if ((td->ep_no == 0) && (temp != 0) && 2177 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2178 2179 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2180 GRXSTSRD_STP_DATA) { 2181 DPRINTFN(5, "faking complete\n"); 2182 /* 2183 * Race condition: We are complete! 2184 */ 2185 return (0); 2186 } else { 2187 /* dump data - wrong direction */ 2188 dwc_otg_common_rx_ack(sc); 2189 } 2190 } 2191 return (1); /* not complete */ 2192 } 2193 2194 static void 2195 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2196 { 2197 struct dwc_otg_td *td; 2198 uint8_t toggle; 2199 uint8_t tmr_val; 2200 uint8_t tmr_res; 2201 2202 DPRINTFN(9, "\n"); 2203 2204 td = xfer->td_transfer_cache; 2205 if (td == NULL) 2206 return; 2207 2208 while (1) { 2209 if ((td->func) (sc, td)) { 2210 /* operation in progress */ 2211 break; 2212 } 2213 if (((void *)td) == xfer->td_transfer_last) { 2214 goto done; 2215 } 2216 if (td->error_any) { 2217 goto done; 2218 } else if (td->remainder > 0) { 2219 /* 2220 * We had a short transfer. If there is no alternate 2221 * next, stop processing ! 2222 */ 2223 if (!td->alt_next) 2224 goto done; 2225 } 2226 2227 /* 2228 * Fetch the next transfer descriptor and transfer 2229 * some flags to the next transfer descriptor 2230 */ 2231 tmr_res = td->tmr_res; 2232 tmr_val = td->tmr_val; 2233 toggle = td->toggle; 2234 td = td->obj_next; 2235 xfer->td_transfer_cache = td; 2236 td->toggle = toggle; /* transfer toggle */ 2237 td->tmr_res = tmr_res; 2238 td->tmr_val = tmr_val; 2239 } 2240 return; 2241 2242 done: 2243 xfer->td_transfer_cache = NULL; 2244 sc->sc_xfer_complete = 1; 2245 } 2246 2247 static uint8_t 2248 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2249 { 2250 struct dwc_otg_td *td; 2251 2252 DPRINTFN(9, "\n"); 2253 2254 td = xfer->td_transfer_cache; 2255 if (td == NULL) { 2256 /* compute all actual lengths */ 2257 dwc_otg_standard_done(xfer); 2258 return (1); 2259 } 2260 return (0); 2261 } 2262 2263 static void 2264 dwc_otg_timer(void *_sc) 2265 { 2266 struct dwc_otg_softc *sc = _sc; 2267 struct usb_xfer *xfer; 2268 struct dwc_otg_td *td; 2269 2270 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2271 2272 DPRINTF("\n"); 2273 2274 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2275 2276 /* increment timer value */ 2277 sc->sc_tmr_val++; 2278 2279 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2280 td = xfer->td_transfer_cache; 2281 if (td != NULL) { 2282 /* reset NAK counter */ 2283 td->did_nak = 0; 2284 } 2285 } 2286 2287 /* enable SOF interrupt, which will poll jobs */ 2288 dwc_otg_enable_sof_irq(sc); 2289 2290 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2291 2292 if (sc->sc_timer_active) { 2293 /* restart timer */ 2294 usb_callout_reset(&sc->sc_timer, 2295 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2296 &dwc_otg_timer, sc); 2297 } 2298 } 2299 2300 static void 2301 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2302 { 2303 if (sc->sc_timer_active != 0) 2304 return; 2305 2306 sc->sc_timer_active = 1; 2307 2308 /* restart timer */ 2309 usb_callout_reset(&sc->sc_timer, 2310 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2311 &dwc_otg_timer, sc); 2312 } 2313 2314 static void 2315 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2316 { 2317 if (sc->sc_timer_active == 0) 2318 return; 2319 2320 sc->sc_timer_active = 0; 2321 2322 /* stop timer */ 2323 usb_callout_stop(&sc->sc_timer); 2324 } 2325 2326 static void 2327 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 2328 { 2329 uint32_t hcchar; 2330 2331 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 2332 2333 /* disable host channel, if any */ 2334 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 2335 /* disable channel */ 2336 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2337 HCCHAR_CHENA | HCCHAR_CHDIS); 2338 /* wait for chip to get its brains in order */ 2339 sc->sc_chan_state[x].wait_sof = 2; 2340 } 2341 2342 /* release TX FIFO usage, if any */ 2343 sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; 2344 sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; 2345 2346 /* don't release TX FIFO usage twice */ 2347 sc->sc_chan_state[x].tx_p_size = 0; 2348 sc->sc_chan_state[x].tx_np_size = 0; 2349 } 2350 2351 static uint16_t 2352 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2353 { 2354 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2355 pinfo->slot_index++; 2356 return (pinfo->slot_index); 2357 } 2358 2359 static uint8_t 2360 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2361 { 2362 TAILQ_HEAD(, usb_xfer) head; 2363 struct usb_xfer *xfer; 2364 struct usb_xfer *xfer_next; 2365 struct dwc_otg_td *td; 2366 uint16_t temp; 2367 uint16_t slot; 2368 uint8_t x; 2369 2370 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2371 2372 if (sc->sc_last_frame_num == temp) 2373 return (0); 2374 2375 sc->sc_last_frame_num = temp; 2376 2377 TAILQ_INIT(&head); 2378 2379 for (x = 0; x != sc->sc_host_ch_max; x++) { 2380 if (sc->sc_chan_state[x].wait_sof == 0) 2381 continue; 2382 2383 sc->sc_needsof = 1; 2384 if (--(sc->sc_chan_state[x].wait_sof) == 0) 2385 dwc_otg_host_channel_disable(sc, x); 2386 } 2387 2388 if ((temp & 7) == 0) { 2389 2390 /* reset the schedule */ 2391 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2392 2393 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2394 td = xfer->td_transfer_cache; 2395 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2396 continue; 2397 2398 /* check for IN direction */ 2399 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2400 continue; 2401 2402 /* execute more frames */ 2403 td->tmr_val = 0; 2404 2405 sc->sc_needsof = 1; 2406 2407 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2408 continue; 2409 2410 /* compute slot */ 2411 slot = dwc_otg_compute_isoc_rx_tt_slot( 2412 sc->sc_tt_info + td->tt_index); 2413 if (slot > 3) { 2414 /* 2415 * Not enough time to get complete 2416 * split executed. 2417 */ 2418 continue; 2419 } 2420 /* Delayed start */ 2421 td->tt_start_slot = temp + slot; 2422 td->tt_scheduled = 1; 2423 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2424 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2425 } 2426 2427 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2428 td = xfer->td_transfer_cache; 2429 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2430 continue; 2431 2432 /* check for OUT direction */ 2433 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2434 continue; 2435 2436 /* execute more frames */ 2437 td->tmr_val = 0; 2438 2439 sc->sc_needsof = 1; 2440 2441 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2442 continue; 2443 2444 /* Start ASAP */ 2445 td->tt_start_slot = temp; 2446 td->tt_scheduled = 1; 2447 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2448 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2449 } 2450 2451 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2452 td = xfer->td_transfer_cache; 2453 if (td == NULL || td->ep_type != UE_INTERRUPT) 2454 continue; 2455 2456 if (td->tt_scheduled != 0) { 2457 sc->sc_needsof = 1; 2458 continue; 2459 } 2460 2461 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2462 continue; 2463 2464 if (td->hcsplt == 0) { 2465 sc->sc_needsof = 1; 2466 td->tt_scheduled = 1; 2467 continue; 2468 } 2469 2470 /* start ASAP */ 2471 td->tt_start_slot = temp; 2472 sc->sc_needsof = 1; 2473 td->tt_scheduled = 1; 2474 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2475 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2476 } 2477 2478 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2479 td = xfer->td_transfer_cache; 2480 if (td == NULL || 2481 td->ep_type != UE_CONTROL || 2482 td->did_nak >= DWC_OTG_NAK_MAX) { 2483 continue; 2484 } 2485 2486 sc->sc_needsof = 1; 2487 2488 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2489 continue; 2490 2491 /* start ASAP */ 2492 td->tt_start_slot = temp; 2493 td->tt_scheduled = 1; 2494 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2495 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2496 } 2497 } 2498 if ((temp & 7) < 6) { 2499 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2500 td = xfer->td_transfer_cache; 2501 if (td == NULL || 2502 td->ep_type != UE_BULK || 2503 td->did_nak >= DWC_OTG_NAK_MAX) { 2504 continue; 2505 } 2506 2507 sc->sc_needsof = 1; 2508 2509 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2510 continue; 2511 2512 /* start ASAP */ 2513 td->tt_start_slot = temp; 2514 td->tt_scheduled = 1; 2515 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2516 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2517 } 2518 } 2519 2520 /* Put TT transfers in execution order at the end */ 2521 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2522 2523 /* move all TT transfers in front, keeping the current order */ 2524 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2525 td = xfer->td_transfer_cache; 2526 if (td == NULL || td->hcsplt == 0) 2527 continue; 2528 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2529 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2530 } 2531 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2532 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2533 2534 /* put non-TT BULK transfers last */ 2535 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2536 td = xfer->td_transfer_cache; 2537 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2538 continue; 2539 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2540 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2541 } 2542 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2543 2544 if ((temp & 7) == 0) { 2545 2546 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2547 (int)temp, (int)sc->sc_needsof); 2548 2549 /* update SOF IRQ mask */ 2550 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2551 if (sc->sc_needsof == 0) { 2552 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2553 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2554 } 2555 } else { 2556 if (sc->sc_needsof != 0) { 2557 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2558 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2559 } 2560 } 2561 2562 /* clear need SOF flag */ 2563 sc->sc_needsof = 0; 2564 } 2565 return (1); 2566 } 2567 2568 static void 2569 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2570 { 2571 struct usb_xfer *xfer; 2572 uint32_t temp; 2573 uint8_t got_rx_status; 2574 uint8_t x; 2575 2576 repeat: 2577 /* get all channel interrupts */ 2578 for (x = 0; x != sc->sc_host_ch_max; x++) { 2579 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2580 if (temp != 0) { 2581 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2582 temp &= ~HCINT_SOFTWARE_ONLY; 2583 sc->sc_chan_state[x].hcint |= temp; 2584 } 2585 } 2586 2587 if (sc->sc_last_rx_status == 0) { 2588 2589 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2590 if (temp & GINTSTS_RXFLVL) { 2591 /* pop current status */ 2592 sc->sc_last_rx_status = 2593 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2594 } 2595 2596 if (sc->sc_last_rx_status != 0) { 2597 2598 uint8_t ep_no; 2599 2600 temp = sc->sc_last_rx_status & 2601 GRXSTSRD_PKTSTS_MASK; 2602 2603 /* non-data messages we simply skip */ 2604 if (temp != GRXSTSRD_STP_DATA && 2605 temp != GRXSTSRD_OUT_DATA) { 2606 dwc_otg_common_rx_ack(sc); 2607 goto repeat; 2608 } 2609 2610 temp = GRXSTSRD_BCNT_GET( 2611 sc->sc_last_rx_status); 2612 ep_no = GRXSTSRD_CHNUM_GET( 2613 sc->sc_last_rx_status); 2614 2615 /* receive data, if any */ 2616 if (temp != 0) { 2617 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2618 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2619 DOTG_DFIFO(ep_no), 2620 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2621 } 2622 2623 /* check if we should dump the data */ 2624 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2625 dwc_otg_common_rx_ack(sc); 2626 goto repeat; 2627 } 2628 2629 got_rx_status = 1; 2630 2631 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2632 sc->sc_last_rx_status, ep_no, 2633 (sc->sc_last_rx_status >> 15) & 3, 2634 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2635 (sc->sc_last_rx_status >> 17) & 15); 2636 } else { 2637 got_rx_status = 0; 2638 } 2639 } else { 2640 uint8_t ep_no; 2641 2642 ep_no = GRXSTSRD_CHNUM_GET( 2643 sc->sc_last_rx_status); 2644 2645 /* check if we should dump the data */ 2646 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2647 dwc_otg_common_rx_ack(sc); 2648 goto repeat; 2649 } 2650 2651 got_rx_status = 1; 2652 } 2653 2654 /* execute FIFOs */ 2655 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2656 dwc_otg_xfer_do_fifo(sc, xfer); 2657 2658 if (got_rx_status) { 2659 /* check if data was consumed */ 2660 if (sc->sc_last_rx_status == 0) 2661 goto repeat; 2662 2663 /* disable RX FIFO level interrupt */ 2664 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2665 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2666 } 2667 2668 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2669 /* update host transfer schedule, so that new transfers can be issued */ 2670 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2671 goto repeat; 2672 } 2673 } 2674 2675 static void 2676 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2677 { 2678 struct usb_xfer *xfer; 2679 repeat: 2680 /* scan for completion events */ 2681 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2682 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2683 goto repeat; 2684 } 2685 } 2686 2687 static void 2688 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2689 { 2690 DPRINTFN(5, "vbus = %u\n", is_on); 2691 2692 /* 2693 * If the USB host mode is forced, then assume VBUS is always 2694 * present else rely on the input to this function: 2695 */ 2696 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2697 2698 if (!sc->sc_flags.status_vbus) { 2699 sc->sc_flags.status_vbus = 1; 2700 2701 /* complete root HUB interrupt endpoint */ 2702 2703 dwc_otg_root_intr(sc); 2704 } 2705 } else { 2706 if (sc->sc_flags.status_vbus) { 2707 sc->sc_flags.status_vbus = 0; 2708 sc->sc_flags.status_bus_reset = 0; 2709 sc->sc_flags.status_suspend = 0; 2710 sc->sc_flags.change_suspend = 0; 2711 sc->sc_flags.change_connect = 1; 2712 2713 /* complete root HUB interrupt endpoint */ 2714 2715 dwc_otg_root_intr(sc); 2716 } 2717 } 2718 } 2719 2720 int 2721 dwc_otg_filter_interrupt(void *arg) 2722 { 2723 struct dwc_otg_softc *sc = arg; 2724 int retval = FILTER_HANDLED; 2725 uint32_t status; 2726 2727 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2728 2729 /* read and clear interrupt status */ 2730 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2731 2732 /* clear interrupts we are handling here */ 2733 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2734 2735 /* check for USB state change interrupts */ 2736 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2737 retval = FILTER_SCHEDULE_THREAD; 2738 2739 /* clear all IN endpoint interrupts */ 2740 if (status & GINTSTS_IEPINT) { 2741 uint32_t temp; 2742 uint8_t x; 2743 2744 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2745 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2746 if (temp & DIEPMSK_XFERCOMPLMSK) { 2747 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2748 DIEPMSK_XFERCOMPLMSK); 2749 } 2750 } 2751 } 2752 2753 /* poll FIFOs, if any */ 2754 dwc_otg_interrupt_poll_locked(sc); 2755 2756 if (sc->sc_xfer_complete != 0) 2757 retval = FILTER_SCHEDULE_THREAD; 2758 2759 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2760 2761 return (retval); 2762 } 2763 2764 void 2765 dwc_otg_interrupt(void *arg) 2766 { 2767 struct dwc_otg_softc *sc = arg; 2768 uint32_t status; 2769 2770 USB_BUS_LOCK(&sc->sc_bus); 2771 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2772 2773 /* read and clear interrupt status */ 2774 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2775 2776 /* clear interrupts we are handling here */ 2777 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2778 2779 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2780 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2781 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2782 2783 if (status & GINTSTS_USBRST) { 2784 2785 /* set correct state */ 2786 sc->sc_flags.status_device_mode = 1; 2787 sc->sc_flags.status_bus_reset = 0; 2788 sc->sc_flags.status_suspend = 0; 2789 sc->sc_flags.change_suspend = 0; 2790 sc->sc_flags.change_connect = 1; 2791 2792 /* Disable SOF interrupt */ 2793 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2794 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2795 2796 /* complete root HUB interrupt endpoint */ 2797 dwc_otg_root_intr(sc); 2798 } 2799 2800 /* check for any bus state change interrupts */ 2801 if (status & GINTSTS_ENUMDONE) { 2802 2803 uint32_t temp; 2804 2805 DPRINTFN(5, "end of reset\n"); 2806 2807 /* set correct state */ 2808 sc->sc_flags.status_device_mode = 1; 2809 sc->sc_flags.status_bus_reset = 1; 2810 sc->sc_flags.status_suspend = 0; 2811 sc->sc_flags.change_suspend = 0; 2812 sc->sc_flags.change_connect = 1; 2813 sc->sc_flags.status_low_speed = 0; 2814 sc->sc_flags.port_enabled = 1; 2815 2816 /* reset FIFOs */ 2817 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2818 2819 /* reset function address */ 2820 dwc_otg_set_address(sc, 0); 2821 2822 /* figure out enumeration speed */ 2823 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2824 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2825 sc->sc_flags.status_high_speed = 1; 2826 else 2827 sc->sc_flags.status_high_speed = 0; 2828 2829 /* 2830 * Disable resume and SOF interrupt, and enable 2831 * suspend and RX frame interrupt: 2832 */ 2833 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2834 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2835 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2836 2837 /* complete root HUB interrupt endpoint */ 2838 dwc_otg_root_intr(sc); 2839 } 2840 2841 if (status & GINTSTS_PRTINT) { 2842 uint32_t hprt; 2843 2844 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2845 2846 /* clear change bits */ 2847 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2848 HPRT_PRTPWR | HPRT_PRTENCHNG | 2849 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2850 sc->sc_hprt_val); 2851 2852 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2853 2854 sc->sc_flags.status_device_mode = 0; 2855 2856 if (hprt & HPRT_PRTCONNSTS) 2857 sc->sc_flags.status_bus_reset = 1; 2858 else 2859 sc->sc_flags.status_bus_reset = 0; 2860 2861 if (hprt & HPRT_PRTENCHNG) 2862 sc->sc_flags.change_enabled = 1; 2863 2864 if (hprt & HPRT_PRTENA) 2865 sc->sc_flags.port_enabled = 1; 2866 else 2867 sc->sc_flags.port_enabled = 0; 2868 2869 if (hprt & HPRT_PRTOVRCURRCHNG) 2870 sc->sc_flags.change_over_current = 1; 2871 2872 if (hprt & HPRT_PRTOVRCURRACT) 2873 sc->sc_flags.port_over_current = 1; 2874 else 2875 sc->sc_flags.port_over_current = 0; 2876 2877 if (hprt & HPRT_PRTPWR) 2878 sc->sc_flags.port_powered = 1; 2879 else 2880 sc->sc_flags.port_powered = 0; 2881 2882 if (((hprt & HPRT_PRTSPD_MASK) 2883 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2884 sc->sc_flags.status_low_speed = 1; 2885 else 2886 sc->sc_flags.status_low_speed = 0; 2887 2888 if (((hprt & HPRT_PRTSPD_MASK) 2889 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2890 sc->sc_flags.status_high_speed = 1; 2891 else 2892 sc->sc_flags.status_high_speed = 0; 2893 2894 if (hprt & HPRT_PRTCONNDET) 2895 sc->sc_flags.change_connect = 1; 2896 2897 if (hprt & HPRT_PRTSUSP) 2898 dwc_otg_suspend_irq(sc); 2899 else 2900 dwc_otg_resume_irq(sc); 2901 2902 /* complete root HUB interrupt endpoint */ 2903 dwc_otg_root_intr(sc); 2904 2905 /* update host frame interval */ 2906 dwc_otg_update_host_frame_interval(sc); 2907 } 2908 2909 /* 2910 * If resume and suspend is set at the same time we interpret 2911 * that like RESUME. Resume is set when there is at least 3 2912 * milliseconds of inactivity on the USB BUS. 2913 */ 2914 if (status & GINTSTS_WKUPINT) { 2915 2916 DPRINTFN(5, "resume interrupt\n"); 2917 2918 dwc_otg_resume_irq(sc); 2919 2920 } else if (status & GINTSTS_USBSUSP) { 2921 2922 DPRINTFN(5, "suspend interrupt\n"); 2923 2924 dwc_otg_suspend_irq(sc); 2925 } 2926 /* check VBUS */ 2927 if (status & (GINTSTS_USBSUSP | 2928 GINTSTS_USBRST | 2929 GINTMSK_OTGINTMSK | 2930 GINTSTS_SESSREQINT)) { 2931 uint32_t temp; 2932 2933 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2934 2935 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2936 2937 dwc_otg_vbus_interrupt(sc, 2938 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2939 } 2940 2941 if (sc->sc_xfer_complete != 0) { 2942 sc->sc_xfer_complete = 0; 2943 2944 /* complete FIFOs, if any */ 2945 dwc_otg_interrupt_complete_locked(sc); 2946 2947 if (sc->sc_flags.status_device_mode == 0) { 2948 /* update host transfer schedule, so that new transfers can be issued */ 2949 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2950 dwc_otg_interrupt_poll_locked(sc); 2951 } 2952 } 2953 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2954 USB_BUS_UNLOCK(&sc->sc_bus); 2955 } 2956 2957 static void 2958 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2959 { 2960 struct dwc_otg_td *td; 2961 2962 /* get current Transfer Descriptor */ 2963 td = temp->td_next; 2964 temp->td = td; 2965 2966 /* prepare for next TD */ 2967 temp->td_next = td->obj_next; 2968 2969 /* fill out the Transfer Descriptor */ 2970 td->func = temp->func; 2971 td->pc = temp->pc; 2972 td->offset = temp->offset; 2973 td->remainder = temp->len; 2974 td->tx_bytes = 0; 2975 td->error_any = 0; 2976 td->error_stall = 0; 2977 td->npkt = 0; 2978 td->did_stall = temp->did_stall; 2979 td->short_pkt = temp->short_pkt; 2980 td->alt_next = temp->setup_alt_next; 2981 td->set_toggle = 0; 2982 td->got_short = 0; 2983 td->did_nak = 0; 2984 td->channel = DWC_OTG_MAX_CHANNELS; 2985 td->state = 0; 2986 td->errcnt = 0; 2987 td->tt_scheduled = 0; 2988 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2989 } 2990 2991 static void 2992 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2993 { 2994 struct dwc_otg_std_temp temp; 2995 struct dwc_otg_td *td; 2996 uint32_t x; 2997 uint8_t need_sync; 2998 uint8_t is_host; 2999 3000 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3001 xfer->address, UE_GET_ADDR(xfer->endpointno), 3002 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3003 3004 temp.max_frame_size = xfer->max_frame_size; 3005 3006 td = xfer->td_start[0]; 3007 xfer->td_transfer_first = td; 3008 xfer->td_transfer_cache = td; 3009 3010 /* setup temp */ 3011 3012 temp.pc = NULL; 3013 temp.td = NULL; 3014 temp.td_next = xfer->td_start[0]; 3015 temp.offset = 0; 3016 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3017 xfer->flags_int.isochronous_xfr; 3018 temp.did_stall = !xfer->flags_int.control_stall; 3019 3020 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3021 3022 /* check if we should prepend a setup message */ 3023 3024 if (xfer->flags_int.control_xfr) { 3025 if (xfer->flags_int.control_hdr) { 3026 3027 if (is_host) 3028 temp.func = &dwc_otg_host_setup_tx; 3029 else 3030 temp.func = &dwc_otg_setup_rx; 3031 3032 temp.len = xfer->frlengths[0]; 3033 temp.pc = xfer->frbuffers + 0; 3034 temp.short_pkt = temp.len ? 1 : 0; 3035 3036 /* check for last frame */ 3037 if (xfer->nframes == 1) { 3038 /* no STATUS stage yet, SETUP is last */ 3039 if (xfer->flags_int.control_act) 3040 temp.setup_alt_next = 0; 3041 } 3042 3043 dwc_otg_setup_standard_chain_sub(&temp); 3044 } 3045 x = 1; 3046 } else { 3047 x = 0; 3048 } 3049 3050 if (x != xfer->nframes) { 3051 if (xfer->endpointno & UE_DIR_IN) { 3052 if (is_host) { 3053 temp.func = &dwc_otg_host_data_rx; 3054 need_sync = 0; 3055 } else { 3056 temp.func = &dwc_otg_data_tx; 3057 need_sync = 1; 3058 } 3059 } else { 3060 if (is_host) { 3061 temp.func = &dwc_otg_host_data_tx; 3062 need_sync = 0; 3063 } else { 3064 temp.func = &dwc_otg_data_rx; 3065 need_sync = 0; 3066 } 3067 } 3068 3069 /* setup "pc" pointer */ 3070 temp.pc = xfer->frbuffers + x; 3071 } else { 3072 need_sync = 0; 3073 } 3074 while (x != xfer->nframes) { 3075 3076 /* DATA0 / DATA1 message */ 3077 3078 temp.len = xfer->frlengths[x]; 3079 3080 x++; 3081 3082 if (x == xfer->nframes) { 3083 if (xfer->flags_int.control_xfr) { 3084 if (xfer->flags_int.control_act) { 3085 temp.setup_alt_next = 0; 3086 } 3087 } else { 3088 temp.setup_alt_next = 0; 3089 } 3090 } 3091 if (temp.len == 0) { 3092 3093 /* make sure that we send an USB packet */ 3094 3095 temp.short_pkt = 0; 3096 3097 } else { 3098 3099 /* regular data transfer */ 3100 3101 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3102 } 3103 3104 dwc_otg_setup_standard_chain_sub(&temp); 3105 3106 if (xfer->flags_int.isochronous_xfr) { 3107 temp.offset += temp.len; 3108 } else { 3109 /* get next Page Cache pointer */ 3110 temp.pc = xfer->frbuffers + x; 3111 } 3112 } 3113 3114 if (xfer->flags_int.control_xfr) { 3115 3116 /* always setup a valid "pc" pointer for status and sync */ 3117 temp.pc = xfer->frbuffers + 0; 3118 temp.len = 0; 3119 temp.short_pkt = 0; 3120 temp.setup_alt_next = 0; 3121 3122 /* check if we need to sync */ 3123 if (need_sync) { 3124 /* we need a SYNC point after TX */ 3125 temp.func = &dwc_otg_data_tx_sync; 3126 dwc_otg_setup_standard_chain_sub(&temp); 3127 } 3128 3129 /* check if we should append a status stage */ 3130 if (!xfer->flags_int.control_act) { 3131 3132 /* 3133 * Send a DATA1 message and invert the current 3134 * endpoint direction. 3135 */ 3136 if (xfer->endpointno & UE_DIR_IN) { 3137 if (is_host) { 3138 temp.func = &dwc_otg_host_data_tx; 3139 need_sync = 0; 3140 } else { 3141 temp.func = &dwc_otg_data_rx; 3142 need_sync = 0; 3143 } 3144 } else { 3145 if (is_host) { 3146 temp.func = &dwc_otg_host_data_rx; 3147 need_sync = 0; 3148 } else { 3149 temp.func = &dwc_otg_data_tx; 3150 need_sync = 1; 3151 } 3152 } 3153 3154 dwc_otg_setup_standard_chain_sub(&temp); 3155 3156 /* data toggle should be DATA1 */ 3157 td = temp.td; 3158 td->set_toggle = 1; 3159 3160 if (need_sync) { 3161 /* we need a SYNC point after TX */ 3162 temp.func = &dwc_otg_data_tx_sync; 3163 dwc_otg_setup_standard_chain_sub(&temp); 3164 } 3165 } 3166 } else { 3167 /* check if we need to sync */ 3168 if (need_sync) { 3169 3170 temp.pc = xfer->frbuffers + 0; 3171 temp.len = 0; 3172 temp.short_pkt = 0; 3173 temp.setup_alt_next = 0; 3174 3175 /* we need a SYNC point after TX */ 3176 temp.func = &dwc_otg_data_tx_sync; 3177 dwc_otg_setup_standard_chain_sub(&temp); 3178 } 3179 } 3180 3181 /* must have at least one frame! */ 3182 td = temp.td; 3183 xfer->td_transfer_last = td; 3184 3185 if (is_host) { 3186 3187 struct dwc_otg_softc *sc; 3188 uint32_t hcchar; 3189 uint32_t hcsplt; 3190 3191 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3192 3193 /* get first again */ 3194 td = xfer->td_transfer_first; 3195 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3196 3197 hcchar = 3198 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3199 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3200 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3201 HCCHAR_CHENA; 3202 3203 /* 3204 * We are not always able to meet the timing 3205 * requirements of the USB interrupt endpoint's 3206 * complete split token, when doing transfers going 3207 * via a transaction translator. Use the CONTROL 3208 * transfer type instead of the INTERRUPT transfer 3209 * type in general, as a means to workaround 3210 * that. This trick should work for both FULL and LOW 3211 * speed USB traffic going through a TT. For non-TT 3212 * traffic it works aswell. The reason for using 3213 * CONTROL type instead of BULK is that some TTs might 3214 * reject LOW speed BULK traffic. 3215 */ 3216 if (td->ep_type == UE_INTERRUPT) 3217 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3218 else 3219 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3220 3221 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3222 hcchar |= HCCHAR_LSPDDEV; 3223 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3224 hcchar |= HCCHAR_EPDIR_IN; 3225 3226 switch (xfer->xroot->udev->speed) { 3227 case USB_SPEED_FULL: 3228 case USB_SPEED_LOW: 3229 /* check if root HUB port is running High Speed */ 3230 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3231 hcsplt = HCSPLT_SPLTENA | 3232 (xfer->xroot->udev->hs_port_no << 3233 HCSPLT_PRTADDR_SHIFT) | 3234 (xfer->xroot->udev->hs_hub_addr << 3235 HCSPLT_HUBADDR_SHIFT); 3236 } else { 3237 hcsplt = 0; 3238 } 3239 if (td->ep_type == UE_INTERRUPT) { 3240 uint32_t ival; 3241 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3242 if (ival == 0) 3243 ival = 1; 3244 else if (ival > 127) 3245 ival = 127; 3246 td->tmr_val = sc->sc_tmr_val + ival; 3247 td->tmr_res = ival; 3248 } else if (td->ep_type == UE_ISOCHRONOUS) { 3249 td->tmr_val = 0; 3250 td->tmr_res = 1; 3251 } else { 3252 td->tmr_val = 0; 3253 td->tmr_res = 0; 3254 } 3255 break; 3256 case USB_SPEED_HIGH: 3257 hcsplt = 0; 3258 if (td->ep_type == UE_INTERRUPT) { 3259 uint32_t ival; 3260 #if 0 3261 hcchar |= ((xfer->max_packet_count & 3) 3262 << HCCHAR_MC_SHIFT); 3263 #endif 3264 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3265 if (ival == 0) 3266 ival = 1; 3267 else if (ival > 127) 3268 ival = 127; 3269 td->tmr_val = sc->sc_tmr_val + ival; 3270 td->tmr_res = ival; 3271 } else if (td->ep_type == UE_ISOCHRONOUS) { 3272 hcchar |= ((xfer->max_packet_count & 3) 3273 << HCCHAR_MC_SHIFT); 3274 td->tmr_val = 0; 3275 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3276 } else { 3277 td->tmr_val = 0; 3278 td->tmr_res = 0; 3279 } 3280 break; 3281 default: 3282 hcsplt = 0; 3283 td->tmr_val = 0; 3284 td->tmr_res = 0; 3285 break; 3286 } 3287 3288 /* store configuration in all TD's */ 3289 while (1) { 3290 td->hcchar = hcchar; 3291 td->hcsplt = hcsplt; 3292 3293 if (((void *)td) == xfer->td_transfer_last) 3294 break; 3295 3296 td = td->obj_next; 3297 } 3298 } 3299 } 3300 3301 static void 3302 dwc_otg_timeout(void *arg) 3303 { 3304 struct usb_xfer *xfer = arg; 3305 3306 DPRINTF("xfer=%p\n", xfer); 3307 3308 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3309 3310 /* transfer is transferred */ 3311 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3312 } 3313 3314 static void 3315 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3316 { 3317 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3318 struct usb_xfer_root *xroot; 3319 struct dwc_otg_td *td; 3320 3321 DPRINTFN(9, "\n"); 3322 3323 /* 3324 * Poll one time in device mode, which will turn on the 3325 * endpoint interrupts. Else wait for SOF interrupt in host 3326 * mode. 3327 */ 3328 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3329 3330 if (sc->sc_flags.status_device_mode != 0) { 3331 dwc_otg_xfer_do_fifo(sc, xfer); 3332 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3333 goto done; 3334 } 3335 3336 /* put transfer on interrupt queue */ 3337 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3338 3339 /* start timeout, if any */ 3340 if (xfer->timeout != 0) { 3341 usbd_transfer_timeout_ms(xfer, 3342 &dwc_otg_timeout, xfer->timeout); 3343 } 3344 3345 if (sc->sc_flags.status_device_mode != 0) 3346 goto done; 3347 3348 /* enable SOF interrupt, if any */ 3349 dwc_otg_enable_sof_irq(sc); 3350 3351 td = xfer->td_transfer_cache; 3352 if (td->ep_type != UE_BULK) 3353 goto done; 3354 3355 xroot = xfer->xroot; 3356 3357 /* 3358 * Optimise the ping-pong effect by waking up other BULK 3359 * transfers belonging to the same device group: 3360 */ 3361 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3362 td = xfer->td_transfer_cache; 3363 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3364 continue; 3365 /* reset NAK counter */ 3366 td->did_nak = 0; 3367 } 3368 done: 3369 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3370 } 3371 3372 static void 3373 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3374 { 3375 DPRINTFN(9, "\n"); 3376 3377 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3378 3379 /* set port bit */ 3380 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3381 3382 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3383 sizeof(sc->sc_hub_idata)); 3384 } 3385 3386 static usb_error_t 3387 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3388 { 3389 struct dwc_otg_td *td; 3390 uint32_t len; 3391 usb_error_t error; 3392 3393 DPRINTFN(9, "\n"); 3394 3395 td = xfer->td_transfer_cache; 3396 3397 do { 3398 len = td->remainder; 3399 3400 /* store last data toggle */ 3401 xfer->endpoint->toggle_next = td->toggle; 3402 3403 if (xfer->aframes != xfer->nframes) { 3404 /* 3405 * Verify the length and subtract 3406 * the remainder from "frlengths[]": 3407 */ 3408 if (len > xfer->frlengths[xfer->aframes]) { 3409 td->error_any = 1; 3410 } else { 3411 xfer->frlengths[xfer->aframes] -= len; 3412 } 3413 } 3414 /* Check for transfer error */ 3415 if (td->error_any) { 3416 /* the transfer is finished */ 3417 error = (td->error_stall ? 3418 USB_ERR_STALLED : USB_ERR_IOERROR); 3419 td = NULL; 3420 break; 3421 } 3422 /* Check for short transfer */ 3423 if (len > 0) { 3424 if (xfer->flags_int.short_frames_ok || 3425 xfer->flags_int.isochronous_xfr) { 3426 /* follow alt next */ 3427 if (td->alt_next) { 3428 td = td->obj_next; 3429 } else { 3430 td = NULL; 3431 } 3432 } else { 3433 /* the transfer is finished */ 3434 td = NULL; 3435 } 3436 error = 0; 3437 break; 3438 } 3439 td = td->obj_next; 3440 3441 /* this USB frame is complete */ 3442 error = 0; 3443 break; 3444 3445 } while (0); 3446 3447 /* update transfer cache */ 3448 3449 xfer->td_transfer_cache = td; 3450 3451 return (error); 3452 } 3453 3454 static void 3455 dwc_otg_standard_done(struct usb_xfer *xfer) 3456 { 3457 usb_error_t err = 0; 3458 3459 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3460 xfer, xfer->endpoint); 3461 3462 /* reset scanner */ 3463 3464 xfer->td_transfer_cache = xfer->td_transfer_first; 3465 3466 if (xfer->flags_int.control_xfr) { 3467 3468 if (xfer->flags_int.control_hdr) { 3469 3470 err = dwc_otg_standard_done_sub(xfer); 3471 } 3472 xfer->aframes = 1; 3473 3474 if (xfer->td_transfer_cache == NULL) { 3475 goto done; 3476 } 3477 } 3478 while (xfer->aframes != xfer->nframes) { 3479 3480 err = dwc_otg_standard_done_sub(xfer); 3481 xfer->aframes++; 3482 3483 if (xfer->td_transfer_cache == NULL) { 3484 goto done; 3485 } 3486 } 3487 3488 if (xfer->flags_int.control_xfr && 3489 !xfer->flags_int.control_act) { 3490 3491 err = dwc_otg_standard_done_sub(xfer); 3492 } 3493 done: 3494 dwc_otg_device_done(xfer, err); 3495 } 3496 3497 /*------------------------------------------------------------------------* 3498 * dwc_otg_device_done 3499 * 3500 * NOTE: this function can be called more than one time on the 3501 * same USB transfer! 3502 *------------------------------------------------------------------------*/ 3503 static void 3504 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3505 { 3506 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3507 3508 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3509 xfer, xfer->endpoint, error); 3510 3511 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3512 3513 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3514 /* Interrupts are cleared by the interrupt handler */ 3515 } else { 3516 struct dwc_otg_td *td; 3517 3518 td = xfer->td_transfer_cache; 3519 if (td != NULL) 3520 dwc_otg_host_channel_free(sc, td); 3521 } 3522 /* dequeue transfer and start next transfer */ 3523 usbd_transfer_done(xfer, error); 3524 3525 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3526 } 3527 3528 static void 3529 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3530 { 3531 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3532 } 3533 3534 static void 3535 dwc_otg_set_stall(struct usb_device *udev, 3536 struct usb_endpoint *ep, uint8_t *did_stall) 3537 { 3538 struct dwc_otg_softc *sc; 3539 uint32_t temp; 3540 uint32_t reg; 3541 uint8_t ep_no; 3542 3543 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3544 3545 /* check mode */ 3546 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3547 /* not supported */ 3548 return; 3549 } 3550 3551 sc = DWC_OTG_BUS2SC(udev->bus); 3552 3553 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3554 3555 /* get endpoint address */ 3556 ep_no = ep->edesc->bEndpointAddress; 3557 3558 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3559 3560 if (ep_no & UE_DIR_IN) { 3561 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3562 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3563 } else { 3564 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3565 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3566 } 3567 3568 /* disable and stall endpoint */ 3569 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3570 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3571 3572 /* clear active OUT ep */ 3573 if (!(ep_no & UE_DIR_IN)) { 3574 3575 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3576 3577 if (sc->sc_last_rx_status != 0 && 3578 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3579 sc->sc_last_rx_status)) { 3580 /* dump data */ 3581 dwc_otg_common_rx_ack(sc); 3582 /* poll interrupt */ 3583 dwc_otg_interrupt_poll_locked(sc); 3584 dwc_otg_interrupt_complete_locked(sc); 3585 } 3586 } 3587 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3588 } 3589 3590 static void 3591 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3592 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3593 { 3594 uint32_t reg; 3595 uint32_t temp; 3596 3597 if (ep_type == UE_CONTROL) { 3598 /* clearing stall is not needed */ 3599 return; 3600 } 3601 3602 if (ep_dir) { 3603 reg = DOTG_DIEPCTL(ep_no); 3604 } else { 3605 reg = DOTG_DOEPCTL(ep_no); 3606 sc->sc_active_rx_ep |= (1U << ep_no); 3607 } 3608 3609 /* round up and mask away the multiplier count */ 3610 mps = (mps + 3) & 0x7FC; 3611 3612 if (ep_type == UE_BULK) { 3613 temp = DIEPCTL_EPTYPE_SET( 3614 DIEPCTL_EPTYPE_BULK) | 3615 DIEPCTL_USBACTEP; 3616 } else if (ep_type == UE_INTERRUPT) { 3617 temp = DIEPCTL_EPTYPE_SET( 3618 DIEPCTL_EPTYPE_INTERRUPT) | 3619 DIEPCTL_USBACTEP; 3620 } else { 3621 temp = DIEPCTL_EPTYPE_SET( 3622 DIEPCTL_EPTYPE_ISOC) | 3623 DIEPCTL_USBACTEP; 3624 } 3625 3626 temp |= DIEPCTL_MPS_SET(mps); 3627 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3628 3629 if (ep_dir) 3630 sc->sc_in_ctl[ep_no] = temp; 3631 else 3632 sc->sc_out_ctl[ep_no] = temp; 3633 3634 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3635 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3636 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3637 3638 /* we only reset the transmit FIFO */ 3639 if (ep_dir) { 3640 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3641 GRSTCTL_TXFIFO(ep_no) | 3642 GRSTCTL_TXFFLSH); 3643 3644 DWC_OTG_WRITE_4(sc, 3645 DOTG_DIEPTSIZ(ep_no), 0); 3646 } 3647 3648 /* poll interrupt */ 3649 dwc_otg_interrupt_poll_locked(sc); 3650 dwc_otg_interrupt_complete_locked(sc); 3651 } 3652 3653 static void 3654 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3655 { 3656 struct dwc_otg_softc *sc; 3657 struct usb_endpoint_descriptor *ed; 3658 3659 DPRINTFN(5, "endpoint=%p\n", ep); 3660 3661 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3662 3663 /* check mode */ 3664 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3665 /* not supported */ 3666 return; 3667 } 3668 /* get softc */ 3669 sc = DWC_OTG_BUS2SC(udev->bus); 3670 3671 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3672 3673 /* get endpoint descriptor */ 3674 ed = ep->edesc; 3675 3676 /* reset endpoint */ 3677 dwc_otg_clear_stall_sub_locked(sc, 3678 UGETW(ed->wMaxPacketSize), 3679 (ed->bEndpointAddress & UE_ADDR), 3680 (ed->bmAttributes & UE_XFERTYPE), 3681 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3682 3683 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3684 } 3685 3686 static void 3687 dwc_otg_device_state_change(struct usb_device *udev) 3688 { 3689 struct dwc_otg_softc *sc; 3690 uint8_t x; 3691 3692 /* check mode */ 3693 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3694 /* not supported */ 3695 return; 3696 } 3697 3698 /* get softc */ 3699 sc = DWC_OTG_BUS2SC(udev->bus); 3700 3701 /* deactivate all other endpoint but the control endpoint */ 3702 if (udev->state == USB_STATE_CONFIGURED || 3703 udev->state == USB_STATE_ADDRESSED) { 3704 3705 USB_BUS_LOCK(&sc->sc_bus); 3706 3707 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3708 3709 if (x < sc->sc_dev_in_ep_max) { 3710 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3711 DIEPCTL_EPDIS); 3712 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3713 } 3714 3715 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3716 DOEPCTL_EPDIS); 3717 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3718 } 3719 USB_BUS_UNLOCK(&sc->sc_bus); 3720 } 3721 } 3722 3723 int 3724 dwc_otg_init(struct dwc_otg_softc *sc) 3725 { 3726 uint32_t temp; 3727 3728 DPRINTF("start\n"); 3729 3730 /* set up the bus structure */ 3731 sc->sc_bus.usbrev = USB_REV_2_0; 3732 sc->sc_bus.methods = &dwc_otg_bus_methods; 3733 3734 usb_callout_init_mtx(&sc->sc_timer, 3735 &sc->sc_bus.bus_mtx, 0); 3736 3737 USB_BUS_LOCK(&sc->sc_bus); 3738 3739 /* turn on clocks */ 3740 dwc_otg_clocks_on(sc); 3741 3742 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3743 DPRINTF("Version = 0x%08x\n", temp); 3744 3745 /* disconnect */ 3746 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3747 DCTL_SFTDISCON); 3748 3749 /* wait for host to detect disconnect */ 3750 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3751 3752 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3753 GRSTCTL_CSFTRST); 3754 3755 /* wait a little bit for block to reset */ 3756 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3757 3758 switch (sc->sc_mode) { 3759 case DWC_MODE_DEVICE: 3760 temp = GUSBCFG_FORCEDEVMODE; 3761 break; 3762 case DWC_MODE_HOST: 3763 temp = GUSBCFG_FORCEHOSTMODE; 3764 break; 3765 default: 3766 temp = 0; 3767 break; 3768 } 3769 3770 /* select HSIC or non-HSIC mode */ 3771 if (dwc_otg_use_hsic) { 3772 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3773 GUSBCFG_PHYIF | 3774 GUSBCFG_TRD_TIM_SET(5) | temp); 3775 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3776 0x000000EC); 3777 3778 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3779 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3780 temp & ~GLPMCFG_HSIC_CONN); 3781 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3782 temp | GLPMCFG_HSIC_CONN); 3783 } else { 3784 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3785 GUSBCFG_ULPI_UTMI_SEL | 3786 GUSBCFG_TRD_TIM_SET(5) | temp); 3787 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3788 3789 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3790 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3791 temp & ~GLPMCFG_HSIC_CONN); 3792 } 3793 3794 /* clear global nak */ 3795 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3796 DCTL_CGOUTNAK | 3797 DCTL_CGNPINNAK); 3798 3799 /* disable USB port */ 3800 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3801 3802 /* wait 10ms */ 3803 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3804 3805 /* enable USB port */ 3806 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3807 3808 /* wait 10ms */ 3809 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3810 3811 /* pull up D+ */ 3812 dwc_otg_pull_up(sc); 3813 3814 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3815 3816 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3817 3818 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3819 3820 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3821 3822 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3823 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3824 3825 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3826 3827 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3828 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3829 3830 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3831 3832 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3833 3834 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3835 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3836 sc->sc_host_ch_max); 3837 3838 /* setup FIFO */ 3839 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3840 USB_BUS_UNLOCK(&sc->sc_bus); 3841 return (EINVAL); 3842 } 3843 3844 /* enable interrupts */ 3845 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3846 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3847 3848 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3849 3850 /* enable all endpoint interrupts */ 3851 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3852 if (temp & GHWCFG2_MPI) { 3853 uint8_t x; 3854 3855 DPRINTF("Multi Process Interrupts\n"); 3856 3857 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3858 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3859 DIEPMSK_XFERCOMPLMSK); 3860 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3861 } 3862 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3863 } else { 3864 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3865 DIEPMSK_XFERCOMPLMSK); 3866 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3867 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3868 } 3869 } 3870 3871 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3872 /* setup clocks */ 3873 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3874 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3875 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3876 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3877 } 3878 3879 /* only enable global IRQ */ 3880 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3881 GAHBCFG_GLBLINTRMSK); 3882 3883 /* turn off clocks */ 3884 dwc_otg_clocks_off(sc); 3885 3886 /* read initial VBUS state */ 3887 3888 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3889 3890 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3891 3892 dwc_otg_vbus_interrupt(sc, 3893 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3894 3895 USB_BUS_UNLOCK(&sc->sc_bus); 3896 3897 /* catch any lost interrupts */ 3898 3899 dwc_otg_do_poll(&sc->sc_bus); 3900 3901 return (0); /* success */ 3902 } 3903 3904 void 3905 dwc_otg_uninit(struct dwc_otg_softc *sc) 3906 { 3907 USB_BUS_LOCK(&sc->sc_bus); 3908 3909 /* stop host timer */ 3910 dwc_otg_timer_stop(sc); 3911 3912 /* set disconnect */ 3913 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3914 DCTL_SFTDISCON); 3915 3916 /* turn off global IRQ */ 3917 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3918 3919 sc->sc_flags.port_enabled = 0; 3920 sc->sc_flags.port_powered = 0; 3921 sc->sc_flags.status_vbus = 0; 3922 sc->sc_flags.status_bus_reset = 0; 3923 sc->sc_flags.status_suspend = 0; 3924 sc->sc_flags.change_suspend = 0; 3925 sc->sc_flags.change_connect = 1; 3926 3927 dwc_otg_pull_down(sc); 3928 dwc_otg_clocks_off(sc); 3929 3930 USB_BUS_UNLOCK(&sc->sc_bus); 3931 3932 usb_callout_drain(&sc->sc_timer); 3933 } 3934 3935 static void 3936 dwc_otg_suspend(struct dwc_otg_softc *sc) 3937 { 3938 return; 3939 } 3940 3941 static void 3942 dwc_otg_resume(struct dwc_otg_softc *sc) 3943 { 3944 return; 3945 } 3946 3947 static void 3948 dwc_otg_do_poll(struct usb_bus *bus) 3949 { 3950 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3951 3952 USB_BUS_LOCK(&sc->sc_bus); 3953 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3954 dwc_otg_interrupt_poll_locked(sc); 3955 dwc_otg_interrupt_complete_locked(sc); 3956 if (sc->sc_flags.status_device_mode == 0) { 3957 /* update host transfer schedule, so that new transfers can be issued */ 3958 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3959 dwc_otg_interrupt_poll_locked(sc); 3960 } 3961 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3962 USB_BUS_UNLOCK(&sc->sc_bus); 3963 } 3964 3965 /*------------------------------------------------------------------------* 3966 * DWC OTG bulk support 3967 * DWC OTG control support 3968 * DWC OTG interrupt support 3969 *------------------------------------------------------------------------*/ 3970 static void 3971 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3972 { 3973 } 3974 3975 static void 3976 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3977 { 3978 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3979 } 3980 3981 static void 3982 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3983 { 3984 } 3985 3986 static void 3987 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3988 { 3989 /* setup TDs */ 3990 dwc_otg_setup_standard_chain(xfer); 3991 dwc_otg_start_standard_chain(xfer); 3992 } 3993 3994 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3995 { 3996 .open = dwc_otg_device_non_isoc_open, 3997 .close = dwc_otg_device_non_isoc_close, 3998 .enter = dwc_otg_device_non_isoc_enter, 3999 .start = dwc_otg_device_non_isoc_start, 4000 }; 4001 4002 /*------------------------------------------------------------------------* 4003 * DWC OTG full speed isochronous support 4004 *------------------------------------------------------------------------*/ 4005 static void 4006 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4007 { 4008 } 4009 4010 static void 4011 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4012 { 4013 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4014 } 4015 4016 static void 4017 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4018 { 4019 } 4020 4021 static void 4022 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4023 { 4024 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4025 uint32_t temp; 4026 uint32_t msframes; 4027 uint32_t framenum; 4028 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4029 4030 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4031 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4032 4033 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4034 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4035 4036 /* get the current frame index */ 4037 framenum = (temp & HFNUM_FRNUM_MASK); 4038 } else { 4039 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4040 4041 /* get the current frame index */ 4042 framenum = DSTS_SOFFN_GET(temp); 4043 } 4044 4045 if (xfer->xroot->udev->parent_hs_hub != NULL) 4046 framenum /= 8; 4047 4048 framenum &= DWC_OTG_FRAME_MASK; 4049 4050 /* 4051 * Compute number of milliseconds worth of data traffic for 4052 * this USB transfer: 4053 */ 4054 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4055 msframes = ((xfer->nframes << shift) + 7) / 8; 4056 else 4057 msframes = xfer->nframes; 4058 4059 /* 4060 * check if the frame index is within the window where the frames 4061 * will be inserted 4062 */ 4063 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4064 4065 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4066 /* 4067 * If there is data underflow or the pipe queue is 4068 * empty we schedule the transfer a few frames ahead 4069 * of the current frame position. Else two isochronous 4070 * transfers might overlap. 4071 */ 4072 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4073 xfer->endpoint->is_synced = 1; 4074 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4075 } 4076 /* 4077 * compute how many milliseconds the insertion is ahead of the 4078 * current frame position: 4079 */ 4080 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4081 4082 /* 4083 * pre-compute when the isochronous transfer will be finished: 4084 */ 4085 xfer->isoc_time_complete = 4086 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4087 4088 /* setup TDs */ 4089 dwc_otg_setup_standard_chain(xfer); 4090 4091 /* compute frame number for next insertion */ 4092 xfer->endpoint->isoc_next += msframes; 4093 4094 /* start TD chain */ 4095 dwc_otg_start_standard_chain(xfer); 4096 } 4097 4098 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4099 { 4100 .open = dwc_otg_device_isoc_open, 4101 .close = dwc_otg_device_isoc_close, 4102 .enter = dwc_otg_device_isoc_enter, 4103 .start = dwc_otg_device_isoc_start, 4104 }; 4105 4106 /*------------------------------------------------------------------------* 4107 * DWC OTG root control support 4108 *------------------------------------------------------------------------* 4109 * Simulate a hardware HUB by handling all the necessary requests. 4110 *------------------------------------------------------------------------*/ 4111 4112 static const struct usb_device_descriptor dwc_otg_devd = { 4113 .bLength = sizeof(struct usb_device_descriptor), 4114 .bDescriptorType = UDESC_DEVICE, 4115 .bcdUSB = {0x00, 0x02}, 4116 .bDeviceClass = UDCLASS_HUB, 4117 .bDeviceSubClass = UDSUBCLASS_HUB, 4118 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4119 .bMaxPacketSize = 64, 4120 .bcdDevice = {0x00, 0x01}, 4121 .iManufacturer = 1, 4122 .iProduct = 2, 4123 .bNumConfigurations = 1, 4124 }; 4125 4126 static const struct dwc_otg_config_desc dwc_otg_confd = { 4127 .confd = { 4128 .bLength = sizeof(struct usb_config_descriptor), 4129 .bDescriptorType = UDESC_CONFIG, 4130 .wTotalLength[0] = sizeof(dwc_otg_confd), 4131 .bNumInterface = 1, 4132 .bConfigurationValue = 1, 4133 .iConfiguration = 0, 4134 .bmAttributes = UC_SELF_POWERED, 4135 .bMaxPower = 0, 4136 }, 4137 .ifcd = { 4138 .bLength = sizeof(struct usb_interface_descriptor), 4139 .bDescriptorType = UDESC_INTERFACE, 4140 .bNumEndpoints = 1, 4141 .bInterfaceClass = UICLASS_HUB, 4142 .bInterfaceSubClass = UISUBCLASS_HUB, 4143 .bInterfaceProtocol = 0, 4144 }, 4145 .endpd = { 4146 .bLength = sizeof(struct usb_endpoint_descriptor), 4147 .bDescriptorType = UDESC_ENDPOINT, 4148 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4149 .bmAttributes = UE_INTERRUPT, 4150 .wMaxPacketSize[0] = 8, 4151 .bInterval = 255, 4152 }, 4153 }; 4154 4155 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4156 4157 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4158 .bDescLength = sizeof(dwc_otg_hubd), 4159 .bDescriptorType = UDESC_HUB, 4160 .bNbrPorts = 1, 4161 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4162 .bPwrOn2PwrGood = 50, 4163 .bHubContrCurrent = 0, 4164 .DeviceRemovable = {0}, /* port is removable */ 4165 }; 4166 4167 #define STRING_VENDOR \ 4168 "D\0W\0C\0O\0T\0G" 4169 4170 #define STRING_PRODUCT \ 4171 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4172 4173 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4174 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4175 4176 static usb_error_t 4177 dwc_otg_roothub_exec(struct usb_device *udev, 4178 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4179 { 4180 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4181 const void *ptr; 4182 uint16_t len; 4183 uint16_t value; 4184 uint16_t index; 4185 usb_error_t err; 4186 4187 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4188 4189 /* buffer reset */ 4190 ptr = (const void *)&sc->sc_hub_temp; 4191 len = 0; 4192 err = 0; 4193 4194 value = UGETW(req->wValue); 4195 index = UGETW(req->wIndex); 4196 4197 /* demultiplex the control request */ 4198 4199 switch (req->bmRequestType) { 4200 case UT_READ_DEVICE: 4201 switch (req->bRequest) { 4202 case UR_GET_DESCRIPTOR: 4203 goto tr_handle_get_descriptor; 4204 case UR_GET_CONFIG: 4205 goto tr_handle_get_config; 4206 case UR_GET_STATUS: 4207 goto tr_handle_get_status; 4208 default: 4209 goto tr_stalled; 4210 } 4211 break; 4212 4213 case UT_WRITE_DEVICE: 4214 switch (req->bRequest) { 4215 case UR_SET_ADDRESS: 4216 goto tr_handle_set_address; 4217 case UR_SET_CONFIG: 4218 goto tr_handle_set_config; 4219 case UR_CLEAR_FEATURE: 4220 goto tr_valid; /* nop */ 4221 case UR_SET_DESCRIPTOR: 4222 goto tr_valid; /* nop */ 4223 case UR_SET_FEATURE: 4224 default: 4225 goto tr_stalled; 4226 } 4227 break; 4228 4229 case UT_WRITE_ENDPOINT: 4230 switch (req->bRequest) { 4231 case UR_CLEAR_FEATURE: 4232 switch (UGETW(req->wValue)) { 4233 case UF_ENDPOINT_HALT: 4234 goto tr_handle_clear_halt; 4235 case UF_DEVICE_REMOTE_WAKEUP: 4236 goto tr_handle_clear_wakeup; 4237 default: 4238 goto tr_stalled; 4239 } 4240 break; 4241 case UR_SET_FEATURE: 4242 switch (UGETW(req->wValue)) { 4243 case UF_ENDPOINT_HALT: 4244 goto tr_handle_set_halt; 4245 case UF_DEVICE_REMOTE_WAKEUP: 4246 goto tr_handle_set_wakeup; 4247 default: 4248 goto tr_stalled; 4249 } 4250 break; 4251 case UR_SYNCH_FRAME: 4252 goto tr_valid; /* nop */ 4253 default: 4254 goto tr_stalled; 4255 } 4256 break; 4257 4258 case UT_READ_ENDPOINT: 4259 switch (req->bRequest) { 4260 case UR_GET_STATUS: 4261 goto tr_handle_get_ep_status; 4262 default: 4263 goto tr_stalled; 4264 } 4265 break; 4266 4267 case UT_WRITE_INTERFACE: 4268 switch (req->bRequest) { 4269 case UR_SET_INTERFACE: 4270 goto tr_handle_set_interface; 4271 case UR_CLEAR_FEATURE: 4272 goto tr_valid; /* nop */ 4273 case UR_SET_FEATURE: 4274 default: 4275 goto tr_stalled; 4276 } 4277 break; 4278 4279 case UT_READ_INTERFACE: 4280 switch (req->bRequest) { 4281 case UR_GET_INTERFACE: 4282 goto tr_handle_get_interface; 4283 case UR_GET_STATUS: 4284 goto tr_handle_get_iface_status; 4285 default: 4286 goto tr_stalled; 4287 } 4288 break; 4289 4290 case UT_WRITE_CLASS_INTERFACE: 4291 case UT_WRITE_VENDOR_INTERFACE: 4292 /* XXX forward */ 4293 break; 4294 4295 case UT_READ_CLASS_INTERFACE: 4296 case UT_READ_VENDOR_INTERFACE: 4297 /* XXX forward */ 4298 break; 4299 4300 case UT_WRITE_CLASS_DEVICE: 4301 switch (req->bRequest) { 4302 case UR_CLEAR_FEATURE: 4303 goto tr_valid; 4304 case UR_SET_DESCRIPTOR: 4305 case UR_SET_FEATURE: 4306 break; 4307 default: 4308 goto tr_stalled; 4309 } 4310 break; 4311 4312 case UT_WRITE_CLASS_OTHER: 4313 switch (req->bRequest) { 4314 case UR_CLEAR_FEATURE: 4315 goto tr_handle_clear_port_feature; 4316 case UR_SET_FEATURE: 4317 goto tr_handle_set_port_feature; 4318 case UR_CLEAR_TT_BUFFER: 4319 case UR_RESET_TT: 4320 case UR_STOP_TT: 4321 goto tr_valid; 4322 4323 default: 4324 goto tr_stalled; 4325 } 4326 break; 4327 4328 case UT_READ_CLASS_OTHER: 4329 switch (req->bRequest) { 4330 case UR_GET_TT_STATE: 4331 goto tr_handle_get_tt_state; 4332 case UR_GET_STATUS: 4333 goto tr_handle_get_port_status; 4334 default: 4335 goto tr_stalled; 4336 } 4337 break; 4338 4339 case UT_READ_CLASS_DEVICE: 4340 switch (req->bRequest) { 4341 case UR_GET_DESCRIPTOR: 4342 goto tr_handle_get_class_descriptor; 4343 case UR_GET_STATUS: 4344 goto tr_handle_get_class_status; 4345 4346 default: 4347 goto tr_stalled; 4348 } 4349 break; 4350 default: 4351 goto tr_stalled; 4352 } 4353 goto tr_valid; 4354 4355 tr_handle_get_descriptor: 4356 switch (value >> 8) { 4357 case UDESC_DEVICE: 4358 if (value & 0xff) { 4359 goto tr_stalled; 4360 } 4361 len = sizeof(dwc_otg_devd); 4362 ptr = (const void *)&dwc_otg_devd; 4363 goto tr_valid; 4364 case UDESC_CONFIG: 4365 if (value & 0xff) { 4366 goto tr_stalled; 4367 } 4368 len = sizeof(dwc_otg_confd); 4369 ptr = (const void *)&dwc_otg_confd; 4370 goto tr_valid; 4371 case UDESC_STRING: 4372 switch (value & 0xff) { 4373 case 0: /* Language table */ 4374 len = sizeof(usb_string_lang_en); 4375 ptr = (const void *)&usb_string_lang_en; 4376 goto tr_valid; 4377 4378 case 1: /* Vendor */ 4379 len = sizeof(dwc_otg_vendor); 4380 ptr = (const void *)&dwc_otg_vendor; 4381 goto tr_valid; 4382 4383 case 2: /* Product */ 4384 len = sizeof(dwc_otg_product); 4385 ptr = (const void *)&dwc_otg_product; 4386 goto tr_valid; 4387 default: 4388 break; 4389 } 4390 break; 4391 default: 4392 goto tr_stalled; 4393 } 4394 goto tr_stalled; 4395 4396 tr_handle_get_config: 4397 len = 1; 4398 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4399 goto tr_valid; 4400 4401 tr_handle_get_status: 4402 len = 2; 4403 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4404 goto tr_valid; 4405 4406 tr_handle_set_address: 4407 if (value & 0xFF00) { 4408 goto tr_stalled; 4409 } 4410 sc->sc_rt_addr = value; 4411 goto tr_valid; 4412 4413 tr_handle_set_config: 4414 if (value >= 2) { 4415 goto tr_stalled; 4416 } 4417 sc->sc_conf = value; 4418 goto tr_valid; 4419 4420 tr_handle_get_interface: 4421 len = 1; 4422 sc->sc_hub_temp.wValue[0] = 0; 4423 goto tr_valid; 4424 4425 tr_handle_get_tt_state: 4426 tr_handle_get_class_status: 4427 tr_handle_get_iface_status: 4428 tr_handle_get_ep_status: 4429 len = 2; 4430 USETW(sc->sc_hub_temp.wValue, 0); 4431 goto tr_valid; 4432 4433 tr_handle_set_halt: 4434 tr_handle_set_interface: 4435 tr_handle_set_wakeup: 4436 tr_handle_clear_wakeup: 4437 tr_handle_clear_halt: 4438 goto tr_valid; 4439 4440 tr_handle_clear_port_feature: 4441 if (index != 1) 4442 goto tr_stalled; 4443 4444 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4445 4446 switch (value) { 4447 case UHF_PORT_SUSPEND: 4448 dwc_otg_wakeup_peer(sc); 4449 break; 4450 4451 case UHF_PORT_ENABLE: 4452 if (sc->sc_flags.status_device_mode == 0) { 4453 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4454 sc->sc_hprt_val | HPRT_PRTENA); 4455 } 4456 sc->sc_flags.port_enabled = 0; 4457 break; 4458 4459 case UHF_C_PORT_RESET: 4460 sc->sc_flags.change_reset = 0; 4461 break; 4462 4463 case UHF_C_PORT_ENABLE: 4464 sc->sc_flags.change_enabled = 0; 4465 break; 4466 4467 case UHF_C_PORT_OVER_CURRENT: 4468 sc->sc_flags.change_over_current = 0; 4469 break; 4470 4471 case UHF_PORT_TEST: 4472 case UHF_PORT_INDICATOR: 4473 /* nops */ 4474 break; 4475 4476 case UHF_PORT_POWER: 4477 sc->sc_flags.port_powered = 0; 4478 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4479 sc->sc_hprt_val = 0; 4480 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4481 } 4482 dwc_otg_pull_down(sc); 4483 dwc_otg_clocks_off(sc); 4484 break; 4485 4486 case UHF_C_PORT_CONNECTION: 4487 /* clear connect change flag */ 4488 sc->sc_flags.change_connect = 0; 4489 break; 4490 4491 case UHF_C_PORT_SUSPEND: 4492 sc->sc_flags.change_suspend = 0; 4493 break; 4494 4495 default: 4496 err = USB_ERR_IOERROR; 4497 goto done; 4498 } 4499 goto tr_valid; 4500 4501 tr_handle_set_port_feature: 4502 if (index != 1) { 4503 goto tr_stalled; 4504 } 4505 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4506 4507 switch (value) { 4508 case UHF_PORT_ENABLE: 4509 break; 4510 4511 case UHF_PORT_SUSPEND: 4512 if (sc->sc_flags.status_device_mode == 0) { 4513 /* set suspend BIT */ 4514 sc->sc_hprt_val |= HPRT_PRTSUSP; 4515 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4516 4517 /* generate HUB suspend event */ 4518 dwc_otg_suspend_irq(sc); 4519 } 4520 break; 4521 4522 case UHF_PORT_RESET: 4523 if (sc->sc_flags.status_device_mode == 0) { 4524 4525 DPRINTF("PORT RESET\n"); 4526 4527 /* enable PORT reset */ 4528 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4529 4530 /* Wait 62.5ms for reset to complete */ 4531 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4532 4533 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4534 4535 /* Wait 62.5ms for reset to complete */ 4536 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4537 4538 /* reset FIFOs */ 4539 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4540 4541 sc->sc_flags.change_reset = 1; 4542 } else { 4543 err = USB_ERR_IOERROR; 4544 } 4545 break; 4546 4547 case UHF_PORT_TEST: 4548 case UHF_PORT_INDICATOR: 4549 /* nops */ 4550 break; 4551 case UHF_PORT_POWER: 4552 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4553 sc->sc_hprt_val |= HPRT_PRTPWR; 4554 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4555 } 4556 sc->sc_flags.port_powered = 1; 4557 break; 4558 default: 4559 err = USB_ERR_IOERROR; 4560 goto done; 4561 } 4562 goto tr_valid; 4563 4564 tr_handle_get_port_status: 4565 4566 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4567 4568 if (index != 1) 4569 goto tr_stalled; 4570 4571 if (sc->sc_flags.status_vbus) 4572 dwc_otg_clocks_on(sc); 4573 else 4574 dwc_otg_clocks_off(sc); 4575 4576 /* Select Device Side Mode */ 4577 4578 if (sc->sc_flags.status_device_mode) { 4579 value = UPS_PORT_MODE_DEVICE; 4580 dwc_otg_timer_stop(sc); 4581 } else { 4582 value = 0; 4583 dwc_otg_timer_start(sc); 4584 } 4585 4586 if (sc->sc_flags.status_high_speed) 4587 value |= UPS_HIGH_SPEED; 4588 else if (sc->sc_flags.status_low_speed) 4589 value |= UPS_LOW_SPEED; 4590 4591 if (sc->sc_flags.port_powered) 4592 value |= UPS_PORT_POWER; 4593 4594 if (sc->sc_flags.port_enabled) 4595 value |= UPS_PORT_ENABLED; 4596 4597 if (sc->sc_flags.port_over_current) 4598 value |= UPS_OVERCURRENT_INDICATOR; 4599 4600 if (sc->sc_flags.status_vbus && 4601 sc->sc_flags.status_bus_reset) 4602 value |= UPS_CURRENT_CONNECT_STATUS; 4603 4604 if (sc->sc_flags.status_suspend) 4605 value |= UPS_SUSPEND; 4606 4607 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4608 4609 value = 0; 4610 4611 if (sc->sc_flags.change_connect) 4612 value |= UPS_C_CONNECT_STATUS; 4613 if (sc->sc_flags.change_suspend) 4614 value |= UPS_C_SUSPEND; 4615 if (sc->sc_flags.change_reset) 4616 value |= UPS_C_PORT_RESET; 4617 if (sc->sc_flags.change_over_current) 4618 value |= UPS_C_OVERCURRENT_INDICATOR; 4619 4620 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4621 len = sizeof(sc->sc_hub_temp.ps); 4622 goto tr_valid; 4623 4624 tr_handle_get_class_descriptor: 4625 if (value & 0xFF) { 4626 goto tr_stalled; 4627 } 4628 ptr = (const void *)&dwc_otg_hubd; 4629 len = sizeof(dwc_otg_hubd); 4630 goto tr_valid; 4631 4632 tr_stalled: 4633 err = USB_ERR_STALLED; 4634 tr_valid: 4635 done: 4636 *plength = len; 4637 *pptr = ptr; 4638 return (err); 4639 } 4640 4641 static void 4642 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4643 { 4644 struct usb_xfer *xfer; 4645 void *last_obj; 4646 uint32_t ntd; 4647 uint32_t n; 4648 uint8_t ep_no; 4649 uint8_t ep_type; 4650 4651 xfer = parm->curr_xfer; 4652 4653 /* 4654 * NOTE: This driver does not use any of the parameters that 4655 * are computed from the following values. Just set some 4656 * reasonable dummies: 4657 */ 4658 parm->hc_max_packet_size = 0x500; 4659 parm->hc_max_packet_count = 3; 4660 parm->hc_max_frame_size = 3 * 0x500; 4661 4662 usbd_transfer_setup_sub(parm); 4663 4664 /* 4665 * compute maximum number of TDs 4666 */ 4667 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4668 4669 if (ep_type == UE_CONTROL) { 4670 4671 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4672 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4673 } else { 4674 4675 ntd = xfer->nframes + 1 /* SYNC */ ; 4676 } 4677 4678 /* 4679 * check if "usbd_transfer_setup_sub" set an error 4680 */ 4681 if (parm->err) 4682 return; 4683 4684 /* 4685 * allocate transfer descriptors 4686 */ 4687 last_obj = NULL; 4688 4689 ep_no = xfer->endpointno & UE_ADDR; 4690 4691 /* 4692 * Check for a valid endpoint profile in USB device mode: 4693 */ 4694 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4695 const struct usb_hw_ep_profile *pf; 4696 4697 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4698 4699 if (pf == NULL) { 4700 /* should not happen */ 4701 parm->err = USB_ERR_INVAL; 4702 return; 4703 } 4704 } 4705 4706 /* align data */ 4707 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4708 4709 for (n = 0; n != ntd; n++) { 4710 4711 struct dwc_otg_td *td; 4712 4713 if (parm->buf) { 4714 4715 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4716 4717 /* compute shared bandwidth resource index for TT */ 4718 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4719 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4720 td->tt_index = parm->udev->device_index; 4721 else 4722 td->tt_index = parm->udev->parent_hs_hub->device_index; 4723 } else { 4724 td->tt_index = parm->udev->device_index; 4725 } 4726 4727 /* init TD */ 4728 td->max_packet_size = xfer->max_packet_size; 4729 td->max_packet_count = xfer->max_packet_count; 4730 td->ep_no = ep_no; 4731 td->ep_type = ep_type; 4732 td->obj_next = last_obj; 4733 4734 last_obj = td; 4735 } 4736 parm->size[0] += sizeof(*td); 4737 } 4738 4739 xfer->td_start[0] = last_obj; 4740 } 4741 4742 static void 4743 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4744 { 4745 return; 4746 } 4747 4748 static void 4749 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4750 struct usb_endpoint *ep) 4751 { 4752 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4753 4754 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4755 ep, udev->address, 4756 edesc->bEndpointAddress, udev->flags.usb_mode, 4757 sc->sc_rt_addr, udev->device_index); 4758 4759 if (udev->device_index != sc->sc_rt_addr) { 4760 4761 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4762 if (udev->speed != USB_SPEED_FULL && 4763 udev->speed != USB_SPEED_HIGH) { 4764 /* not supported */ 4765 return; 4766 } 4767 } else { 4768 if (udev->speed == USB_SPEED_HIGH) { 4769 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4770 /* high bandwidth endpoint - not tested */ 4771 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4772 return; 4773 } 4774 } 4775 } 4776 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4777 ep->methods = &dwc_otg_device_isoc_methods; 4778 else 4779 ep->methods = &dwc_otg_device_non_isoc_methods; 4780 } 4781 } 4782 4783 static void 4784 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4785 { 4786 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4787 4788 switch (state) { 4789 case USB_HW_POWER_SUSPEND: 4790 dwc_otg_suspend(sc); 4791 break; 4792 case USB_HW_POWER_SHUTDOWN: 4793 dwc_otg_uninit(sc); 4794 break; 4795 case USB_HW_POWER_RESUME: 4796 dwc_otg_resume(sc); 4797 break; 4798 default: 4799 break; 4800 } 4801 } 4802 4803 static void 4804 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4805 { 4806 /* DMA delay - wait until any use of memory is finished */ 4807 *pus = (2125); /* microseconds */ 4808 } 4809 4810 static void 4811 dwc_otg_device_resume(struct usb_device *udev) 4812 { 4813 DPRINTF("\n"); 4814 4815 /* poll all transfers again to restart resumed ones */ 4816 dwc_otg_do_poll(udev->bus); 4817 } 4818 4819 static void 4820 dwc_otg_device_suspend(struct usb_device *udev) 4821 { 4822 DPRINTF("\n"); 4823 } 4824 4825 static const struct usb_bus_methods dwc_otg_bus_methods = 4826 { 4827 .endpoint_init = &dwc_otg_ep_init, 4828 .xfer_setup = &dwc_otg_xfer_setup, 4829 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4830 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4831 .xfer_stall = &dwc_otg_xfer_stall, 4832 .set_stall = &dwc_otg_set_stall, 4833 .clear_stall = &dwc_otg_clear_stall, 4834 .roothub_exec = &dwc_otg_roothub_exec, 4835 .xfer_poll = &dwc_otg_do_poll, 4836 .device_state_change = &dwc_otg_device_state_change, 4837 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4838 .get_dma_delay = &dwc_otg_get_dma_delay, 4839 .device_resume = &dwc_otg_device_resume, 4840 .device_suspend = &dwc_otg_device_suspend, 4841 }; 4842