1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_ENABLED \ 97 (GINTMSK_ENUMDONEMSK | \ 98 GINTMSK_USBRSTMSK | \ 99 GINTMSK_USBSUSPMSK | \ 100 GINTMSK_IEPINTMSK | \ 101 GINTMSK_SESSREQINTMSK | \ 102 GINTMSK_RXFLVLMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTMSK_OTGINTMSK | \ 105 GINTMSK_PRTINTMSK) 106 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 108 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 109 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 110 GINTSTS_SESSREQINT) 111 112 #define DWC_OTG_PHY_ULPI 0 113 #define DWC_OTG_PHY_HSIC 1 114 #define DWC_OTG_PHY_INTERNAL 2 115 116 #ifndef DWC_OTG_PHY_DEFAULT 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 118 #endif 119 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 121 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 124 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 125 126 #ifdef USB_DEBUG 127 static int dwc_otg_debug; 128 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 130 &dwc_otg_debug, 0, "DWC OTG debug level"); 131 #endif 132 133 #define DWC_OTG_INTR_ENDPT 1 134 135 /* prototypes */ 136 137 static const struct usb_bus_methods dwc_otg_bus_methods; 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 140 141 static dwc_otg_cmd_t dwc_otg_setup_rx; 142 static dwc_otg_cmd_t dwc_otg_data_rx; 143 static dwc_otg_cmd_t dwc_otg_data_tx; 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 145 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_tx; 148 static dwc_otg_cmd_t dwc_otg_host_data_rx; 149 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 151 static void dwc_otg_do_poll(struct usb_bus *); 152 static void dwc_otg_standard_done(struct usb_xfer *); 153 static void dwc_otg_root_intr(struct dwc_otg_softc *); 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static void 184 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 185 uint32_t offset, uint32_t fifo, uint32_t count) 186 { 187 uint32_t temp; 188 189 /* round down length to nearest 4-bytes */ 190 temp = count & ~3; 191 192 /* check if we can write the data directly */ 193 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 194 struct usb_page_search buf_res; 195 196 /* pre-subtract length */ 197 count -= temp; 198 199 /* iterate buffer list */ 200 do { 201 /* get current buffer pointer */ 202 usbd_get_page(pc, offset, &buf_res); 203 204 if (buf_res.length > temp) 205 buf_res.length = temp; 206 207 /* transfer data into FIFO */ 208 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 209 fifo, buf_res.buffer, buf_res.length / 4); 210 211 offset += buf_res.length; 212 fifo += buf_res.length; 213 temp -= buf_res.length; 214 } while (temp != 0); 215 } 216 217 /* check for remainder */ 218 if (count != 0) { 219 /* clear topmost word before copy */ 220 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 221 222 /* copy out data */ 223 usbd_copy_out(pc, offset, 224 sc->sc_bounce_buffer, count); 225 226 /* transfer data into FIFO */ 227 bus_space_write_region_4(sc->sc_io_tag, 228 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 229 (count + 3) / 4); 230 } 231 } 232 233 static void 234 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 235 uint32_t offset, uint32_t count) 236 { 237 uint32_t temp; 238 239 /* round down length to nearest 4-bytes */ 240 temp = count & ~3; 241 242 /* check if we can read the data directly */ 243 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 244 struct usb_page_search buf_res; 245 246 /* pre-subtract length */ 247 count -= temp; 248 249 /* iterate buffer list */ 250 do { 251 /* get current buffer pointer */ 252 usbd_get_page(pc, offset, &buf_res); 253 254 if (buf_res.length > temp) 255 buf_res.length = temp; 256 257 /* transfer data from FIFO */ 258 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 259 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 260 261 offset += buf_res.length; 262 sc->sc_current_rx_fifo += buf_res.length; 263 sc->sc_current_rx_bytes -= buf_res.length; 264 temp -= buf_res.length; 265 } while (temp != 0); 266 } 267 268 /* check for remainder */ 269 if (count != 0) { 270 /* read data into bounce buffer */ 271 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 272 sc->sc_current_rx_fifo, 273 sc->sc_bounce_buffer, (count + 3) / 4); 274 275 /* store data into proper buffer */ 276 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 277 278 /* round length up to nearest 4 bytes */ 279 count = (count + 3) & ~3; 280 281 /* update counters */ 282 sc->sc_current_rx_bytes -= count; 283 sc->sc_current_rx_fifo += count; 284 } 285 } 286 287 static void 288 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 289 { 290 uint32_t temp; 291 292 /* reset FIFO */ 293 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 294 295 /* wait for reset to complete */ 296 for (temp = 0; temp != 16; temp++) { 297 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 298 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 299 break; 300 } 301 } 302 303 static int 304 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 305 { 306 struct dwc_otg_profile *pf; 307 uint32_t fifo_size; 308 uint32_t fifo_regs; 309 uint32_t tx_start; 310 uint8_t x; 311 312 fifo_size = sc->sc_fifo_size; 313 314 /* 315 * NOTE: Reserved fixed size area at end of RAM, which must 316 * not be allocated to the FIFOs: 317 */ 318 fifo_regs = 4 * 16; 319 320 if (fifo_size < fifo_regs) { 321 DPRINTF("Too little FIFO\n"); 322 return (EINVAL); 323 } 324 325 /* subtract FIFO regs from total once */ 326 fifo_size -= fifo_regs; 327 328 /* split equally for IN and OUT */ 329 fifo_size /= 2; 330 331 /* Align to 4 bytes boundary (refer to PGM) */ 332 fifo_size &= ~3; 333 334 /* set global receive FIFO size */ 335 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 336 337 tx_start = fifo_size; 338 339 if (fifo_size < 64) { 340 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 341 return (EINVAL); 342 } 343 344 if (mode == DWC_MODE_HOST) { 345 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* split equally for periodic and non-periodic */ 350 fifo_size /= 2; 351 352 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 353 354 /* align to 4 bytes boundary */ 355 fifo_size &= ~3; 356 357 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 358 ((fifo_size / 4) << 16) | 359 (tx_start / 4)); 360 361 tx_start += fifo_size; 362 363 for (x = 0; x != sc->sc_host_ch_max; x++) { 364 /* enable all host interrupts */ 365 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 366 HCINT_DEFAULT_MASK); 367 } 368 369 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 370 ((fifo_size / 4) << 16) | 371 (tx_start / 4)); 372 373 /* reset host channel state */ 374 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 375 376 /* enable all host channel interrupts */ 377 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 378 (1U << sc->sc_host_ch_max) - 1U); 379 } 380 381 if (mode == DWC_MODE_DEVICE) { 382 383 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 384 (0x10 << 16) | (tx_start / 4)); 385 fifo_size -= 0x40; 386 tx_start += 0x40; 387 388 /* setup control endpoint profile */ 389 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 390 391 /* reset active endpoints */ 392 sc->sc_active_rx_ep = 1; 393 394 for (x = 1; x != sc->sc_dev_ep_max; x++) { 395 396 pf = sc->sc_hw_ep_profile + x; 397 398 pf->usb.max_out_frame_size = 1024 * 3; 399 pf->usb.is_simplex = 0; /* assume duplex */ 400 pf->usb.support_bulk = 1; 401 pf->usb.support_interrupt = 1; 402 pf->usb.support_isochronous = 1; 403 pf->usb.support_out = 1; 404 405 if (x < sc->sc_dev_in_ep_max) { 406 uint32_t limit; 407 408 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 409 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 410 DWC_OTG_TX_MAX_FIFO_SIZE); 411 412 /* see if there is enough FIFO space */ 413 if (limit <= fifo_size) { 414 pf->max_buffer = limit; 415 pf->usb.support_in = 1; 416 } else { 417 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 418 if (limit <= fifo_size) { 419 pf->usb.support_in = 1; 420 } else { 421 pf->usb.is_simplex = 1; 422 limit = 0; 423 } 424 } 425 /* set FIFO size */ 426 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 427 ((limit / 4) << 16) | (tx_start / 4)); 428 tx_start += limit; 429 fifo_size -= limit; 430 pf->usb.max_in_frame_size = limit; 431 } else { 432 pf->usb.is_simplex = 1; 433 } 434 435 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 436 pf->usb.max_in_frame_size, 437 pf->usb.max_out_frame_size); 438 } 439 } 440 441 /* reset RX FIFO */ 442 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 443 444 if (mode != DWC_MODE_OTG) { 445 /* reset all TX FIFOs */ 446 dwc_otg_tx_fifo_reset(sc, 447 GRSTCTL_TXFIFO(0x10) | 448 GRSTCTL_TXFFLSH); 449 } else { 450 /* reset active endpoints */ 451 sc->sc_active_rx_ep = 0; 452 453 /* reset host channel state */ 454 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 455 } 456 return (0); 457 } 458 459 static void 460 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 461 { 462 463 /* 464 * Disabled until further. Assuming that the register is already 465 * programmed correctly by the boot loader. 466 */ 467 #if 0 468 uint32_t temp; 469 470 /* setup HOST frame interval register, based on existing value */ 471 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 472 if (temp >= 10000) 473 temp /= 1000; 474 else 475 temp /= 125; 476 477 /* figure out nearest X-tal value */ 478 if (temp >= 54) 479 temp = 60; /* MHz */ 480 else if (temp >= 39) 481 temp = 48; /* MHz */ 482 else 483 temp = 30; /* MHz */ 484 485 if (sc->sc_flags.status_high_speed) 486 temp *= 125; 487 else 488 temp *= 1000; 489 490 DPRINTF("HFIR=0x%08x\n", temp); 491 492 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 493 #endif 494 } 495 496 static void 497 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 498 { 499 if (sc->sc_flags.clocks_off && 500 sc->sc_flags.port_powered) { 501 502 DPRINTFN(5, "\n"); 503 504 /* TODO - platform specific */ 505 506 sc->sc_flags.clocks_off = 0; 507 } 508 } 509 510 static void 511 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 512 { 513 if (!sc->sc_flags.clocks_off) { 514 515 DPRINTFN(5, "\n"); 516 517 /* TODO - platform specific */ 518 519 sc->sc_flags.clocks_off = 1; 520 } 521 } 522 523 static void 524 dwc_otg_pull_up(struct dwc_otg_softc *sc) 525 { 526 uint32_t temp; 527 528 /* pullup D+, if possible */ 529 530 if (!sc->sc_flags.d_pulled_up && 531 sc->sc_flags.port_powered) { 532 sc->sc_flags.d_pulled_up = 1; 533 534 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 535 temp &= ~DCTL_SFTDISCON; 536 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 537 } 538 } 539 540 static void 541 dwc_otg_pull_down(struct dwc_otg_softc *sc) 542 { 543 uint32_t temp; 544 545 /* pulldown D+, if possible */ 546 547 if (sc->sc_flags.d_pulled_up) { 548 sc->sc_flags.d_pulled_up = 0; 549 550 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 551 temp |= DCTL_SFTDISCON; 552 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 553 } 554 } 555 556 static void 557 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 558 { 559 /* In device mode we don't use the SOF interrupt */ 560 if (sc->sc_flags.status_device_mode != 0) 561 return; 562 /* Ensure the SOF interrupt is not disabled */ 563 sc->sc_needsof = 1; 564 /* Check if the SOF interrupt is already enabled */ 565 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 566 return; 567 sc->sc_irq_mask |= GINTMSK_SOFMSK; 568 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 569 } 570 571 static void 572 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 573 { 574 if (sc->sc_flags.status_suspend) { 575 /* update status bits */ 576 sc->sc_flags.status_suspend = 0; 577 sc->sc_flags.change_suspend = 1; 578 579 if (sc->sc_flags.status_device_mode) { 580 /* 581 * Disable resume interrupt and enable suspend 582 * interrupt: 583 */ 584 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 585 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 586 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 587 } 588 589 /* complete root HUB interrupt endpoint */ 590 dwc_otg_root_intr(sc); 591 } 592 } 593 594 static void 595 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 596 { 597 if (!sc->sc_flags.status_suspend) { 598 /* update status bits */ 599 sc->sc_flags.status_suspend = 1; 600 sc->sc_flags.change_suspend = 1; 601 602 if (sc->sc_flags.status_device_mode) { 603 /* 604 * Disable suspend interrupt and enable resume 605 * interrupt: 606 */ 607 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 608 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 609 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 610 } 611 612 /* complete root HUB interrupt endpoint */ 613 dwc_otg_root_intr(sc); 614 } 615 } 616 617 static void 618 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 619 { 620 if (!sc->sc_flags.status_suspend) 621 return; 622 623 DPRINTFN(5, "Remote wakeup\n"); 624 625 if (sc->sc_flags.status_device_mode) { 626 uint32_t temp; 627 628 /* enable remote wakeup signalling */ 629 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 630 temp |= DCTL_RMTWKUPSIG; 631 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 632 633 /* Wait 8ms for remote wakeup to complete. */ 634 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 635 636 temp &= ~DCTL_RMTWKUPSIG; 637 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 638 } else { 639 /* enable USB port */ 640 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 641 642 /* wait 10ms */ 643 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 644 645 /* resume port */ 646 sc->sc_hprt_val |= HPRT_PRTRES; 647 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 648 649 /* Wait 100ms for resume signalling to complete. */ 650 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 651 652 /* clear suspend and resume */ 653 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 654 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 655 656 /* Wait 4ms */ 657 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 658 } 659 660 /* need to fake resume IRQ */ 661 dwc_otg_resume_irq(sc); 662 } 663 664 static void 665 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 666 { 667 uint32_t temp; 668 669 DPRINTFN(5, "addr=%d\n", addr); 670 671 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 672 temp &= ~DCFG_DEVADDR_SET(0x7F); 673 temp |= DCFG_DEVADDR_SET(addr); 674 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 675 } 676 677 static void 678 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 679 { 680 DPRINTFN(5, "RX status clear\n"); 681 682 /* enable RX FIFO level interrupt */ 683 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 684 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 685 686 if (sc->sc_current_rx_bytes != 0) { 687 /* need to dump remaining data */ 688 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 689 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 690 sc->sc_current_rx_bytes / 4); 691 /* clear number of active bytes to receive */ 692 sc->sc_current_rx_bytes = 0; 693 } 694 /* clear cached status */ 695 sc->sc_last_rx_status = 0; 696 } 697 698 static void 699 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 700 { 701 uint32_t hcint; 702 703 /* clear all pending interrupts */ 704 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 705 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 706 707 /* clear buffered interrupts */ 708 sc->sc_chan_state[x].hcint = 0; 709 } 710 711 static uint8_t 712 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 713 { 714 uint32_t temp; 715 716 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 717 718 if (td->ep_type == UE_ISOCHRONOUS) { 719 /* 720 * NOTE: USB INTERRUPT transactions are executed like 721 * USB CONTROL transactions! See the setup standard 722 * chain function for more information. 723 */ 724 if (!(temp & GINTSTS_PTXFEMP)) { 725 DPRINTF("Periodic TX FIFO is not empty\n"); 726 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 727 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 728 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 729 } 730 return (1); /* busy */ 731 } 732 } else { 733 if (!(temp & GINTSTS_NPTXFEMP)) { 734 DPRINTF("Non-periodic TX FIFO is not empty\n"); 735 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 736 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 737 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 738 } 739 return (1); /* busy */ 740 } 741 } 742 return (0); /* ready for transmit */ 743 } 744 745 static uint8_t 746 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 747 struct dwc_otg_td *td, uint8_t is_out) 748 { 749 uint8_t x; 750 uint8_t y; 751 uint8_t z; 752 753 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 754 return (0); /* already allocated */ 755 756 /* check if device is suspended */ 757 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 758 return (1); /* busy - cannot transfer data */ 759 760 /* compute needed TX FIFO size */ 761 if (is_out != 0) { 762 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 763 return (1); /* busy - cannot transfer data */ 764 } 765 z = td->max_packet_count; 766 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 767 /* check if channel is allocated */ 768 if (sc->sc_chan_state[x].allocated != 0) 769 continue; 770 /* check if channel is still enabled */ 771 if (sc->sc_chan_state[x].wait_halted != 0) 772 continue; 773 /* store channel number */ 774 td->channel[y++] = x; 775 /* check if we got all channels */ 776 if (y == z) 777 break; 778 } 779 if (y != z) { 780 /* reset channel variable */ 781 td->channel[0] = DWC_OTG_MAX_CHANNELS; 782 td->channel[1] = DWC_OTG_MAX_CHANNELS; 783 td->channel[2] = DWC_OTG_MAX_CHANNELS; 784 /* wait a bit */ 785 dwc_otg_enable_sof_irq(sc); 786 return (1); /* busy - not enough channels */ 787 } 788 789 for (y = 0; y != z; y++) { 790 x = td->channel[y]; 791 792 /* set allocated */ 793 sc->sc_chan_state[x].allocated = 1; 794 795 /* set wait halted */ 796 sc->sc_chan_state[x].wait_halted = 1; 797 798 /* clear interrupts */ 799 dwc_otg_clear_hcint(sc, x); 800 801 DPRINTF("CH=%d HCCHAR=0x%08x " 802 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 803 804 /* set active channel */ 805 sc->sc_active_rx_ep |= (1 << x); 806 } 807 return (0); /* allocated */ 808 } 809 810 static void 811 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 812 { 813 uint32_t hcchar; 814 uint8_t x; 815 816 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 817 return; /* already freed */ 818 819 /* free channel */ 820 x = td->channel[index]; 821 td->channel[index] = DWC_OTG_MAX_CHANNELS; 822 823 DPRINTF("CH=%d\n", x); 824 825 /* 826 * We need to let programmed host channels run till complete 827 * else the host channel will stop functioning. 828 */ 829 sc->sc_chan_state[x].allocated = 0; 830 831 /* ack any pending messages */ 832 if (sc->sc_last_rx_status != 0 && 833 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 834 dwc_otg_common_rx_ack(sc); 835 } 836 837 /* clear active channel */ 838 sc->sc_active_rx_ep &= ~(1 << x); 839 840 /* check if already halted */ 841 if (sc->sc_chan_state[x].wait_halted == 0) 842 return; 843 844 /* disable host channel */ 845 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 846 if (hcchar & HCCHAR_CHENA) { 847 DPRINTF("Halting channel %d\n", x); 848 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 849 hcchar | HCCHAR_CHDIS); 850 /* don't write HCCHAR until the channel is halted */ 851 } else { 852 sc->sc_chan_state[x].wait_halted = 0; 853 } 854 } 855 856 static void 857 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 858 { 859 uint8_t x; 860 for (x = 0; x != td->max_packet_count; x++) 861 dwc_otg_host_channel_free_sub(sc, td, x); 862 } 863 864 static void 865 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 866 { 867 uint8_t x; 868 /* dump any pending messages */ 869 if (sc->sc_last_rx_status == 0) 870 return; 871 for (x = 0; x != td->max_packet_count; x++) { 872 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 873 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 874 continue; 875 dwc_otg_common_rx_ack(sc); 876 break; 877 } 878 } 879 880 static uint8_t 881 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 882 { 883 struct usb_device_request req __aligned(4); 884 uint32_t hcint; 885 uint32_t hcchar; 886 uint8_t delta; 887 888 dwc_otg_host_dump_rx(sc, td); 889 890 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 891 hcint = sc->sc_chan_state[td->channel[0]].hcint; 892 893 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 894 td->channel[0], td->state, hcint, 895 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 896 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 897 } else { 898 hcint = 0; 899 goto check_state; 900 } 901 902 if (hcint & (HCINT_RETRY | 903 HCINT_ACK | HCINT_NYET)) { 904 /* give success bits priority over failure bits */ 905 } else if (hcint & HCINT_STALL) { 906 DPRINTF("CH=%d STALL\n", td->channel[0]); 907 td->error_stall = 1; 908 td->error_any = 1; 909 goto complete; 910 } else if (hcint & HCINT_ERRORS) { 911 DPRINTF("CH=%d ERROR\n", td->channel[0]); 912 td->errcnt++; 913 if (td->hcsplt != 0 || td->errcnt >= 3) { 914 td->error_any = 1; 915 goto complete; 916 } 917 } 918 919 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 920 HCINT_ACK | HCINT_NYET)) { 921 if (!(hcint & HCINT_ERRORS)) 922 td->errcnt = 0; 923 } 924 925 check_state: 926 switch (td->state) { 927 case DWC_CHAN_ST_START: 928 goto send_pkt; 929 930 case DWC_CHAN_ST_WAIT_ANE: 931 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 932 td->did_nak = 1; 933 td->tt_scheduled = 0; 934 goto send_pkt; 935 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 936 td->offset += td->tx_bytes; 937 td->remainder -= td->tx_bytes; 938 td->toggle = 1; 939 td->tt_scheduled = 0; 940 goto complete; 941 } 942 break; 943 944 case DWC_CHAN_ST_WAIT_S_ANE: 945 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 946 td->did_nak = 1; 947 td->tt_scheduled = 0; 948 goto send_pkt; 949 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 950 goto send_cpkt; 951 } 952 break; 953 954 case DWC_CHAN_ST_WAIT_C_ANE: 955 if (hcint & HCINT_NYET) { 956 goto send_cpkt; 957 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 958 td->did_nak = 1; 959 td->tt_scheduled = 0; 960 goto send_pkt; 961 } else if (hcint & HCINT_ACK) { 962 td->offset += td->tx_bytes; 963 td->remainder -= td->tx_bytes; 964 td->toggle = 1; 965 goto complete; 966 } 967 break; 968 969 case DWC_CHAN_ST_WAIT_C_PKT: 970 goto send_cpkt; 971 972 default: 973 break; 974 } 975 goto busy; 976 977 send_pkt: 978 /* free existing channel, if any */ 979 dwc_otg_host_channel_free(sc, td); 980 981 if (sizeof(req) != td->remainder) { 982 td->error_any = 1; 983 goto complete; 984 } 985 986 if (td->hcsplt != 0) { 987 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 988 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 989 td->state = DWC_CHAN_ST_START; 990 goto busy; 991 } 992 delta = sc->sc_last_frame_num - td->tt_start_slot; 993 if (delta > 5) { 994 /* missed it */ 995 td->tt_scheduled = 0; 996 td->state = DWC_CHAN_ST_START; 997 goto busy; 998 } 999 } 1000 1001 /* allocate a new channel */ 1002 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1003 td->state = DWC_CHAN_ST_START; 1004 goto busy; 1005 } 1006 1007 if (td->hcsplt != 0) { 1008 td->hcsplt &= ~HCSPLT_COMPSPLT; 1009 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1010 } else { 1011 td->state = DWC_CHAN_ST_WAIT_ANE; 1012 } 1013 1014 /* copy out control request */ 1015 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1016 1017 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1018 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1019 (1 << HCTSIZ_PKTCNT_SHIFT) | 1020 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1021 1022 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1023 1024 hcchar = td->hcchar; 1025 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1026 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1027 1028 /* must enable channel before writing data to FIFO */ 1029 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1030 1031 /* transfer data into FIFO */ 1032 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1033 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1034 1035 /* wait until next slot before trying complete split */ 1036 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1037 1038 /* store number of bytes transmitted */ 1039 td->tx_bytes = sizeof(req); 1040 goto busy; 1041 1042 send_cpkt: 1043 /* free existing channel, if any */ 1044 dwc_otg_host_channel_free(sc, td); 1045 1046 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1047 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1048 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1049 goto busy; 1050 } 1051 delta = sc->sc_last_frame_num - td->tt_start_slot; 1052 if (delta > DWC_OTG_TT_SLOT_MAX) { 1053 /* we missed the service interval */ 1054 if (td->ep_type != UE_ISOCHRONOUS) 1055 td->error_any = 1; 1056 goto complete; 1057 } 1058 /* allocate a new channel */ 1059 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1060 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1061 goto busy; 1062 } 1063 1064 /* wait until next slot before trying complete split */ 1065 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1066 1067 td->hcsplt |= HCSPLT_COMPSPLT; 1068 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1069 1070 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1071 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1072 1073 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1074 1075 hcchar = td->hcchar; 1076 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1077 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1078 1079 /* must enable channel before writing data to FIFO */ 1080 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1081 1082 busy: 1083 return (1); /* busy */ 1084 1085 complete: 1086 dwc_otg_host_channel_free(sc, td); 1087 return (0); /* complete */ 1088 } 1089 1090 static uint8_t 1091 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1092 { 1093 struct usb_device_request req __aligned(4); 1094 uint32_t temp; 1095 uint16_t count; 1096 1097 /* check endpoint status */ 1098 1099 if (sc->sc_last_rx_status == 0) 1100 goto not_complete; 1101 1102 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1103 goto not_complete; 1104 1105 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1106 GRXSTSRD_STP_DATA) { 1107 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1108 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1109 /* release FIFO */ 1110 dwc_otg_common_rx_ack(sc); 1111 goto not_complete; 1112 } 1113 /* release FIFO */ 1114 dwc_otg_common_rx_ack(sc); 1115 return (0); /* complete */ 1116 } 1117 1118 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1119 GRXSTSRD_DPID_DATA0) { 1120 /* release FIFO */ 1121 dwc_otg_common_rx_ack(sc); 1122 goto not_complete; 1123 } 1124 1125 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1126 1127 /* clear did stall */ 1128 td->did_stall = 0; 1129 1130 /* get the packet byte count */ 1131 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1132 1133 if (count != sizeof(req)) { 1134 DPRINTFN(0, "Unsupported SETUP packet " 1135 "length, %d bytes\n", count); 1136 /* release FIFO */ 1137 dwc_otg_common_rx_ack(sc); 1138 goto not_complete; 1139 } 1140 1141 /* read FIFO */ 1142 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1143 1144 /* copy out control request */ 1145 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1146 1147 td->offset = sizeof(req); 1148 td->remainder = 0; 1149 1150 /* sneak peek the set address */ 1151 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1152 (req.bRequest == UR_SET_ADDRESS)) { 1153 /* must write address before ZLP */ 1154 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1155 } 1156 1157 /* don't send any data by default */ 1158 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1159 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1160 1161 /* reset IN endpoint buffer */ 1162 dwc_otg_tx_fifo_reset(sc, 1163 GRSTCTL_TXFIFO(0) | 1164 GRSTCTL_TXFFLSH); 1165 1166 /* acknowledge RX status */ 1167 dwc_otg_common_rx_ack(sc); 1168 td->did_stall = 1; 1169 1170 not_complete: 1171 /* abort any ongoing transfer, before enabling again */ 1172 if (!td->did_stall) { 1173 td->did_stall = 1; 1174 1175 DPRINTFN(5, "stalling IN and OUT direction\n"); 1176 1177 temp = sc->sc_out_ctl[0]; 1178 1179 /* set stall after enabling endpoint */ 1180 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1181 temp | DOEPCTL_STALL); 1182 1183 temp = sc->sc_in_ctl[0]; 1184 1185 /* set stall assuming endpoint is enabled */ 1186 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1187 temp | DIEPCTL_STALL); 1188 } 1189 return (1); /* not complete */ 1190 } 1191 1192 static uint8_t 1193 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1194 { 1195 uint8_t delta; 1196 1197 delta = sc->sc_tmr_val - td->tmr_val; 1198 if (delta >= 128) 1199 return (1); /* busy */ 1200 1201 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1202 1203 /* set toggle, if any */ 1204 if (td->set_toggle) { 1205 td->set_toggle = 0; 1206 td->toggle = 1; 1207 } 1208 return (0); 1209 } 1210 1211 static uint8_t 1212 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1213 { 1214 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1215 1216 if (td->ep_type == UE_ISOCHRONOUS) { 1217 /* non TT isochronous traffic */ 1218 if (frame_num & (td->tmr_res - 1)) 1219 goto busy; 1220 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1221 goto busy; 1222 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1223 td->toggle = 0; 1224 return (0); 1225 } else if (td->ep_type == UE_INTERRUPT) { 1226 if (!td->tt_scheduled) 1227 goto busy; 1228 td->tt_scheduled = 0; 1229 return (0); 1230 } else if (td->did_nak != 0) { 1231 /* check if we should pause sending queries for 125us */ 1232 if (td->tmr_res == frame_num) { 1233 /* wait a bit */ 1234 dwc_otg_enable_sof_irq(sc); 1235 goto busy; 1236 } 1237 } else if (td->set_toggle) { 1238 td->set_toggle = 0; 1239 td->toggle = 1; 1240 } 1241 /* query for data one more time */ 1242 td->tmr_res = frame_num; 1243 td->did_nak = 0; 1244 return (0); 1245 busy: 1246 return (1); 1247 } 1248 1249 static uint8_t 1250 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1251 uint8_t channel) 1252 { 1253 uint32_t count; 1254 1255 /* check endpoint status */ 1256 if (sc->sc_last_rx_status == 0) 1257 goto busy; 1258 1259 if (channel >= DWC_OTG_MAX_CHANNELS) 1260 goto busy; 1261 1262 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1263 goto busy; 1264 1265 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1266 case GRXSTSRH_IN_DATA: 1267 1268 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1269 (int)td->state, (int)sc->sc_last_rx_status); 1270 1271 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1272 /* 1273 * When using SPLIT transactions on interrupt 1274 * endpoints, sometimes data occurs twice. 1275 */ 1276 DPRINTF("Data already received\n"); 1277 break; 1278 } 1279 1280 /* get the packet byte count */ 1281 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1282 1283 /* check for ISOCHRONOUS endpoint */ 1284 if (td->ep_type == UE_ISOCHRONOUS) { 1285 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1286 GRXSTSRD_DPID_DATA0) { 1287 /* more data to be received */ 1288 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1289 } else { 1290 /* all data received */ 1291 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1292 /* verify the packet byte count */ 1293 if (count != td->remainder) { 1294 /* we have a short packet */ 1295 td->short_pkt = 1; 1296 td->got_short = 1; 1297 } 1298 } 1299 } else { 1300 /* verify the packet byte count */ 1301 if (count != td->max_packet_size) { 1302 if (count < td->max_packet_size) { 1303 /* we have a short packet */ 1304 td->short_pkt = 1; 1305 td->got_short = 1; 1306 } else { 1307 /* invalid USB packet */ 1308 td->error_any = 1; 1309 1310 /* release FIFO */ 1311 dwc_otg_common_rx_ack(sc); 1312 goto complete; 1313 } 1314 } 1315 td->toggle ^= 1; 1316 td->tt_scheduled = 0; 1317 } 1318 1319 /* verify the packet byte count */ 1320 if (count > td->remainder) { 1321 /* invalid USB packet */ 1322 td->error_any = 1; 1323 1324 /* release FIFO */ 1325 dwc_otg_common_rx_ack(sc); 1326 goto complete; 1327 } 1328 1329 /* read data from FIFO */ 1330 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1331 1332 td->remainder -= count; 1333 td->offset += count; 1334 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1335 break; 1336 default: 1337 break; 1338 } 1339 /* release FIFO */ 1340 dwc_otg_common_rx_ack(sc); 1341 busy: 1342 return (0); 1343 complete: 1344 return (1); 1345 } 1346 1347 static uint8_t 1348 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1349 { 1350 uint32_t hcint = 0; 1351 uint32_t hcchar; 1352 uint8_t delta; 1353 uint8_t channel; 1354 uint8_t x; 1355 1356 for (x = 0; x != td->max_packet_count; x++) { 1357 channel = td->channel[x]; 1358 if (channel >= DWC_OTG_MAX_CHANNELS) 1359 continue; 1360 hcint |= sc->sc_chan_state[channel].hcint; 1361 1362 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1363 channel, td->state, hcint, 1364 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1365 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1366 1367 /* check interrupt bits */ 1368 if (hcint & (HCINT_RETRY | 1369 HCINT_ACK | HCINT_NYET)) { 1370 /* give success bits priority over failure bits */ 1371 } else if (hcint & HCINT_STALL) { 1372 DPRINTF("CH=%d STALL\n", channel); 1373 td->error_stall = 1; 1374 td->error_any = 1; 1375 goto complete; 1376 } else if (hcint & HCINT_ERRORS) { 1377 DPRINTF("CH=%d ERROR\n", channel); 1378 td->errcnt++; 1379 if (td->hcsplt != 0 || td->errcnt >= 3) { 1380 if (td->ep_type != UE_ISOCHRONOUS) { 1381 td->error_any = 1; 1382 goto complete; 1383 } 1384 } 1385 } 1386 1387 /* check channels for data, if any */ 1388 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1389 goto complete; 1390 1391 /* refresh interrupt status */ 1392 hcint |= sc->sc_chan_state[channel].hcint; 1393 1394 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1395 HCINT_ACK | HCINT_NYET)) { 1396 if (!(hcint & HCINT_ERRORS)) 1397 td->errcnt = 0; 1398 } 1399 } 1400 1401 switch (td->state) { 1402 case DWC_CHAN_ST_START: 1403 if (td->hcsplt != 0) 1404 goto receive_spkt; 1405 else 1406 goto receive_pkt; 1407 1408 case DWC_CHAN_ST_WAIT_ANE: 1409 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1410 if (td->ep_type == UE_INTERRUPT) { 1411 /* 1412 * The USB specification does not 1413 * mandate a particular data toggle 1414 * value for USB INTERRUPT 1415 * transfers. Switch the data toggle 1416 * value to receive the packet 1417 * correctly: 1418 */ 1419 if (hcint & HCINT_DATATGLERR) { 1420 DPRINTF("Retrying packet due to " 1421 "data toggle error\n"); 1422 td->toggle ^= 1; 1423 goto receive_pkt; 1424 } 1425 } else if (td->ep_type == UE_ISOCHRONOUS) { 1426 goto complete; 1427 } 1428 td->did_nak = 1; 1429 td->tt_scheduled = 0; 1430 if (td->hcsplt != 0) 1431 goto receive_spkt; 1432 else 1433 goto receive_pkt; 1434 } else if (hcint & HCINT_NYET) { 1435 if (td->hcsplt != 0) { 1436 /* try again */ 1437 goto receive_pkt; 1438 } else { 1439 /* not a valid token for IN endpoints */ 1440 td->error_any = 1; 1441 goto complete; 1442 } 1443 } else if (hcint & HCINT_ACK) { 1444 /* wait for data - ACK arrived first */ 1445 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1446 goto busy; 1447 1448 if (td->ep_type == UE_ISOCHRONOUS) { 1449 /* check if we are complete */ 1450 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1451 goto complete; 1452 } else { 1453 /* get more packets */ 1454 goto busy; 1455 } 1456 } else { 1457 /* check if we are complete */ 1458 if ((td->remainder == 0) || (td->got_short != 0)) { 1459 if (td->short_pkt) 1460 goto complete; 1461 1462 /* 1463 * Else need to receive a zero length 1464 * packet. 1465 */ 1466 } 1467 td->tt_scheduled = 0; 1468 td->did_nak = 0; 1469 if (td->hcsplt != 0) 1470 goto receive_spkt; 1471 else 1472 goto receive_pkt; 1473 } 1474 } 1475 break; 1476 1477 case DWC_CHAN_ST_WAIT_S_ANE: 1478 /* 1479 * NOTE: The DWC OTG hardware provides a fake ACK in 1480 * case of interrupt and isochronous transfers: 1481 */ 1482 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1483 td->did_nak = 1; 1484 td->tt_scheduled = 0; 1485 goto receive_spkt; 1486 } else if (hcint & HCINT_NYET) { 1487 td->tt_scheduled = 0; 1488 goto receive_spkt; 1489 } else if (hcint & HCINT_ACK) { 1490 td->did_nak = 0; 1491 goto receive_pkt; 1492 } 1493 break; 1494 1495 case DWC_CHAN_ST_WAIT_C_PKT: 1496 goto receive_pkt; 1497 1498 default: 1499 break; 1500 } 1501 goto busy; 1502 1503 receive_pkt: 1504 /* free existing channel, if any */ 1505 dwc_otg_host_channel_free(sc, td); 1506 1507 if (td->hcsplt != 0) { 1508 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1509 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1510 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1511 goto busy; 1512 } 1513 delta = sc->sc_last_frame_num - td->tt_start_slot; 1514 if (delta > DWC_OTG_TT_SLOT_MAX) { 1515 if (td->ep_type != UE_ISOCHRONOUS) { 1516 /* we missed the service interval */ 1517 td->error_any = 1; 1518 } 1519 goto complete; 1520 } 1521 /* complete split */ 1522 td->hcsplt |= HCSPLT_COMPSPLT; 1523 } else if (dwc_otg_host_rate_check(sc, td)) { 1524 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1525 goto busy; 1526 } 1527 1528 /* allocate a new channel */ 1529 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1530 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1531 goto busy; 1532 } 1533 1534 /* set toggle, if any */ 1535 if (td->set_toggle) { 1536 td->set_toggle = 0; 1537 td->toggle = 1; 1538 } 1539 1540 td->state = DWC_CHAN_ST_WAIT_ANE; 1541 1542 for (x = 0; x != td->max_packet_count; x++) { 1543 channel = td->channel[x]; 1544 1545 /* receive one packet */ 1546 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1547 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1548 (1 << HCTSIZ_PKTCNT_SHIFT) | 1549 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1550 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1551 1552 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1553 1554 hcchar = td->hcchar; 1555 hcchar |= HCCHAR_EPDIR_IN; 1556 1557 /* receive complete split ASAP */ 1558 if ((sc->sc_last_frame_num & 1) != 0 && 1559 td->ep_type == UE_ISOCHRONOUS) 1560 hcchar |= HCCHAR_ODDFRM; 1561 else 1562 hcchar &= ~HCCHAR_ODDFRM; 1563 1564 /* must enable channel before data can be received */ 1565 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1566 } 1567 /* wait until next slot before trying complete split */ 1568 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1569 1570 goto busy; 1571 1572 receive_spkt: 1573 /* free existing channel(s), if any */ 1574 dwc_otg_host_channel_free(sc, td); 1575 1576 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1577 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1578 td->state = DWC_CHAN_ST_START; 1579 goto busy; 1580 } 1581 delta = sc->sc_last_frame_num - td->tt_start_slot; 1582 if (delta > 5) { 1583 /* missed it */ 1584 td->tt_scheduled = 0; 1585 td->state = DWC_CHAN_ST_START; 1586 goto busy; 1587 } 1588 1589 /* allocate a new channel */ 1590 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1591 td->state = DWC_CHAN_ST_START; 1592 goto busy; 1593 } 1594 1595 channel = td->channel[0]; 1596 1597 td->hcsplt &= ~HCSPLT_COMPSPLT; 1598 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1599 1600 /* receive one packet */ 1601 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1602 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1603 1604 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1605 1606 /* send after next SOF event */ 1607 if ((sc->sc_last_frame_num & 1) == 0 && 1608 td->ep_type == UE_ISOCHRONOUS) 1609 td->hcchar |= HCCHAR_ODDFRM; 1610 else 1611 td->hcchar &= ~HCCHAR_ODDFRM; 1612 1613 hcchar = td->hcchar; 1614 hcchar |= HCCHAR_EPDIR_IN; 1615 1616 /* wait until next slot before trying complete split */ 1617 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1618 1619 /* must enable channel before data can be received */ 1620 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1621 busy: 1622 return (1); /* busy */ 1623 1624 complete: 1625 dwc_otg_host_channel_free(sc, td); 1626 return (0); /* complete */ 1627 } 1628 1629 static uint8_t 1630 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1631 { 1632 uint32_t temp; 1633 uint16_t count; 1634 uint8_t got_short; 1635 1636 got_short = 0; 1637 1638 /* check endpoint status */ 1639 if (sc->sc_last_rx_status == 0) 1640 goto not_complete; 1641 1642 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1643 goto not_complete; 1644 1645 /* check for SETUP packet */ 1646 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1647 GRXSTSRD_STP_DATA || 1648 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1649 GRXSTSRD_STP_COMPLETE) { 1650 if (td->remainder == 0) { 1651 /* 1652 * We are actually complete and have 1653 * received the next SETUP 1654 */ 1655 DPRINTFN(5, "faking complete\n"); 1656 return (0); /* complete */ 1657 } 1658 /* 1659 * USB Host Aborted the transfer. 1660 */ 1661 td->error_any = 1; 1662 return (0); /* complete */ 1663 } 1664 1665 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1666 GRXSTSRD_OUT_DATA) { 1667 /* release FIFO */ 1668 dwc_otg_common_rx_ack(sc); 1669 goto not_complete; 1670 } 1671 1672 /* get the packet byte count */ 1673 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1674 1675 /* verify the packet byte count */ 1676 if (count != td->max_packet_size) { 1677 if (count < td->max_packet_size) { 1678 /* we have a short packet */ 1679 td->short_pkt = 1; 1680 got_short = 1; 1681 } else { 1682 /* invalid USB packet */ 1683 td->error_any = 1; 1684 1685 /* release FIFO */ 1686 dwc_otg_common_rx_ack(sc); 1687 return (0); /* we are complete */ 1688 } 1689 } 1690 /* verify the packet byte count */ 1691 if (count > td->remainder) { 1692 /* invalid USB packet */ 1693 td->error_any = 1; 1694 1695 /* release FIFO */ 1696 dwc_otg_common_rx_ack(sc); 1697 return (0); /* we are complete */ 1698 } 1699 1700 /* read data from FIFO */ 1701 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1702 1703 td->remainder -= count; 1704 td->offset += count; 1705 1706 /* release FIFO */ 1707 dwc_otg_common_rx_ack(sc); 1708 1709 temp = sc->sc_out_ctl[td->ep_no]; 1710 1711 /* check for isochronous mode */ 1712 if ((temp & DIEPCTL_EPTYPE_MASK) == 1713 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1714 /* toggle odd or even frame bit */ 1715 if (temp & DIEPCTL_SETD1PID) { 1716 temp &= ~DIEPCTL_SETD1PID; 1717 temp |= DIEPCTL_SETD0PID; 1718 } else { 1719 temp &= ~DIEPCTL_SETD0PID; 1720 temp |= DIEPCTL_SETD1PID; 1721 } 1722 sc->sc_out_ctl[td->ep_no] = temp; 1723 } 1724 1725 /* check if we are complete */ 1726 if ((td->remainder == 0) || got_short) { 1727 if (td->short_pkt) { 1728 /* we are complete */ 1729 return (0); 1730 } 1731 /* else need to receive a zero length packet */ 1732 } 1733 1734 not_complete: 1735 1736 /* enable SETUP and transfer complete interrupt */ 1737 if (td->ep_no == 0) { 1738 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1739 DXEPTSIZ_SET_MULTI(3) | 1740 DXEPTSIZ_SET_NPKT(1) | 1741 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1742 } else { 1743 /* allow reception of multiple packets */ 1744 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1745 DXEPTSIZ_SET_MULTI(1) | 1746 DXEPTSIZ_SET_NPKT(4) | 1747 DXEPTSIZ_SET_NBYTES(4 * 1748 ((td->max_packet_size + 3) & ~3))); 1749 } 1750 temp = sc->sc_out_ctl[td->ep_no]; 1751 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1752 DOEPCTL_EPENA | DOEPCTL_CNAK); 1753 1754 return (1); /* not complete */ 1755 } 1756 1757 static uint8_t 1758 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1759 { 1760 uint32_t count; 1761 uint32_t hcint; 1762 uint32_t hcchar; 1763 uint8_t delta; 1764 uint8_t channel; 1765 uint8_t x; 1766 1767 dwc_otg_host_dump_rx(sc, td); 1768 1769 /* check that last channel is complete */ 1770 channel = td->channel[td->npkt]; 1771 1772 if (channel < DWC_OTG_MAX_CHANNELS) { 1773 hcint = sc->sc_chan_state[channel].hcint; 1774 1775 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1776 channel, td->state, hcint, 1777 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1778 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1779 1780 if (hcint & (HCINT_RETRY | 1781 HCINT_ACK | HCINT_NYET)) { 1782 /* give success bits priority over failure bits */ 1783 } else if (hcint & HCINT_STALL) { 1784 DPRINTF("CH=%d STALL\n", channel); 1785 td->error_stall = 1; 1786 td->error_any = 1; 1787 goto complete; 1788 } else if (hcint & HCINT_ERRORS) { 1789 DPRINTF("CH=%d ERROR\n", channel); 1790 td->errcnt++; 1791 if (td->hcsplt != 0 || td->errcnt >= 3) { 1792 td->error_any = 1; 1793 goto complete; 1794 } 1795 } 1796 1797 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1798 HCINT_ACK | HCINT_NYET)) { 1799 1800 if (!(hcint & HCINT_ERRORS)) 1801 td->errcnt = 0; 1802 } 1803 } else { 1804 hcint = 0; 1805 } 1806 1807 switch (td->state) { 1808 case DWC_CHAN_ST_START: 1809 goto send_pkt; 1810 1811 case DWC_CHAN_ST_WAIT_ANE: 1812 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1813 td->did_nak = 1; 1814 td->tt_scheduled = 0; 1815 goto send_pkt; 1816 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1817 td->offset += td->tx_bytes; 1818 td->remainder -= td->tx_bytes; 1819 td->toggle ^= 1; 1820 /* check if next response will be a NAK */ 1821 if (hcint & HCINT_NYET) 1822 td->did_nak = 1; 1823 else 1824 td->did_nak = 0; 1825 td->tt_scheduled = 0; 1826 1827 /* check remainder */ 1828 if (td->remainder == 0) { 1829 if (td->short_pkt) 1830 goto complete; 1831 1832 /* 1833 * Else we need to transmit a short 1834 * packet: 1835 */ 1836 } 1837 goto send_pkt; 1838 } 1839 break; 1840 1841 case DWC_CHAN_ST_WAIT_S_ANE: 1842 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1843 td->did_nak = 1; 1844 td->tt_scheduled = 0; 1845 goto send_pkt; 1846 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1847 td->did_nak = 0; 1848 goto send_cpkt; 1849 } 1850 break; 1851 1852 case DWC_CHAN_ST_WAIT_C_ANE: 1853 if (hcint & HCINT_NYET) { 1854 goto send_cpkt; 1855 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1856 td->did_nak = 1; 1857 td->tt_scheduled = 0; 1858 goto send_pkt; 1859 } else if (hcint & HCINT_ACK) { 1860 td->offset += td->tx_bytes; 1861 td->remainder -= td->tx_bytes; 1862 td->toggle ^= 1; 1863 td->did_nak = 0; 1864 td->tt_scheduled = 0; 1865 1866 /* check remainder */ 1867 if (td->remainder == 0) { 1868 if (td->short_pkt) 1869 goto complete; 1870 1871 /* else we need to transmit a short packet */ 1872 } 1873 goto send_pkt; 1874 } 1875 break; 1876 1877 case DWC_CHAN_ST_WAIT_C_PKT: 1878 goto send_cpkt; 1879 1880 case DWC_CHAN_ST_TX_WAIT_ISOC: 1881 /* Check if ISOCHRONOUS OUT traffic is complete */ 1882 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1883 break; 1884 1885 td->offset += td->tx_bytes; 1886 td->remainder -= td->tx_bytes; 1887 goto complete; 1888 default: 1889 break; 1890 } 1891 goto busy; 1892 1893 send_pkt: 1894 /* free existing channel(s), if any */ 1895 dwc_otg_host_channel_free(sc, td); 1896 1897 if (td->hcsplt != 0) { 1898 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1899 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1900 td->state = DWC_CHAN_ST_START; 1901 goto busy; 1902 } 1903 delta = sc->sc_last_frame_num - td->tt_start_slot; 1904 if (delta > 5) { 1905 /* missed it */ 1906 td->tt_scheduled = 0; 1907 td->state = DWC_CHAN_ST_START; 1908 goto busy; 1909 } 1910 } else if (dwc_otg_host_rate_check(sc, td)) { 1911 td->state = DWC_CHAN_ST_START; 1912 goto busy; 1913 } 1914 1915 /* allocate a new channel */ 1916 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1917 td->state = DWC_CHAN_ST_START; 1918 goto busy; 1919 } 1920 1921 /* set toggle, if any */ 1922 if (td->set_toggle) { 1923 td->set_toggle = 0; 1924 td->toggle = 1; 1925 } 1926 1927 if (td->ep_type == UE_ISOCHRONOUS) { 1928 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1929 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1930 td->hcsplt &= ~HCSPLT_COMPSPLT; 1931 if (td->hcsplt != 0) { 1932 /* get maximum transfer length */ 1933 count = td->remainder; 1934 if (count > HCSPLT_XACTLEN_BURST) { 1935 DPRINTF("TT overflow\n"); 1936 td->error_any = 1; 1937 goto complete; 1938 } 1939 /* Update transaction position */ 1940 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1941 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1942 } 1943 } else if (td->hcsplt != 0) { 1944 td->hcsplt &= ~HCSPLT_COMPSPLT; 1945 /* Wait for ACK/NAK/ERR from TT */ 1946 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1947 } else { 1948 /* Wait for ACK/NAK/STALL from device */ 1949 td->state = DWC_CHAN_ST_WAIT_ANE; 1950 } 1951 1952 td->tx_bytes = 0; 1953 1954 for (x = 0; x != td->max_packet_count; x++) { 1955 uint32_t rem_bytes; 1956 1957 channel = td->channel[x]; 1958 1959 /* send one packet at a time */ 1960 count = td->max_packet_size; 1961 rem_bytes = td->remainder - td->tx_bytes; 1962 if (rem_bytes < count) { 1963 /* we have a short packet */ 1964 td->short_pkt = 1; 1965 count = rem_bytes; 1966 } 1967 if (count == rem_bytes) { 1968 /* last packet */ 1969 switch (x) { 1970 case 0: 1971 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1972 (count << HCTSIZ_XFERSIZE_SHIFT) | 1973 (1 << HCTSIZ_PKTCNT_SHIFT) | 1974 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1975 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1976 break; 1977 case 1: 1978 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1979 (count << HCTSIZ_XFERSIZE_SHIFT) | 1980 (1 << HCTSIZ_PKTCNT_SHIFT) | 1981 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1982 break; 1983 default: 1984 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1985 (count << HCTSIZ_XFERSIZE_SHIFT) | 1986 (1 << HCTSIZ_PKTCNT_SHIFT) | 1987 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1988 break; 1989 } 1990 } else if (td->ep_type == UE_ISOCHRONOUS && 1991 td->max_packet_count > 1) { 1992 /* ISOCHRONOUS multi packet */ 1993 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1994 (count << HCTSIZ_XFERSIZE_SHIFT) | 1995 (1 << HCTSIZ_PKTCNT_SHIFT) | 1996 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1997 } else { 1998 /* TODO: HCTSIZ_DOPNG */ 1999 /* standard BULK/INTERRUPT/CONTROL packet */ 2000 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2001 (count << HCTSIZ_XFERSIZE_SHIFT) | 2002 (1 << HCTSIZ_PKTCNT_SHIFT) | 2003 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2004 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2005 } 2006 2007 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2008 2009 hcchar = td->hcchar; 2010 hcchar &= ~HCCHAR_EPDIR_IN; 2011 2012 /* send after next SOF event */ 2013 if ((sc->sc_last_frame_num & 1) == 0 && 2014 td->ep_type == UE_ISOCHRONOUS) 2015 hcchar |= HCCHAR_ODDFRM; 2016 else 2017 hcchar &= ~HCCHAR_ODDFRM; 2018 2019 /* must enable before writing data to FIFO */ 2020 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2021 2022 if (count != 0) { 2023 /* write data into FIFO */ 2024 dwc_otg_write_fifo(sc, td->pc, td->offset + 2025 td->tx_bytes, DOTG_DFIFO(channel), count); 2026 } 2027 2028 /* store number of bytes transmitted */ 2029 td->tx_bytes += count; 2030 2031 /* store last packet index */ 2032 td->npkt = x; 2033 2034 /* check for last packet */ 2035 if (count == rem_bytes) 2036 break; 2037 } 2038 goto busy; 2039 2040 send_cpkt: 2041 /* free existing channel, if any */ 2042 dwc_otg_host_channel_free(sc, td); 2043 2044 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2045 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2046 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2047 goto busy; 2048 } 2049 delta = sc->sc_last_frame_num - td->tt_start_slot; 2050 if (delta > DWC_OTG_TT_SLOT_MAX) { 2051 /* we missed the service interval */ 2052 if (td->ep_type != UE_ISOCHRONOUS) 2053 td->error_any = 1; 2054 goto complete; 2055 } 2056 2057 /* allocate a new channel */ 2058 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2059 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2060 goto busy; 2061 } 2062 2063 channel = td->channel[0]; 2064 2065 td->hcsplt |= HCSPLT_COMPSPLT; 2066 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2067 2068 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2069 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2070 2071 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2072 2073 hcchar = td->hcchar; 2074 hcchar &= ~HCCHAR_EPDIR_IN; 2075 2076 /* receive complete split ASAP */ 2077 if ((sc->sc_last_frame_num & 1) != 0 && 2078 td->ep_type == UE_ISOCHRONOUS) 2079 hcchar |= HCCHAR_ODDFRM; 2080 else 2081 hcchar &= ~HCCHAR_ODDFRM; 2082 2083 /* must enable channel before data can be received */ 2084 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2085 2086 /* wait until next slot before trying complete split */ 2087 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2088 busy: 2089 return (1); /* busy */ 2090 2091 complete: 2092 dwc_otg_host_channel_free(sc, td); 2093 return (0); /* complete */ 2094 } 2095 2096 static uint8_t 2097 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2098 { 2099 uint32_t max_buffer; 2100 uint32_t count; 2101 uint32_t fifo_left; 2102 uint32_t mpkt; 2103 uint32_t temp; 2104 uint8_t to; 2105 2106 to = 3; /* don't loop forever! */ 2107 2108 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2109 2110 repeat: 2111 /* check for for endpoint 0 data */ 2112 2113 temp = sc->sc_last_rx_status; 2114 2115 if ((td->ep_no == 0) && (temp != 0) && 2116 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2117 2118 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2119 GRXSTSRD_STP_DATA && 2120 (temp & GRXSTSRD_PKTSTS_MASK) != 2121 GRXSTSRD_STP_COMPLETE) { 2122 2123 /* dump data - wrong direction */ 2124 dwc_otg_common_rx_ack(sc); 2125 } else { 2126 /* 2127 * The current transfer was cancelled 2128 * by the USB Host: 2129 */ 2130 td->error_any = 1; 2131 return (0); /* complete */ 2132 } 2133 } 2134 2135 /* fill in more TX data, if possible */ 2136 if (td->tx_bytes != 0) { 2137 2138 uint16_t cpkt; 2139 2140 /* check if packets have been transferred */ 2141 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2142 2143 /* get current packet number */ 2144 cpkt = DXEPTSIZ_GET_NPKT(temp); 2145 2146 if (cpkt >= td->npkt) { 2147 fifo_left = 0; 2148 } else { 2149 if (max_buffer != 0) { 2150 fifo_left = (td->npkt - cpkt) * 2151 td->max_packet_size; 2152 2153 if (fifo_left > max_buffer) 2154 fifo_left = max_buffer; 2155 } else { 2156 fifo_left = td->max_packet_size; 2157 } 2158 } 2159 2160 count = td->tx_bytes; 2161 if (count > fifo_left) 2162 count = fifo_left; 2163 2164 if (count != 0) { 2165 /* write data into FIFO */ 2166 dwc_otg_write_fifo(sc, td->pc, td->offset, 2167 DOTG_DFIFO(td->ep_no), count); 2168 2169 td->tx_bytes -= count; 2170 td->remainder -= count; 2171 td->offset += count; 2172 td->npkt = cpkt; 2173 } 2174 if (td->tx_bytes != 0) 2175 goto not_complete; 2176 2177 /* check remainder */ 2178 if (td->remainder == 0) { 2179 if (td->short_pkt) 2180 return (0); /* complete */ 2181 2182 /* else we need to transmit a short packet */ 2183 } 2184 } 2185 2186 if (!to--) 2187 goto not_complete; 2188 2189 /* check if not all packets have been transferred */ 2190 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2191 2192 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2193 2194 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2195 "DIEPCTL=0x%08x\n", td->ep_no, 2196 DXEPTSIZ_GET_NPKT(temp), 2197 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2198 2199 goto not_complete; 2200 } 2201 2202 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2203 2204 /* try to optimise by sending more data */ 2205 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2206 2207 /* send multiple packets at the same time */ 2208 mpkt = max_buffer / td->max_packet_size; 2209 2210 if (mpkt > 0x3FE) 2211 mpkt = 0x3FE; 2212 2213 count = td->remainder; 2214 if (count > 0x7FFFFF) 2215 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2216 2217 td->npkt = count / td->max_packet_size; 2218 2219 /* 2220 * NOTE: We could use 0x3FE instead of "mpkt" in the 2221 * check below to get more throughput, but then we 2222 * have a dependency towards non-generic chip features 2223 * to disable the TX-FIFO-EMPTY interrupts on a per 2224 * endpoint basis. Increase the maximum buffer size of 2225 * the IN endpoint to increase the performance. 2226 */ 2227 if (td->npkt > mpkt) { 2228 td->npkt = mpkt; 2229 count = td->max_packet_size * mpkt; 2230 } else if ((count == 0) || (count % td->max_packet_size)) { 2231 /* we are transmitting a short packet */ 2232 td->npkt++; 2233 td->short_pkt = 1; 2234 } 2235 } else { 2236 /* send one packet at a time */ 2237 mpkt = 1; 2238 count = td->max_packet_size; 2239 if (td->remainder < count) { 2240 /* we have a short packet */ 2241 td->short_pkt = 1; 2242 count = td->remainder; 2243 } 2244 td->npkt = 1; 2245 } 2246 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2247 DXEPTSIZ_SET_MULTI(1) | 2248 DXEPTSIZ_SET_NPKT(td->npkt) | 2249 DXEPTSIZ_SET_NBYTES(count)); 2250 2251 /* make room for buffering */ 2252 td->npkt += mpkt; 2253 2254 temp = sc->sc_in_ctl[td->ep_no]; 2255 2256 /* check for isochronous mode */ 2257 if ((temp & DIEPCTL_EPTYPE_MASK) == 2258 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2259 /* toggle odd or even frame bit */ 2260 if (temp & DIEPCTL_SETD1PID) { 2261 temp &= ~DIEPCTL_SETD1PID; 2262 temp |= DIEPCTL_SETD0PID; 2263 } else { 2264 temp &= ~DIEPCTL_SETD0PID; 2265 temp |= DIEPCTL_SETD1PID; 2266 } 2267 sc->sc_in_ctl[td->ep_no] = temp; 2268 } 2269 2270 /* must enable before writing data to FIFO */ 2271 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2272 DIEPCTL_EPENA | DIEPCTL_CNAK); 2273 2274 td->tx_bytes = count; 2275 2276 /* check remainder */ 2277 if (td->tx_bytes == 0 && 2278 td->remainder == 0) { 2279 if (td->short_pkt) 2280 return (0); /* complete */ 2281 2282 /* else we need to transmit a short packet */ 2283 } 2284 goto repeat; 2285 2286 not_complete: 2287 return (1); /* not complete */ 2288 } 2289 2290 static uint8_t 2291 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2292 { 2293 uint32_t temp; 2294 2295 /* 2296 * If all packets are transferred we are complete: 2297 */ 2298 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2299 2300 /* check that all packets have been transferred */ 2301 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2302 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2303 goto not_complete; 2304 } 2305 return (0); 2306 2307 not_complete: 2308 2309 /* we only want to know if there is a SETUP packet or free IN packet */ 2310 2311 temp = sc->sc_last_rx_status; 2312 2313 if ((td->ep_no == 0) && (temp != 0) && 2314 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2315 2316 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2317 GRXSTSRD_STP_DATA || 2318 (temp & GRXSTSRD_PKTSTS_MASK) == 2319 GRXSTSRD_STP_COMPLETE) { 2320 DPRINTFN(5, "faking complete\n"); 2321 /* 2322 * Race condition: We are complete! 2323 */ 2324 return (0); 2325 } else { 2326 /* dump data - wrong direction */ 2327 dwc_otg_common_rx_ack(sc); 2328 } 2329 } 2330 return (1); /* not complete */ 2331 } 2332 2333 static void 2334 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2335 { 2336 struct dwc_otg_td *td; 2337 uint8_t toggle; 2338 uint8_t tmr_val; 2339 uint8_t tmr_res; 2340 2341 DPRINTFN(9, "\n"); 2342 2343 td = xfer->td_transfer_cache; 2344 if (td == NULL) 2345 return; 2346 2347 while (1) { 2348 if ((td->func) (sc, td)) { 2349 /* operation in progress */ 2350 break; 2351 } 2352 if (((void *)td) == xfer->td_transfer_last) { 2353 goto done; 2354 } 2355 if (td->error_any) { 2356 goto done; 2357 } else if (td->remainder > 0) { 2358 /* 2359 * We had a short transfer. If there is no alternate 2360 * next, stop processing ! 2361 */ 2362 if (!td->alt_next) 2363 goto done; 2364 } 2365 2366 /* 2367 * Fetch the next transfer descriptor and transfer 2368 * some flags to the next transfer descriptor 2369 */ 2370 tmr_res = td->tmr_res; 2371 tmr_val = td->tmr_val; 2372 toggle = td->toggle; 2373 td = td->obj_next; 2374 xfer->td_transfer_cache = td; 2375 td->toggle = toggle; /* transfer toggle */ 2376 td->tmr_res = tmr_res; 2377 td->tmr_val = tmr_val; 2378 } 2379 return; 2380 2381 done: 2382 xfer->td_transfer_cache = NULL; 2383 sc->sc_xfer_complete = 1; 2384 } 2385 2386 static uint8_t 2387 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2388 { 2389 struct dwc_otg_td *td; 2390 2391 DPRINTFN(9, "\n"); 2392 2393 td = xfer->td_transfer_cache; 2394 if (td == NULL) { 2395 /* compute all actual lengths */ 2396 dwc_otg_standard_done(xfer); 2397 return (1); 2398 } 2399 return (0); 2400 } 2401 2402 static void 2403 dwc_otg_timer(void *_sc) 2404 { 2405 struct dwc_otg_softc *sc = _sc; 2406 2407 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2408 2409 DPRINTF("\n"); 2410 2411 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2412 2413 /* increment timer value */ 2414 sc->sc_tmr_val++; 2415 2416 /* enable SOF interrupt, which will poll jobs */ 2417 dwc_otg_enable_sof_irq(sc); 2418 2419 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2420 2421 if (sc->sc_timer_active) { 2422 /* restart timer */ 2423 usb_callout_reset(&sc->sc_timer, 2424 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2425 &dwc_otg_timer, sc); 2426 } 2427 } 2428 2429 static void 2430 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2431 { 2432 if (sc->sc_timer_active != 0) 2433 return; 2434 2435 sc->sc_timer_active = 1; 2436 2437 /* restart timer */ 2438 usb_callout_reset(&sc->sc_timer, 2439 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2440 &dwc_otg_timer, sc); 2441 } 2442 2443 static void 2444 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2445 { 2446 if (sc->sc_timer_active == 0) 2447 return; 2448 2449 sc->sc_timer_active = 0; 2450 2451 /* stop timer */ 2452 usb_callout_stop(&sc->sc_timer); 2453 } 2454 2455 static uint16_t 2456 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2457 { 2458 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2459 pinfo->slot_index++; 2460 return (pinfo->slot_index); 2461 } 2462 2463 static uint8_t 2464 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2465 { 2466 TAILQ_HEAD(, usb_xfer) head; 2467 struct usb_xfer *xfer; 2468 struct usb_xfer *xfer_next; 2469 struct dwc_otg_td *td; 2470 uint16_t temp; 2471 uint16_t slot; 2472 2473 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2474 2475 if (sc->sc_last_frame_num == temp) 2476 return (0); 2477 2478 sc->sc_last_frame_num = temp; 2479 2480 TAILQ_INIT(&head); 2481 2482 if ((temp & 7) == 0) { 2483 2484 /* reset the schedule */ 2485 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2486 2487 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2488 td = xfer->td_transfer_cache; 2489 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2490 continue; 2491 2492 /* check for IN direction */ 2493 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2494 continue; 2495 2496 sc->sc_needsof = 1; 2497 2498 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2499 continue; 2500 2501 /* compute slot */ 2502 slot = dwc_otg_compute_isoc_rx_tt_slot( 2503 sc->sc_tt_info + td->tt_index); 2504 if (slot > 3) { 2505 /* 2506 * Not enough time to get complete 2507 * split executed. 2508 */ 2509 continue; 2510 } 2511 /* Delayed start */ 2512 td->tt_start_slot = temp + slot; 2513 td->tt_scheduled = 1; 2514 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2515 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2516 } 2517 2518 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2519 td = xfer->td_transfer_cache; 2520 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2521 continue; 2522 2523 /* check for OUT direction */ 2524 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2525 continue; 2526 2527 sc->sc_needsof = 1; 2528 2529 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2530 continue; 2531 2532 /* Start ASAP */ 2533 td->tt_start_slot = temp; 2534 td->tt_scheduled = 1; 2535 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2536 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2537 } 2538 2539 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2540 td = xfer->td_transfer_cache; 2541 if (td == NULL || td->ep_type != UE_INTERRUPT) 2542 continue; 2543 2544 if (td->tt_scheduled != 0) { 2545 sc->sc_needsof = 1; 2546 continue; 2547 } 2548 2549 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2550 continue; 2551 2552 if (td->hcsplt == 0) { 2553 sc->sc_needsof = 1; 2554 td->tt_scheduled = 1; 2555 continue; 2556 } 2557 2558 /* start ASAP */ 2559 td->tt_start_slot = temp; 2560 sc->sc_needsof = 1; 2561 td->tt_scheduled = 1; 2562 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2563 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2564 } 2565 2566 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2567 td = xfer->td_transfer_cache; 2568 if (td == NULL || 2569 td->ep_type != UE_CONTROL) { 2570 continue; 2571 } 2572 2573 sc->sc_needsof = 1; 2574 2575 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2576 continue; 2577 2578 /* start ASAP */ 2579 td->tt_start_slot = temp; 2580 td->tt_scheduled = 1; 2581 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2582 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2583 } 2584 } 2585 if ((temp & 7) < 6) { 2586 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2587 td = xfer->td_transfer_cache; 2588 if (td == NULL || 2589 td->ep_type != UE_BULK) { 2590 continue; 2591 } 2592 2593 sc->sc_needsof = 1; 2594 2595 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2596 continue; 2597 2598 /* start ASAP */ 2599 td->tt_start_slot = temp; 2600 td->tt_scheduled = 1; 2601 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2602 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2603 } 2604 } 2605 2606 /* Put TT transfers in execution order at the end */ 2607 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2608 2609 /* move all TT transfers in front, keeping the current order */ 2610 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2611 td = xfer->td_transfer_cache; 2612 if (td == NULL || td->hcsplt == 0) 2613 continue; 2614 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2615 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2616 } 2617 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2618 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2619 2620 /* put non-TT non-ISOCHRONOUS transfers last */ 2621 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2622 td = xfer->td_transfer_cache; 2623 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2624 continue; 2625 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2626 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2627 } 2628 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2629 2630 if ((temp & 7) == 0) { 2631 2632 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2633 (int)temp, (int)sc->sc_needsof); 2634 2635 /* update SOF IRQ mask */ 2636 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2637 if (sc->sc_needsof == 0) { 2638 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2639 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2640 } 2641 } else { 2642 if (sc->sc_needsof != 0) { 2643 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2644 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2645 } 2646 } 2647 2648 /* clear need SOF flag */ 2649 sc->sc_needsof = 0; 2650 } 2651 return (1); 2652 } 2653 2654 static void 2655 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2656 { 2657 struct usb_xfer *xfer; 2658 uint32_t count; 2659 uint32_t temp; 2660 uint32_t haint; 2661 uint8_t got_rx_status; 2662 uint8_t x; 2663 2664 if (sc->sc_flags.status_device_mode == 0) { 2665 /* 2666 * Update host transfer schedule, so that new 2667 * transfers can be issued: 2668 */ 2669 dwc_otg_update_host_transfer_schedule_locked(sc); 2670 } 2671 count = 0; 2672 repeat: 2673 if (++count == 16) { 2674 /* give other interrupts a chance */ 2675 DPRINTF("Yield\n"); 2676 return; 2677 } 2678 2679 /* get all host channel interrupts */ 2680 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2681 while (1) { 2682 x = ffs(haint) - 1; 2683 if (x >= sc->sc_host_ch_max) 2684 break; 2685 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2686 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2687 temp &= ~HCINT_SOFTWARE_ONLY; 2688 sc->sc_chan_state[x].hcint |= temp; 2689 haint &= ~(1U << x); 2690 } 2691 2692 if (sc->sc_last_rx_status == 0) { 2693 2694 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2695 if (temp & GINTSTS_RXFLVL) { 2696 /* pop current status */ 2697 sc->sc_last_rx_status = 2698 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2699 } 2700 2701 if (sc->sc_last_rx_status != 0) { 2702 2703 uint8_t ep_no; 2704 2705 temp = sc->sc_last_rx_status & 2706 GRXSTSRD_PKTSTS_MASK; 2707 2708 /* non-data messages we simply skip */ 2709 if (temp != GRXSTSRD_STP_DATA && 2710 temp != GRXSTSRD_STP_COMPLETE && 2711 temp != GRXSTSRD_OUT_DATA) { 2712 /* check for halted channel */ 2713 if (temp == GRXSTSRH_HALTED) { 2714 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2715 sc->sc_chan_state[ep_no].wait_halted = 0; 2716 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2717 } 2718 /* store bytes and FIFO offset */ 2719 sc->sc_current_rx_bytes = 0; 2720 sc->sc_current_rx_fifo = 0; 2721 2722 /* acknowledge status */ 2723 dwc_otg_common_rx_ack(sc); 2724 goto repeat; 2725 } 2726 2727 temp = GRXSTSRD_BCNT_GET( 2728 sc->sc_last_rx_status); 2729 ep_no = GRXSTSRD_CHNUM_GET( 2730 sc->sc_last_rx_status); 2731 2732 /* store bytes and FIFO offset */ 2733 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2734 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2735 2736 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2737 2738 /* check if we should dump the data */ 2739 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2740 dwc_otg_common_rx_ack(sc); 2741 goto repeat; 2742 } 2743 2744 got_rx_status = 1; 2745 2746 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2747 sc->sc_last_rx_status, ep_no, 2748 (sc->sc_last_rx_status >> 15) & 3, 2749 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2750 (sc->sc_last_rx_status >> 17) & 15); 2751 } else { 2752 got_rx_status = 0; 2753 } 2754 } else { 2755 uint8_t ep_no; 2756 2757 ep_no = GRXSTSRD_CHNUM_GET( 2758 sc->sc_last_rx_status); 2759 2760 /* check if we should dump the data */ 2761 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2762 dwc_otg_common_rx_ack(sc); 2763 goto repeat; 2764 } 2765 2766 got_rx_status = 1; 2767 } 2768 2769 /* execute FIFOs */ 2770 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2771 dwc_otg_xfer_do_fifo(sc, xfer); 2772 2773 if (got_rx_status) { 2774 /* check if data was consumed */ 2775 if (sc->sc_last_rx_status == 0) 2776 goto repeat; 2777 2778 /* disable RX FIFO level interrupt */ 2779 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2780 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2781 } 2782 } 2783 2784 static void 2785 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2786 { 2787 struct usb_xfer *xfer; 2788 repeat: 2789 /* scan for completion events */ 2790 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2791 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2792 goto repeat; 2793 } 2794 } 2795 2796 static void 2797 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2798 { 2799 DPRINTFN(5, "vbus = %u\n", is_on); 2800 2801 /* 2802 * If the USB host mode is forced, then assume VBUS is always 2803 * present else rely on the input to this function: 2804 */ 2805 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2806 2807 if (!sc->sc_flags.status_vbus) { 2808 sc->sc_flags.status_vbus = 1; 2809 2810 /* complete root HUB interrupt endpoint */ 2811 2812 dwc_otg_root_intr(sc); 2813 } 2814 } else { 2815 if (sc->sc_flags.status_vbus) { 2816 sc->sc_flags.status_vbus = 0; 2817 sc->sc_flags.status_bus_reset = 0; 2818 sc->sc_flags.status_suspend = 0; 2819 sc->sc_flags.change_suspend = 0; 2820 sc->sc_flags.change_connect = 1; 2821 2822 /* complete root HUB interrupt endpoint */ 2823 2824 dwc_otg_root_intr(sc); 2825 } 2826 } 2827 } 2828 2829 int 2830 dwc_otg_filter_interrupt(void *arg) 2831 { 2832 struct dwc_otg_softc *sc = arg; 2833 int retval = FILTER_HANDLED; 2834 uint32_t status; 2835 2836 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2837 2838 /* read and clear interrupt status */ 2839 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2840 2841 /* clear interrupts we are handling here */ 2842 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2843 2844 /* check for USB state change interrupts */ 2845 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2846 retval = FILTER_SCHEDULE_THREAD; 2847 2848 /* clear FIFO empty interrupts */ 2849 if (status & sc->sc_irq_mask & 2850 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2851 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2852 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2853 } 2854 /* clear all IN endpoint interrupts */ 2855 if (status & GINTSTS_IEPINT) { 2856 uint32_t temp; 2857 uint8_t x; 2858 2859 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2860 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2861 if (temp & DIEPMSK_XFERCOMPLMSK) { 2862 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2863 DIEPMSK_XFERCOMPLMSK); 2864 } 2865 } 2866 } 2867 2868 /* poll FIFOs, if any */ 2869 dwc_otg_interrupt_poll_locked(sc); 2870 2871 if (sc->sc_xfer_complete != 0) 2872 retval = FILTER_SCHEDULE_THREAD; 2873 2874 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2875 2876 return (retval); 2877 } 2878 2879 void 2880 dwc_otg_interrupt(void *arg) 2881 { 2882 struct dwc_otg_softc *sc = arg; 2883 uint32_t status; 2884 2885 USB_BUS_LOCK(&sc->sc_bus); 2886 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2887 2888 /* read and clear interrupt status */ 2889 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2890 2891 /* clear interrupts we are handling here */ 2892 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2893 2894 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2895 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2896 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2897 2898 if (status & GINTSTS_USBRST) { 2899 2900 /* set correct state */ 2901 sc->sc_flags.status_device_mode = 1; 2902 sc->sc_flags.status_bus_reset = 0; 2903 sc->sc_flags.status_suspend = 0; 2904 sc->sc_flags.change_suspend = 0; 2905 sc->sc_flags.change_connect = 1; 2906 2907 /* Disable SOF interrupt */ 2908 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2909 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2910 2911 /* complete root HUB interrupt endpoint */ 2912 dwc_otg_root_intr(sc); 2913 } 2914 2915 /* check for any bus state change interrupts */ 2916 if (status & GINTSTS_ENUMDONE) { 2917 2918 uint32_t temp; 2919 2920 DPRINTFN(5, "end of reset\n"); 2921 2922 /* set correct state */ 2923 sc->sc_flags.status_device_mode = 1; 2924 sc->sc_flags.status_bus_reset = 1; 2925 sc->sc_flags.status_suspend = 0; 2926 sc->sc_flags.change_suspend = 0; 2927 sc->sc_flags.change_connect = 1; 2928 sc->sc_flags.status_low_speed = 0; 2929 sc->sc_flags.port_enabled = 1; 2930 2931 /* reset FIFOs */ 2932 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2933 2934 /* reset function address */ 2935 dwc_otg_set_address(sc, 0); 2936 2937 /* figure out enumeration speed */ 2938 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2939 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2940 sc->sc_flags.status_high_speed = 1; 2941 else 2942 sc->sc_flags.status_high_speed = 0; 2943 2944 /* 2945 * Disable resume and SOF interrupt, and enable 2946 * suspend and RX frame interrupt: 2947 */ 2948 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2949 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2950 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2951 2952 /* complete root HUB interrupt endpoint */ 2953 dwc_otg_root_intr(sc); 2954 } 2955 2956 if (status & GINTSTS_PRTINT) { 2957 uint32_t hprt; 2958 2959 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2960 2961 /* clear change bits */ 2962 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2963 HPRT_PRTPWR | HPRT_PRTENCHNG | 2964 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2965 sc->sc_hprt_val); 2966 2967 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2968 2969 sc->sc_flags.status_device_mode = 0; 2970 2971 if (hprt & HPRT_PRTCONNSTS) 2972 sc->sc_flags.status_bus_reset = 1; 2973 else 2974 sc->sc_flags.status_bus_reset = 0; 2975 2976 if (hprt & HPRT_PRTENCHNG) 2977 sc->sc_flags.change_enabled = 1; 2978 2979 if (hprt & HPRT_PRTENA) 2980 sc->sc_flags.port_enabled = 1; 2981 else 2982 sc->sc_flags.port_enabled = 0; 2983 2984 if (hprt & HPRT_PRTOVRCURRCHNG) 2985 sc->sc_flags.change_over_current = 1; 2986 2987 if (hprt & HPRT_PRTOVRCURRACT) 2988 sc->sc_flags.port_over_current = 1; 2989 else 2990 sc->sc_flags.port_over_current = 0; 2991 2992 if (hprt & HPRT_PRTPWR) 2993 sc->sc_flags.port_powered = 1; 2994 else 2995 sc->sc_flags.port_powered = 0; 2996 2997 if (((hprt & HPRT_PRTSPD_MASK) 2998 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2999 sc->sc_flags.status_low_speed = 1; 3000 else 3001 sc->sc_flags.status_low_speed = 0; 3002 3003 if (((hprt & HPRT_PRTSPD_MASK) 3004 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3005 sc->sc_flags.status_high_speed = 1; 3006 else 3007 sc->sc_flags.status_high_speed = 0; 3008 3009 if (hprt & HPRT_PRTCONNDET) 3010 sc->sc_flags.change_connect = 1; 3011 3012 if (hprt & HPRT_PRTSUSP) 3013 dwc_otg_suspend_irq(sc); 3014 else 3015 dwc_otg_resume_irq(sc); 3016 3017 /* complete root HUB interrupt endpoint */ 3018 dwc_otg_root_intr(sc); 3019 3020 /* update host frame interval */ 3021 dwc_otg_update_host_frame_interval(sc); 3022 } 3023 3024 /* 3025 * If resume and suspend is set at the same time we interpret 3026 * that like RESUME. Resume is set when there is at least 3 3027 * milliseconds of inactivity on the USB BUS. 3028 */ 3029 if (status & GINTSTS_WKUPINT) { 3030 3031 DPRINTFN(5, "resume interrupt\n"); 3032 3033 dwc_otg_resume_irq(sc); 3034 3035 } else if (status & GINTSTS_USBSUSP) { 3036 3037 DPRINTFN(5, "suspend interrupt\n"); 3038 3039 dwc_otg_suspend_irq(sc); 3040 } 3041 /* check VBUS */ 3042 if (status & (GINTSTS_USBSUSP | 3043 GINTSTS_USBRST | 3044 GINTMSK_OTGINTMSK | 3045 GINTSTS_SESSREQINT)) { 3046 uint32_t temp; 3047 3048 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3049 3050 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3051 3052 dwc_otg_vbus_interrupt(sc, 3053 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3054 } 3055 3056 if (sc->sc_xfer_complete != 0) { 3057 sc->sc_xfer_complete = 0; 3058 3059 /* complete FIFOs, if any */ 3060 dwc_otg_interrupt_complete_locked(sc); 3061 } 3062 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3063 USB_BUS_UNLOCK(&sc->sc_bus); 3064 } 3065 3066 static void 3067 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3068 { 3069 struct dwc_otg_td *td; 3070 3071 /* get current Transfer Descriptor */ 3072 td = temp->td_next; 3073 temp->td = td; 3074 3075 /* prepare for next TD */ 3076 temp->td_next = td->obj_next; 3077 3078 /* fill out the Transfer Descriptor */ 3079 td->func = temp->func; 3080 td->pc = temp->pc; 3081 td->offset = temp->offset; 3082 td->remainder = temp->len; 3083 td->tx_bytes = 0; 3084 td->error_any = 0; 3085 td->error_stall = 0; 3086 td->npkt = 0; 3087 td->did_stall = temp->did_stall; 3088 td->short_pkt = temp->short_pkt; 3089 td->alt_next = temp->setup_alt_next; 3090 td->set_toggle = 0; 3091 td->got_short = 0; 3092 td->did_nak = 0; 3093 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3094 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3095 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3096 td->state = 0; 3097 td->errcnt = 0; 3098 td->tt_scheduled = 0; 3099 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3100 } 3101 3102 static void 3103 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3104 { 3105 struct dwc_otg_std_temp temp; 3106 struct dwc_otg_td *td; 3107 uint32_t x; 3108 uint8_t need_sync; 3109 uint8_t is_host; 3110 3111 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3112 xfer->address, UE_GET_ADDR(xfer->endpointno), 3113 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3114 3115 temp.max_frame_size = xfer->max_frame_size; 3116 3117 td = xfer->td_start[0]; 3118 xfer->td_transfer_first = td; 3119 xfer->td_transfer_cache = td; 3120 3121 /* setup temp */ 3122 3123 temp.pc = NULL; 3124 temp.td = NULL; 3125 temp.td_next = xfer->td_start[0]; 3126 temp.offset = 0; 3127 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3128 xfer->flags_int.isochronous_xfr; 3129 temp.did_stall = !xfer->flags_int.control_stall; 3130 3131 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3132 3133 /* check if we should prepend a setup message */ 3134 3135 if (xfer->flags_int.control_xfr) { 3136 if (xfer->flags_int.control_hdr) { 3137 3138 if (is_host) 3139 temp.func = &dwc_otg_host_setup_tx; 3140 else 3141 temp.func = &dwc_otg_setup_rx; 3142 3143 temp.len = xfer->frlengths[0]; 3144 temp.pc = xfer->frbuffers + 0; 3145 temp.short_pkt = temp.len ? 1 : 0; 3146 3147 /* check for last frame */ 3148 if (xfer->nframes == 1) { 3149 /* no STATUS stage yet, SETUP is last */ 3150 if (xfer->flags_int.control_act) 3151 temp.setup_alt_next = 0; 3152 } 3153 3154 dwc_otg_setup_standard_chain_sub(&temp); 3155 } 3156 x = 1; 3157 } else { 3158 x = 0; 3159 } 3160 3161 if (x != xfer->nframes) { 3162 if (xfer->endpointno & UE_DIR_IN) { 3163 if (is_host) { 3164 temp.func = &dwc_otg_host_data_rx; 3165 need_sync = 0; 3166 } else { 3167 temp.func = &dwc_otg_data_tx; 3168 need_sync = 1; 3169 } 3170 } else { 3171 if (is_host) { 3172 temp.func = &dwc_otg_host_data_tx; 3173 need_sync = 0; 3174 } else { 3175 temp.func = &dwc_otg_data_rx; 3176 need_sync = 0; 3177 } 3178 } 3179 3180 /* setup "pc" pointer */ 3181 temp.pc = xfer->frbuffers + x; 3182 } else { 3183 need_sync = 0; 3184 } 3185 while (x != xfer->nframes) { 3186 3187 /* DATA0 / DATA1 message */ 3188 3189 temp.len = xfer->frlengths[x]; 3190 3191 x++; 3192 3193 if (x == xfer->nframes) { 3194 if (xfer->flags_int.control_xfr) { 3195 if (xfer->flags_int.control_act) { 3196 temp.setup_alt_next = 0; 3197 } 3198 } else { 3199 temp.setup_alt_next = 0; 3200 } 3201 } 3202 if (temp.len == 0) { 3203 3204 /* make sure that we send an USB packet */ 3205 3206 temp.short_pkt = 0; 3207 3208 } else { 3209 3210 /* regular data transfer */ 3211 3212 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3213 } 3214 3215 dwc_otg_setup_standard_chain_sub(&temp); 3216 3217 if (xfer->flags_int.isochronous_xfr) { 3218 temp.offset += temp.len; 3219 } else { 3220 /* get next Page Cache pointer */ 3221 temp.pc = xfer->frbuffers + x; 3222 } 3223 } 3224 3225 if (xfer->flags_int.control_xfr) { 3226 3227 /* always setup a valid "pc" pointer for status and sync */ 3228 temp.pc = xfer->frbuffers + 0; 3229 temp.len = 0; 3230 temp.short_pkt = 0; 3231 temp.setup_alt_next = 0; 3232 3233 /* check if we need to sync */ 3234 if (need_sync) { 3235 /* we need a SYNC point after TX */ 3236 temp.func = &dwc_otg_data_tx_sync; 3237 dwc_otg_setup_standard_chain_sub(&temp); 3238 } 3239 3240 /* check if we should append a status stage */ 3241 if (!xfer->flags_int.control_act) { 3242 3243 /* 3244 * Send a DATA1 message and invert the current 3245 * endpoint direction. 3246 */ 3247 if (xfer->endpointno & UE_DIR_IN) { 3248 if (is_host) { 3249 temp.func = &dwc_otg_host_data_tx; 3250 need_sync = 0; 3251 } else { 3252 temp.func = &dwc_otg_data_rx; 3253 need_sync = 0; 3254 } 3255 } else { 3256 if (is_host) { 3257 temp.func = &dwc_otg_host_data_rx; 3258 need_sync = 0; 3259 } else { 3260 temp.func = &dwc_otg_data_tx; 3261 need_sync = 1; 3262 } 3263 } 3264 3265 dwc_otg_setup_standard_chain_sub(&temp); 3266 3267 /* data toggle should be DATA1 */ 3268 td = temp.td; 3269 td->set_toggle = 1; 3270 3271 if (need_sync) { 3272 /* we need a SYNC point after TX */ 3273 temp.func = &dwc_otg_data_tx_sync; 3274 dwc_otg_setup_standard_chain_sub(&temp); 3275 } 3276 } 3277 } else { 3278 /* check if we need to sync */ 3279 if (need_sync) { 3280 3281 temp.pc = xfer->frbuffers + 0; 3282 temp.len = 0; 3283 temp.short_pkt = 0; 3284 temp.setup_alt_next = 0; 3285 3286 /* we need a SYNC point after TX */ 3287 temp.func = &dwc_otg_data_tx_sync; 3288 dwc_otg_setup_standard_chain_sub(&temp); 3289 } 3290 } 3291 3292 /* must have at least one frame! */ 3293 td = temp.td; 3294 xfer->td_transfer_last = td; 3295 3296 if (is_host) { 3297 3298 struct dwc_otg_softc *sc; 3299 uint32_t hcchar; 3300 uint32_t hcsplt; 3301 3302 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3303 3304 /* get first again */ 3305 td = xfer->td_transfer_first; 3306 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3307 3308 hcchar = 3309 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3310 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3311 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3312 HCCHAR_CHENA; 3313 3314 /* 3315 * We are not always able to meet the timing 3316 * requirements of the USB interrupt endpoint's 3317 * complete split token, when doing transfers going 3318 * via a transaction translator. Use the CONTROL 3319 * transfer type instead of the INTERRUPT transfer 3320 * type in general, as a means to workaround 3321 * that. This trick should work for both FULL and LOW 3322 * speed USB traffic going through a TT. For non-TT 3323 * traffic it works aswell. The reason for using 3324 * CONTROL type instead of BULK is that some TTs might 3325 * reject LOW speed BULK traffic. 3326 */ 3327 if (td->ep_type == UE_INTERRUPT) 3328 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3329 else 3330 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3331 3332 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3333 hcchar |= HCCHAR_LSPDDEV; 3334 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3335 hcchar |= HCCHAR_EPDIR_IN; 3336 3337 switch (xfer->xroot->udev->speed) { 3338 case USB_SPEED_FULL: 3339 case USB_SPEED_LOW: 3340 /* check if root HUB port is running High Speed */ 3341 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3342 hcsplt = HCSPLT_SPLTENA | 3343 (xfer->xroot->udev->hs_port_no << 3344 HCSPLT_PRTADDR_SHIFT) | 3345 (xfer->xroot->udev->hs_hub_addr << 3346 HCSPLT_HUBADDR_SHIFT); 3347 } else { 3348 hcsplt = 0; 3349 } 3350 if (td->ep_type == UE_INTERRUPT) { 3351 uint32_t ival; 3352 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3353 if (ival == 0) 3354 ival = 1; 3355 else if (ival > 127) 3356 ival = 127; 3357 td->tmr_val = sc->sc_tmr_val + ival; 3358 td->tmr_res = ival; 3359 } else if (td->ep_type == UE_ISOCHRONOUS) { 3360 td->tmr_res = 1; 3361 td->tmr_val = sc->sc_last_frame_num; 3362 if (td->hcchar & HCCHAR_EPDIR_IN) 3363 td->tmr_val++; 3364 } else { 3365 td->tmr_val = 0; 3366 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3367 } 3368 break; 3369 case USB_SPEED_HIGH: 3370 hcsplt = 0; 3371 if (td->ep_type == UE_INTERRUPT) { 3372 uint32_t ival; 3373 hcchar |= ((xfer->max_packet_count & 3) 3374 << HCCHAR_MC_SHIFT); 3375 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3376 if (ival == 0) 3377 ival = 1; 3378 else if (ival > 127) 3379 ival = 127; 3380 td->tmr_val = sc->sc_tmr_val + ival; 3381 td->tmr_res = ival; 3382 } else if (td->ep_type == UE_ISOCHRONOUS) { 3383 hcchar |= ((xfer->max_packet_count & 3) 3384 << HCCHAR_MC_SHIFT); 3385 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3386 td->tmr_val = sc->sc_last_frame_num; 3387 if (td->hcchar & HCCHAR_EPDIR_IN) 3388 td->tmr_val += td->tmr_res; 3389 3390 } else { 3391 td->tmr_val = 0; 3392 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3393 } 3394 break; 3395 default: 3396 hcsplt = 0; 3397 td->tmr_val = 0; 3398 td->tmr_res = 0; 3399 break; 3400 } 3401 3402 /* store configuration in all TD's */ 3403 while (1) { 3404 td->hcchar = hcchar; 3405 td->hcsplt = hcsplt; 3406 3407 if (((void *)td) == xfer->td_transfer_last) 3408 break; 3409 3410 td = td->obj_next; 3411 } 3412 } 3413 } 3414 3415 static void 3416 dwc_otg_timeout(void *arg) 3417 { 3418 struct usb_xfer *xfer = arg; 3419 3420 DPRINTF("xfer=%p\n", xfer); 3421 3422 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3423 3424 /* transfer is transferred */ 3425 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3426 } 3427 3428 static void 3429 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3430 { 3431 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3432 3433 DPRINTFN(9, "\n"); 3434 3435 /* 3436 * Poll one time in device mode, which will turn on the 3437 * endpoint interrupts. Else wait for SOF interrupt in host 3438 * mode. 3439 */ 3440 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3441 3442 if (sc->sc_flags.status_device_mode != 0) { 3443 dwc_otg_xfer_do_fifo(sc, xfer); 3444 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3445 goto done; 3446 } else { 3447 struct dwc_otg_td *td = xfer->td_transfer_cache; 3448 if (td->ep_type == UE_ISOCHRONOUS && 3449 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3450 /* 3451 * Need to start ISOCHRONOUS OUT transfer ASAP 3452 * because execution is delayed by one 125us 3453 * microframe: 3454 */ 3455 dwc_otg_xfer_do_fifo(sc, xfer); 3456 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3457 goto done; 3458 } 3459 } 3460 3461 /* put transfer on interrupt queue */ 3462 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3463 3464 /* start timeout, if any */ 3465 if (xfer->timeout != 0) { 3466 usbd_transfer_timeout_ms(xfer, 3467 &dwc_otg_timeout, xfer->timeout); 3468 } 3469 3470 if (sc->sc_flags.status_device_mode != 0) 3471 goto done; 3472 3473 /* enable SOF interrupt, if any */ 3474 dwc_otg_enable_sof_irq(sc); 3475 done: 3476 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3477 } 3478 3479 static void 3480 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3481 { 3482 DPRINTFN(9, "\n"); 3483 3484 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3485 3486 /* set port bit */ 3487 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3488 3489 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3490 sizeof(sc->sc_hub_idata)); 3491 } 3492 3493 static usb_error_t 3494 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3495 { 3496 struct dwc_otg_td *td; 3497 uint32_t len; 3498 usb_error_t error; 3499 3500 DPRINTFN(9, "\n"); 3501 3502 td = xfer->td_transfer_cache; 3503 3504 do { 3505 len = td->remainder; 3506 3507 /* store last data toggle */ 3508 xfer->endpoint->toggle_next = td->toggle; 3509 3510 if (xfer->aframes != xfer->nframes) { 3511 /* 3512 * Verify the length and subtract 3513 * the remainder from "frlengths[]": 3514 */ 3515 if (len > xfer->frlengths[xfer->aframes]) { 3516 td->error_any = 1; 3517 } else { 3518 xfer->frlengths[xfer->aframes] -= len; 3519 } 3520 } 3521 /* Check for transfer error */ 3522 if (td->error_any) { 3523 /* the transfer is finished */ 3524 error = (td->error_stall ? 3525 USB_ERR_STALLED : USB_ERR_IOERROR); 3526 td = NULL; 3527 break; 3528 } 3529 /* Check for short transfer */ 3530 if (len > 0) { 3531 if (xfer->flags_int.short_frames_ok || 3532 xfer->flags_int.isochronous_xfr) { 3533 /* follow alt next */ 3534 if (td->alt_next) { 3535 td = td->obj_next; 3536 } else { 3537 td = NULL; 3538 } 3539 } else { 3540 /* the transfer is finished */ 3541 td = NULL; 3542 } 3543 error = 0; 3544 break; 3545 } 3546 td = td->obj_next; 3547 3548 /* this USB frame is complete */ 3549 error = 0; 3550 break; 3551 3552 } while (0); 3553 3554 /* update transfer cache */ 3555 3556 xfer->td_transfer_cache = td; 3557 3558 return (error); 3559 } 3560 3561 static void 3562 dwc_otg_standard_done(struct usb_xfer *xfer) 3563 { 3564 usb_error_t err = 0; 3565 3566 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3567 xfer, xfer->endpoint); 3568 3569 /* reset scanner */ 3570 3571 xfer->td_transfer_cache = xfer->td_transfer_first; 3572 3573 if (xfer->flags_int.control_xfr) { 3574 3575 if (xfer->flags_int.control_hdr) { 3576 3577 err = dwc_otg_standard_done_sub(xfer); 3578 } 3579 xfer->aframes = 1; 3580 3581 if (xfer->td_transfer_cache == NULL) { 3582 goto done; 3583 } 3584 } 3585 while (xfer->aframes != xfer->nframes) { 3586 3587 err = dwc_otg_standard_done_sub(xfer); 3588 xfer->aframes++; 3589 3590 if (xfer->td_transfer_cache == NULL) { 3591 goto done; 3592 } 3593 } 3594 3595 if (xfer->flags_int.control_xfr && 3596 !xfer->flags_int.control_act) { 3597 3598 err = dwc_otg_standard_done_sub(xfer); 3599 } 3600 done: 3601 dwc_otg_device_done(xfer, err); 3602 } 3603 3604 /*------------------------------------------------------------------------* 3605 * dwc_otg_device_done 3606 * 3607 * NOTE: this function can be called more than one time on the 3608 * same USB transfer! 3609 *------------------------------------------------------------------------*/ 3610 static void 3611 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3612 { 3613 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3614 3615 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3616 xfer, xfer->endpoint, error); 3617 3618 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3619 3620 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3621 /* Interrupts are cleared by the interrupt handler */ 3622 } else { 3623 struct dwc_otg_td *td; 3624 3625 td = xfer->td_transfer_cache; 3626 if (td != NULL) 3627 dwc_otg_host_channel_free(sc, td); 3628 } 3629 /* dequeue transfer and start next transfer */ 3630 usbd_transfer_done(xfer, error); 3631 3632 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3633 } 3634 3635 static void 3636 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3637 { 3638 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3639 } 3640 3641 static void 3642 dwc_otg_set_stall(struct usb_device *udev, 3643 struct usb_endpoint *ep, uint8_t *did_stall) 3644 { 3645 struct dwc_otg_softc *sc; 3646 uint32_t temp; 3647 uint32_t reg; 3648 uint8_t ep_no; 3649 3650 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3651 3652 /* check mode */ 3653 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3654 /* not supported */ 3655 return; 3656 } 3657 3658 sc = DWC_OTG_BUS2SC(udev->bus); 3659 3660 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3661 3662 /* get endpoint address */ 3663 ep_no = ep->edesc->bEndpointAddress; 3664 3665 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3666 3667 if (ep_no & UE_DIR_IN) { 3668 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3669 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3670 } else { 3671 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3672 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3673 } 3674 3675 /* disable and stall endpoint */ 3676 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3677 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3678 3679 /* clear active OUT ep */ 3680 if (!(ep_no & UE_DIR_IN)) { 3681 3682 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3683 3684 if (sc->sc_last_rx_status != 0 && 3685 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3686 sc->sc_last_rx_status)) { 3687 /* dump data */ 3688 dwc_otg_common_rx_ack(sc); 3689 /* poll interrupt */ 3690 dwc_otg_interrupt_poll_locked(sc); 3691 dwc_otg_interrupt_complete_locked(sc); 3692 } 3693 } 3694 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3695 } 3696 3697 static void 3698 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3699 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3700 { 3701 uint32_t reg; 3702 uint32_t temp; 3703 3704 if (ep_type == UE_CONTROL) { 3705 /* clearing stall is not needed */ 3706 return; 3707 } 3708 3709 if (ep_dir) { 3710 reg = DOTG_DIEPCTL(ep_no); 3711 } else { 3712 reg = DOTG_DOEPCTL(ep_no); 3713 sc->sc_active_rx_ep |= (1U << ep_no); 3714 } 3715 3716 /* round up and mask away the multiplier count */ 3717 mps = (mps + 3) & 0x7FC; 3718 3719 if (ep_type == UE_BULK) { 3720 temp = DIEPCTL_EPTYPE_SET( 3721 DIEPCTL_EPTYPE_BULK) | 3722 DIEPCTL_USBACTEP; 3723 } else if (ep_type == UE_INTERRUPT) { 3724 temp = DIEPCTL_EPTYPE_SET( 3725 DIEPCTL_EPTYPE_INTERRUPT) | 3726 DIEPCTL_USBACTEP; 3727 } else { 3728 temp = DIEPCTL_EPTYPE_SET( 3729 DIEPCTL_EPTYPE_ISOC) | 3730 DIEPCTL_USBACTEP; 3731 } 3732 3733 temp |= DIEPCTL_MPS_SET(mps); 3734 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3735 3736 if (ep_dir) 3737 sc->sc_in_ctl[ep_no] = temp; 3738 else 3739 sc->sc_out_ctl[ep_no] = temp; 3740 3741 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3742 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3743 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3744 3745 /* we only reset the transmit FIFO */ 3746 if (ep_dir) { 3747 dwc_otg_tx_fifo_reset(sc, 3748 GRSTCTL_TXFIFO(ep_no) | 3749 GRSTCTL_TXFFLSH); 3750 3751 DWC_OTG_WRITE_4(sc, 3752 DOTG_DIEPTSIZ(ep_no), 0); 3753 } 3754 3755 /* poll interrupt */ 3756 dwc_otg_interrupt_poll_locked(sc); 3757 dwc_otg_interrupt_complete_locked(sc); 3758 } 3759 3760 static void 3761 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3762 { 3763 struct dwc_otg_softc *sc; 3764 struct usb_endpoint_descriptor *ed; 3765 3766 DPRINTFN(5, "endpoint=%p\n", ep); 3767 3768 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3769 3770 /* check mode */ 3771 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3772 /* not supported */ 3773 return; 3774 } 3775 /* get softc */ 3776 sc = DWC_OTG_BUS2SC(udev->bus); 3777 3778 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3779 3780 /* get endpoint descriptor */ 3781 ed = ep->edesc; 3782 3783 /* reset endpoint */ 3784 dwc_otg_clear_stall_sub_locked(sc, 3785 UGETW(ed->wMaxPacketSize), 3786 (ed->bEndpointAddress & UE_ADDR), 3787 (ed->bmAttributes & UE_XFERTYPE), 3788 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3789 3790 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3791 } 3792 3793 static void 3794 dwc_otg_device_state_change(struct usb_device *udev) 3795 { 3796 struct dwc_otg_softc *sc; 3797 uint8_t x; 3798 3799 /* check mode */ 3800 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3801 /* not supported */ 3802 return; 3803 } 3804 3805 /* get softc */ 3806 sc = DWC_OTG_BUS2SC(udev->bus); 3807 3808 /* deactivate all other endpoint but the control endpoint */ 3809 if (udev->state == USB_STATE_CONFIGURED || 3810 udev->state == USB_STATE_ADDRESSED) { 3811 3812 USB_BUS_LOCK(&sc->sc_bus); 3813 3814 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3815 3816 if (x < sc->sc_dev_in_ep_max) { 3817 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3818 DIEPCTL_EPDIS); 3819 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3820 } 3821 3822 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3823 DOEPCTL_EPDIS); 3824 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3825 } 3826 USB_BUS_UNLOCK(&sc->sc_bus); 3827 } 3828 } 3829 3830 int 3831 dwc_otg_init(struct dwc_otg_softc *sc) 3832 { 3833 uint32_t temp; 3834 3835 DPRINTF("start\n"); 3836 3837 /* set up the bus structure */ 3838 sc->sc_bus.usbrev = USB_REV_2_0; 3839 sc->sc_bus.methods = &dwc_otg_bus_methods; 3840 3841 usb_callout_init_mtx(&sc->sc_timer, 3842 &sc->sc_bus.bus_mtx, 0); 3843 3844 USB_BUS_LOCK(&sc->sc_bus); 3845 3846 /* turn on clocks */ 3847 dwc_otg_clocks_on(sc); 3848 3849 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3850 DPRINTF("Version = 0x%08x\n", temp); 3851 3852 /* disconnect */ 3853 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3854 DCTL_SFTDISCON); 3855 3856 /* wait for host to detect disconnect */ 3857 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3858 3859 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3860 GRSTCTL_CSFTRST); 3861 3862 /* wait a little bit for block to reset */ 3863 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3864 3865 switch (sc->sc_mode) { 3866 case DWC_MODE_DEVICE: 3867 temp = GUSBCFG_FORCEDEVMODE; 3868 break; 3869 case DWC_MODE_HOST: 3870 temp = GUSBCFG_FORCEHOSTMODE; 3871 break; 3872 default: 3873 temp = 0; 3874 break; 3875 } 3876 3877 /* select HSIC, ULPI or internal PHY mode */ 3878 switch (dwc_otg_phy_type) { 3879 case DWC_OTG_PHY_HSIC: 3880 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3881 GUSBCFG_PHYIF | 3882 GUSBCFG_TRD_TIM_SET(5) | temp); 3883 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3884 0x000000EC); 3885 3886 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3887 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3888 temp & ~GLPMCFG_HSIC_CONN); 3889 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3890 temp | GLPMCFG_HSIC_CONN); 3891 break; 3892 case DWC_OTG_PHY_ULPI: 3893 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3894 GUSBCFG_ULPI_UTMI_SEL | 3895 GUSBCFG_TRD_TIM_SET(5) | temp); 3896 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3897 3898 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3899 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3900 temp & ~GLPMCFG_HSIC_CONN); 3901 break; 3902 case DWC_OTG_PHY_INTERNAL: 3903 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3904 GUSBCFG_PHYSEL | 3905 GUSBCFG_TRD_TIM_SET(5) | temp); 3906 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3907 3908 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3909 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3910 temp & ~GLPMCFG_HSIC_CONN); 3911 3912 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3913 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3914 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3915 DOTG_GGPIO_PWRDWN); 3916 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3917 break; 3918 default: 3919 break; 3920 } 3921 3922 /* clear global nak */ 3923 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3924 DCTL_CGOUTNAK | 3925 DCTL_CGNPINNAK); 3926 3927 /* disable USB port */ 3928 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3929 3930 /* wait 10ms */ 3931 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3932 3933 /* enable USB port */ 3934 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3935 3936 /* wait 10ms */ 3937 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3938 3939 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3940 3941 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3942 3943 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3944 3945 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3946 3947 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3948 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3949 3950 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3951 3952 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3953 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3954 3955 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3956 3957 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3958 3959 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3960 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3961 sc->sc_host_ch_max); 3962 3963 /* setup FIFO */ 3964 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3965 USB_BUS_UNLOCK(&sc->sc_bus); 3966 return (EINVAL); 3967 } 3968 3969 /* enable interrupts */ 3970 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3971 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3972 3973 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3974 3975 /* enable all endpoint interrupts */ 3976 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3977 if (temp & GHWCFG2_MPI) { 3978 uint8_t x; 3979 3980 DPRINTF("Disable Multi Process Interrupts\n"); 3981 3982 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3983 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3984 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3985 } 3986 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 3987 } 3988 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3989 DIEPMSK_XFERCOMPLMSK); 3990 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3991 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3992 } 3993 3994 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3995 /* setup clocks */ 3996 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3997 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3998 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3999 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4000 } 4001 4002 /* only enable global IRQ */ 4003 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4004 GAHBCFG_GLBLINTRMSK); 4005 4006 /* turn off clocks */ 4007 dwc_otg_clocks_off(sc); 4008 4009 /* read initial VBUS state */ 4010 4011 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4012 4013 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4014 4015 dwc_otg_vbus_interrupt(sc, 4016 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4017 4018 USB_BUS_UNLOCK(&sc->sc_bus); 4019 4020 /* catch any lost interrupts */ 4021 4022 dwc_otg_do_poll(&sc->sc_bus); 4023 4024 return (0); /* success */ 4025 } 4026 4027 void 4028 dwc_otg_uninit(struct dwc_otg_softc *sc) 4029 { 4030 USB_BUS_LOCK(&sc->sc_bus); 4031 4032 /* stop host timer */ 4033 dwc_otg_timer_stop(sc); 4034 4035 /* set disconnect */ 4036 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4037 DCTL_SFTDISCON); 4038 4039 /* turn off global IRQ */ 4040 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4041 4042 sc->sc_flags.port_enabled = 0; 4043 sc->sc_flags.port_powered = 0; 4044 sc->sc_flags.status_vbus = 0; 4045 sc->sc_flags.status_bus_reset = 0; 4046 sc->sc_flags.status_suspend = 0; 4047 sc->sc_flags.change_suspend = 0; 4048 sc->sc_flags.change_connect = 1; 4049 4050 dwc_otg_pull_down(sc); 4051 dwc_otg_clocks_off(sc); 4052 4053 USB_BUS_UNLOCK(&sc->sc_bus); 4054 4055 usb_callout_drain(&sc->sc_timer); 4056 } 4057 4058 static void 4059 dwc_otg_suspend(struct dwc_otg_softc *sc) 4060 { 4061 return; 4062 } 4063 4064 static void 4065 dwc_otg_resume(struct dwc_otg_softc *sc) 4066 { 4067 return; 4068 } 4069 4070 static void 4071 dwc_otg_do_poll(struct usb_bus *bus) 4072 { 4073 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4074 4075 USB_BUS_LOCK(&sc->sc_bus); 4076 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4077 dwc_otg_interrupt_poll_locked(sc); 4078 dwc_otg_interrupt_complete_locked(sc); 4079 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4080 USB_BUS_UNLOCK(&sc->sc_bus); 4081 } 4082 4083 /*------------------------------------------------------------------------* 4084 * DWC OTG bulk support 4085 * DWC OTG control support 4086 * DWC OTG interrupt support 4087 *------------------------------------------------------------------------*/ 4088 static void 4089 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4090 { 4091 } 4092 4093 static void 4094 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4095 { 4096 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4097 } 4098 4099 static void 4100 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4101 { 4102 } 4103 4104 static void 4105 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4106 { 4107 /* setup TDs */ 4108 dwc_otg_setup_standard_chain(xfer); 4109 dwc_otg_start_standard_chain(xfer); 4110 } 4111 4112 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4113 { 4114 .open = dwc_otg_device_non_isoc_open, 4115 .close = dwc_otg_device_non_isoc_close, 4116 .enter = dwc_otg_device_non_isoc_enter, 4117 .start = dwc_otg_device_non_isoc_start, 4118 }; 4119 4120 /*------------------------------------------------------------------------* 4121 * DWC OTG full speed isochronous support 4122 *------------------------------------------------------------------------*/ 4123 static void 4124 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4125 { 4126 } 4127 4128 static void 4129 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4130 { 4131 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4132 } 4133 4134 static void 4135 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4136 { 4137 } 4138 4139 static void 4140 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4141 { 4142 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4143 uint32_t temp; 4144 uint32_t msframes; 4145 uint32_t framenum; 4146 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4147 4148 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4149 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4150 4151 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4152 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4153 4154 /* get the current frame index */ 4155 framenum = (temp & HFNUM_FRNUM_MASK); 4156 } else { 4157 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4158 4159 /* get the current frame index */ 4160 framenum = DSTS_SOFFN_GET(temp); 4161 } 4162 4163 if (xfer->xroot->udev->parent_hs_hub != NULL) 4164 framenum /= 8; 4165 4166 framenum &= DWC_OTG_FRAME_MASK; 4167 4168 /* 4169 * Compute number of milliseconds worth of data traffic for 4170 * this USB transfer: 4171 */ 4172 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4173 msframes = ((xfer->nframes << shift) + 7) / 8; 4174 else 4175 msframes = xfer->nframes; 4176 4177 /* 4178 * check if the frame index is within the window where the frames 4179 * will be inserted 4180 */ 4181 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4182 4183 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4184 /* 4185 * If there is data underflow or the pipe queue is 4186 * empty we schedule the transfer a few frames ahead 4187 * of the current frame position. Else two isochronous 4188 * transfers might overlap. 4189 */ 4190 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4191 xfer->endpoint->is_synced = 1; 4192 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4193 } 4194 /* 4195 * compute how many milliseconds the insertion is ahead of the 4196 * current frame position: 4197 */ 4198 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4199 4200 /* 4201 * pre-compute when the isochronous transfer will be finished: 4202 */ 4203 xfer->isoc_time_complete = 4204 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4205 4206 /* setup TDs */ 4207 dwc_otg_setup_standard_chain(xfer); 4208 4209 /* compute frame number for next insertion */ 4210 xfer->endpoint->isoc_next += msframes; 4211 4212 /* start TD chain */ 4213 dwc_otg_start_standard_chain(xfer); 4214 } 4215 4216 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4217 { 4218 .open = dwc_otg_device_isoc_open, 4219 .close = dwc_otg_device_isoc_close, 4220 .enter = dwc_otg_device_isoc_enter, 4221 .start = dwc_otg_device_isoc_start, 4222 }; 4223 4224 /*------------------------------------------------------------------------* 4225 * DWC OTG root control support 4226 *------------------------------------------------------------------------* 4227 * Simulate a hardware HUB by handling all the necessary requests. 4228 *------------------------------------------------------------------------*/ 4229 4230 static const struct usb_device_descriptor dwc_otg_devd = { 4231 .bLength = sizeof(struct usb_device_descriptor), 4232 .bDescriptorType = UDESC_DEVICE, 4233 .bcdUSB = {0x00, 0x02}, 4234 .bDeviceClass = UDCLASS_HUB, 4235 .bDeviceSubClass = UDSUBCLASS_HUB, 4236 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4237 .bMaxPacketSize = 64, 4238 .bcdDevice = {0x00, 0x01}, 4239 .iManufacturer = 1, 4240 .iProduct = 2, 4241 .bNumConfigurations = 1, 4242 }; 4243 4244 static const struct dwc_otg_config_desc dwc_otg_confd = { 4245 .confd = { 4246 .bLength = sizeof(struct usb_config_descriptor), 4247 .bDescriptorType = UDESC_CONFIG, 4248 .wTotalLength[0] = sizeof(dwc_otg_confd), 4249 .bNumInterface = 1, 4250 .bConfigurationValue = 1, 4251 .iConfiguration = 0, 4252 .bmAttributes = UC_SELF_POWERED, 4253 .bMaxPower = 0, 4254 }, 4255 .ifcd = { 4256 .bLength = sizeof(struct usb_interface_descriptor), 4257 .bDescriptorType = UDESC_INTERFACE, 4258 .bNumEndpoints = 1, 4259 .bInterfaceClass = UICLASS_HUB, 4260 .bInterfaceSubClass = UISUBCLASS_HUB, 4261 .bInterfaceProtocol = 0, 4262 }, 4263 .endpd = { 4264 .bLength = sizeof(struct usb_endpoint_descriptor), 4265 .bDescriptorType = UDESC_ENDPOINT, 4266 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4267 .bmAttributes = UE_INTERRUPT, 4268 .wMaxPacketSize[0] = 8, 4269 .bInterval = 255, 4270 }, 4271 }; 4272 4273 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4274 4275 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4276 .bDescLength = sizeof(dwc_otg_hubd), 4277 .bDescriptorType = UDESC_HUB, 4278 .bNbrPorts = 1, 4279 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4280 .bPwrOn2PwrGood = 50, 4281 .bHubContrCurrent = 0, 4282 .DeviceRemovable = {0}, /* port is removable */ 4283 }; 4284 4285 #define STRING_VENDOR \ 4286 "D\0W\0C\0O\0T\0G" 4287 4288 #define STRING_PRODUCT \ 4289 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4290 4291 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4292 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4293 4294 static usb_error_t 4295 dwc_otg_roothub_exec(struct usb_device *udev, 4296 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4297 { 4298 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4299 const void *ptr; 4300 uint16_t len; 4301 uint16_t value; 4302 uint16_t index; 4303 usb_error_t err; 4304 4305 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4306 4307 /* buffer reset */ 4308 ptr = (const void *)&sc->sc_hub_temp; 4309 len = 0; 4310 err = 0; 4311 4312 value = UGETW(req->wValue); 4313 index = UGETW(req->wIndex); 4314 4315 /* demultiplex the control request */ 4316 4317 switch (req->bmRequestType) { 4318 case UT_READ_DEVICE: 4319 switch (req->bRequest) { 4320 case UR_GET_DESCRIPTOR: 4321 goto tr_handle_get_descriptor; 4322 case UR_GET_CONFIG: 4323 goto tr_handle_get_config; 4324 case UR_GET_STATUS: 4325 goto tr_handle_get_status; 4326 default: 4327 goto tr_stalled; 4328 } 4329 break; 4330 4331 case UT_WRITE_DEVICE: 4332 switch (req->bRequest) { 4333 case UR_SET_ADDRESS: 4334 goto tr_handle_set_address; 4335 case UR_SET_CONFIG: 4336 goto tr_handle_set_config; 4337 case UR_CLEAR_FEATURE: 4338 goto tr_valid; /* nop */ 4339 case UR_SET_DESCRIPTOR: 4340 goto tr_valid; /* nop */ 4341 case UR_SET_FEATURE: 4342 default: 4343 goto tr_stalled; 4344 } 4345 break; 4346 4347 case UT_WRITE_ENDPOINT: 4348 switch (req->bRequest) { 4349 case UR_CLEAR_FEATURE: 4350 switch (UGETW(req->wValue)) { 4351 case UF_ENDPOINT_HALT: 4352 goto tr_handle_clear_halt; 4353 case UF_DEVICE_REMOTE_WAKEUP: 4354 goto tr_handle_clear_wakeup; 4355 default: 4356 goto tr_stalled; 4357 } 4358 break; 4359 case UR_SET_FEATURE: 4360 switch (UGETW(req->wValue)) { 4361 case UF_ENDPOINT_HALT: 4362 goto tr_handle_set_halt; 4363 case UF_DEVICE_REMOTE_WAKEUP: 4364 goto tr_handle_set_wakeup; 4365 default: 4366 goto tr_stalled; 4367 } 4368 break; 4369 case UR_SYNCH_FRAME: 4370 goto tr_valid; /* nop */ 4371 default: 4372 goto tr_stalled; 4373 } 4374 break; 4375 4376 case UT_READ_ENDPOINT: 4377 switch (req->bRequest) { 4378 case UR_GET_STATUS: 4379 goto tr_handle_get_ep_status; 4380 default: 4381 goto tr_stalled; 4382 } 4383 break; 4384 4385 case UT_WRITE_INTERFACE: 4386 switch (req->bRequest) { 4387 case UR_SET_INTERFACE: 4388 goto tr_handle_set_interface; 4389 case UR_CLEAR_FEATURE: 4390 goto tr_valid; /* nop */ 4391 case UR_SET_FEATURE: 4392 default: 4393 goto tr_stalled; 4394 } 4395 break; 4396 4397 case UT_READ_INTERFACE: 4398 switch (req->bRequest) { 4399 case UR_GET_INTERFACE: 4400 goto tr_handle_get_interface; 4401 case UR_GET_STATUS: 4402 goto tr_handle_get_iface_status; 4403 default: 4404 goto tr_stalled; 4405 } 4406 break; 4407 4408 case UT_WRITE_CLASS_INTERFACE: 4409 case UT_WRITE_VENDOR_INTERFACE: 4410 /* XXX forward */ 4411 break; 4412 4413 case UT_READ_CLASS_INTERFACE: 4414 case UT_READ_VENDOR_INTERFACE: 4415 /* XXX forward */ 4416 break; 4417 4418 case UT_WRITE_CLASS_DEVICE: 4419 switch (req->bRequest) { 4420 case UR_CLEAR_FEATURE: 4421 goto tr_valid; 4422 case UR_SET_DESCRIPTOR: 4423 case UR_SET_FEATURE: 4424 break; 4425 default: 4426 goto tr_stalled; 4427 } 4428 break; 4429 4430 case UT_WRITE_CLASS_OTHER: 4431 switch (req->bRequest) { 4432 case UR_CLEAR_FEATURE: 4433 goto tr_handle_clear_port_feature; 4434 case UR_SET_FEATURE: 4435 goto tr_handle_set_port_feature; 4436 case UR_CLEAR_TT_BUFFER: 4437 case UR_RESET_TT: 4438 case UR_STOP_TT: 4439 goto tr_valid; 4440 4441 default: 4442 goto tr_stalled; 4443 } 4444 break; 4445 4446 case UT_READ_CLASS_OTHER: 4447 switch (req->bRequest) { 4448 case UR_GET_TT_STATE: 4449 goto tr_handle_get_tt_state; 4450 case UR_GET_STATUS: 4451 goto tr_handle_get_port_status; 4452 default: 4453 goto tr_stalled; 4454 } 4455 break; 4456 4457 case UT_READ_CLASS_DEVICE: 4458 switch (req->bRequest) { 4459 case UR_GET_DESCRIPTOR: 4460 goto tr_handle_get_class_descriptor; 4461 case UR_GET_STATUS: 4462 goto tr_handle_get_class_status; 4463 4464 default: 4465 goto tr_stalled; 4466 } 4467 break; 4468 default: 4469 goto tr_stalled; 4470 } 4471 goto tr_valid; 4472 4473 tr_handle_get_descriptor: 4474 switch (value >> 8) { 4475 case UDESC_DEVICE: 4476 if (value & 0xff) { 4477 goto tr_stalled; 4478 } 4479 len = sizeof(dwc_otg_devd); 4480 ptr = (const void *)&dwc_otg_devd; 4481 goto tr_valid; 4482 case UDESC_CONFIG: 4483 if (value & 0xff) { 4484 goto tr_stalled; 4485 } 4486 len = sizeof(dwc_otg_confd); 4487 ptr = (const void *)&dwc_otg_confd; 4488 goto tr_valid; 4489 case UDESC_STRING: 4490 switch (value & 0xff) { 4491 case 0: /* Language table */ 4492 len = sizeof(usb_string_lang_en); 4493 ptr = (const void *)&usb_string_lang_en; 4494 goto tr_valid; 4495 4496 case 1: /* Vendor */ 4497 len = sizeof(dwc_otg_vendor); 4498 ptr = (const void *)&dwc_otg_vendor; 4499 goto tr_valid; 4500 4501 case 2: /* Product */ 4502 len = sizeof(dwc_otg_product); 4503 ptr = (const void *)&dwc_otg_product; 4504 goto tr_valid; 4505 default: 4506 break; 4507 } 4508 break; 4509 default: 4510 goto tr_stalled; 4511 } 4512 goto tr_stalled; 4513 4514 tr_handle_get_config: 4515 len = 1; 4516 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4517 goto tr_valid; 4518 4519 tr_handle_get_status: 4520 len = 2; 4521 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4522 goto tr_valid; 4523 4524 tr_handle_set_address: 4525 if (value & 0xFF00) { 4526 goto tr_stalled; 4527 } 4528 sc->sc_rt_addr = value; 4529 goto tr_valid; 4530 4531 tr_handle_set_config: 4532 if (value >= 2) { 4533 goto tr_stalled; 4534 } 4535 sc->sc_conf = value; 4536 goto tr_valid; 4537 4538 tr_handle_get_interface: 4539 len = 1; 4540 sc->sc_hub_temp.wValue[0] = 0; 4541 goto tr_valid; 4542 4543 tr_handle_get_tt_state: 4544 tr_handle_get_class_status: 4545 tr_handle_get_iface_status: 4546 tr_handle_get_ep_status: 4547 len = 2; 4548 USETW(sc->sc_hub_temp.wValue, 0); 4549 goto tr_valid; 4550 4551 tr_handle_set_halt: 4552 tr_handle_set_interface: 4553 tr_handle_set_wakeup: 4554 tr_handle_clear_wakeup: 4555 tr_handle_clear_halt: 4556 goto tr_valid; 4557 4558 tr_handle_clear_port_feature: 4559 if (index != 1) 4560 goto tr_stalled; 4561 4562 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4563 4564 switch (value) { 4565 case UHF_PORT_SUSPEND: 4566 dwc_otg_wakeup_peer(sc); 4567 break; 4568 4569 case UHF_PORT_ENABLE: 4570 if (sc->sc_flags.status_device_mode == 0) { 4571 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4572 sc->sc_hprt_val | HPRT_PRTENA); 4573 } 4574 sc->sc_flags.port_enabled = 0; 4575 break; 4576 4577 case UHF_C_PORT_RESET: 4578 sc->sc_flags.change_reset = 0; 4579 break; 4580 4581 case UHF_C_PORT_ENABLE: 4582 sc->sc_flags.change_enabled = 0; 4583 break; 4584 4585 case UHF_C_PORT_OVER_CURRENT: 4586 sc->sc_flags.change_over_current = 0; 4587 break; 4588 4589 case UHF_PORT_TEST: 4590 case UHF_PORT_INDICATOR: 4591 /* nops */ 4592 break; 4593 4594 case UHF_PORT_POWER: 4595 sc->sc_flags.port_powered = 0; 4596 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4597 sc->sc_hprt_val = 0; 4598 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4599 } 4600 dwc_otg_pull_down(sc); 4601 dwc_otg_clocks_off(sc); 4602 break; 4603 4604 case UHF_C_PORT_CONNECTION: 4605 /* clear connect change flag */ 4606 sc->sc_flags.change_connect = 0; 4607 break; 4608 4609 case UHF_C_PORT_SUSPEND: 4610 sc->sc_flags.change_suspend = 0; 4611 break; 4612 4613 default: 4614 err = USB_ERR_IOERROR; 4615 goto done; 4616 } 4617 goto tr_valid; 4618 4619 tr_handle_set_port_feature: 4620 if (index != 1) { 4621 goto tr_stalled; 4622 } 4623 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4624 4625 switch (value) { 4626 case UHF_PORT_ENABLE: 4627 break; 4628 4629 case UHF_PORT_SUSPEND: 4630 if (sc->sc_flags.status_device_mode == 0) { 4631 /* set suspend BIT */ 4632 sc->sc_hprt_val |= HPRT_PRTSUSP; 4633 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4634 4635 /* generate HUB suspend event */ 4636 dwc_otg_suspend_irq(sc); 4637 } 4638 break; 4639 4640 case UHF_PORT_RESET: 4641 if (sc->sc_flags.status_device_mode == 0) { 4642 4643 DPRINTF("PORT RESET\n"); 4644 4645 /* enable PORT reset */ 4646 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4647 4648 /* Wait 62.5ms for reset to complete */ 4649 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4650 4651 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4652 4653 /* Wait 62.5ms for reset to complete */ 4654 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4655 4656 /* reset FIFOs */ 4657 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4658 4659 sc->sc_flags.change_reset = 1; 4660 } else { 4661 err = USB_ERR_IOERROR; 4662 } 4663 break; 4664 4665 case UHF_PORT_TEST: 4666 case UHF_PORT_INDICATOR: 4667 /* nops */ 4668 break; 4669 case UHF_PORT_POWER: 4670 sc->sc_flags.port_powered = 1; 4671 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4672 sc->sc_hprt_val |= HPRT_PRTPWR; 4673 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4674 } 4675 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4676 /* pull up D+, if any */ 4677 dwc_otg_pull_up(sc); 4678 } 4679 break; 4680 default: 4681 err = USB_ERR_IOERROR; 4682 goto done; 4683 } 4684 goto tr_valid; 4685 4686 tr_handle_get_port_status: 4687 4688 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4689 4690 if (index != 1) 4691 goto tr_stalled; 4692 4693 if (sc->sc_flags.status_vbus) 4694 dwc_otg_clocks_on(sc); 4695 else 4696 dwc_otg_clocks_off(sc); 4697 4698 /* Select Device Side Mode */ 4699 4700 if (sc->sc_flags.status_device_mode) { 4701 value = UPS_PORT_MODE_DEVICE; 4702 dwc_otg_timer_stop(sc); 4703 } else { 4704 value = 0; 4705 dwc_otg_timer_start(sc); 4706 } 4707 4708 if (sc->sc_flags.status_high_speed) 4709 value |= UPS_HIGH_SPEED; 4710 else if (sc->sc_flags.status_low_speed) 4711 value |= UPS_LOW_SPEED; 4712 4713 if (sc->sc_flags.port_powered) 4714 value |= UPS_PORT_POWER; 4715 4716 if (sc->sc_flags.port_enabled) 4717 value |= UPS_PORT_ENABLED; 4718 4719 if (sc->sc_flags.port_over_current) 4720 value |= UPS_OVERCURRENT_INDICATOR; 4721 4722 if (sc->sc_flags.status_vbus && 4723 sc->sc_flags.status_bus_reset) 4724 value |= UPS_CURRENT_CONNECT_STATUS; 4725 4726 if (sc->sc_flags.status_suspend) 4727 value |= UPS_SUSPEND; 4728 4729 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4730 4731 value = 0; 4732 4733 if (sc->sc_flags.change_connect) 4734 value |= UPS_C_CONNECT_STATUS; 4735 if (sc->sc_flags.change_suspend) 4736 value |= UPS_C_SUSPEND; 4737 if (sc->sc_flags.change_reset) 4738 value |= UPS_C_PORT_RESET; 4739 if (sc->sc_flags.change_over_current) 4740 value |= UPS_C_OVERCURRENT_INDICATOR; 4741 4742 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4743 len = sizeof(sc->sc_hub_temp.ps); 4744 goto tr_valid; 4745 4746 tr_handle_get_class_descriptor: 4747 if (value & 0xFF) { 4748 goto tr_stalled; 4749 } 4750 ptr = (const void *)&dwc_otg_hubd; 4751 len = sizeof(dwc_otg_hubd); 4752 goto tr_valid; 4753 4754 tr_stalled: 4755 err = USB_ERR_STALLED; 4756 tr_valid: 4757 done: 4758 *plength = len; 4759 *pptr = ptr; 4760 return (err); 4761 } 4762 4763 static void 4764 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4765 { 4766 struct usb_xfer *xfer; 4767 void *last_obj; 4768 uint32_t ntd; 4769 uint32_t n; 4770 uint8_t ep_no; 4771 uint8_t ep_type; 4772 4773 xfer = parm->curr_xfer; 4774 4775 /* 4776 * NOTE: This driver does not use any of the parameters that 4777 * are computed from the following values. Just set some 4778 * reasonable dummies: 4779 */ 4780 parm->hc_max_packet_size = 0x500; 4781 parm->hc_max_packet_count = 3; 4782 parm->hc_max_frame_size = 3 * 0x500; 4783 4784 usbd_transfer_setup_sub(parm); 4785 4786 /* 4787 * compute maximum number of TDs 4788 */ 4789 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4790 4791 if (ep_type == UE_CONTROL) { 4792 4793 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4794 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4795 } else { 4796 4797 ntd = xfer->nframes + 1 /* SYNC */ ; 4798 } 4799 4800 /* 4801 * check if "usbd_transfer_setup_sub" set an error 4802 */ 4803 if (parm->err) 4804 return; 4805 4806 /* 4807 * allocate transfer descriptors 4808 */ 4809 last_obj = NULL; 4810 4811 ep_no = xfer->endpointno & UE_ADDR; 4812 4813 /* 4814 * Check for a valid endpoint profile in USB device mode: 4815 */ 4816 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4817 const struct usb_hw_ep_profile *pf; 4818 4819 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4820 4821 if (pf == NULL) { 4822 /* should not happen */ 4823 parm->err = USB_ERR_INVAL; 4824 return; 4825 } 4826 } 4827 4828 /* align data */ 4829 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4830 4831 for (n = 0; n != ntd; n++) { 4832 4833 struct dwc_otg_td *td; 4834 4835 if (parm->buf) { 4836 4837 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4838 4839 /* compute shared bandwidth resource index for TT */ 4840 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4841 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4842 td->tt_index = parm->udev->device_index; 4843 else 4844 td->tt_index = parm->udev->parent_hs_hub->device_index; 4845 } else { 4846 td->tt_index = parm->udev->device_index; 4847 } 4848 4849 /* init TD */ 4850 td->max_packet_size = xfer->max_packet_size; 4851 td->max_packet_count = xfer->max_packet_count; 4852 /* range check */ 4853 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4854 td->max_packet_count = 1; 4855 td->ep_no = ep_no; 4856 td->ep_type = ep_type; 4857 td->obj_next = last_obj; 4858 4859 last_obj = td; 4860 } 4861 parm->size[0] += sizeof(*td); 4862 } 4863 4864 xfer->td_start[0] = last_obj; 4865 } 4866 4867 static void 4868 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4869 { 4870 return; 4871 } 4872 4873 static void 4874 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4875 struct usb_endpoint *ep) 4876 { 4877 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4878 4879 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4880 ep, udev->address, 4881 edesc->bEndpointAddress, udev->flags.usb_mode, 4882 sc->sc_rt_addr, udev->device_index); 4883 4884 if (udev->device_index != sc->sc_rt_addr) { 4885 4886 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4887 if (udev->speed != USB_SPEED_FULL && 4888 udev->speed != USB_SPEED_HIGH) { 4889 /* not supported */ 4890 return; 4891 } 4892 } else { 4893 if (udev->speed == USB_SPEED_HIGH && 4894 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4895 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4896 /* not supported */ 4897 DPRINTFN(-1, "Non-isochronous high bandwidth " 4898 "endpoint not supported\n"); 4899 return; 4900 } 4901 } 4902 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4903 ep->methods = &dwc_otg_device_isoc_methods; 4904 else 4905 ep->methods = &dwc_otg_device_non_isoc_methods; 4906 } 4907 } 4908 4909 static void 4910 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4911 { 4912 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4913 4914 switch (state) { 4915 case USB_HW_POWER_SUSPEND: 4916 dwc_otg_suspend(sc); 4917 break; 4918 case USB_HW_POWER_SHUTDOWN: 4919 dwc_otg_uninit(sc); 4920 break; 4921 case USB_HW_POWER_RESUME: 4922 dwc_otg_resume(sc); 4923 break; 4924 default: 4925 break; 4926 } 4927 } 4928 4929 static void 4930 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4931 { 4932 /* DMA delay - wait until any use of memory is finished */ 4933 *pus = (2125); /* microseconds */ 4934 } 4935 4936 static void 4937 dwc_otg_device_resume(struct usb_device *udev) 4938 { 4939 DPRINTF("\n"); 4940 4941 /* poll all transfers again to restart resumed ones */ 4942 dwc_otg_do_poll(udev->bus); 4943 } 4944 4945 static void 4946 dwc_otg_device_suspend(struct usb_device *udev) 4947 { 4948 DPRINTF("\n"); 4949 } 4950 4951 static const struct usb_bus_methods dwc_otg_bus_methods = 4952 { 4953 .endpoint_init = &dwc_otg_ep_init, 4954 .xfer_setup = &dwc_otg_xfer_setup, 4955 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4956 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4957 .xfer_stall = &dwc_otg_xfer_stall, 4958 .set_stall = &dwc_otg_set_stall, 4959 .clear_stall = &dwc_otg_clear_stall, 4960 .roothub_exec = &dwc_otg_roothub_exec, 4961 .xfer_poll = &dwc_otg_do_poll, 4962 .device_state_change = &dwc_otg_device_state_change, 4963 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4964 .get_dma_delay = &dwc_otg_get_dma_delay, 4965 .device_resume = &dwc_otg_device_resume, 4966 .device_suspend = &dwc_otg_device_suspend, 4967 }; 4968