1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_ENABLED \ 97 (GINTMSK_ENUMDONEMSK | \ 98 GINTMSK_USBRSTMSK | \ 99 GINTMSK_USBSUSPMSK | \ 100 GINTMSK_IEPINTMSK | \ 101 GINTMSK_SESSREQINTMSK | \ 102 GINTMSK_RXFLVLMSK | \ 103 GINTMSK_HCHINTMSK | \ 104 GINTMSK_OTGINTMSK | \ 105 GINTMSK_PRTINTMSK) 106 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 108 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 109 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 110 GINTSTS_SESSREQINT) 111 112 #define DWC_OTG_PHY_ULPI 0 113 #define DWC_OTG_PHY_HSIC 1 114 #define DWC_OTG_PHY_INTERNAL 2 115 116 #ifndef DWC_OTG_PHY_DEFAULT 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 118 #endif 119 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 121 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 124 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 125 126 #ifdef USB_DEBUG 127 static int dwc_otg_debug; 128 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 130 &dwc_otg_debug, 0, "DWC OTG debug level"); 131 #endif 132 133 #define DWC_OTG_INTR_ENDPT 1 134 135 /* prototypes */ 136 137 static const struct usb_bus_methods dwc_otg_bus_methods; 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 140 141 static dwc_otg_cmd_t dwc_otg_setup_rx; 142 static dwc_otg_cmd_t dwc_otg_data_rx; 143 static dwc_otg_cmd_t dwc_otg_data_tx; 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 145 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_tx; 148 static dwc_otg_cmd_t dwc_otg_host_data_rx; 149 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 151 static void dwc_otg_do_poll(struct usb_bus *); 152 static void dwc_otg_standard_done(struct usb_xfer *); 153 static void dwc_otg_root_intr(struct dwc_otg_softc *); 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static void 184 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 185 { 186 uint32_t temp; 187 188 /* reset FIFO */ 189 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 190 191 /* wait for reset to complete */ 192 for (temp = 0; temp != 16; temp++) { 193 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 194 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 195 break; 196 } 197 } 198 199 static int 200 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 201 { 202 struct dwc_otg_profile *pf; 203 uint32_t fifo_size; 204 uint32_t fifo_regs; 205 uint32_t tx_start; 206 uint8_t x; 207 208 fifo_size = sc->sc_fifo_size; 209 210 /* 211 * NOTE: Reserved fixed size area at end of RAM, which must 212 * not be allocated to the FIFOs: 213 */ 214 fifo_regs = 4 * 16; 215 216 if (fifo_size < fifo_regs) { 217 DPRINTF("Too little FIFO\n"); 218 return (EINVAL); 219 } 220 221 /* subtract FIFO regs from total once */ 222 fifo_size -= fifo_regs; 223 224 /* split equally for IN and OUT */ 225 fifo_size /= 2; 226 227 /* Align to 4 bytes boundary (refer to PGM) */ 228 fifo_size &= ~3; 229 230 /* set global receive FIFO size */ 231 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 232 233 tx_start = fifo_size; 234 235 if (fifo_size < 64) { 236 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 237 return (EINVAL); 238 } 239 240 if (mode == DWC_MODE_HOST) { 241 242 /* reset active endpoints */ 243 sc->sc_active_rx_ep = 0; 244 245 /* split equally for periodic and non-periodic */ 246 fifo_size /= 2; 247 248 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 249 250 /* align to 4 bytes boundary */ 251 fifo_size &= ~3; 252 253 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 254 ((fifo_size / 4) << 16) | 255 (tx_start / 4)); 256 257 tx_start += fifo_size; 258 259 for (x = 0; x != sc->sc_host_ch_max; x++) { 260 /* enable all host interrupts */ 261 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 262 HCINT_DEFAULT_MASK); 263 } 264 265 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 266 ((fifo_size / 4) << 16) | 267 (tx_start / 4)); 268 269 /* reset host channel state */ 270 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 271 272 /* enable all host channel interrupts */ 273 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 274 (1U << sc->sc_host_ch_max) - 1U); 275 } 276 277 if (mode == DWC_MODE_DEVICE) { 278 279 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 280 (0x10 << 16) | (tx_start / 4)); 281 fifo_size -= 0x40; 282 tx_start += 0x40; 283 284 /* setup control endpoint profile */ 285 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 286 287 /* reset active endpoints */ 288 sc->sc_active_rx_ep = 1; 289 290 for (x = 1; x != sc->sc_dev_ep_max; x++) { 291 292 pf = sc->sc_hw_ep_profile + x; 293 294 pf->usb.max_out_frame_size = 1024 * 3; 295 pf->usb.is_simplex = 0; /* assume duplex */ 296 pf->usb.support_bulk = 1; 297 pf->usb.support_interrupt = 1; 298 pf->usb.support_isochronous = 1; 299 pf->usb.support_out = 1; 300 301 if (x < sc->sc_dev_in_ep_max) { 302 uint32_t limit; 303 304 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 305 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 306 DWC_OTG_TX_MAX_FIFO_SIZE); 307 308 /* see if there is enough FIFO space */ 309 if (limit <= fifo_size) { 310 pf->max_buffer = limit; 311 pf->usb.support_in = 1; 312 } else { 313 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 314 if (limit <= fifo_size) { 315 pf->usb.support_in = 1; 316 } else { 317 pf->usb.is_simplex = 1; 318 limit = 0; 319 } 320 } 321 /* set FIFO size */ 322 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 323 ((limit / 4) << 16) | (tx_start / 4)); 324 tx_start += limit; 325 fifo_size -= limit; 326 pf->usb.max_in_frame_size = limit; 327 } else { 328 pf->usb.is_simplex = 1; 329 } 330 331 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 332 pf->usb.max_in_frame_size, 333 pf->usb.max_out_frame_size); 334 } 335 } 336 337 /* reset RX FIFO */ 338 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 339 340 if (mode != DWC_MODE_OTG) { 341 /* reset all TX FIFOs */ 342 dwc_otg_tx_fifo_reset(sc, 343 GRSTCTL_TXFIFO(0x10) | 344 GRSTCTL_TXFFLSH); 345 } else { 346 /* reset active endpoints */ 347 sc->sc_active_rx_ep = 0; 348 349 /* reset host channel state */ 350 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 351 } 352 return (0); 353 } 354 355 static void 356 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 357 { 358 359 /* 360 * Disabled until further. Assuming that the register is already 361 * programmed correctly by the boot loader. 362 */ 363 #if 0 364 uint32_t temp; 365 366 /* setup HOST frame interval register, based on existing value */ 367 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 368 if (temp >= 10000) 369 temp /= 1000; 370 else 371 temp /= 125; 372 373 /* figure out nearest X-tal value */ 374 if (temp >= 54) 375 temp = 60; /* MHz */ 376 else if (temp >= 39) 377 temp = 48; /* MHz */ 378 else 379 temp = 30; /* MHz */ 380 381 if (sc->sc_flags.status_high_speed) 382 temp *= 125; 383 else 384 temp *= 1000; 385 386 DPRINTF("HFIR=0x%08x\n", temp); 387 388 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 389 #endif 390 } 391 392 static void 393 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 394 { 395 if (sc->sc_flags.clocks_off && 396 sc->sc_flags.port_powered) { 397 398 DPRINTFN(5, "\n"); 399 400 /* TODO - platform specific */ 401 402 sc->sc_flags.clocks_off = 0; 403 } 404 } 405 406 static void 407 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 408 { 409 if (!sc->sc_flags.clocks_off) { 410 411 DPRINTFN(5, "\n"); 412 413 /* TODO - platform specific */ 414 415 sc->sc_flags.clocks_off = 1; 416 } 417 } 418 419 static void 420 dwc_otg_pull_up(struct dwc_otg_softc *sc) 421 { 422 uint32_t temp; 423 424 /* pullup D+, if possible */ 425 426 if (!sc->sc_flags.d_pulled_up && 427 sc->sc_flags.port_powered) { 428 sc->sc_flags.d_pulled_up = 1; 429 430 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 431 temp &= ~DCTL_SFTDISCON; 432 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 433 } 434 } 435 436 static void 437 dwc_otg_pull_down(struct dwc_otg_softc *sc) 438 { 439 uint32_t temp; 440 441 /* pulldown D+, if possible */ 442 443 if (sc->sc_flags.d_pulled_up) { 444 sc->sc_flags.d_pulled_up = 0; 445 446 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 447 temp |= DCTL_SFTDISCON; 448 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 449 } 450 } 451 452 static void 453 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 454 { 455 /* In device mode we don't use the SOF interrupt */ 456 if (sc->sc_flags.status_device_mode != 0) 457 return; 458 /* Ensure the SOF interrupt is not disabled */ 459 sc->sc_needsof = 1; 460 /* Check if the SOF interrupt is already enabled */ 461 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 462 return; 463 sc->sc_irq_mask |= GINTMSK_SOFMSK; 464 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 465 } 466 467 static void 468 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 469 { 470 if (sc->sc_flags.status_suspend) { 471 /* update status bits */ 472 sc->sc_flags.status_suspend = 0; 473 sc->sc_flags.change_suspend = 1; 474 475 if (sc->sc_flags.status_device_mode) { 476 /* 477 * Disable resume interrupt and enable suspend 478 * interrupt: 479 */ 480 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 481 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 482 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 483 } 484 485 /* complete root HUB interrupt endpoint */ 486 dwc_otg_root_intr(sc); 487 } 488 } 489 490 static void 491 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 492 { 493 if (!sc->sc_flags.status_suspend) { 494 /* update status bits */ 495 sc->sc_flags.status_suspend = 1; 496 sc->sc_flags.change_suspend = 1; 497 498 if (sc->sc_flags.status_device_mode) { 499 /* 500 * Disable suspend interrupt and enable resume 501 * interrupt: 502 */ 503 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 504 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 505 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 506 } 507 508 /* complete root HUB interrupt endpoint */ 509 dwc_otg_root_intr(sc); 510 } 511 } 512 513 static void 514 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 515 { 516 if (!sc->sc_flags.status_suspend) 517 return; 518 519 DPRINTFN(5, "Remote wakeup\n"); 520 521 if (sc->sc_flags.status_device_mode) { 522 uint32_t temp; 523 524 /* enable remote wakeup signalling */ 525 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 526 temp |= DCTL_RMTWKUPSIG; 527 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 528 529 /* Wait 8ms for remote wakeup to complete. */ 530 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 531 532 temp &= ~DCTL_RMTWKUPSIG; 533 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 534 } else { 535 /* enable USB port */ 536 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 537 538 /* wait 10ms */ 539 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 540 541 /* resume port */ 542 sc->sc_hprt_val |= HPRT_PRTRES; 543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 544 545 /* Wait 100ms for resume signalling to complete. */ 546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 547 548 /* clear suspend and resume */ 549 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 550 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 551 552 /* Wait 4ms */ 553 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 554 } 555 556 /* need to fake resume IRQ */ 557 dwc_otg_resume_irq(sc); 558 } 559 560 static void 561 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 562 { 563 uint32_t temp; 564 565 DPRINTFN(5, "addr=%d\n", addr); 566 567 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 568 temp &= ~DCFG_DEVADDR_SET(0x7F); 569 temp |= DCFG_DEVADDR_SET(addr); 570 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 571 } 572 573 static void 574 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 575 { 576 DPRINTFN(5, "RX status clear\n"); 577 578 /* enable RX FIFO level interrupt */ 579 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 580 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 581 582 /* clear cached status */ 583 sc->sc_last_rx_status = 0; 584 } 585 586 static void 587 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 588 { 589 uint32_t hcint; 590 591 /* clear all pending interrupts */ 592 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 593 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 594 595 /* clear buffered interrupts */ 596 sc->sc_chan_state[x].hcint = 0; 597 } 598 599 static uint8_t 600 dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 601 { 602 uint32_t temp; 603 604 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 605 606 if (td->ep_type == UE_INTERRUPT || 607 td->ep_type == UE_ISOCHRONOUS) { 608 if (!(temp & GINTSTS_PTXFEMP)) { 609 DPRINTF("Periodic TX FIFO is not empty\n"); 610 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 611 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 612 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 613 } 614 return (1); /* busy */ 615 } 616 } else { 617 if (!(temp & GINTSTS_NPTXFEMP)) { 618 DPRINTF("Non-periodic TX FIFO is not empty\n"); 619 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 620 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 621 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 622 } 623 return (1); /* busy */ 624 } 625 } 626 return (0); /* ready for transmit */ 627 } 628 629 static uint8_t 630 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 631 struct dwc_otg_td *td, uint8_t is_out) 632 { 633 uint8_t x; 634 635 if (td->channel < DWC_OTG_MAX_CHANNELS) 636 return (0); /* already allocated */ 637 638 /* check if device is suspended */ 639 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 640 return (1); /* busy - cannot transfer data */ 641 642 /* compute needed TX FIFO size */ 643 if (is_out != 0) { 644 if (dwc_otg_host_check_fifo_empty(sc, td) != 0) 645 return (1); /* busy - cannot transfer data */ 646 } 647 648 for (x = 0; x != sc->sc_host_ch_max; x++) { 649 /* check if channel is allocated */ 650 if (sc->sc_chan_state[x].allocated != 0) 651 continue; 652 /* check if channel is still enabled */ 653 if (sc->sc_chan_state[x].wait_halted != 0) 654 continue; 655 656 sc->sc_chan_state[x].allocated = 1; 657 658 /* clear interrupts */ 659 dwc_otg_clear_hcint(sc, x); 660 661 DPRINTF("CH=%d HCCHAR=0x%08x " 662 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 663 664 /* set active channel */ 665 sc->sc_active_rx_ep |= (1 << x); 666 667 /* set channel */ 668 td->channel = x; 669 670 return (0); /* allocated */ 671 } 672 /* wait a bit */ 673 dwc_otg_enable_sof_irq(sc); 674 return (1); /* busy */ 675 } 676 677 static void 678 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 679 { 680 uint32_t hcchar; 681 uint8_t x; 682 683 if (td->channel >= DWC_OTG_MAX_CHANNELS) 684 return; /* already freed */ 685 686 /* free channel */ 687 x = td->channel; 688 td->channel = DWC_OTG_MAX_CHANNELS; 689 690 DPRINTF("CH=%d\n", x); 691 692 /* 693 * We need to let programmed host channels run till complete 694 * else the host channel will stop functioning. 695 */ 696 sc->sc_chan_state[x].allocated = 0; 697 698 /* ack any pending messages */ 699 if (sc->sc_last_rx_status != 0 && 700 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 701 dwc_otg_common_rx_ack(sc); 702 } 703 704 /* clear active channel */ 705 sc->sc_active_rx_ep &= ~(1 << x); 706 707 /* disable host channel */ 708 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 709 if (hcchar & HCCHAR_CHENA) { 710 DPRINTF("Halting channel %d\n", x); 711 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 712 hcchar | HCCHAR_CHDIS); 713 sc->sc_chan_state[x].wait_halted = 1; 714 /* don't write HCCHAR until the channel is halted */ 715 } 716 } 717 718 static void 719 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 720 { 721 /* dump any pending messages */ 722 if (sc->sc_last_rx_status != 0) { 723 if (td->channel < DWC_OTG_MAX_CHANNELS && 724 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 725 dwc_otg_common_rx_ack(sc); 726 } 727 } 728 } 729 730 static uint8_t 731 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 732 { 733 struct usb_device_request req __aligned(4); 734 uint32_t hcint; 735 uint32_t hcchar; 736 uint8_t delta; 737 738 dwc_otg_host_dump_rx(sc, td); 739 740 if (td->channel < DWC_OTG_MAX_CHANNELS) { 741 hcint = sc->sc_chan_state[td->channel].hcint; 742 743 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 744 td->channel, td->state, hcint, 745 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 746 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 747 } else { 748 hcint = 0; 749 goto check_state; 750 } 751 752 if (hcint & (HCINT_RETRY | 753 HCINT_ACK | HCINT_NYET)) { 754 /* give success bits priority over failure bits */ 755 } else if (hcint & HCINT_STALL) { 756 DPRINTF("CH=%d STALL\n", td->channel); 757 td->error_stall = 1; 758 td->error_any = 1; 759 goto complete; 760 } else if (hcint & HCINT_ERRORS) { 761 DPRINTF("CH=%d ERROR\n", td->channel); 762 td->errcnt++; 763 if (td->hcsplt != 0 || td->errcnt >= 3) { 764 td->error_any = 1; 765 goto complete; 766 } 767 } 768 769 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 770 HCINT_ACK | HCINT_NYET)) { 771 if (!(hcint & HCINT_ERRORS)) 772 td->errcnt = 0; 773 } 774 775 check_state: 776 switch (td->state) { 777 case DWC_CHAN_ST_START: 778 goto send_pkt; 779 780 case DWC_CHAN_ST_WAIT_ANE: 781 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 782 td->did_nak = 1; 783 td->tt_scheduled = 0; 784 goto send_pkt; 785 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 786 td->offset += td->tx_bytes; 787 td->remainder -= td->tx_bytes; 788 td->toggle = 1; 789 td->tt_scheduled = 0; 790 goto complete; 791 } 792 break; 793 794 case DWC_CHAN_ST_WAIT_S_ANE: 795 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 796 td->did_nak = 1; 797 td->tt_scheduled = 0; 798 goto send_pkt; 799 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 800 goto send_cpkt; 801 } 802 break; 803 804 case DWC_CHAN_ST_WAIT_C_ANE: 805 if (hcint & HCINT_NYET) { 806 goto send_cpkt; 807 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 808 td->did_nak = 1; 809 td->tt_scheduled = 0; 810 goto send_pkt; 811 } else if (hcint & HCINT_ACK) { 812 td->offset += td->tx_bytes; 813 td->remainder -= td->tx_bytes; 814 td->toggle = 1; 815 goto complete; 816 } 817 break; 818 819 case DWC_CHAN_ST_WAIT_C_PKT: 820 goto send_cpkt; 821 822 default: 823 break; 824 } 825 goto busy; 826 827 send_pkt: 828 /* free existing channel, if any */ 829 dwc_otg_host_channel_free(sc, td); 830 831 if (sizeof(req) != td->remainder) { 832 td->error_any = 1; 833 goto complete; 834 } 835 836 if (td->hcsplt != 0) { 837 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 838 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 839 td->state = DWC_CHAN_ST_START; 840 goto busy; 841 } 842 delta = sc->sc_last_frame_num - td->tt_start_slot; 843 if (delta > 5) { 844 /* missed it */ 845 td->tt_scheduled = 0; 846 td->state = DWC_CHAN_ST_START; 847 goto busy; 848 } 849 } 850 851 /* allocate a new channel */ 852 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 853 td->state = DWC_CHAN_ST_START; 854 goto busy; 855 } 856 857 if (td->hcsplt != 0) { 858 td->hcsplt &= ~HCSPLT_COMPSPLT; 859 td->state = DWC_CHAN_ST_WAIT_S_ANE; 860 } else { 861 td->state = DWC_CHAN_ST_WAIT_ANE; 862 } 863 864 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 865 866 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 867 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 868 (1 << HCTSIZ_PKTCNT_SHIFT) | 869 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 870 871 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 872 873 hcchar = td->hcchar; 874 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 875 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 876 877 /* must enable channel before writing data to FIFO */ 878 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 879 880 /* transfer data into FIFO */ 881 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 882 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 883 884 /* wait until next slot before trying complete split */ 885 td->tt_complete_slot = sc->sc_last_frame_num + 1; 886 887 /* store number of bytes transmitted */ 888 td->tx_bytes = sizeof(req); 889 goto busy; 890 891 send_cpkt: 892 /* free existing channel, if any */ 893 dwc_otg_host_channel_free(sc, td); 894 895 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 896 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 897 td->state = DWC_CHAN_ST_WAIT_C_PKT; 898 goto busy; 899 } 900 delta = sc->sc_last_frame_num - td->tt_start_slot; 901 if (delta > DWC_OTG_TT_SLOT_MAX) { 902 /* we missed the service interval */ 903 if (td->ep_type != UE_ISOCHRONOUS) 904 td->error_any = 1; 905 goto complete; 906 } 907 /* allocate a new channel */ 908 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 909 td->state = DWC_CHAN_ST_WAIT_C_PKT; 910 goto busy; 911 } 912 913 /* wait until next slot before trying complete split */ 914 td->tt_complete_slot = sc->sc_last_frame_num + 1; 915 916 td->hcsplt |= HCSPLT_COMPSPLT; 917 td->state = DWC_CHAN_ST_WAIT_C_ANE; 918 919 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 920 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 921 922 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 923 924 hcchar = td->hcchar; 925 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 926 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 927 928 /* must enable channel before writing data to FIFO */ 929 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 930 931 busy: 932 return (1); /* busy */ 933 934 complete: 935 dwc_otg_host_channel_free(sc, td); 936 return (0); /* complete */ 937 } 938 939 static uint8_t 940 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 941 { 942 struct usb_device_request req __aligned(4); 943 uint32_t temp; 944 uint16_t count; 945 946 /* check endpoint status */ 947 948 if (sc->sc_last_rx_status == 0) 949 goto not_complete; 950 951 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 952 goto not_complete; 953 954 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 955 GRXSTSRD_STP_DATA) { 956 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 957 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 958 /* release FIFO */ 959 dwc_otg_common_rx_ack(sc); 960 goto not_complete; 961 } 962 /* release FIFO */ 963 dwc_otg_common_rx_ack(sc); 964 return (0); /* complete */ 965 } 966 967 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 968 GRXSTSRD_DPID_DATA0) { 969 /* release FIFO */ 970 dwc_otg_common_rx_ack(sc); 971 goto not_complete; 972 } 973 974 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 975 976 /* clear did stall */ 977 td->did_stall = 0; 978 979 /* get the packet byte count */ 980 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 981 982 if (count != sizeof(req)) { 983 DPRINTFN(0, "Unsupported SETUP packet " 984 "length, %d bytes\n", count); 985 /* release FIFO */ 986 dwc_otg_common_rx_ack(sc); 987 goto not_complete; 988 } 989 990 /* copy in control request */ 991 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 992 993 /* copy data into real buffer */ 994 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 995 996 td->offset = sizeof(req); 997 td->remainder = 0; 998 999 /* sneak peek the set address */ 1000 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1001 (req.bRequest == UR_SET_ADDRESS)) { 1002 /* must write address before ZLP */ 1003 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1004 } 1005 1006 /* don't send any data by default */ 1007 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1008 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1009 1010 /* reset IN endpoint buffer */ 1011 dwc_otg_tx_fifo_reset(sc, 1012 GRSTCTL_TXFIFO(0) | 1013 GRSTCTL_TXFFLSH); 1014 1015 /* acknowledge RX status */ 1016 dwc_otg_common_rx_ack(sc); 1017 td->did_stall = 1; 1018 1019 not_complete: 1020 /* abort any ongoing transfer, before enabling again */ 1021 if (!td->did_stall) { 1022 td->did_stall = 1; 1023 1024 DPRINTFN(5, "stalling IN and OUT direction\n"); 1025 1026 temp = sc->sc_out_ctl[0]; 1027 1028 /* set stall after enabling endpoint */ 1029 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1030 temp | DOEPCTL_STALL); 1031 1032 temp = sc->sc_in_ctl[0]; 1033 1034 /* set stall assuming endpoint is enabled */ 1035 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1036 temp | DIEPCTL_STALL); 1037 } 1038 return (1); /* not complete */ 1039 } 1040 1041 static uint8_t 1042 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1043 { 1044 uint8_t delta; 1045 1046 delta = sc->sc_tmr_val - td->tmr_val; 1047 if (delta >= 128) 1048 return (1); /* busy */ 1049 1050 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1051 1052 /* set toggle, if any */ 1053 if (td->set_toggle) { 1054 td->set_toggle = 0; 1055 td->toggle = 1; 1056 } 1057 return (0); 1058 } 1059 1060 static uint8_t 1061 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1062 { 1063 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1064 1065 if (td->ep_type == UE_ISOCHRONOUS) { 1066 /* non TT isochronous traffic */ 1067 if ((td->tmr_val != 0) || 1068 (frame_num & (td->tmr_res - 1))) { 1069 goto busy; 1070 } 1071 td->tmr_val = 1; /* executed */ 1072 td->toggle = 0; 1073 return (0); 1074 } else if (td->ep_type == UE_INTERRUPT) { 1075 if (!td->tt_scheduled) 1076 goto busy; 1077 td->tt_scheduled = 0; 1078 return (0); 1079 } else if (td->did_nak != 0) { 1080 /* check if we should pause sending queries for 125us */ 1081 if (td->tmr_res == frame_num) { 1082 /* wait a bit */ 1083 dwc_otg_enable_sof_irq(sc); 1084 goto busy; 1085 } 1086 } else if (td->set_toggle) { 1087 td->set_toggle = 0; 1088 td->toggle = 1; 1089 } 1090 /* query for data one more time */ 1091 td->tmr_res = frame_num; 1092 td->did_nak = 0; 1093 return (0); 1094 busy: 1095 return (1); 1096 } 1097 1098 static uint8_t 1099 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1100 { 1101 uint32_t count; 1102 uint8_t channel; 1103 1104 /* check endpoint status */ 1105 if (sc->sc_last_rx_status == 0) 1106 goto busy; 1107 1108 channel = td->channel; 1109 if (channel >= DWC_OTG_MAX_CHANNELS) 1110 goto busy; 1111 1112 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1113 goto busy; 1114 1115 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1116 case GRXSTSRH_IN_DATA: 1117 1118 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1119 (int)td->state, (int)sc->sc_last_rx_status); 1120 1121 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1122 /* 1123 * When using SPLIT transactions on interrupt 1124 * endpoints, sometimes data occurs twice. 1125 */ 1126 DPRINTF("Data already received\n"); 1127 break; 1128 } 1129 1130 /* get the packet byte count */ 1131 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1132 1133 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1134 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1135 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1136 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1137 } else { 1138 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1139 1140 /* verify the packet byte count */ 1141 if (count < td->max_packet_size) { 1142 /* we have a short packet */ 1143 td->short_pkt = 1; 1144 td->got_short = 1; 1145 } 1146 } 1147 td->toggle = 0; 1148 } else { 1149 /* verify the packet byte count */ 1150 if (count != td->max_packet_size) { 1151 if (count < td->max_packet_size) { 1152 /* we have a short packet */ 1153 td->short_pkt = 1; 1154 td->got_short = 1; 1155 } else { 1156 /* invalid USB packet */ 1157 td->error_any = 1; 1158 1159 /* release FIFO */ 1160 dwc_otg_common_rx_ack(sc); 1161 goto complete; 1162 } 1163 } 1164 td->toggle ^= 1; 1165 td->tt_scheduled = 0; 1166 } 1167 1168 /* verify the packet byte count */ 1169 if (count > td->remainder) { 1170 /* invalid USB packet */ 1171 td->error_any = 1; 1172 1173 /* release FIFO */ 1174 dwc_otg_common_rx_ack(sc); 1175 goto complete; 1176 } 1177 1178 usbd_copy_in(td->pc, td->offset, 1179 sc->sc_rx_bounce_buffer, count); 1180 1181 td->remainder -= count; 1182 td->offset += count; 1183 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1184 break; 1185 default: 1186 break; 1187 } 1188 /* release FIFO */ 1189 dwc_otg_common_rx_ack(sc); 1190 busy: 1191 return (0); 1192 complete: 1193 return (1); 1194 } 1195 1196 static uint8_t 1197 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1198 { 1199 uint32_t hcint; 1200 uint32_t hcchar; 1201 uint8_t delta; 1202 uint8_t channel; 1203 1204 channel = td->channel; 1205 1206 if (channel < DWC_OTG_MAX_CHANNELS) { 1207 hcint = sc->sc_chan_state[channel].hcint; 1208 1209 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1210 channel, td->state, hcint, 1211 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1212 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1213 1214 /* check interrupt bits */ 1215 if (hcint & (HCINT_RETRY | 1216 HCINT_ACK | HCINT_NYET)) { 1217 /* give success bits priority over failure bits */ 1218 } else if (hcint & HCINT_STALL) { 1219 DPRINTF("CH=%d STALL\n", channel); 1220 td->error_stall = 1; 1221 td->error_any = 1; 1222 goto complete; 1223 } else if (hcint & HCINT_ERRORS) { 1224 DPRINTF("CH=%d ERROR\n", channel); 1225 td->errcnt++; 1226 if (td->hcsplt != 0 || td->errcnt >= 3) { 1227 if (td->ep_type != UE_ISOCHRONOUS) { 1228 td->error_any = 1; 1229 goto complete; 1230 } 1231 } 1232 } 1233 1234 /* check channels for data, if any */ 1235 if (dwc_otg_host_data_rx_sub(sc, td)) 1236 goto complete; 1237 1238 /* refresh interrupt status */ 1239 hcint = sc->sc_chan_state[channel].hcint; 1240 1241 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1242 HCINT_ACK | HCINT_NYET)) { 1243 if (!(hcint & HCINT_ERRORS)) 1244 td->errcnt = 0; 1245 } 1246 } else { 1247 hcint = 0; 1248 } 1249 1250 switch (td->state) { 1251 case DWC_CHAN_ST_START: 1252 if (td->hcsplt != 0) 1253 goto receive_spkt; 1254 else 1255 goto receive_pkt; 1256 1257 case DWC_CHAN_ST_WAIT_ANE: 1258 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1259 if (td->ep_type == UE_INTERRUPT) { 1260 /* 1261 * The USB specification does not 1262 * mandate a particular data toggle 1263 * value for USB INTERRUPT 1264 * transfers. Switch the data toggle 1265 * value to receive the packet 1266 * correctly: 1267 */ 1268 if (hcint & HCINT_DATATGLERR) { 1269 DPRINTF("Retrying packet due to " 1270 "data toggle error\n"); 1271 td->toggle ^= 1; 1272 goto receive_pkt; 1273 } 1274 } 1275 td->did_nak = 1; 1276 td->tt_scheduled = 0; 1277 if (td->hcsplt != 0) 1278 goto receive_spkt; 1279 else 1280 goto receive_pkt; 1281 } else if (hcint & HCINT_NYET) { 1282 if (td->hcsplt != 0) { 1283 /* try again */ 1284 goto receive_pkt; 1285 } else { 1286 /* not a valid token for IN endpoints */ 1287 td->error_any = 1; 1288 goto complete; 1289 } 1290 } else if (hcint & HCINT_ACK) { 1291 /* wait for data - ACK arrived first */ 1292 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1293 goto busy; 1294 1295 if (td->ep_type == UE_ISOCHRONOUS) { 1296 /* check if we are complete */ 1297 if ((td->remainder == 0) || 1298 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1299 goto complete; 1300 } 1301 /* get another packet */ 1302 goto receive_pkt; 1303 } else { 1304 /* check if we are complete */ 1305 if ((td->remainder == 0) || (td->got_short != 0)) { 1306 if (td->short_pkt) 1307 goto complete; 1308 1309 /* 1310 * Else need to receive a zero length 1311 * packet. 1312 */ 1313 } 1314 td->tt_scheduled = 0; 1315 td->did_nak = 0; 1316 if (td->hcsplt != 0) 1317 goto receive_spkt; 1318 else 1319 goto receive_pkt; 1320 } 1321 } 1322 break; 1323 1324 case DWC_CHAN_ST_WAIT_S_ANE: 1325 /* 1326 * NOTE: The DWC OTG hardware provides a fake ACK in 1327 * case of interrupt and isochronous transfers: 1328 */ 1329 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1330 td->did_nak = 1; 1331 td->tt_scheduled = 0; 1332 goto receive_spkt; 1333 } else if (hcint & HCINT_NYET) { 1334 td->tt_scheduled = 0; 1335 goto receive_spkt; 1336 } else if (hcint & HCINT_ACK) { 1337 td->did_nak = 0; 1338 goto receive_pkt; 1339 } 1340 break; 1341 1342 case DWC_CHAN_ST_WAIT_C_PKT: 1343 goto receive_pkt; 1344 1345 default: 1346 break; 1347 } 1348 goto busy; 1349 1350 receive_pkt: 1351 /* free existing channel, if any */ 1352 dwc_otg_host_channel_free(sc, td); 1353 1354 if (td->hcsplt != 0) { 1355 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1356 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1357 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1358 goto busy; 1359 } 1360 delta = sc->sc_last_frame_num - td->tt_start_slot; 1361 if (delta > DWC_OTG_TT_SLOT_MAX) { 1362 if (td->ep_type != UE_ISOCHRONOUS) { 1363 /* we missed the service interval */ 1364 td->error_any = 1; 1365 } 1366 goto complete; 1367 } 1368 /* complete split */ 1369 td->hcsplt |= HCSPLT_COMPSPLT; 1370 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1371 dwc_otg_host_rate_check(sc, td)) { 1372 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1373 goto busy; 1374 } 1375 1376 /* allocate a new channel */ 1377 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1378 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1379 goto busy; 1380 } 1381 1382 channel = td->channel; 1383 1384 /* set toggle, if any */ 1385 if (td->set_toggle) { 1386 td->set_toggle = 0; 1387 td->toggle = 1; 1388 } 1389 1390 td->state = DWC_CHAN_ST_WAIT_ANE; 1391 1392 /* receive one packet */ 1393 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1394 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1395 (1 << HCTSIZ_PKTCNT_SHIFT) | 1396 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1397 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1398 1399 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1400 1401 hcchar = td->hcchar; 1402 hcchar |= HCCHAR_EPDIR_IN; 1403 1404 /* receive complete split ASAP */ 1405 if ((sc->sc_last_frame_num & 1) != 0 && 1406 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1407 hcchar |= HCCHAR_ODDFRM; 1408 else 1409 hcchar &= ~HCCHAR_ODDFRM; 1410 1411 /* must enable channel before data can be received */ 1412 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1413 1414 /* wait until next slot before trying complete split */ 1415 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1416 1417 goto busy; 1418 1419 receive_spkt: 1420 /* free existing channel(s), if any */ 1421 dwc_otg_host_channel_free(sc, td); 1422 1423 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1424 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1425 td->state = DWC_CHAN_ST_START; 1426 goto busy; 1427 } 1428 delta = sc->sc_last_frame_num - td->tt_start_slot; 1429 if (delta > 5) { 1430 /* missed it */ 1431 td->tt_scheduled = 0; 1432 td->state = DWC_CHAN_ST_START; 1433 goto busy; 1434 } 1435 1436 /* allocate a new channel */ 1437 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1438 td->state = DWC_CHAN_ST_START; 1439 goto busy; 1440 } 1441 1442 channel = td->channel; 1443 1444 td->hcsplt &= ~HCSPLT_COMPSPLT; 1445 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1446 1447 /* receive one packet */ 1448 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1449 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1450 1451 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1452 1453 /* send after next SOF event */ 1454 if ((sc->sc_last_frame_num & 1) == 0 && 1455 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1456 td->hcchar |= HCCHAR_ODDFRM; 1457 else 1458 td->hcchar &= ~HCCHAR_ODDFRM; 1459 1460 hcchar = td->hcchar; 1461 hcchar |= HCCHAR_EPDIR_IN; 1462 1463 /* wait until next slot before trying complete split */ 1464 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1465 1466 /* must enable channel before data can be received */ 1467 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1468 busy: 1469 return (1); /* busy */ 1470 1471 complete: 1472 dwc_otg_host_channel_free(sc, td); 1473 return (0); /* complete */ 1474 } 1475 1476 static uint8_t 1477 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1478 { 1479 uint32_t temp; 1480 uint16_t count; 1481 uint8_t got_short; 1482 1483 got_short = 0; 1484 1485 /* check endpoint status */ 1486 if (sc->sc_last_rx_status == 0) 1487 goto not_complete; 1488 1489 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1490 goto not_complete; 1491 1492 /* check for SETUP packet */ 1493 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1494 GRXSTSRD_STP_DATA || 1495 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1496 GRXSTSRD_STP_COMPLETE) { 1497 if (td->remainder == 0) { 1498 /* 1499 * We are actually complete and have 1500 * received the next SETUP 1501 */ 1502 DPRINTFN(5, "faking complete\n"); 1503 return (0); /* complete */ 1504 } 1505 /* 1506 * USB Host Aborted the transfer. 1507 */ 1508 td->error_any = 1; 1509 return (0); /* complete */ 1510 } 1511 1512 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1513 GRXSTSRD_OUT_DATA) { 1514 /* release FIFO */ 1515 dwc_otg_common_rx_ack(sc); 1516 goto not_complete; 1517 } 1518 1519 /* get the packet byte count */ 1520 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1521 1522 /* verify the packet byte count */ 1523 if (count != td->max_packet_size) { 1524 if (count < td->max_packet_size) { 1525 /* we have a short packet */ 1526 td->short_pkt = 1; 1527 got_short = 1; 1528 } else { 1529 /* invalid USB packet */ 1530 td->error_any = 1; 1531 1532 /* release FIFO */ 1533 dwc_otg_common_rx_ack(sc); 1534 return (0); /* we are complete */ 1535 } 1536 } 1537 /* verify the packet byte count */ 1538 if (count > td->remainder) { 1539 /* invalid USB packet */ 1540 td->error_any = 1; 1541 1542 /* release FIFO */ 1543 dwc_otg_common_rx_ack(sc); 1544 return (0); /* we are complete */ 1545 } 1546 1547 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1548 td->remainder -= count; 1549 td->offset += count; 1550 1551 /* release FIFO */ 1552 dwc_otg_common_rx_ack(sc); 1553 1554 temp = sc->sc_out_ctl[td->ep_no]; 1555 1556 /* check for isochronous mode */ 1557 if ((temp & DIEPCTL_EPTYPE_MASK) == 1558 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1559 /* toggle odd or even frame bit */ 1560 if (temp & DIEPCTL_SETD1PID) { 1561 temp &= ~DIEPCTL_SETD1PID; 1562 temp |= DIEPCTL_SETD0PID; 1563 } else { 1564 temp &= ~DIEPCTL_SETD0PID; 1565 temp |= DIEPCTL_SETD1PID; 1566 } 1567 sc->sc_out_ctl[td->ep_no] = temp; 1568 } 1569 1570 /* check if we are complete */ 1571 if ((td->remainder == 0) || got_short) { 1572 if (td->short_pkt) { 1573 /* we are complete */ 1574 return (0); 1575 } 1576 /* else need to receive a zero length packet */ 1577 } 1578 1579 not_complete: 1580 1581 /* enable SETUP and transfer complete interrupt */ 1582 if (td->ep_no == 0) { 1583 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1584 DXEPTSIZ_SET_MULTI(3) | 1585 DXEPTSIZ_SET_NPKT(1) | 1586 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1587 } else { 1588 /* allow reception of multiple packets */ 1589 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1590 DXEPTSIZ_SET_MULTI(1) | 1591 DXEPTSIZ_SET_NPKT(4) | 1592 DXEPTSIZ_SET_NBYTES(4 * 1593 ((td->max_packet_size + 3) & ~3))); 1594 } 1595 temp = sc->sc_out_ctl[td->ep_no]; 1596 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1597 DOEPCTL_EPENA | DOEPCTL_CNAK); 1598 1599 return (1); /* not complete */ 1600 } 1601 1602 static uint8_t 1603 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1604 { 1605 uint32_t count; 1606 uint32_t hcint; 1607 uint32_t hcchar; 1608 uint8_t delta; 1609 uint8_t channel; 1610 1611 dwc_otg_host_dump_rx(sc, td); 1612 1613 channel = td->channel; 1614 1615 if (channel < DWC_OTG_MAX_CHANNELS) { 1616 hcint = sc->sc_chan_state[channel].hcint; 1617 1618 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1619 channel, td->state, hcint, 1620 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1621 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1622 1623 if (hcint & (HCINT_RETRY | 1624 HCINT_ACK | HCINT_NYET)) { 1625 /* give success bits priority over failure bits */ 1626 } else if (hcint & HCINT_STALL) { 1627 DPRINTF("CH=%d STALL\n", channel); 1628 td->error_stall = 1; 1629 td->error_any = 1; 1630 goto complete; 1631 } else if (hcint & HCINT_ERRORS) { 1632 DPRINTF("CH=%d ERROR\n", channel); 1633 td->errcnt++; 1634 if (td->hcsplt != 0 || td->errcnt >= 3) { 1635 td->error_any = 1; 1636 goto complete; 1637 } 1638 } 1639 1640 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1641 HCINT_ACK | HCINT_NYET)) { 1642 1643 if (!(hcint & HCINT_ERRORS)) 1644 td->errcnt = 0; 1645 } 1646 } else { 1647 hcint = 0; 1648 } 1649 1650 switch (td->state) { 1651 case DWC_CHAN_ST_START: 1652 goto send_pkt; 1653 1654 case DWC_CHAN_ST_WAIT_ANE: 1655 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1656 td->did_nak = 1; 1657 td->tt_scheduled = 0; 1658 goto send_pkt; 1659 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1660 td->offset += td->tx_bytes; 1661 td->remainder -= td->tx_bytes; 1662 td->toggle ^= 1; 1663 /* check if next response will be a NAK */ 1664 if (hcint & HCINT_NYET) 1665 td->did_nak = 1; 1666 else 1667 td->did_nak = 0; 1668 td->tt_scheduled = 0; 1669 1670 /* check remainder */ 1671 if (td->remainder == 0) { 1672 if (td->short_pkt) 1673 goto complete; 1674 1675 /* 1676 * Else we need to transmit a short 1677 * packet: 1678 */ 1679 } 1680 goto send_pkt; 1681 } 1682 break; 1683 1684 case DWC_CHAN_ST_WAIT_S_ANE: 1685 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1686 td->did_nak = 1; 1687 td->tt_scheduled = 0; 1688 goto send_pkt; 1689 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1690 td->did_nak = 0; 1691 goto send_cpkt; 1692 } 1693 break; 1694 1695 case DWC_CHAN_ST_WAIT_C_ANE: 1696 if (hcint & HCINT_NYET) { 1697 goto send_cpkt; 1698 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1699 td->did_nak = 1; 1700 td->tt_scheduled = 0; 1701 goto send_pkt; 1702 } else if (hcint & HCINT_ACK) { 1703 td->offset += td->tx_bytes; 1704 td->remainder -= td->tx_bytes; 1705 td->toggle ^= 1; 1706 td->did_nak = 0; 1707 td->tt_scheduled = 0; 1708 1709 /* check remainder */ 1710 if (td->remainder == 0) { 1711 if (td->short_pkt) 1712 goto complete; 1713 1714 /* else we need to transmit a short packet */ 1715 } 1716 goto send_pkt; 1717 } 1718 break; 1719 1720 case DWC_CHAN_ST_WAIT_C_PKT: 1721 goto send_cpkt; 1722 1723 case DWC_CHAN_ST_TX_WAIT_ISOC: 1724 1725 /* Check if isochronous OUT traffic is complete */ 1726 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1727 break; 1728 1729 td->offset += td->tx_bytes; 1730 td->remainder -= td->tx_bytes; 1731 1732 if (td->hcsplt != 0 || td->remainder == 0) 1733 goto complete; 1734 1735 /* check for next packet */ 1736 if (td->max_packet_count > 1) 1737 td->tt_xactpos++; 1738 1739 /* free existing channel, if any */ 1740 dwc_otg_host_channel_free(sc, td); 1741 1742 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1743 1744 /* FALLTHROUGH */ 1745 1746 case DWC_CHAN_ST_TX_PKT_ISOC: 1747 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1748 break; 1749 channel = td->channel; 1750 goto send_isoc_pkt; 1751 default: 1752 break; 1753 } 1754 goto busy; 1755 1756 send_pkt: 1757 /* free existing channel(s), if any */ 1758 dwc_otg_host_channel_free(sc, td); 1759 1760 if (td->hcsplt != 0) { 1761 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1762 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1763 td->state = DWC_CHAN_ST_START; 1764 goto busy; 1765 } 1766 delta = sc->sc_last_frame_num - td->tt_start_slot; 1767 if (delta > 5) { 1768 /* missed it */ 1769 td->tt_scheduled = 0; 1770 td->state = DWC_CHAN_ST_START; 1771 goto busy; 1772 } 1773 } else if (dwc_otg_host_rate_check(sc, td)) { 1774 td->state = DWC_CHAN_ST_START; 1775 goto busy; 1776 } 1777 1778 /* allocate a new channel */ 1779 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1780 td->state = DWC_CHAN_ST_START; 1781 goto busy; 1782 } 1783 1784 channel = td->channel; 1785 1786 /* set toggle, if any */ 1787 if (td->set_toggle) { 1788 td->set_toggle = 0; 1789 td->toggle = 1; 1790 } 1791 1792 if (td->ep_type == UE_ISOCHRONOUS) { 1793 send_isoc_pkt: 1794 /* Isochronous OUT transfers don't have any ACKs */ 1795 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1796 td->hcsplt &= ~HCSPLT_COMPSPLT; 1797 if (td->hcsplt != 0) { 1798 /* get maximum transfer length */ 1799 count = td->remainder; 1800 if (count > HCSPLT_XACTLEN_BURST) { 1801 DPRINTF("TT overflow\n"); 1802 td->error_any = 1; 1803 goto complete; 1804 } 1805 /* Update transaction position */ 1806 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1807 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1808 } else { 1809 /* send one packet at a time */ 1810 count = td->max_packet_size; 1811 if (td->remainder < count) { 1812 /* we have a short packet */ 1813 td->short_pkt = 1; 1814 count = td->remainder; 1815 } 1816 } 1817 } else if (td->hcsplt != 0) { 1818 1819 td->hcsplt &= ~HCSPLT_COMPSPLT; 1820 1821 /* Wait for ACK/NAK/ERR from TT */ 1822 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1823 1824 /* send one packet at a time */ 1825 count = td->max_packet_size; 1826 if (td->remainder < count) { 1827 /* we have a short packet */ 1828 td->short_pkt = 1; 1829 count = td->remainder; 1830 } 1831 } else { 1832 /* Wait for ACK/NAK/STALL from device */ 1833 td->state = DWC_CHAN_ST_WAIT_ANE; 1834 1835 /* send one packet at a time */ 1836 count = td->max_packet_size; 1837 if (td->remainder < count) { 1838 /* we have a short packet */ 1839 td->short_pkt = 1; 1840 count = td->remainder; 1841 } 1842 } 1843 1844 /* check for High-Speed multi-packets */ 1845 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1846 if (td->npkt == 0) { 1847 if (td->remainder >= (3 * td->max_packet_size)) 1848 td->npkt = 3; 1849 else if (td->remainder >= (2 * td->max_packet_size)) 1850 td->npkt = 2; 1851 else 1852 td->npkt = 1; 1853 1854 if (td->npkt > td->max_packet_count) 1855 td->npkt = td->max_packet_count; 1856 1857 td->tt_xactpos = 1; /* overload */ 1858 } 1859 if (td->tt_xactpos == td->npkt) { 1860 if (td->npkt == 1) { 1861 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1862 (count << HCTSIZ_XFERSIZE_SHIFT) | 1863 (1 << HCTSIZ_PKTCNT_SHIFT) | 1864 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1865 } else if (td->npkt == 2) { 1866 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1867 (count << HCTSIZ_XFERSIZE_SHIFT) | 1868 (1 << HCTSIZ_PKTCNT_SHIFT) | 1869 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1870 } else { 1871 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1872 (count << HCTSIZ_XFERSIZE_SHIFT) | 1873 (1 << HCTSIZ_PKTCNT_SHIFT) | 1874 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1875 } 1876 td->npkt = 0; 1877 } else { 1878 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1879 (count << HCTSIZ_XFERSIZE_SHIFT) | 1880 (1 << HCTSIZ_PKTCNT_SHIFT) | 1881 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1882 } 1883 } else { 1884 /* TODO: HCTSIZ_DOPNG */ 1885 1886 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1887 (count << HCTSIZ_XFERSIZE_SHIFT) | 1888 (1 << HCTSIZ_PKTCNT_SHIFT) | 1889 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1890 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1891 } 1892 1893 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1894 1895 hcchar = td->hcchar; 1896 hcchar &= ~HCCHAR_EPDIR_IN; 1897 1898 /* send after next SOF event */ 1899 if ((sc->sc_last_frame_num & 1) == 0 && 1900 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1901 hcchar |= HCCHAR_ODDFRM; 1902 else 1903 hcchar &= ~HCCHAR_ODDFRM; 1904 1905 /* must enable before writing data to FIFO */ 1906 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1907 1908 if (count != 0) { 1909 1910 /* clear topmost word before copy */ 1911 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1912 1913 /* copy out data */ 1914 usbd_copy_out(td->pc, td->offset, 1915 sc->sc_tx_bounce_buffer, count); 1916 1917 /* transfer data into FIFO */ 1918 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1919 DOTG_DFIFO(channel), 1920 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1921 } 1922 1923 /* store number of bytes transmitted */ 1924 td->tx_bytes = count; 1925 goto busy; 1926 1927 send_cpkt: 1928 /* free existing channel, if any */ 1929 dwc_otg_host_channel_free(sc, td); 1930 1931 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1932 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1933 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1934 goto busy; 1935 } 1936 delta = sc->sc_last_frame_num - td->tt_start_slot; 1937 if (delta > DWC_OTG_TT_SLOT_MAX) { 1938 /* we missed the service interval */ 1939 if (td->ep_type != UE_ISOCHRONOUS) 1940 td->error_any = 1; 1941 goto complete; 1942 } 1943 1944 /* allocate a new channel */ 1945 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1946 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1947 goto busy; 1948 } 1949 1950 channel = td->channel; 1951 1952 td->hcsplt |= HCSPLT_COMPSPLT; 1953 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1954 1955 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1956 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1957 1958 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1959 1960 hcchar = td->hcchar; 1961 hcchar &= ~HCCHAR_EPDIR_IN; 1962 1963 /* receive complete split ASAP */ 1964 if ((sc->sc_last_frame_num & 1) != 0 && 1965 (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS)) 1966 hcchar |= HCCHAR_ODDFRM; 1967 else 1968 hcchar &= ~HCCHAR_ODDFRM; 1969 1970 /* must enable channel before data can be received */ 1971 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1972 1973 /* wait until next slot before trying complete split */ 1974 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1975 busy: 1976 return (1); /* busy */ 1977 1978 complete: 1979 dwc_otg_host_channel_free(sc, td); 1980 return (0); /* complete */ 1981 } 1982 1983 static uint8_t 1984 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1985 { 1986 uint32_t max_buffer; 1987 uint32_t count; 1988 uint32_t fifo_left; 1989 uint32_t mpkt; 1990 uint32_t temp; 1991 uint8_t to; 1992 1993 to = 3; /* don't loop forever! */ 1994 1995 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1996 1997 repeat: 1998 /* check for for endpoint 0 data */ 1999 2000 temp = sc->sc_last_rx_status; 2001 2002 if ((td->ep_no == 0) && (temp != 0) && 2003 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2004 2005 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2006 GRXSTSRD_STP_DATA && 2007 (temp & GRXSTSRD_PKTSTS_MASK) != 2008 GRXSTSRD_STP_COMPLETE) { 2009 2010 /* dump data - wrong direction */ 2011 dwc_otg_common_rx_ack(sc); 2012 } else { 2013 /* 2014 * The current transfer was cancelled 2015 * by the USB Host: 2016 */ 2017 td->error_any = 1; 2018 return (0); /* complete */ 2019 } 2020 } 2021 2022 /* fill in more TX data, if possible */ 2023 if (td->tx_bytes != 0) { 2024 2025 uint16_t cpkt; 2026 2027 /* check if packets have been transferred */ 2028 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2029 2030 /* get current packet number */ 2031 cpkt = DXEPTSIZ_GET_NPKT(temp); 2032 2033 if (cpkt >= td->npkt) { 2034 fifo_left = 0; 2035 } else { 2036 if (max_buffer != 0) { 2037 fifo_left = (td->npkt - cpkt) * 2038 td->max_packet_size; 2039 2040 if (fifo_left > max_buffer) 2041 fifo_left = max_buffer; 2042 } else { 2043 fifo_left = td->max_packet_size; 2044 } 2045 } 2046 2047 count = td->tx_bytes; 2048 if (count > fifo_left) 2049 count = fifo_left; 2050 2051 if (count != 0) { 2052 2053 /* clear topmost word before copy */ 2054 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2055 2056 /* copy out data */ 2057 usbd_copy_out(td->pc, td->offset, 2058 sc->sc_tx_bounce_buffer, count); 2059 2060 /* transfer data into FIFO */ 2061 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2062 DOTG_DFIFO(td->ep_no), 2063 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2064 2065 td->tx_bytes -= count; 2066 td->remainder -= count; 2067 td->offset += count; 2068 td->npkt = cpkt; 2069 } 2070 if (td->tx_bytes != 0) 2071 goto not_complete; 2072 2073 /* check remainder */ 2074 if (td->remainder == 0) { 2075 if (td->short_pkt) 2076 return (0); /* complete */ 2077 2078 /* else we need to transmit a short packet */ 2079 } 2080 } 2081 2082 if (!to--) 2083 goto not_complete; 2084 2085 /* check if not all packets have been transferred */ 2086 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2087 2088 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2089 2090 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2091 "DIEPCTL=0x%08x\n", td->ep_no, 2092 DXEPTSIZ_GET_NPKT(temp), 2093 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2094 2095 goto not_complete; 2096 } 2097 2098 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2099 2100 /* try to optimise by sending more data */ 2101 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2102 2103 /* send multiple packets at the same time */ 2104 mpkt = max_buffer / td->max_packet_size; 2105 2106 if (mpkt > 0x3FE) 2107 mpkt = 0x3FE; 2108 2109 count = td->remainder; 2110 if (count > 0x7FFFFF) 2111 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2112 2113 td->npkt = count / td->max_packet_size; 2114 2115 /* 2116 * NOTE: We could use 0x3FE instead of "mpkt" in the 2117 * check below to get more throughput, but then we 2118 * have a dependency towards non-generic chip features 2119 * to disable the TX-FIFO-EMPTY interrupts on a per 2120 * endpoint basis. Increase the maximum buffer size of 2121 * the IN endpoint to increase the performance. 2122 */ 2123 if (td->npkt > mpkt) { 2124 td->npkt = mpkt; 2125 count = td->max_packet_size * mpkt; 2126 } else if ((count == 0) || (count % td->max_packet_size)) { 2127 /* we are transmitting a short packet */ 2128 td->npkt++; 2129 td->short_pkt = 1; 2130 } 2131 } else { 2132 /* send one packet at a time */ 2133 mpkt = 1; 2134 count = td->max_packet_size; 2135 if (td->remainder < count) { 2136 /* we have a short packet */ 2137 td->short_pkt = 1; 2138 count = td->remainder; 2139 } 2140 td->npkt = 1; 2141 } 2142 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2143 DXEPTSIZ_SET_MULTI(1) | 2144 DXEPTSIZ_SET_NPKT(td->npkt) | 2145 DXEPTSIZ_SET_NBYTES(count)); 2146 2147 /* make room for buffering */ 2148 td->npkt += mpkt; 2149 2150 temp = sc->sc_in_ctl[td->ep_no]; 2151 2152 /* check for isochronous mode */ 2153 if ((temp & DIEPCTL_EPTYPE_MASK) == 2154 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2155 /* toggle odd or even frame bit */ 2156 if (temp & DIEPCTL_SETD1PID) { 2157 temp &= ~DIEPCTL_SETD1PID; 2158 temp |= DIEPCTL_SETD0PID; 2159 } else { 2160 temp &= ~DIEPCTL_SETD0PID; 2161 temp |= DIEPCTL_SETD1PID; 2162 } 2163 sc->sc_in_ctl[td->ep_no] = temp; 2164 } 2165 2166 /* must enable before writing data to FIFO */ 2167 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2168 DIEPCTL_EPENA | DIEPCTL_CNAK); 2169 2170 td->tx_bytes = count; 2171 2172 /* check remainder */ 2173 if (td->tx_bytes == 0 && 2174 td->remainder == 0) { 2175 if (td->short_pkt) 2176 return (0); /* complete */ 2177 2178 /* else we need to transmit a short packet */ 2179 } 2180 goto repeat; 2181 2182 not_complete: 2183 return (1); /* not complete */ 2184 } 2185 2186 static uint8_t 2187 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2188 { 2189 uint32_t temp; 2190 2191 /* 2192 * If all packets are transferred we are complete: 2193 */ 2194 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2195 2196 /* check that all packets have been transferred */ 2197 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2198 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2199 goto not_complete; 2200 } 2201 return (0); 2202 2203 not_complete: 2204 2205 /* we only want to know if there is a SETUP packet or free IN packet */ 2206 2207 temp = sc->sc_last_rx_status; 2208 2209 if ((td->ep_no == 0) && (temp != 0) && 2210 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2211 2212 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2213 GRXSTSRD_STP_DATA || 2214 (temp & GRXSTSRD_PKTSTS_MASK) == 2215 GRXSTSRD_STP_COMPLETE) { 2216 DPRINTFN(5, "faking complete\n"); 2217 /* 2218 * Race condition: We are complete! 2219 */ 2220 return (0); 2221 } else { 2222 /* dump data - wrong direction */ 2223 dwc_otg_common_rx_ack(sc); 2224 } 2225 } 2226 return (1); /* not complete */ 2227 } 2228 2229 static void 2230 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2231 { 2232 struct dwc_otg_td *td; 2233 uint8_t toggle; 2234 uint8_t tmr_val; 2235 uint8_t tmr_res; 2236 2237 DPRINTFN(9, "\n"); 2238 2239 td = xfer->td_transfer_cache; 2240 if (td == NULL) 2241 return; 2242 2243 while (1) { 2244 if ((td->func) (sc, td)) { 2245 /* operation in progress */ 2246 break; 2247 } 2248 if (((void *)td) == xfer->td_transfer_last) { 2249 goto done; 2250 } 2251 if (td->error_any) { 2252 goto done; 2253 } else if (td->remainder > 0) { 2254 /* 2255 * We had a short transfer. If there is no alternate 2256 * next, stop processing ! 2257 */ 2258 if (!td->alt_next) 2259 goto done; 2260 } 2261 2262 /* 2263 * Fetch the next transfer descriptor and transfer 2264 * some flags to the next transfer descriptor 2265 */ 2266 tmr_res = td->tmr_res; 2267 tmr_val = td->tmr_val; 2268 toggle = td->toggle; 2269 td = td->obj_next; 2270 xfer->td_transfer_cache = td; 2271 td->toggle = toggle; /* transfer toggle */ 2272 td->tmr_res = tmr_res; 2273 td->tmr_val = tmr_val; 2274 } 2275 return; 2276 2277 done: 2278 xfer->td_transfer_cache = NULL; 2279 sc->sc_xfer_complete = 1; 2280 } 2281 2282 static uint8_t 2283 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2284 { 2285 struct dwc_otg_td *td; 2286 2287 DPRINTFN(9, "\n"); 2288 2289 td = xfer->td_transfer_cache; 2290 if (td == NULL) { 2291 /* compute all actual lengths */ 2292 dwc_otg_standard_done(xfer); 2293 return (1); 2294 } 2295 return (0); 2296 } 2297 2298 static void 2299 dwc_otg_timer(void *_sc) 2300 { 2301 struct dwc_otg_softc *sc = _sc; 2302 2303 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2304 2305 DPRINTF("\n"); 2306 2307 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2308 2309 /* increment timer value */ 2310 sc->sc_tmr_val++; 2311 2312 /* enable SOF interrupt, which will poll jobs */ 2313 dwc_otg_enable_sof_irq(sc); 2314 2315 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2316 2317 if (sc->sc_timer_active) { 2318 /* restart timer */ 2319 usb_callout_reset(&sc->sc_timer, 2320 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2321 &dwc_otg_timer, sc); 2322 } 2323 } 2324 2325 static void 2326 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2327 { 2328 if (sc->sc_timer_active != 0) 2329 return; 2330 2331 sc->sc_timer_active = 1; 2332 2333 /* restart timer */ 2334 usb_callout_reset(&sc->sc_timer, 2335 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2336 &dwc_otg_timer, sc); 2337 } 2338 2339 static void 2340 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2341 { 2342 if (sc->sc_timer_active == 0) 2343 return; 2344 2345 sc->sc_timer_active = 0; 2346 2347 /* stop timer */ 2348 usb_callout_stop(&sc->sc_timer); 2349 } 2350 2351 static uint16_t 2352 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2353 { 2354 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2355 pinfo->slot_index++; 2356 return (pinfo->slot_index); 2357 } 2358 2359 static uint8_t 2360 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2361 { 2362 TAILQ_HEAD(, usb_xfer) head; 2363 struct usb_xfer *xfer; 2364 struct usb_xfer *xfer_next; 2365 struct dwc_otg_td *td; 2366 uint16_t temp; 2367 uint16_t slot; 2368 2369 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2370 2371 if (sc->sc_last_frame_num == temp) 2372 return (0); 2373 2374 sc->sc_last_frame_num = temp; 2375 2376 TAILQ_INIT(&head); 2377 2378 if ((temp & 7) == 0) { 2379 2380 /* reset the schedule */ 2381 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2382 2383 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2384 td = xfer->td_transfer_cache; 2385 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2386 continue; 2387 2388 /* check for IN direction */ 2389 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2390 continue; 2391 2392 /* execute more frames */ 2393 td->tmr_val = 0; 2394 2395 sc->sc_needsof = 1; 2396 2397 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2398 continue; 2399 2400 /* compute slot */ 2401 slot = dwc_otg_compute_isoc_rx_tt_slot( 2402 sc->sc_tt_info + td->tt_index); 2403 if (slot > 3) { 2404 /* 2405 * Not enough time to get complete 2406 * split executed. 2407 */ 2408 continue; 2409 } 2410 /* Delayed start */ 2411 td->tt_start_slot = temp + slot; 2412 td->tt_scheduled = 1; 2413 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2414 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2415 } 2416 2417 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2418 td = xfer->td_transfer_cache; 2419 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2420 continue; 2421 2422 /* check for OUT direction */ 2423 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2424 continue; 2425 2426 /* execute more frames */ 2427 td->tmr_val = 0; 2428 2429 sc->sc_needsof = 1; 2430 2431 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2432 continue; 2433 2434 /* Start ASAP */ 2435 td->tt_start_slot = temp; 2436 td->tt_scheduled = 1; 2437 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2438 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2439 } 2440 2441 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2442 td = xfer->td_transfer_cache; 2443 if (td == NULL || td->ep_type != UE_INTERRUPT) 2444 continue; 2445 2446 if (td->tt_scheduled != 0) { 2447 sc->sc_needsof = 1; 2448 continue; 2449 } 2450 2451 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2452 continue; 2453 2454 if (td->hcsplt == 0) { 2455 sc->sc_needsof = 1; 2456 td->tt_scheduled = 1; 2457 continue; 2458 } 2459 2460 /* start ASAP */ 2461 td->tt_start_slot = temp; 2462 sc->sc_needsof = 1; 2463 td->tt_scheduled = 1; 2464 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2465 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2466 } 2467 2468 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2469 td = xfer->td_transfer_cache; 2470 if (td == NULL || 2471 td->ep_type != UE_CONTROL) { 2472 continue; 2473 } 2474 2475 sc->sc_needsof = 1; 2476 2477 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2478 continue; 2479 2480 /* start ASAP */ 2481 td->tt_start_slot = temp; 2482 td->tt_scheduled = 1; 2483 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2484 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2485 } 2486 } 2487 if ((temp & 7) < 6) { 2488 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2489 td = xfer->td_transfer_cache; 2490 if (td == NULL || 2491 td->ep_type != UE_BULK) { 2492 continue; 2493 } 2494 2495 sc->sc_needsof = 1; 2496 2497 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2498 continue; 2499 2500 /* start ASAP */ 2501 td->tt_start_slot = temp; 2502 td->tt_scheduled = 1; 2503 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2504 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2505 } 2506 } 2507 2508 /* Put TT transfers in execution order at the end */ 2509 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2510 2511 /* move all TT transfers in front, keeping the current order */ 2512 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2513 td = xfer->td_transfer_cache; 2514 if (td == NULL || td->hcsplt == 0) 2515 continue; 2516 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2517 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2518 } 2519 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2520 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2521 2522 /* put non-TT BULK transfers last */ 2523 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2524 td = xfer->td_transfer_cache; 2525 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2526 continue; 2527 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2528 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2529 } 2530 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2531 2532 if ((temp & 7) == 0) { 2533 2534 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2535 (int)temp, (int)sc->sc_needsof); 2536 2537 /* update SOF IRQ mask */ 2538 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2539 if (sc->sc_needsof == 0) { 2540 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2541 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2542 } 2543 } else { 2544 if (sc->sc_needsof != 0) { 2545 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2546 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2547 } 2548 } 2549 2550 /* clear need SOF flag */ 2551 sc->sc_needsof = 0; 2552 } 2553 return (1); 2554 } 2555 2556 static void 2557 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2558 { 2559 struct usb_xfer *xfer; 2560 uint32_t count; 2561 uint32_t temp; 2562 uint8_t got_rx_status; 2563 uint8_t x; 2564 2565 if (sc->sc_flags.status_device_mode == 0) { 2566 /* 2567 * Update host transfer schedule, so that new 2568 * transfers can be issued: 2569 */ 2570 dwc_otg_update_host_transfer_schedule_locked(sc); 2571 } 2572 count = 0; 2573 repeat: 2574 if (++count == 16) { 2575 /* give other interrupts a chance */ 2576 DPRINTF("Yield\n"); 2577 return; 2578 } 2579 /* get all host channel interrupts */ 2580 for (x = 0; x != sc->sc_host_ch_max; x++) { 2581 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2582 if (temp != 0) { 2583 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2584 temp &= ~HCINT_SOFTWARE_ONLY; 2585 sc->sc_chan_state[x].hcint |= temp; 2586 } 2587 } 2588 2589 if (sc->sc_last_rx_status == 0) { 2590 2591 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2592 if (temp & GINTSTS_RXFLVL) { 2593 /* pop current status */ 2594 sc->sc_last_rx_status = 2595 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2596 } 2597 2598 if (sc->sc_last_rx_status != 0) { 2599 2600 uint8_t ep_no; 2601 2602 temp = sc->sc_last_rx_status & 2603 GRXSTSRD_PKTSTS_MASK; 2604 2605 /* non-data messages we simply skip */ 2606 if (temp != GRXSTSRD_STP_DATA && 2607 temp != GRXSTSRD_STP_COMPLETE && 2608 temp != GRXSTSRD_OUT_DATA) { 2609 /* check for halted channel */ 2610 if (temp == GRXSTSRH_HALTED) { 2611 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2612 sc->sc_chan_state[ep_no].wait_halted = 0; 2613 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2614 } 2615 dwc_otg_common_rx_ack(sc); 2616 goto repeat; 2617 } 2618 2619 temp = GRXSTSRD_BCNT_GET( 2620 sc->sc_last_rx_status); 2621 ep_no = GRXSTSRD_CHNUM_GET( 2622 sc->sc_last_rx_status); 2623 2624 /* receive data, if any */ 2625 if (temp != 0) { 2626 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2627 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2628 DOTG_DFIFO(ep_no), 2629 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2630 } 2631 2632 /* check if we should dump the data */ 2633 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2634 dwc_otg_common_rx_ack(sc); 2635 goto repeat; 2636 } 2637 2638 got_rx_status = 1; 2639 2640 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2641 sc->sc_last_rx_status, ep_no, 2642 (sc->sc_last_rx_status >> 15) & 3, 2643 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2644 (sc->sc_last_rx_status >> 17) & 15); 2645 } else { 2646 got_rx_status = 0; 2647 } 2648 } else { 2649 uint8_t ep_no; 2650 2651 ep_no = GRXSTSRD_CHNUM_GET( 2652 sc->sc_last_rx_status); 2653 2654 /* check if we should dump the data */ 2655 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2656 dwc_otg_common_rx_ack(sc); 2657 goto repeat; 2658 } 2659 2660 got_rx_status = 1; 2661 } 2662 2663 /* execute FIFOs */ 2664 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2665 dwc_otg_xfer_do_fifo(sc, xfer); 2666 2667 if (got_rx_status) { 2668 /* check if data was consumed */ 2669 if (sc->sc_last_rx_status == 0) 2670 goto repeat; 2671 2672 /* disable RX FIFO level interrupt */ 2673 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2674 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2675 } 2676 } 2677 2678 static void 2679 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2680 { 2681 struct usb_xfer *xfer; 2682 repeat: 2683 /* scan for completion events */ 2684 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2685 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2686 goto repeat; 2687 } 2688 } 2689 2690 static void 2691 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2692 { 2693 DPRINTFN(5, "vbus = %u\n", is_on); 2694 2695 /* 2696 * If the USB host mode is forced, then assume VBUS is always 2697 * present else rely on the input to this function: 2698 */ 2699 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2700 2701 if (!sc->sc_flags.status_vbus) { 2702 sc->sc_flags.status_vbus = 1; 2703 2704 /* complete root HUB interrupt endpoint */ 2705 2706 dwc_otg_root_intr(sc); 2707 } 2708 } else { 2709 if (sc->sc_flags.status_vbus) { 2710 sc->sc_flags.status_vbus = 0; 2711 sc->sc_flags.status_bus_reset = 0; 2712 sc->sc_flags.status_suspend = 0; 2713 sc->sc_flags.change_suspend = 0; 2714 sc->sc_flags.change_connect = 1; 2715 2716 /* complete root HUB interrupt endpoint */ 2717 2718 dwc_otg_root_intr(sc); 2719 } 2720 } 2721 } 2722 2723 int 2724 dwc_otg_filter_interrupt(void *arg) 2725 { 2726 struct dwc_otg_softc *sc = arg; 2727 int retval = FILTER_HANDLED; 2728 uint32_t status; 2729 2730 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2731 2732 /* read and clear interrupt status */ 2733 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2734 2735 /* clear interrupts we are handling here */ 2736 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2737 2738 /* check for USB state change interrupts */ 2739 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2740 retval = FILTER_SCHEDULE_THREAD; 2741 2742 /* clear FIFO empty interrupts */ 2743 if (status & sc->sc_irq_mask & 2744 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2745 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2746 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2747 } 2748 /* clear all IN endpoint interrupts */ 2749 if (status & GINTSTS_IEPINT) { 2750 uint32_t temp; 2751 uint8_t x; 2752 2753 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2754 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2755 if (temp & DIEPMSK_XFERCOMPLMSK) { 2756 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2757 DIEPMSK_XFERCOMPLMSK); 2758 } 2759 } 2760 } 2761 2762 /* poll FIFOs, if any */ 2763 dwc_otg_interrupt_poll_locked(sc); 2764 2765 if (sc->sc_xfer_complete != 0) 2766 retval = FILTER_SCHEDULE_THREAD; 2767 2768 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2769 2770 return (retval); 2771 } 2772 2773 void 2774 dwc_otg_interrupt(void *arg) 2775 { 2776 struct dwc_otg_softc *sc = arg; 2777 uint32_t status; 2778 2779 USB_BUS_LOCK(&sc->sc_bus); 2780 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2781 2782 /* read and clear interrupt status */ 2783 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2784 2785 /* clear interrupts we are handling here */ 2786 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2787 2788 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2789 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2790 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2791 2792 if (status & GINTSTS_USBRST) { 2793 2794 /* set correct state */ 2795 sc->sc_flags.status_device_mode = 1; 2796 sc->sc_flags.status_bus_reset = 0; 2797 sc->sc_flags.status_suspend = 0; 2798 sc->sc_flags.change_suspend = 0; 2799 sc->sc_flags.change_connect = 1; 2800 2801 /* Disable SOF interrupt */ 2802 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2803 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2804 2805 /* complete root HUB interrupt endpoint */ 2806 dwc_otg_root_intr(sc); 2807 } 2808 2809 /* check for any bus state change interrupts */ 2810 if (status & GINTSTS_ENUMDONE) { 2811 2812 uint32_t temp; 2813 2814 DPRINTFN(5, "end of reset\n"); 2815 2816 /* set correct state */ 2817 sc->sc_flags.status_device_mode = 1; 2818 sc->sc_flags.status_bus_reset = 1; 2819 sc->sc_flags.status_suspend = 0; 2820 sc->sc_flags.change_suspend = 0; 2821 sc->sc_flags.change_connect = 1; 2822 sc->sc_flags.status_low_speed = 0; 2823 sc->sc_flags.port_enabled = 1; 2824 2825 /* reset FIFOs */ 2826 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2827 2828 /* reset function address */ 2829 dwc_otg_set_address(sc, 0); 2830 2831 /* figure out enumeration speed */ 2832 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2833 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2834 sc->sc_flags.status_high_speed = 1; 2835 else 2836 sc->sc_flags.status_high_speed = 0; 2837 2838 /* 2839 * Disable resume and SOF interrupt, and enable 2840 * suspend and RX frame interrupt: 2841 */ 2842 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2843 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2844 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2845 2846 /* complete root HUB interrupt endpoint */ 2847 dwc_otg_root_intr(sc); 2848 } 2849 2850 if (status & GINTSTS_PRTINT) { 2851 uint32_t hprt; 2852 2853 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2854 2855 /* clear change bits */ 2856 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2857 HPRT_PRTPWR | HPRT_PRTENCHNG | 2858 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2859 sc->sc_hprt_val); 2860 2861 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2862 2863 sc->sc_flags.status_device_mode = 0; 2864 2865 if (hprt & HPRT_PRTCONNSTS) 2866 sc->sc_flags.status_bus_reset = 1; 2867 else 2868 sc->sc_flags.status_bus_reset = 0; 2869 2870 if (hprt & HPRT_PRTENCHNG) 2871 sc->sc_flags.change_enabled = 1; 2872 2873 if (hprt & HPRT_PRTENA) 2874 sc->sc_flags.port_enabled = 1; 2875 else 2876 sc->sc_flags.port_enabled = 0; 2877 2878 if (hprt & HPRT_PRTOVRCURRCHNG) 2879 sc->sc_flags.change_over_current = 1; 2880 2881 if (hprt & HPRT_PRTOVRCURRACT) 2882 sc->sc_flags.port_over_current = 1; 2883 else 2884 sc->sc_flags.port_over_current = 0; 2885 2886 if (hprt & HPRT_PRTPWR) 2887 sc->sc_flags.port_powered = 1; 2888 else 2889 sc->sc_flags.port_powered = 0; 2890 2891 if (((hprt & HPRT_PRTSPD_MASK) 2892 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2893 sc->sc_flags.status_low_speed = 1; 2894 else 2895 sc->sc_flags.status_low_speed = 0; 2896 2897 if (((hprt & HPRT_PRTSPD_MASK) 2898 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2899 sc->sc_flags.status_high_speed = 1; 2900 else 2901 sc->sc_flags.status_high_speed = 0; 2902 2903 if (hprt & HPRT_PRTCONNDET) 2904 sc->sc_flags.change_connect = 1; 2905 2906 if (hprt & HPRT_PRTSUSP) 2907 dwc_otg_suspend_irq(sc); 2908 else 2909 dwc_otg_resume_irq(sc); 2910 2911 /* complete root HUB interrupt endpoint */ 2912 dwc_otg_root_intr(sc); 2913 2914 /* update host frame interval */ 2915 dwc_otg_update_host_frame_interval(sc); 2916 } 2917 2918 /* 2919 * If resume and suspend is set at the same time we interpret 2920 * that like RESUME. Resume is set when there is at least 3 2921 * milliseconds of inactivity on the USB BUS. 2922 */ 2923 if (status & GINTSTS_WKUPINT) { 2924 2925 DPRINTFN(5, "resume interrupt\n"); 2926 2927 dwc_otg_resume_irq(sc); 2928 2929 } else if (status & GINTSTS_USBSUSP) { 2930 2931 DPRINTFN(5, "suspend interrupt\n"); 2932 2933 dwc_otg_suspend_irq(sc); 2934 } 2935 /* check VBUS */ 2936 if (status & (GINTSTS_USBSUSP | 2937 GINTSTS_USBRST | 2938 GINTMSK_OTGINTMSK | 2939 GINTSTS_SESSREQINT)) { 2940 uint32_t temp; 2941 2942 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2943 2944 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2945 2946 dwc_otg_vbus_interrupt(sc, 2947 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2948 } 2949 2950 if (sc->sc_xfer_complete != 0) { 2951 sc->sc_xfer_complete = 0; 2952 2953 /* complete FIFOs, if any */ 2954 dwc_otg_interrupt_complete_locked(sc); 2955 } 2956 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2957 USB_BUS_UNLOCK(&sc->sc_bus); 2958 } 2959 2960 static void 2961 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2962 { 2963 struct dwc_otg_td *td; 2964 2965 /* get current Transfer Descriptor */ 2966 td = temp->td_next; 2967 temp->td = td; 2968 2969 /* prepare for next TD */ 2970 temp->td_next = td->obj_next; 2971 2972 /* fill out the Transfer Descriptor */ 2973 td->func = temp->func; 2974 td->pc = temp->pc; 2975 td->offset = temp->offset; 2976 td->remainder = temp->len; 2977 td->tx_bytes = 0; 2978 td->error_any = 0; 2979 td->error_stall = 0; 2980 td->npkt = 0; 2981 td->did_stall = temp->did_stall; 2982 td->short_pkt = temp->short_pkt; 2983 td->alt_next = temp->setup_alt_next; 2984 td->set_toggle = 0; 2985 td->got_short = 0; 2986 td->did_nak = 0; 2987 td->channel = DWC_OTG_MAX_CHANNELS; 2988 td->state = 0; 2989 td->errcnt = 0; 2990 td->tt_scheduled = 0; 2991 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2992 } 2993 2994 static void 2995 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2996 { 2997 struct dwc_otg_std_temp temp; 2998 struct dwc_otg_td *td; 2999 uint32_t x; 3000 uint8_t need_sync; 3001 uint8_t is_host; 3002 3003 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3004 xfer->address, UE_GET_ADDR(xfer->endpointno), 3005 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3006 3007 temp.max_frame_size = xfer->max_frame_size; 3008 3009 td = xfer->td_start[0]; 3010 xfer->td_transfer_first = td; 3011 xfer->td_transfer_cache = td; 3012 3013 /* setup temp */ 3014 3015 temp.pc = NULL; 3016 temp.td = NULL; 3017 temp.td_next = xfer->td_start[0]; 3018 temp.offset = 0; 3019 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3020 xfer->flags_int.isochronous_xfr; 3021 temp.did_stall = !xfer->flags_int.control_stall; 3022 3023 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3024 3025 /* check if we should prepend a setup message */ 3026 3027 if (xfer->flags_int.control_xfr) { 3028 if (xfer->flags_int.control_hdr) { 3029 3030 if (is_host) 3031 temp.func = &dwc_otg_host_setup_tx; 3032 else 3033 temp.func = &dwc_otg_setup_rx; 3034 3035 temp.len = xfer->frlengths[0]; 3036 temp.pc = xfer->frbuffers + 0; 3037 temp.short_pkt = temp.len ? 1 : 0; 3038 3039 /* check for last frame */ 3040 if (xfer->nframes == 1) { 3041 /* no STATUS stage yet, SETUP is last */ 3042 if (xfer->flags_int.control_act) 3043 temp.setup_alt_next = 0; 3044 } 3045 3046 dwc_otg_setup_standard_chain_sub(&temp); 3047 } 3048 x = 1; 3049 } else { 3050 x = 0; 3051 } 3052 3053 if (x != xfer->nframes) { 3054 if (xfer->endpointno & UE_DIR_IN) { 3055 if (is_host) { 3056 temp.func = &dwc_otg_host_data_rx; 3057 need_sync = 0; 3058 } else { 3059 temp.func = &dwc_otg_data_tx; 3060 need_sync = 1; 3061 } 3062 } else { 3063 if (is_host) { 3064 temp.func = &dwc_otg_host_data_tx; 3065 need_sync = 0; 3066 } else { 3067 temp.func = &dwc_otg_data_rx; 3068 need_sync = 0; 3069 } 3070 } 3071 3072 /* setup "pc" pointer */ 3073 temp.pc = xfer->frbuffers + x; 3074 } else { 3075 need_sync = 0; 3076 } 3077 while (x != xfer->nframes) { 3078 3079 /* DATA0 / DATA1 message */ 3080 3081 temp.len = xfer->frlengths[x]; 3082 3083 x++; 3084 3085 if (x == xfer->nframes) { 3086 if (xfer->flags_int.control_xfr) { 3087 if (xfer->flags_int.control_act) { 3088 temp.setup_alt_next = 0; 3089 } 3090 } else { 3091 temp.setup_alt_next = 0; 3092 } 3093 } 3094 if (temp.len == 0) { 3095 3096 /* make sure that we send an USB packet */ 3097 3098 temp.short_pkt = 0; 3099 3100 } else { 3101 3102 /* regular data transfer */ 3103 3104 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3105 } 3106 3107 dwc_otg_setup_standard_chain_sub(&temp); 3108 3109 if (xfer->flags_int.isochronous_xfr) { 3110 temp.offset += temp.len; 3111 } else { 3112 /* get next Page Cache pointer */ 3113 temp.pc = xfer->frbuffers + x; 3114 } 3115 } 3116 3117 if (xfer->flags_int.control_xfr) { 3118 3119 /* always setup a valid "pc" pointer for status and sync */ 3120 temp.pc = xfer->frbuffers + 0; 3121 temp.len = 0; 3122 temp.short_pkt = 0; 3123 temp.setup_alt_next = 0; 3124 3125 /* check if we need to sync */ 3126 if (need_sync) { 3127 /* we need a SYNC point after TX */ 3128 temp.func = &dwc_otg_data_tx_sync; 3129 dwc_otg_setup_standard_chain_sub(&temp); 3130 } 3131 3132 /* check if we should append a status stage */ 3133 if (!xfer->flags_int.control_act) { 3134 3135 /* 3136 * Send a DATA1 message and invert the current 3137 * endpoint direction. 3138 */ 3139 if (xfer->endpointno & UE_DIR_IN) { 3140 if (is_host) { 3141 temp.func = &dwc_otg_host_data_tx; 3142 need_sync = 0; 3143 } else { 3144 temp.func = &dwc_otg_data_rx; 3145 need_sync = 0; 3146 } 3147 } else { 3148 if (is_host) { 3149 temp.func = &dwc_otg_host_data_rx; 3150 need_sync = 0; 3151 } else { 3152 temp.func = &dwc_otg_data_tx; 3153 need_sync = 1; 3154 } 3155 } 3156 3157 dwc_otg_setup_standard_chain_sub(&temp); 3158 3159 /* data toggle should be DATA1 */ 3160 td = temp.td; 3161 td->set_toggle = 1; 3162 3163 if (need_sync) { 3164 /* we need a SYNC point after TX */ 3165 temp.func = &dwc_otg_data_tx_sync; 3166 dwc_otg_setup_standard_chain_sub(&temp); 3167 } 3168 } 3169 } else { 3170 /* check if we need to sync */ 3171 if (need_sync) { 3172 3173 temp.pc = xfer->frbuffers + 0; 3174 temp.len = 0; 3175 temp.short_pkt = 0; 3176 temp.setup_alt_next = 0; 3177 3178 /* we need a SYNC point after TX */ 3179 temp.func = &dwc_otg_data_tx_sync; 3180 dwc_otg_setup_standard_chain_sub(&temp); 3181 } 3182 } 3183 3184 /* must have at least one frame! */ 3185 td = temp.td; 3186 xfer->td_transfer_last = td; 3187 3188 if (is_host) { 3189 3190 struct dwc_otg_softc *sc; 3191 uint32_t hcchar; 3192 uint32_t hcsplt; 3193 3194 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3195 3196 /* get first again */ 3197 td = xfer->td_transfer_first; 3198 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3199 3200 hcchar = 3201 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3202 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3203 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3204 HCCHAR_CHENA; 3205 3206 /* 3207 * We are not always able to meet the timing 3208 * requirements of the USB interrupt endpoint's 3209 * complete split token, when doing transfers going 3210 * via a transaction translator. Use the CONTROL 3211 * transfer type instead of the INTERRUPT transfer 3212 * type in general, as a means to workaround 3213 * that. This trick should work for both FULL and LOW 3214 * speed USB traffic going through a TT. For non-TT 3215 * traffic it works aswell. The reason for using 3216 * CONTROL type instead of BULK is that some TTs might 3217 * reject LOW speed BULK traffic. 3218 */ 3219 if (td->ep_type == UE_INTERRUPT) 3220 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3221 else 3222 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3223 3224 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3225 hcchar |= HCCHAR_LSPDDEV; 3226 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3227 hcchar |= HCCHAR_EPDIR_IN; 3228 3229 switch (xfer->xroot->udev->speed) { 3230 case USB_SPEED_FULL: 3231 case USB_SPEED_LOW: 3232 /* check if root HUB port is running High Speed */ 3233 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3234 hcsplt = HCSPLT_SPLTENA | 3235 (xfer->xroot->udev->hs_port_no << 3236 HCSPLT_PRTADDR_SHIFT) | 3237 (xfer->xroot->udev->hs_hub_addr << 3238 HCSPLT_HUBADDR_SHIFT); 3239 } else { 3240 hcsplt = 0; 3241 } 3242 if (td->ep_type == UE_INTERRUPT) { 3243 uint32_t ival; 3244 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3245 if (ival == 0) 3246 ival = 1; 3247 else if (ival > 127) 3248 ival = 127; 3249 td->tmr_val = sc->sc_tmr_val + ival; 3250 td->tmr_res = ival; 3251 } else if (td->ep_type == UE_ISOCHRONOUS) { 3252 td->tmr_val = 0; 3253 td->tmr_res = 1; 3254 } else { 3255 td->tmr_val = 0; 3256 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3257 } 3258 break; 3259 case USB_SPEED_HIGH: 3260 hcsplt = 0; 3261 if (td->ep_type == UE_INTERRUPT) { 3262 uint32_t ival; 3263 #if 0 3264 hcchar |= ((xfer->max_packet_count & 3) 3265 << HCCHAR_MC_SHIFT); 3266 #endif 3267 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3268 if (ival == 0) 3269 ival = 1; 3270 else if (ival > 127) 3271 ival = 127; 3272 td->tmr_val = sc->sc_tmr_val + ival; 3273 td->tmr_res = ival; 3274 } else if (td->ep_type == UE_ISOCHRONOUS) { 3275 hcchar |= ((xfer->max_packet_count & 3) 3276 << HCCHAR_MC_SHIFT); 3277 td->tmr_val = 0; 3278 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3279 } else { 3280 td->tmr_val = 0; 3281 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3282 } 3283 break; 3284 default: 3285 hcsplt = 0; 3286 td->tmr_val = 0; 3287 td->tmr_res = 0; 3288 break; 3289 } 3290 3291 /* store configuration in all TD's */ 3292 while (1) { 3293 td->hcchar = hcchar; 3294 td->hcsplt = hcsplt; 3295 3296 if (((void *)td) == xfer->td_transfer_last) 3297 break; 3298 3299 td = td->obj_next; 3300 } 3301 } 3302 } 3303 3304 static void 3305 dwc_otg_timeout(void *arg) 3306 { 3307 struct usb_xfer *xfer = arg; 3308 3309 DPRINTF("xfer=%p\n", xfer); 3310 3311 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3312 3313 /* transfer is transferred */ 3314 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3315 } 3316 3317 static void 3318 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3319 { 3320 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3321 3322 DPRINTFN(9, "\n"); 3323 3324 /* 3325 * Poll one time in device mode, which will turn on the 3326 * endpoint interrupts. Else wait for SOF interrupt in host 3327 * mode. 3328 */ 3329 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3330 3331 if (sc->sc_flags.status_device_mode != 0) { 3332 dwc_otg_xfer_do_fifo(sc, xfer); 3333 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3334 goto done; 3335 } 3336 3337 /* put transfer on interrupt queue */ 3338 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3339 3340 /* start timeout, if any */ 3341 if (xfer->timeout != 0) { 3342 usbd_transfer_timeout_ms(xfer, 3343 &dwc_otg_timeout, xfer->timeout); 3344 } 3345 3346 if (sc->sc_flags.status_device_mode != 0) 3347 goto done; 3348 3349 /* enable SOF interrupt, if any */ 3350 dwc_otg_enable_sof_irq(sc); 3351 done: 3352 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3353 } 3354 3355 static void 3356 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3357 { 3358 DPRINTFN(9, "\n"); 3359 3360 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3361 3362 /* set port bit */ 3363 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3364 3365 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3366 sizeof(sc->sc_hub_idata)); 3367 } 3368 3369 static usb_error_t 3370 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3371 { 3372 struct dwc_otg_td *td; 3373 uint32_t len; 3374 usb_error_t error; 3375 3376 DPRINTFN(9, "\n"); 3377 3378 td = xfer->td_transfer_cache; 3379 3380 do { 3381 len = td->remainder; 3382 3383 /* store last data toggle */ 3384 xfer->endpoint->toggle_next = td->toggle; 3385 3386 if (xfer->aframes != xfer->nframes) { 3387 /* 3388 * Verify the length and subtract 3389 * the remainder from "frlengths[]": 3390 */ 3391 if (len > xfer->frlengths[xfer->aframes]) { 3392 td->error_any = 1; 3393 } else { 3394 xfer->frlengths[xfer->aframes] -= len; 3395 } 3396 } 3397 /* Check for transfer error */ 3398 if (td->error_any) { 3399 /* the transfer is finished */ 3400 error = (td->error_stall ? 3401 USB_ERR_STALLED : USB_ERR_IOERROR); 3402 td = NULL; 3403 break; 3404 } 3405 /* Check for short transfer */ 3406 if (len > 0) { 3407 if (xfer->flags_int.short_frames_ok || 3408 xfer->flags_int.isochronous_xfr) { 3409 /* follow alt next */ 3410 if (td->alt_next) { 3411 td = td->obj_next; 3412 } else { 3413 td = NULL; 3414 } 3415 } else { 3416 /* the transfer is finished */ 3417 td = NULL; 3418 } 3419 error = 0; 3420 break; 3421 } 3422 td = td->obj_next; 3423 3424 /* this USB frame is complete */ 3425 error = 0; 3426 break; 3427 3428 } while (0); 3429 3430 /* update transfer cache */ 3431 3432 xfer->td_transfer_cache = td; 3433 3434 return (error); 3435 } 3436 3437 static void 3438 dwc_otg_standard_done(struct usb_xfer *xfer) 3439 { 3440 usb_error_t err = 0; 3441 3442 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3443 xfer, xfer->endpoint); 3444 3445 /* reset scanner */ 3446 3447 xfer->td_transfer_cache = xfer->td_transfer_first; 3448 3449 if (xfer->flags_int.control_xfr) { 3450 3451 if (xfer->flags_int.control_hdr) { 3452 3453 err = dwc_otg_standard_done_sub(xfer); 3454 } 3455 xfer->aframes = 1; 3456 3457 if (xfer->td_transfer_cache == NULL) { 3458 goto done; 3459 } 3460 } 3461 while (xfer->aframes != xfer->nframes) { 3462 3463 err = dwc_otg_standard_done_sub(xfer); 3464 xfer->aframes++; 3465 3466 if (xfer->td_transfer_cache == NULL) { 3467 goto done; 3468 } 3469 } 3470 3471 if (xfer->flags_int.control_xfr && 3472 !xfer->flags_int.control_act) { 3473 3474 err = dwc_otg_standard_done_sub(xfer); 3475 } 3476 done: 3477 dwc_otg_device_done(xfer, err); 3478 } 3479 3480 /*------------------------------------------------------------------------* 3481 * dwc_otg_device_done 3482 * 3483 * NOTE: this function can be called more than one time on the 3484 * same USB transfer! 3485 *------------------------------------------------------------------------*/ 3486 static void 3487 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3488 { 3489 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3490 3491 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3492 xfer, xfer->endpoint, error); 3493 3494 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3495 3496 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3497 /* Interrupts are cleared by the interrupt handler */ 3498 } else { 3499 struct dwc_otg_td *td; 3500 3501 td = xfer->td_transfer_cache; 3502 if (td != NULL) 3503 dwc_otg_host_channel_free(sc, td); 3504 } 3505 /* dequeue transfer and start next transfer */ 3506 usbd_transfer_done(xfer, error); 3507 3508 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3509 } 3510 3511 static void 3512 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3513 { 3514 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3515 } 3516 3517 static void 3518 dwc_otg_set_stall(struct usb_device *udev, 3519 struct usb_endpoint *ep, uint8_t *did_stall) 3520 { 3521 struct dwc_otg_softc *sc; 3522 uint32_t temp; 3523 uint32_t reg; 3524 uint8_t ep_no; 3525 3526 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3527 3528 /* check mode */ 3529 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3530 /* not supported */ 3531 return; 3532 } 3533 3534 sc = DWC_OTG_BUS2SC(udev->bus); 3535 3536 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3537 3538 /* get endpoint address */ 3539 ep_no = ep->edesc->bEndpointAddress; 3540 3541 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3542 3543 if (ep_no & UE_DIR_IN) { 3544 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3545 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3546 } else { 3547 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3548 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3549 } 3550 3551 /* disable and stall endpoint */ 3552 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3553 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3554 3555 /* clear active OUT ep */ 3556 if (!(ep_no & UE_DIR_IN)) { 3557 3558 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3559 3560 if (sc->sc_last_rx_status != 0 && 3561 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3562 sc->sc_last_rx_status)) { 3563 /* dump data */ 3564 dwc_otg_common_rx_ack(sc); 3565 /* poll interrupt */ 3566 dwc_otg_interrupt_poll_locked(sc); 3567 dwc_otg_interrupt_complete_locked(sc); 3568 } 3569 } 3570 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3571 } 3572 3573 static void 3574 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3575 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3576 { 3577 uint32_t reg; 3578 uint32_t temp; 3579 3580 if (ep_type == UE_CONTROL) { 3581 /* clearing stall is not needed */ 3582 return; 3583 } 3584 3585 if (ep_dir) { 3586 reg = DOTG_DIEPCTL(ep_no); 3587 } else { 3588 reg = DOTG_DOEPCTL(ep_no); 3589 sc->sc_active_rx_ep |= (1U << ep_no); 3590 } 3591 3592 /* round up and mask away the multiplier count */ 3593 mps = (mps + 3) & 0x7FC; 3594 3595 if (ep_type == UE_BULK) { 3596 temp = DIEPCTL_EPTYPE_SET( 3597 DIEPCTL_EPTYPE_BULK) | 3598 DIEPCTL_USBACTEP; 3599 } else if (ep_type == UE_INTERRUPT) { 3600 temp = DIEPCTL_EPTYPE_SET( 3601 DIEPCTL_EPTYPE_INTERRUPT) | 3602 DIEPCTL_USBACTEP; 3603 } else { 3604 temp = DIEPCTL_EPTYPE_SET( 3605 DIEPCTL_EPTYPE_ISOC) | 3606 DIEPCTL_USBACTEP; 3607 } 3608 3609 temp |= DIEPCTL_MPS_SET(mps); 3610 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3611 3612 if (ep_dir) 3613 sc->sc_in_ctl[ep_no] = temp; 3614 else 3615 sc->sc_out_ctl[ep_no] = temp; 3616 3617 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3618 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3619 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3620 3621 /* we only reset the transmit FIFO */ 3622 if (ep_dir) { 3623 dwc_otg_tx_fifo_reset(sc, 3624 GRSTCTL_TXFIFO(ep_no) | 3625 GRSTCTL_TXFFLSH); 3626 3627 DWC_OTG_WRITE_4(sc, 3628 DOTG_DIEPTSIZ(ep_no), 0); 3629 } 3630 3631 /* poll interrupt */ 3632 dwc_otg_interrupt_poll_locked(sc); 3633 dwc_otg_interrupt_complete_locked(sc); 3634 } 3635 3636 static void 3637 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3638 { 3639 struct dwc_otg_softc *sc; 3640 struct usb_endpoint_descriptor *ed; 3641 3642 DPRINTFN(5, "endpoint=%p\n", ep); 3643 3644 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3645 3646 /* check mode */ 3647 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3648 /* not supported */ 3649 return; 3650 } 3651 /* get softc */ 3652 sc = DWC_OTG_BUS2SC(udev->bus); 3653 3654 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3655 3656 /* get endpoint descriptor */ 3657 ed = ep->edesc; 3658 3659 /* reset endpoint */ 3660 dwc_otg_clear_stall_sub_locked(sc, 3661 UGETW(ed->wMaxPacketSize), 3662 (ed->bEndpointAddress & UE_ADDR), 3663 (ed->bmAttributes & UE_XFERTYPE), 3664 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3665 3666 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3667 } 3668 3669 static void 3670 dwc_otg_device_state_change(struct usb_device *udev) 3671 { 3672 struct dwc_otg_softc *sc; 3673 uint8_t x; 3674 3675 /* check mode */ 3676 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3677 /* not supported */ 3678 return; 3679 } 3680 3681 /* get softc */ 3682 sc = DWC_OTG_BUS2SC(udev->bus); 3683 3684 /* deactivate all other endpoint but the control endpoint */ 3685 if (udev->state == USB_STATE_CONFIGURED || 3686 udev->state == USB_STATE_ADDRESSED) { 3687 3688 USB_BUS_LOCK(&sc->sc_bus); 3689 3690 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3691 3692 if (x < sc->sc_dev_in_ep_max) { 3693 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3694 DIEPCTL_EPDIS); 3695 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3696 } 3697 3698 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3699 DOEPCTL_EPDIS); 3700 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3701 } 3702 USB_BUS_UNLOCK(&sc->sc_bus); 3703 } 3704 } 3705 3706 int 3707 dwc_otg_init(struct dwc_otg_softc *sc) 3708 { 3709 uint32_t temp; 3710 3711 DPRINTF("start\n"); 3712 3713 /* set up the bus structure */ 3714 sc->sc_bus.usbrev = USB_REV_2_0; 3715 sc->sc_bus.methods = &dwc_otg_bus_methods; 3716 3717 usb_callout_init_mtx(&sc->sc_timer, 3718 &sc->sc_bus.bus_mtx, 0); 3719 3720 USB_BUS_LOCK(&sc->sc_bus); 3721 3722 /* turn on clocks */ 3723 dwc_otg_clocks_on(sc); 3724 3725 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3726 DPRINTF("Version = 0x%08x\n", temp); 3727 3728 /* disconnect */ 3729 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3730 DCTL_SFTDISCON); 3731 3732 /* wait for host to detect disconnect */ 3733 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3734 3735 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3736 GRSTCTL_CSFTRST); 3737 3738 /* wait a little bit for block to reset */ 3739 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3740 3741 switch (sc->sc_mode) { 3742 case DWC_MODE_DEVICE: 3743 temp = GUSBCFG_FORCEDEVMODE; 3744 break; 3745 case DWC_MODE_HOST: 3746 temp = GUSBCFG_FORCEHOSTMODE; 3747 break; 3748 default: 3749 temp = 0; 3750 break; 3751 } 3752 3753 /* select HSIC, ULPI or internal PHY mode */ 3754 switch (dwc_otg_phy_type) { 3755 case DWC_OTG_PHY_HSIC: 3756 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3757 GUSBCFG_PHYIF | 3758 GUSBCFG_TRD_TIM_SET(5) | temp); 3759 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3760 0x000000EC); 3761 3762 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3763 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3764 temp & ~GLPMCFG_HSIC_CONN); 3765 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3766 temp | GLPMCFG_HSIC_CONN); 3767 break; 3768 case DWC_OTG_PHY_ULPI: 3769 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3770 GUSBCFG_ULPI_UTMI_SEL | 3771 GUSBCFG_TRD_TIM_SET(5) | temp); 3772 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3773 3774 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3775 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3776 temp & ~GLPMCFG_HSIC_CONN); 3777 break; 3778 case DWC_OTG_PHY_INTERNAL: 3779 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3780 GUSBCFG_PHYSEL | 3781 GUSBCFG_TRD_TIM_SET(5) | temp); 3782 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3783 3784 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3785 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3786 temp & ~GLPMCFG_HSIC_CONN); 3787 3788 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3789 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3790 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3791 DOTG_GGPIO_PWRDWN); 3792 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3793 break; 3794 default: 3795 break; 3796 } 3797 3798 /* clear global nak */ 3799 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3800 DCTL_CGOUTNAK | 3801 DCTL_CGNPINNAK); 3802 3803 /* disable USB port */ 3804 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3805 3806 /* wait 10ms */ 3807 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3808 3809 /* enable USB port */ 3810 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3811 3812 /* wait 10ms */ 3813 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3814 3815 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3816 3817 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3818 3819 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3820 3821 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3822 3823 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3824 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3825 3826 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3827 3828 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3829 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3830 3831 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3832 3833 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3834 3835 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3836 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3837 sc->sc_host_ch_max); 3838 3839 /* setup FIFO */ 3840 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3841 USB_BUS_UNLOCK(&sc->sc_bus); 3842 return (EINVAL); 3843 } 3844 3845 /* enable interrupts */ 3846 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3847 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3848 3849 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3850 3851 /* enable all endpoint interrupts */ 3852 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3853 if (temp & GHWCFG2_MPI) { 3854 uint8_t x; 3855 3856 DPRINTF("Disable Multi Process Interrupts\n"); 3857 3858 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3859 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3860 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3861 } 3862 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 3863 } 3864 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3865 DIEPMSK_XFERCOMPLMSK); 3866 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3867 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3868 } 3869 3870 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3871 /* setup clocks */ 3872 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3873 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3874 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3875 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3876 } 3877 3878 /* only enable global IRQ */ 3879 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3880 GAHBCFG_GLBLINTRMSK); 3881 3882 /* turn off clocks */ 3883 dwc_otg_clocks_off(sc); 3884 3885 /* read initial VBUS state */ 3886 3887 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3888 3889 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3890 3891 dwc_otg_vbus_interrupt(sc, 3892 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3893 3894 USB_BUS_UNLOCK(&sc->sc_bus); 3895 3896 /* catch any lost interrupts */ 3897 3898 dwc_otg_do_poll(&sc->sc_bus); 3899 3900 return (0); /* success */ 3901 } 3902 3903 void 3904 dwc_otg_uninit(struct dwc_otg_softc *sc) 3905 { 3906 USB_BUS_LOCK(&sc->sc_bus); 3907 3908 /* stop host timer */ 3909 dwc_otg_timer_stop(sc); 3910 3911 /* set disconnect */ 3912 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3913 DCTL_SFTDISCON); 3914 3915 /* turn off global IRQ */ 3916 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3917 3918 sc->sc_flags.port_enabled = 0; 3919 sc->sc_flags.port_powered = 0; 3920 sc->sc_flags.status_vbus = 0; 3921 sc->sc_flags.status_bus_reset = 0; 3922 sc->sc_flags.status_suspend = 0; 3923 sc->sc_flags.change_suspend = 0; 3924 sc->sc_flags.change_connect = 1; 3925 3926 dwc_otg_pull_down(sc); 3927 dwc_otg_clocks_off(sc); 3928 3929 USB_BUS_UNLOCK(&sc->sc_bus); 3930 3931 usb_callout_drain(&sc->sc_timer); 3932 } 3933 3934 static void 3935 dwc_otg_suspend(struct dwc_otg_softc *sc) 3936 { 3937 return; 3938 } 3939 3940 static void 3941 dwc_otg_resume(struct dwc_otg_softc *sc) 3942 { 3943 return; 3944 } 3945 3946 static void 3947 dwc_otg_do_poll(struct usb_bus *bus) 3948 { 3949 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3950 3951 USB_BUS_LOCK(&sc->sc_bus); 3952 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3953 dwc_otg_interrupt_poll_locked(sc); 3954 dwc_otg_interrupt_complete_locked(sc); 3955 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3956 USB_BUS_UNLOCK(&sc->sc_bus); 3957 } 3958 3959 /*------------------------------------------------------------------------* 3960 * DWC OTG bulk support 3961 * DWC OTG control support 3962 * DWC OTG interrupt support 3963 *------------------------------------------------------------------------*/ 3964 static void 3965 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3966 { 3967 } 3968 3969 static void 3970 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3971 { 3972 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3973 } 3974 3975 static void 3976 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3977 { 3978 } 3979 3980 static void 3981 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3982 { 3983 /* setup TDs */ 3984 dwc_otg_setup_standard_chain(xfer); 3985 dwc_otg_start_standard_chain(xfer); 3986 } 3987 3988 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3989 { 3990 .open = dwc_otg_device_non_isoc_open, 3991 .close = dwc_otg_device_non_isoc_close, 3992 .enter = dwc_otg_device_non_isoc_enter, 3993 .start = dwc_otg_device_non_isoc_start, 3994 }; 3995 3996 /*------------------------------------------------------------------------* 3997 * DWC OTG full speed isochronous support 3998 *------------------------------------------------------------------------*/ 3999 static void 4000 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4001 { 4002 } 4003 4004 static void 4005 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4006 { 4007 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4008 } 4009 4010 static void 4011 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4012 { 4013 } 4014 4015 static void 4016 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4017 { 4018 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4019 uint32_t temp; 4020 uint32_t msframes; 4021 uint32_t framenum; 4022 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4023 4024 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4025 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4026 4027 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4028 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4029 4030 /* get the current frame index */ 4031 framenum = (temp & HFNUM_FRNUM_MASK); 4032 } else { 4033 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4034 4035 /* get the current frame index */ 4036 framenum = DSTS_SOFFN_GET(temp); 4037 } 4038 4039 if (xfer->xroot->udev->parent_hs_hub != NULL) 4040 framenum /= 8; 4041 4042 framenum &= DWC_OTG_FRAME_MASK; 4043 4044 /* 4045 * Compute number of milliseconds worth of data traffic for 4046 * this USB transfer: 4047 */ 4048 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4049 msframes = ((xfer->nframes << shift) + 7) / 8; 4050 else 4051 msframes = xfer->nframes; 4052 4053 /* 4054 * check if the frame index is within the window where the frames 4055 * will be inserted 4056 */ 4057 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4058 4059 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4060 /* 4061 * If there is data underflow or the pipe queue is 4062 * empty we schedule the transfer a few frames ahead 4063 * of the current frame position. Else two isochronous 4064 * transfers might overlap. 4065 */ 4066 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4067 xfer->endpoint->is_synced = 1; 4068 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4069 } 4070 /* 4071 * compute how many milliseconds the insertion is ahead of the 4072 * current frame position: 4073 */ 4074 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4075 4076 /* 4077 * pre-compute when the isochronous transfer will be finished: 4078 */ 4079 xfer->isoc_time_complete = 4080 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4081 4082 /* setup TDs */ 4083 dwc_otg_setup_standard_chain(xfer); 4084 4085 /* compute frame number for next insertion */ 4086 xfer->endpoint->isoc_next += msframes; 4087 4088 /* start TD chain */ 4089 dwc_otg_start_standard_chain(xfer); 4090 } 4091 4092 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4093 { 4094 .open = dwc_otg_device_isoc_open, 4095 .close = dwc_otg_device_isoc_close, 4096 .enter = dwc_otg_device_isoc_enter, 4097 .start = dwc_otg_device_isoc_start, 4098 }; 4099 4100 /*------------------------------------------------------------------------* 4101 * DWC OTG root control support 4102 *------------------------------------------------------------------------* 4103 * Simulate a hardware HUB by handling all the necessary requests. 4104 *------------------------------------------------------------------------*/ 4105 4106 static const struct usb_device_descriptor dwc_otg_devd = { 4107 .bLength = sizeof(struct usb_device_descriptor), 4108 .bDescriptorType = UDESC_DEVICE, 4109 .bcdUSB = {0x00, 0x02}, 4110 .bDeviceClass = UDCLASS_HUB, 4111 .bDeviceSubClass = UDSUBCLASS_HUB, 4112 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4113 .bMaxPacketSize = 64, 4114 .bcdDevice = {0x00, 0x01}, 4115 .iManufacturer = 1, 4116 .iProduct = 2, 4117 .bNumConfigurations = 1, 4118 }; 4119 4120 static const struct dwc_otg_config_desc dwc_otg_confd = { 4121 .confd = { 4122 .bLength = sizeof(struct usb_config_descriptor), 4123 .bDescriptorType = UDESC_CONFIG, 4124 .wTotalLength[0] = sizeof(dwc_otg_confd), 4125 .bNumInterface = 1, 4126 .bConfigurationValue = 1, 4127 .iConfiguration = 0, 4128 .bmAttributes = UC_SELF_POWERED, 4129 .bMaxPower = 0, 4130 }, 4131 .ifcd = { 4132 .bLength = sizeof(struct usb_interface_descriptor), 4133 .bDescriptorType = UDESC_INTERFACE, 4134 .bNumEndpoints = 1, 4135 .bInterfaceClass = UICLASS_HUB, 4136 .bInterfaceSubClass = UISUBCLASS_HUB, 4137 .bInterfaceProtocol = 0, 4138 }, 4139 .endpd = { 4140 .bLength = sizeof(struct usb_endpoint_descriptor), 4141 .bDescriptorType = UDESC_ENDPOINT, 4142 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4143 .bmAttributes = UE_INTERRUPT, 4144 .wMaxPacketSize[0] = 8, 4145 .bInterval = 255, 4146 }, 4147 }; 4148 4149 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4150 4151 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4152 .bDescLength = sizeof(dwc_otg_hubd), 4153 .bDescriptorType = UDESC_HUB, 4154 .bNbrPorts = 1, 4155 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4156 .bPwrOn2PwrGood = 50, 4157 .bHubContrCurrent = 0, 4158 .DeviceRemovable = {0}, /* port is removable */ 4159 }; 4160 4161 #define STRING_VENDOR \ 4162 "D\0W\0C\0O\0T\0G" 4163 4164 #define STRING_PRODUCT \ 4165 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4166 4167 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4168 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4169 4170 static usb_error_t 4171 dwc_otg_roothub_exec(struct usb_device *udev, 4172 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4173 { 4174 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4175 const void *ptr; 4176 uint16_t len; 4177 uint16_t value; 4178 uint16_t index; 4179 usb_error_t err; 4180 4181 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4182 4183 /* buffer reset */ 4184 ptr = (const void *)&sc->sc_hub_temp; 4185 len = 0; 4186 err = 0; 4187 4188 value = UGETW(req->wValue); 4189 index = UGETW(req->wIndex); 4190 4191 /* demultiplex the control request */ 4192 4193 switch (req->bmRequestType) { 4194 case UT_READ_DEVICE: 4195 switch (req->bRequest) { 4196 case UR_GET_DESCRIPTOR: 4197 goto tr_handle_get_descriptor; 4198 case UR_GET_CONFIG: 4199 goto tr_handle_get_config; 4200 case UR_GET_STATUS: 4201 goto tr_handle_get_status; 4202 default: 4203 goto tr_stalled; 4204 } 4205 break; 4206 4207 case UT_WRITE_DEVICE: 4208 switch (req->bRequest) { 4209 case UR_SET_ADDRESS: 4210 goto tr_handle_set_address; 4211 case UR_SET_CONFIG: 4212 goto tr_handle_set_config; 4213 case UR_CLEAR_FEATURE: 4214 goto tr_valid; /* nop */ 4215 case UR_SET_DESCRIPTOR: 4216 goto tr_valid; /* nop */ 4217 case UR_SET_FEATURE: 4218 default: 4219 goto tr_stalled; 4220 } 4221 break; 4222 4223 case UT_WRITE_ENDPOINT: 4224 switch (req->bRequest) { 4225 case UR_CLEAR_FEATURE: 4226 switch (UGETW(req->wValue)) { 4227 case UF_ENDPOINT_HALT: 4228 goto tr_handle_clear_halt; 4229 case UF_DEVICE_REMOTE_WAKEUP: 4230 goto tr_handle_clear_wakeup; 4231 default: 4232 goto tr_stalled; 4233 } 4234 break; 4235 case UR_SET_FEATURE: 4236 switch (UGETW(req->wValue)) { 4237 case UF_ENDPOINT_HALT: 4238 goto tr_handle_set_halt; 4239 case UF_DEVICE_REMOTE_WAKEUP: 4240 goto tr_handle_set_wakeup; 4241 default: 4242 goto tr_stalled; 4243 } 4244 break; 4245 case UR_SYNCH_FRAME: 4246 goto tr_valid; /* nop */ 4247 default: 4248 goto tr_stalled; 4249 } 4250 break; 4251 4252 case UT_READ_ENDPOINT: 4253 switch (req->bRequest) { 4254 case UR_GET_STATUS: 4255 goto tr_handle_get_ep_status; 4256 default: 4257 goto tr_stalled; 4258 } 4259 break; 4260 4261 case UT_WRITE_INTERFACE: 4262 switch (req->bRequest) { 4263 case UR_SET_INTERFACE: 4264 goto tr_handle_set_interface; 4265 case UR_CLEAR_FEATURE: 4266 goto tr_valid; /* nop */ 4267 case UR_SET_FEATURE: 4268 default: 4269 goto tr_stalled; 4270 } 4271 break; 4272 4273 case UT_READ_INTERFACE: 4274 switch (req->bRequest) { 4275 case UR_GET_INTERFACE: 4276 goto tr_handle_get_interface; 4277 case UR_GET_STATUS: 4278 goto tr_handle_get_iface_status; 4279 default: 4280 goto tr_stalled; 4281 } 4282 break; 4283 4284 case UT_WRITE_CLASS_INTERFACE: 4285 case UT_WRITE_VENDOR_INTERFACE: 4286 /* XXX forward */ 4287 break; 4288 4289 case UT_READ_CLASS_INTERFACE: 4290 case UT_READ_VENDOR_INTERFACE: 4291 /* XXX forward */ 4292 break; 4293 4294 case UT_WRITE_CLASS_DEVICE: 4295 switch (req->bRequest) { 4296 case UR_CLEAR_FEATURE: 4297 goto tr_valid; 4298 case UR_SET_DESCRIPTOR: 4299 case UR_SET_FEATURE: 4300 break; 4301 default: 4302 goto tr_stalled; 4303 } 4304 break; 4305 4306 case UT_WRITE_CLASS_OTHER: 4307 switch (req->bRequest) { 4308 case UR_CLEAR_FEATURE: 4309 goto tr_handle_clear_port_feature; 4310 case UR_SET_FEATURE: 4311 goto tr_handle_set_port_feature; 4312 case UR_CLEAR_TT_BUFFER: 4313 case UR_RESET_TT: 4314 case UR_STOP_TT: 4315 goto tr_valid; 4316 4317 default: 4318 goto tr_stalled; 4319 } 4320 break; 4321 4322 case UT_READ_CLASS_OTHER: 4323 switch (req->bRequest) { 4324 case UR_GET_TT_STATE: 4325 goto tr_handle_get_tt_state; 4326 case UR_GET_STATUS: 4327 goto tr_handle_get_port_status; 4328 default: 4329 goto tr_stalled; 4330 } 4331 break; 4332 4333 case UT_READ_CLASS_DEVICE: 4334 switch (req->bRequest) { 4335 case UR_GET_DESCRIPTOR: 4336 goto tr_handle_get_class_descriptor; 4337 case UR_GET_STATUS: 4338 goto tr_handle_get_class_status; 4339 4340 default: 4341 goto tr_stalled; 4342 } 4343 break; 4344 default: 4345 goto tr_stalled; 4346 } 4347 goto tr_valid; 4348 4349 tr_handle_get_descriptor: 4350 switch (value >> 8) { 4351 case UDESC_DEVICE: 4352 if (value & 0xff) { 4353 goto tr_stalled; 4354 } 4355 len = sizeof(dwc_otg_devd); 4356 ptr = (const void *)&dwc_otg_devd; 4357 goto tr_valid; 4358 case UDESC_CONFIG: 4359 if (value & 0xff) { 4360 goto tr_stalled; 4361 } 4362 len = sizeof(dwc_otg_confd); 4363 ptr = (const void *)&dwc_otg_confd; 4364 goto tr_valid; 4365 case UDESC_STRING: 4366 switch (value & 0xff) { 4367 case 0: /* Language table */ 4368 len = sizeof(usb_string_lang_en); 4369 ptr = (const void *)&usb_string_lang_en; 4370 goto tr_valid; 4371 4372 case 1: /* Vendor */ 4373 len = sizeof(dwc_otg_vendor); 4374 ptr = (const void *)&dwc_otg_vendor; 4375 goto tr_valid; 4376 4377 case 2: /* Product */ 4378 len = sizeof(dwc_otg_product); 4379 ptr = (const void *)&dwc_otg_product; 4380 goto tr_valid; 4381 default: 4382 break; 4383 } 4384 break; 4385 default: 4386 goto tr_stalled; 4387 } 4388 goto tr_stalled; 4389 4390 tr_handle_get_config: 4391 len = 1; 4392 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4393 goto tr_valid; 4394 4395 tr_handle_get_status: 4396 len = 2; 4397 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4398 goto tr_valid; 4399 4400 tr_handle_set_address: 4401 if (value & 0xFF00) { 4402 goto tr_stalled; 4403 } 4404 sc->sc_rt_addr = value; 4405 goto tr_valid; 4406 4407 tr_handle_set_config: 4408 if (value >= 2) { 4409 goto tr_stalled; 4410 } 4411 sc->sc_conf = value; 4412 goto tr_valid; 4413 4414 tr_handle_get_interface: 4415 len = 1; 4416 sc->sc_hub_temp.wValue[0] = 0; 4417 goto tr_valid; 4418 4419 tr_handle_get_tt_state: 4420 tr_handle_get_class_status: 4421 tr_handle_get_iface_status: 4422 tr_handle_get_ep_status: 4423 len = 2; 4424 USETW(sc->sc_hub_temp.wValue, 0); 4425 goto tr_valid; 4426 4427 tr_handle_set_halt: 4428 tr_handle_set_interface: 4429 tr_handle_set_wakeup: 4430 tr_handle_clear_wakeup: 4431 tr_handle_clear_halt: 4432 goto tr_valid; 4433 4434 tr_handle_clear_port_feature: 4435 if (index != 1) 4436 goto tr_stalled; 4437 4438 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4439 4440 switch (value) { 4441 case UHF_PORT_SUSPEND: 4442 dwc_otg_wakeup_peer(sc); 4443 break; 4444 4445 case UHF_PORT_ENABLE: 4446 if (sc->sc_flags.status_device_mode == 0) { 4447 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4448 sc->sc_hprt_val | HPRT_PRTENA); 4449 } 4450 sc->sc_flags.port_enabled = 0; 4451 break; 4452 4453 case UHF_C_PORT_RESET: 4454 sc->sc_flags.change_reset = 0; 4455 break; 4456 4457 case UHF_C_PORT_ENABLE: 4458 sc->sc_flags.change_enabled = 0; 4459 break; 4460 4461 case UHF_C_PORT_OVER_CURRENT: 4462 sc->sc_flags.change_over_current = 0; 4463 break; 4464 4465 case UHF_PORT_TEST: 4466 case UHF_PORT_INDICATOR: 4467 /* nops */ 4468 break; 4469 4470 case UHF_PORT_POWER: 4471 sc->sc_flags.port_powered = 0; 4472 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4473 sc->sc_hprt_val = 0; 4474 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4475 } 4476 dwc_otg_pull_down(sc); 4477 dwc_otg_clocks_off(sc); 4478 break; 4479 4480 case UHF_C_PORT_CONNECTION: 4481 /* clear connect change flag */ 4482 sc->sc_flags.change_connect = 0; 4483 break; 4484 4485 case UHF_C_PORT_SUSPEND: 4486 sc->sc_flags.change_suspend = 0; 4487 break; 4488 4489 default: 4490 err = USB_ERR_IOERROR; 4491 goto done; 4492 } 4493 goto tr_valid; 4494 4495 tr_handle_set_port_feature: 4496 if (index != 1) { 4497 goto tr_stalled; 4498 } 4499 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4500 4501 switch (value) { 4502 case UHF_PORT_ENABLE: 4503 break; 4504 4505 case UHF_PORT_SUSPEND: 4506 if (sc->sc_flags.status_device_mode == 0) { 4507 /* set suspend BIT */ 4508 sc->sc_hprt_val |= HPRT_PRTSUSP; 4509 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4510 4511 /* generate HUB suspend event */ 4512 dwc_otg_suspend_irq(sc); 4513 } 4514 break; 4515 4516 case UHF_PORT_RESET: 4517 if (sc->sc_flags.status_device_mode == 0) { 4518 4519 DPRINTF("PORT RESET\n"); 4520 4521 /* enable PORT reset */ 4522 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4523 4524 /* Wait 62.5ms for reset to complete */ 4525 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4526 4527 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4528 4529 /* Wait 62.5ms for reset to complete */ 4530 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4531 4532 /* reset FIFOs */ 4533 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4534 4535 sc->sc_flags.change_reset = 1; 4536 } else { 4537 err = USB_ERR_IOERROR; 4538 } 4539 break; 4540 4541 case UHF_PORT_TEST: 4542 case UHF_PORT_INDICATOR: 4543 /* nops */ 4544 break; 4545 case UHF_PORT_POWER: 4546 sc->sc_flags.port_powered = 1; 4547 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4548 sc->sc_hprt_val |= HPRT_PRTPWR; 4549 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4550 } 4551 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4552 /* pull up D+, if any */ 4553 dwc_otg_pull_up(sc); 4554 } 4555 break; 4556 default: 4557 err = USB_ERR_IOERROR; 4558 goto done; 4559 } 4560 goto tr_valid; 4561 4562 tr_handle_get_port_status: 4563 4564 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4565 4566 if (index != 1) 4567 goto tr_stalled; 4568 4569 if (sc->sc_flags.status_vbus) 4570 dwc_otg_clocks_on(sc); 4571 else 4572 dwc_otg_clocks_off(sc); 4573 4574 /* Select Device Side Mode */ 4575 4576 if (sc->sc_flags.status_device_mode) { 4577 value = UPS_PORT_MODE_DEVICE; 4578 dwc_otg_timer_stop(sc); 4579 } else { 4580 value = 0; 4581 dwc_otg_timer_start(sc); 4582 } 4583 4584 if (sc->sc_flags.status_high_speed) 4585 value |= UPS_HIGH_SPEED; 4586 else if (sc->sc_flags.status_low_speed) 4587 value |= UPS_LOW_SPEED; 4588 4589 if (sc->sc_flags.port_powered) 4590 value |= UPS_PORT_POWER; 4591 4592 if (sc->sc_flags.port_enabled) 4593 value |= UPS_PORT_ENABLED; 4594 4595 if (sc->sc_flags.port_over_current) 4596 value |= UPS_OVERCURRENT_INDICATOR; 4597 4598 if (sc->sc_flags.status_vbus && 4599 sc->sc_flags.status_bus_reset) 4600 value |= UPS_CURRENT_CONNECT_STATUS; 4601 4602 if (sc->sc_flags.status_suspend) 4603 value |= UPS_SUSPEND; 4604 4605 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4606 4607 value = 0; 4608 4609 if (sc->sc_flags.change_connect) 4610 value |= UPS_C_CONNECT_STATUS; 4611 if (sc->sc_flags.change_suspend) 4612 value |= UPS_C_SUSPEND; 4613 if (sc->sc_flags.change_reset) 4614 value |= UPS_C_PORT_RESET; 4615 if (sc->sc_flags.change_over_current) 4616 value |= UPS_C_OVERCURRENT_INDICATOR; 4617 4618 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4619 len = sizeof(sc->sc_hub_temp.ps); 4620 goto tr_valid; 4621 4622 tr_handle_get_class_descriptor: 4623 if (value & 0xFF) { 4624 goto tr_stalled; 4625 } 4626 ptr = (const void *)&dwc_otg_hubd; 4627 len = sizeof(dwc_otg_hubd); 4628 goto tr_valid; 4629 4630 tr_stalled: 4631 err = USB_ERR_STALLED; 4632 tr_valid: 4633 done: 4634 *plength = len; 4635 *pptr = ptr; 4636 return (err); 4637 } 4638 4639 static void 4640 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4641 { 4642 struct usb_xfer *xfer; 4643 void *last_obj; 4644 uint32_t ntd; 4645 uint32_t n; 4646 uint8_t ep_no; 4647 uint8_t ep_type; 4648 4649 xfer = parm->curr_xfer; 4650 4651 /* 4652 * NOTE: This driver does not use any of the parameters that 4653 * are computed from the following values. Just set some 4654 * reasonable dummies: 4655 */ 4656 parm->hc_max_packet_size = 0x500; 4657 parm->hc_max_packet_count = 3; 4658 parm->hc_max_frame_size = 3 * 0x500; 4659 4660 usbd_transfer_setup_sub(parm); 4661 4662 /* 4663 * compute maximum number of TDs 4664 */ 4665 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4666 4667 if (ep_type == UE_CONTROL) { 4668 4669 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4670 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4671 } else { 4672 4673 ntd = xfer->nframes + 1 /* SYNC */ ; 4674 } 4675 4676 /* 4677 * check if "usbd_transfer_setup_sub" set an error 4678 */ 4679 if (parm->err) 4680 return; 4681 4682 /* 4683 * allocate transfer descriptors 4684 */ 4685 last_obj = NULL; 4686 4687 ep_no = xfer->endpointno & UE_ADDR; 4688 4689 /* 4690 * Check for a valid endpoint profile in USB device mode: 4691 */ 4692 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4693 const struct usb_hw_ep_profile *pf; 4694 4695 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4696 4697 if (pf == NULL) { 4698 /* should not happen */ 4699 parm->err = USB_ERR_INVAL; 4700 return; 4701 } 4702 } 4703 4704 /* align data */ 4705 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4706 4707 for (n = 0; n != ntd; n++) { 4708 4709 struct dwc_otg_td *td; 4710 4711 if (parm->buf) { 4712 4713 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4714 4715 /* compute shared bandwidth resource index for TT */ 4716 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4717 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4718 td->tt_index = parm->udev->device_index; 4719 else 4720 td->tt_index = parm->udev->parent_hs_hub->device_index; 4721 } else { 4722 td->tt_index = parm->udev->device_index; 4723 } 4724 4725 /* init TD */ 4726 td->max_packet_size = xfer->max_packet_size; 4727 td->max_packet_count = xfer->max_packet_count; 4728 td->ep_no = ep_no; 4729 td->ep_type = ep_type; 4730 td->obj_next = last_obj; 4731 4732 last_obj = td; 4733 } 4734 parm->size[0] += sizeof(*td); 4735 } 4736 4737 xfer->td_start[0] = last_obj; 4738 } 4739 4740 static void 4741 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4742 { 4743 return; 4744 } 4745 4746 static void 4747 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4748 struct usb_endpoint *ep) 4749 { 4750 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4751 4752 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4753 ep, udev->address, 4754 edesc->bEndpointAddress, udev->flags.usb_mode, 4755 sc->sc_rt_addr, udev->device_index); 4756 4757 if (udev->device_index != sc->sc_rt_addr) { 4758 4759 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4760 if (udev->speed != USB_SPEED_FULL && 4761 udev->speed != USB_SPEED_HIGH) { 4762 /* not supported */ 4763 return; 4764 } 4765 } else { 4766 if (udev->speed == USB_SPEED_HIGH) { 4767 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4768 /* high bandwidth endpoint - not tested */ 4769 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4770 return; 4771 } 4772 } 4773 } 4774 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4775 ep->methods = &dwc_otg_device_isoc_methods; 4776 else 4777 ep->methods = &dwc_otg_device_non_isoc_methods; 4778 } 4779 } 4780 4781 static void 4782 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4783 { 4784 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4785 4786 switch (state) { 4787 case USB_HW_POWER_SUSPEND: 4788 dwc_otg_suspend(sc); 4789 break; 4790 case USB_HW_POWER_SHUTDOWN: 4791 dwc_otg_uninit(sc); 4792 break; 4793 case USB_HW_POWER_RESUME: 4794 dwc_otg_resume(sc); 4795 break; 4796 default: 4797 break; 4798 } 4799 } 4800 4801 static void 4802 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4803 { 4804 /* DMA delay - wait until any use of memory is finished */ 4805 *pus = (2125); /* microseconds */ 4806 } 4807 4808 static void 4809 dwc_otg_device_resume(struct usb_device *udev) 4810 { 4811 DPRINTF("\n"); 4812 4813 /* poll all transfers again to restart resumed ones */ 4814 dwc_otg_do_poll(udev->bus); 4815 } 4816 4817 static void 4818 dwc_otg_device_suspend(struct usb_device *udev) 4819 { 4820 DPRINTF("\n"); 4821 } 4822 4823 static const struct usb_bus_methods dwc_otg_bus_methods = 4824 { 4825 .endpoint_init = &dwc_otg_ep_init, 4826 .xfer_setup = &dwc_otg_xfer_setup, 4827 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4828 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4829 .xfer_stall = &dwc_otg_xfer_stall, 4830 .set_stall = &dwc_otg_set_stall, 4831 .clear_stall = &dwc_otg_clear_stall, 4832 .roothub_exec = &dwc_otg_roothub_exec, 4833 .xfer_poll = &dwc_otg_do_poll, 4834 .device_state_change = &dwc_otg_device_state_change, 4835 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4836 .get_dma_delay = &dwc_otg_get_dma_delay, 4837 .device_resume = &dwc_otg_device_resume, 4838 .device_suspend = &dwc_otg_device_suspend, 4839 }; 4840