1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the DesignWare series USB 2.0 OTG 29 * Controller. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 #include <dev/usb/controller/dwc_otgreg.h> 85 86 #define DWC_OTG_BUS2SC(bus) \ 87 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 89 90 #define DWC_OTG_PC2SC(pc) \ 91 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 92 93 #define DWC_OTG_MSK_GINT_ENABLED \ 94 (GINTSTS_ENUMDONE | \ 95 GINTSTS_USBRST | \ 96 GINTSTS_USBSUSP | \ 97 GINTSTS_IEPINT | \ 98 GINTSTS_RXFLVL | \ 99 GINTSTS_SESSREQINT | \ 100 GINTMSK_OTGINTMSK | \ 101 GINTMSK_HCHINTMSK | \ 102 GINTSTS_PRTINT) 103 104 static int dwc_otg_use_hsic; 105 106 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 107 108 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 109 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 110 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 111 112 #ifdef USB_DEBUG 113 static int dwc_otg_debug; 114 115 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 116 &dwc_otg_debug, 0, "DWC OTG debug level"); 117 #endif 118 119 #define DWC_OTG_INTR_ENDPT 1 120 121 /* prototypes */ 122 123 struct usb_bus_methods dwc_otg_bus_methods; 124 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 125 struct usb_pipe_methods dwc_otg_device_isoc_methods; 126 127 static dwc_otg_cmd_t dwc_otg_setup_rx; 128 static dwc_otg_cmd_t dwc_otg_data_rx; 129 static dwc_otg_cmd_t dwc_otg_data_tx; 130 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 131 132 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 133 static dwc_otg_cmd_t dwc_otg_host_data_tx; 134 static dwc_otg_cmd_t dwc_otg_host_data_rx; 135 136 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 137 static void dwc_otg_do_poll(struct usb_bus *); 138 static void dwc_otg_standard_done(struct usb_xfer *); 139 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 140 static void dwc_otg_interrupt_poll(struct dwc_otg_softc *sc); 141 142 /* 143 * Here is a configuration that the chip supports. 144 */ 145 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 146 147 [0] = { 148 .max_in_frame_size = 64,/* fixed */ 149 .max_out_frame_size = 64, /* fixed */ 150 .is_simplex = 1, 151 .support_control = 1, 152 } 153 }; 154 155 static void 156 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 157 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 158 { 159 struct dwc_otg_softc *sc; 160 161 sc = DWC_OTG_BUS2SC(udev->bus); 162 163 if (ep_addr < sc->sc_dev_ep_max) 164 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 165 else 166 *ppf = NULL; 167 } 168 169 static int 170 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 171 { 172 struct dwc_otg_profile *pf; 173 uint32_t fifo_size; 174 uint32_t fifo_regs; 175 uint32_t tx_start; 176 uint8_t x; 177 178 fifo_size = sc->sc_fifo_size; 179 180 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 181 182 if (fifo_size >= fifo_regs) 183 fifo_size -= fifo_regs; 184 else 185 fifo_size = 0; 186 187 /* split equally for IN and OUT */ 188 fifo_size /= 2; 189 190 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 191 192 /* align to 4-bytes */ 193 fifo_size &= ~3; 194 195 tx_start = fifo_size; 196 197 if (fifo_size < 0x40) { 198 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 199 USB_BUS_UNLOCK(&sc->sc_bus); 200 return (EINVAL); 201 } 202 203 if (mode == DWC_MODE_HOST) { 204 205 /* reset active endpoints */ 206 sc->sc_active_rx_ep = 0; 207 208 fifo_size /= 2; 209 210 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 211 ((fifo_size / 4) << 16) | 212 (tx_start / 4)); 213 214 tx_start += fifo_size; 215 216 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 217 ((fifo_size / 4) << 16) | 218 (tx_start / 4)); 219 220 for (x = 0; x != sc->sc_host_ch_max; x++) { 221 /* enable interrupts */ 222 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 223 HCINT_STALL | HCINT_BBLERR | 224 HCINT_XACTERR | 225 HCINT_NAK | HCINT_ACK | HCINT_NYET | 226 HCINT_CHHLTD | HCINT_FRMOVRUN | 227 HCINT_DATATGLERR); 228 } 229 230 /* enable host channel interrupts */ 231 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 232 (1U << sc->sc_host_ch_max) - 1U); 233 } 234 235 if (mode == DWC_MODE_DEVICE) { 236 237 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 238 (0x10 << 16) | (tx_start / 4)); 239 fifo_size -= 0x40; 240 tx_start += 0x40; 241 242 /* setup control endpoint profile */ 243 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 244 245 /* reset active endpoints */ 246 sc->sc_active_rx_ep = 1; 247 248 for (x = 1; x != sc->sc_dev_ep_max; x++) { 249 250 pf = sc->sc_hw_ep_profile + x; 251 252 pf->usb.max_out_frame_size = 1024 * 3; 253 pf->usb.is_simplex = 0; /* assume duplex */ 254 pf->usb.support_bulk = 1; 255 pf->usb.support_interrupt = 1; 256 pf->usb.support_isochronous = 1; 257 pf->usb.support_out = 1; 258 259 if (x < sc->sc_dev_in_ep_max) { 260 uint32_t limit; 261 262 limit = (x == 1) ? DWC_OTG_MAX_TXN : 263 (DWC_OTG_MAX_TXN / 2); 264 265 if (fifo_size >= limit) { 266 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 267 ((limit / 4) << 16) | 268 (tx_start / 4)); 269 tx_start += limit; 270 fifo_size -= limit; 271 pf->usb.max_in_frame_size = 0x200; 272 pf->usb.support_in = 1; 273 pf->max_buffer = limit; 274 275 } else if (fifo_size >= 0x80) { 276 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 277 ((0x80 / 4) << 16) | (tx_start / 4)); 278 tx_start += 0x80; 279 fifo_size -= 0x80; 280 pf->usb.max_in_frame_size = 0x40; 281 pf->usb.support_in = 1; 282 283 } else { 284 pf->usb.is_simplex = 1; 285 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 286 (0x0 << 16) | (tx_start / 4)); 287 } 288 } else { 289 pf->usb.is_simplex = 1; 290 } 291 292 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 293 pf->usb.max_in_frame_size, 294 pf->usb.max_out_frame_size); 295 } 296 } 297 298 /* reset RX FIFO */ 299 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 300 GRSTCTL_RXFFLSH); 301 302 if (mode != DWC_MODE_OTG) { 303 /* reset all TX FIFOs */ 304 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 305 GRSTCTL_TXFIFO(0x10) | 306 GRSTCTL_TXFFLSH); 307 } else { 308 /* reset active endpoints */ 309 sc->sc_active_rx_ep = 0; 310 } 311 return (0); 312 } 313 314 static void 315 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 316 { 317 if (sc->sc_flags.clocks_off && 318 sc->sc_flags.port_powered) { 319 320 DPRINTFN(5, "\n"); 321 322 /* TODO - platform specific */ 323 324 sc->sc_flags.clocks_off = 0; 325 } 326 } 327 328 static void 329 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 330 { 331 if (!sc->sc_flags.clocks_off) { 332 333 DPRINTFN(5, "\n"); 334 335 /* TODO - platform specific */ 336 337 sc->sc_flags.clocks_off = 1; 338 } 339 } 340 341 static void 342 dwc_otg_pull_up(struct dwc_otg_softc *sc) 343 { 344 uint32_t temp; 345 346 /* pullup D+, if possible */ 347 348 if (!sc->sc_flags.d_pulled_up && 349 sc->sc_flags.port_powered) { 350 sc->sc_flags.d_pulled_up = 1; 351 352 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 353 temp &= ~DCTL_SFTDISCON; 354 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 355 } 356 } 357 358 static void 359 dwc_otg_pull_down(struct dwc_otg_softc *sc) 360 { 361 uint32_t temp; 362 363 /* pulldown D+, if possible */ 364 365 if (sc->sc_flags.d_pulled_up) { 366 sc->sc_flags.d_pulled_up = 0; 367 368 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 369 temp |= DCTL_SFTDISCON; 370 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 371 } 372 } 373 374 static void 375 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 376 { 377 if (sc->sc_flags.status_suspend) { 378 /* update status bits */ 379 sc->sc_flags.status_suspend = 0; 380 sc->sc_flags.change_suspend = 1; 381 382 if (sc->sc_flags.status_device_mode) { 383 /* 384 * Disable resume interrupt and enable suspend 385 * interrupt: 386 */ 387 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 388 sc->sc_irq_mask |= GINTSTS_USBSUSP; 389 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 390 } 391 392 /* complete root HUB interrupt endpoint */ 393 dwc_otg_root_intr(sc); 394 } 395 } 396 397 static void 398 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 399 { 400 if (!sc->sc_flags.status_suspend) { 401 /* update status bits */ 402 sc->sc_flags.status_suspend = 1; 403 sc->sc_flags.change_suspend = 1; 404 405 if (sc->sc_flags.status_device_mode) { 406 /* 407 * Disable suspend interrupt and enable resume 408 * interrupt: 409 */ 410 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 411 sc->sc_irq_mask |= GINTSTS_WKUPINT; 412 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 413 } 414 415 /* complete root HUB interrupt endpoint */ 416 dwc_otg_root_intr(sc); 417 } 418 } 419 420 static void 421 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 422 { 423 if (!sc->sc_flags.status_suspend) 424 return; 425 426 DPRINTFN(5, "Remote wakeup\n"); 427 428 if (sc->sc_flags.status_device_mode) { 429 uint32_t temp; 430 431 /* enable remote wakeup signalling */ 432 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 433 temp |= DCTL_RMTWKUPSIG; 434 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 435 436 /* Wait 8ms for remote wakeup to complete. */ 437 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 438 439 temp &= ~DCTL_RMTWKUPSIG; 440 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 441 } else { 442 /* enable USB port */ 443 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 444 445 /* wait 10ms */ 446 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 447 448 /* resume port */ 449 sc->sc_hprt_val |= HPRT_PRTRES; 450 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 451 452 /* Wait 100ms for resume signalling to complete. */ 453 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 454 455 /* clear suspend and resume */ 456 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 457 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 458 459 /* Wait 4ms */ 460 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 461 } 462 463 /* need to fake resume IRQ */ 464 dwc_otg_resume_irq(sc); 465 } 466 467 static void 468 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 469 { 470 uint32_t temp; 471 472 DPRINTFN(5, "addr=%d\n", addr); 473 474 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 475 temp &= ~DCFG_DEVADDR_SET(0x7F); 476 temp |= DCFG_DEVADDR_SET(addr); 477 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 478 } 479 480 static void 481 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 482 { 483 DPRINTFN(5, "RX status clear\n"); 484 485 /* enable RX FIFO level interrupt */ 486 sc->sc_irq_mask |= GINTSTS_RXFLVL; 487 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 488 489 /* clear cached status */ 490 sc->sc_last_rx_status = 0; 491 } 492 493 static void 494 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 495 { 496 uint32_t hcint; 497 498 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 499 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 500 501 /* clear buffered interrupts */ 502 sc->sc_chan_state[x].hcint = 0; 503 } 504 505 static uint8_t 506 dwc_otg_host_channel_wait(struct dwc_otg_td *td) 507 { 508 struct dwc_otg_softc *sc; 509 uint8_t x; 510 511 x = td->channel; 512 513 DPRINTF("CH=%d\n", x); 514 515 /* get pointer to softc */ 516 sc = DWC_OTG_PC2SC(td->pc); 517 518 if (sc->sc_chan_state[x].wait_sof == 0) { 519 dwc_otg_clear_hcint(sc, x); 520 return (1); /* done */ 521 } 522 523 if (x == 0) 524 return (0); /* wait */ 525 526 /* assume NAK-ing is next */ 527 if (sc->sc_chan_state[x].hcint & HCINT_NYET) 528 return (0); /* wait */ 529 530 /* find new disabled channel */ 531 for (x = 1; x != sc->sc_host_ch_max; x++) { 532 533 if (sc->sc_chan_state[x].allocated) 534 continue; 535 if (sc->sc_chan_state[x].wait_sof != 0) 536 continue; 537 538 sc->sc_chan_state[td->channel].allocated = 0; 539 sc->sc_chan_state[x].allocated = 1; 540 541 if (sc->sc_chan_state[td->channel].suspended) { 542 sc->sc_chan_state[td->channel].suspended = 0; 543 sc->sc_chan_state[x].suspended = 1; 544 } 545 546 /* clear interrupts */ 547 dwc_otg_clear_hcint(sc, x); 548 549 DPRINTF("CH=%d HCCHAR=0x%08x " 550 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 551 552 /* ack any pending messages */ 553 if (sc->sc_last_rx_status != 0 && 554 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == td->channel) { 555 /* get rid of message */ 556 dwc_otg_common_rx_ack(sc); 557 } 558 559 /* move active channel */ 560 sc->sc_active_rx_ep &= ~(1 << td->channel); 561 sc->sc_active_rx_ep |= (1 << x); 562 563 /* set channel */ 564 td->channel = x; 565 566 return (1); /* new channel allocated */ 567 } 568 return (0); /* wait */ 569 } 570 571 static uint8_t 572 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 573 { 574 struct dwc_otg_softc *sc; 575 uint8_t x; 576 uint8_t max_channel; 577 578 if (td->channel < DWC_OTG_MAX_CHANNELS) 579 return (0); /* already allocated */ 580 581 /* get pointer to softc */ 582 sc = DWC_OTG_PC2SC(td->pc); 583 584 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 585 max_channel = 1; 586 x = 0; 587 } else { 588 max_channel = sc->sc_host_ch_max; 589 x = 1; 590 } 591 592 for (; x != max_channel; x++) { 593 594 if (sc->sc_chan_state[x].allocated) 595 continue; 596 if (sc->sc_chan_state[x].wait_sof != 0) 597 continue; 598 599 sc->sc_chan_state[x].allocated = 1; 600 601 /* clear interrupts */ 602 dwc_otg_clear_hcint(sc, x); 603 604 DPRINTF("CH=%d HCCHAR=0x%08x " 605 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 606 607 /* set active channel */ 608 sc->sc_active_rx_ep |= (1 << x); 609 610 /* set channel */ 611 td->channel = x; 612 613 return (0); /* allocated */ 614 } 615 return (1); /* busy */ 616 } 617 618 static void 619 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 620 { 621 uint32_t hcchar; 622 if (sc->sc_chan_state[x].wait_sof != 0) 623 return; 624 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 625 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 626 /* disable channel */ 627 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 628 HCCHAR_CHENA | HCCHAR_CHDIS); 629 /* don't re-use channel until next SOF is transmitted */ 630 sc->sc_chan_state[x].wait_sof = 2; 631 /* enable SOF interrupt */ 632 sc->sc_irq_mask |= GINTMSK_SOFMSK; 633 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 634 } 635 } 636 637 static void 638 dwc_otg_host_channel_free(struct dwc_otg_td *td) 639 { 640 struct dwc_otg_softc *sc; 641 uint8_t x; 642 643 if (td->channel >= DWC_OTG_MAX_CHANNELS) 644 return; /* already freed */ 645 646 /* free channel */ 647 x = td->channel; 648 td->channel = DWC_OTG_MAX_CHANNELS; 649 650 DPRINTF("CH=%d\n", x); 651 652 /* get pointer to softc */ 653 sc = DWC_OTG_PC2SC(td->pc); 654 655 dwc_otg_host_channel_disable(sc, x); 656 657 sc->sc_chan_state[x].allocated = 0; 658 sc->sc_chan_state[x].suspended = 0; 659 660 /* ack any pending messages */ 661 if (sc->sc_last_rx_status != 0 && 662 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 663 dwc_otg_common_rx_ack(sc); 664 } 665 666 /* clear active channel */ 667 sc->sc_active_rx_ep &= ~(1 << x); 668 } 669 670 static uint8_t 671 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 672 { 673 struct usb_device_request req __aligned(4); 674 struct dwc_otg_softc *sc; 675 uint32_t hcint; 676 uint32_t hcchar; 677 678 if (dwc_otg_host_channel_alloc(td)) 679 return (1); /* busy */ 680 681 /* get pointer to softc */ 682 sc = DWC_OTG_PC2SC(td->pc); 683 684 hcint = sc->sc_chan_state[td->channel].hcint; 685 686 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 687 td->channel, td->state, hcint, 688 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 689 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 690 691 if (hcint & HCINT_STALL) { 692 DPRINTF("CH=%d STALL\n", td->channel); 693 td->error_stall = 1; 694 td->error_any = 1; 695 return (0); /* complete */ 696 } 697 698 if (hcint & HCINT_ERRORS) { 699 DPRINTF("CH=%d ERROR\n", td->channel); 700 td->errcnt++; 701 if (td->hcsplt != 0 || td->errcnt >= 3) { 702 td->error_any = 1; 703 return (0); /* complete */ 704 } 705 } 706 707 /* channel must be disabled before we can complete the transfer */ 708 709 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 710 HCINT_ACK | HCINT_NYET)) { 711 712 dwc_otg_host_channel_disable(sc, td->channel); 713 714 if (!(hcint & HCINT_ERRORS)) 715 td->errcnt = 0; 716 } 717 718 switch (td->state) { 719 case DWC_CHAN_ST_START: 720 goto send_pkt; 721 722 case DWC_CHAN_ST_WAIT_ANE: 723 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 724 if (!dwc_otg_host_channel_wait(td)) 725 break; 726 td->did_nak = 1; 727 goto send_pkt; 728 } 729 if (hcint & (HCINT_ACK | HCINT_NYET)) { 730 if (!dwc_otg_host_channel_wait(td)) 731 break; 732 td->offset += td->tx_bytes; 733 td->remainder -= td->tx_bytes; 734 td->toggle = 1; 735 return (0); /* complete */ 736 } 737 break; 738 case DWC_CHAN_ST_WAIT_S_ANE: 739 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 740 if (!dwc_otg_host_channel_wait(td)) 741 break; 742 td->did_nak = 1; 743 goto send_pkt; 744 } 745 if (hcint & (HCINT_ACK | HCINT_NYET)) { 746 if (!dwc_otg_host_channel_wait(td)) 747 break; 748 goto send_cpkt; 749 } 750 break; 751 case DWC_CHAN_ST_WAIT_C_ANE: 752 if (hcint & HCINT_NYET) { 753 if (!dwc_otg_host_channel_wait(td)) 754 break; 755 goto send_cpkt; 756 } 757 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 758 if (!dwc_otg_host_channel_wait(td)) 759 break; 760 td->did_nak = 1; 761 goto send_pkt; 762 } 763 if (hcint & HCINT_ACK) { 764 if (!dwc_otg_host_channel_wait(td)) 765 break; 766 td->offset += td->tx_bytes; 767 td->remainder -= td->tx_bytes; 768 td->toggle = 1; 769 return (0); /* complete */ 770 } 771 break; 772 default: 773 break; 774 } 775 return (1); /* busy */ 776 777 send_pkt: 778 if (sizeof(req) != td->remainder) { 779 td->error_any = 1; 780 return (0); /* complete */ 781 } 782 783 if (td->hcsplt != 0) { 784 td->hcsplt &= ~HCSPLT_COMPSPLT; 785 td->state = DWC_CHAN_ST_WAIT_S_ANE; 786 } else { 787 td->state = DWC_CHAN_ST_WAIT_ANE; 788 } 789 790 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 791 792 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 793 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 794 (1 << HCTSIZ_PKTCNT_SHIFT) | 795 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 796 797 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 798 799 hcchar = td->hcchar; 800 hcchar &= ~HCCHAR_EPDIR_IN; 801 802 /* must enable channel before writing data to FIFO */ 803 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 804 805 /* transfer data into FIFO */ 806 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 807 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 808 809 /* store number of bytes transmitted */ 810 td->tx_bytes = sizeof(req); 811 812 return (1); /* busy */ 813 814 send_cpkt: 815 td->hcsplt |= HCSPLT_COMPSPLT; 816 td->state = DWC_CHAN_ST_WAIT_C_ANE; 817 818 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 819 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 820 821 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 822 823 hcchar = td->hcchar; 824 hcchar &= ~HCCHAR_EPDIR_IN; 825 826 /* must enable channel before writing data to FIFO */ 827 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 828 829 return (1); /* busy */ 830 } 831 832 static uint8_t 833 dwc_otg_setup_rx(struct dwc_otg_td *td) 834 { 835 struct dwc_otg_softc *sc; 836 struct usb_device_request req __aligned(4); 837 uint32_t temp; 838 uint16_t count; 839 840 /* get pointer to softc */ 841 sc = DWC_OTG_PC2SC(td->pc); 842 843 /* check endpoint status */ 844 845 if (sc->sc_last_rx_status == 0) 846 goto not_complete; 847 848 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 849 goto not_complete; 850 851 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 852 GRXSTSRD_DPID_DATA0) { 853 /* release FIFO */ 854 dwc_otg_common_rx_ack(sc); 855 goto not_complete; 856 } 857 858 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 859 GRXSTSRD_STP_DATA) { 860 /* release FIFO */ 861 dwc_otg_common_rx_ack(sc); 862 goto not_complete; 863 } 864 865 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 866 867 /* clear did stall */ 868 td->did_stall = 0; 869 870 /* get the packet byte count */ 871 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 872 873 /* verify data length */ 874 if (count != td->remainder) { 875 DPRINTFN(0, "Invalid SETUP packet " 876 "length, %d bytes\n", count); 877 /* release FIFO */ 878 dwc_otg_common_rx_ack(sc); 879 goto not_complete; 880 } 881 if (count != sizeof(req)) { 882 DPRINTFN(0, "Unsupported SETUP packet " 883 "length, %d bytes\n", count); 884 /* release FIFO */ 885 dwc_otg_common_rx_ack(sc); 886 goto not_complete; 887 } 888 889 /* copy in control request */ 890 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 891 892 /* copy data into real buffer */ 893 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 894 895 td->offset = sizeof(req); 896 td->remainder = 0; 897 898 /* sneak peek the set address */ 899 if ((req.bmRequestType == UT_WRITE_DEVICE) && 900 (req.bRequest == UR_SET_ADDRESS)) { 901 /* must write address before ZLP */ 902 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 903 } 904 905 /* don't send any data by default */ 906 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 907 DXEPTSIZ_SET_NPKT(0) | 908 DXEPTSIZ_SET_NBYTES(0)); 909 910 temp = sc->sc_in_ctl[0]; 911 912 /* enable IN endpoint */ 913 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 914 temp | DIEPCTL_EPENA); 915 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 916 temp | DIEPCTL_SNAK); 917 918 /* reset IN endpoint buffer */ 919 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 920 GRSTCTL_TXFIFO(0) | 921 GRSTCTL_TXFFLSH); 922 923 /* acknowledge RX status */ 924 dwc_otg_common_rx_ack(sc); 925 return (0); /* complete */ 926 927 not_complete: 928 /* abort any ongoing transfer, before enabling again */ 929 930 temp = sc->sc_out_ctl[0]; 931 932 temp |= DOEPCTL_EPENA | 933 DOEPCTL_SNAK; 934 935 /* enable OUT endpoint */ 936 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 937 938 if (!td->did_stall) { 939 td->did_stall = 1; 940 941 DPRINTFN(5, "stalling IN and OUT direction\n"); 942 943 /* set stall after enabling endpoint */ 944 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 945 temp | DOEPCTL_STALL); 946 947 temp = sc->sc_in_ctl[0]; 948 949 /* set stall assuming endpoint is enabled */ 950 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 951 temp | DIEPCTL_STALL); 952 } 953 954 /* setup number of buffers to receive */ 955 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 956 DXEPTSIZ_SET_MULTI(3) | 957 DXEPTSIZ_SET_NPKT(1) | 958 DXEPTSIZ_SET_NBYTES(sizeof(req))); 959 960 return (1); /* not complete */ 961 } 962 963 static uint8_t 964 dwc_otg_host_rate_check(struct dwc_otg_td *td, 965 uint8_t do_inc) 966 { 967 struct dwc_otg_softc *sc; 968 uint8_t ep_type; 969 970 /* get pointer to softc */ 971 sc = DWC_OTG_PC2SC(td->pc); 972 973 ep_type = ((td->hcchar & 974 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 975 976 if (sc->sc_chan_state[td->channel].suspended) 977 goto busy; 978 979 if (ep_type == UE_ISOCHRONOUS) { 980 if (td->tmr_val & 1) 981 td->hcchar |= HCCHAR_ODDFRM; 982 else 983 td->hcchar &= ~HCCHAR_ODDFRM; 984 if (do_inc) 985 td->tmr_val += td->tmr_res; 986 } else if (ep_type == UE_INTERRUPT) { 987 if ((sc->sc_tmr_val & 0xFF) != td->tmr_val) 988 goto busy; 989 if (do_inc) 990 td->tmr_val += td->tmr_res; 991 } else if (td->did_nak != 0) { 992 goto busy; 993 } 994 995 if (ep_type == UE_ISOCHRONOUS) { 996 td->toggle = 0; 997 } else if (td->set_toggle) { 998 td->set_toggle = 0; 999 td->toggle = 1; 1000 } 1001 return (0); 1002 busy: 1003 return (1); 1004 } 1005 1006 static uint8_t 1007 dwc_otg_host_data_rx(struct dwc_otg_td *td) 1008 { 1009 struct dwc_otg_softc *sc; 1010 uint32_t hcint; 1011 uint32_t hcchar; 1012 uint32_t count; 1013 1014 if (dwc_otg_host_channel_alloc(td)) 1015 return (1); /* busy */ 1016 1017 /* get pointer to softc */ 1018 sc = DWC_OTG_PC2SC(td->pc); 1019 1020 hcint = sc->sc_chan_state[td->channel].hcint; 1021 1022 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1023 td->channel, td->state, hcint, 1024 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1025 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1026 1027 /* check interrupt bits */ 1028 1029 if (hcint & HCINT_STALL) { 1030 DPRINTF("CH=%d STALL\n", td->channel); 1031 td->error_stall = 1; 1032 td->error_any = 1; 1033 return (0); /* complete */ 1034 } 1035 1036 if (hcint & HCINT_ERRORS) { 1037 DPRINTF("CH=%d ERROR\n", td->channel); 1038 td->errcnt++; 1039 if (td->hcsplt != 0 || td->errcnt >= 3) { 1040 td->error_any = 1; 1041 return (0); /* complete */ 1042 } 1043 } 1044 1045 /* channel must be disabled before we can complete the transfer */ 1046 1047 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1048 HCINT_ACK | HCINT_NYET)) { 1049 1050 dwc_otg_host_channel_disable(sc, td->channel); 1051 1052 if (!(hcint & HCINT_ERRORS)) 1053 td->errcnt = 0; 1054 } 1055 1056 /* check endpoint status */ 1057 if (sc->sc_last_rx_status == 0) 1058 goto check_state; 1059 1060 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 1061 goto check_state; 1062 1063 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1064 case GRXSTSRH_IN_DATA: 1065 1066 DPRINTF("DATA\n"); 1067 1068 td->toggle ^= 1; 1069 1070 /* get the packet byte count */ 1071 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1072 1073 /* verify the packet byte count */ 1074 if (count != td->max_packet_size) { 1075 if (count < td->max_packet_size) { 1076 /* we have a short packet */ 1077 td->short_pkt = 1; 1078 td->got_short = 1; 1079 } else { 1080 /* invalid USB packet */ 1081 td->error_any = 1; 1082 1083 /* release FIFO */ 1084 dwc_otg_common_rx_ack(sc); 1085 return (0); /* we are complete */ 1086 } 1087 } 1088 1089 /* verify the packet byte count */ 1090 if (count > td->remainder) { 1091 /* invalid USB packet */ 1092 td->error_any = 1; 1093 1094 /* release FIFO */ 1095 dwc_otg_common_rx_ack(sc); 1096 return (0); /* we are complete */ 1097 } 1098 1099 usbd_copy_in(td->pc, td->offset, 1100 sc->sc_rx_bounce_buffer, count); 1101 1102 td->remainder -= count; 1103 td->offset += count; 1104 hcint |= HCINT_SOFTWARE_ONLY | HCINT_ACK; 1105 sc->sc_chan_state[td->channel].hcint = hcint; 1106 break; 1107 1108 default: 1109 DPRINTF("OTHER\n"); 1110 break; 1111 } 1112 /* release FIFO */ 1113 dwc_otg_common_rx_ack(sc); 1114 1115 check_state: 1116 switch (td->state) { 1117 case DWC_CHAN_ST_START: 1118 if (td->hcsplt != 0) 1119 goto receive_spkt; 1120 else 1121 goto receive_pkt; 1122 1123 case DWC_CHAN_ST_WAIT_ANE: 1124 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1125 if (!dwc_otg_host_channel_wait(td)) 1126 break; 1127 1128 td->did_nak = 1; 1129 if (td->hcsplt != 0) 1130 goto receive_spkt; 1131 else 1132 goto receive_pkt; 1133 } 1134 if (hcint & HCINT_NYET) { 1135 if (td->hcsplt != 0) 1136 goto receive_pkt; 1137 } 1138 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1139 break; 1140 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1141 if (!dwc_otg_host_channel_wait(td)) 1142 break; 1143 1144 /* check if we are complete */ 1145 if ((td->remainder == 0) || (td->got_short != 0)) { 1146 if (td->short_pkt) 1147 return (0); /* complete */ 1148 1149 /* 1150 * Else need to receive a zero length 1151 * packet. 1152 */ 1153 } 1154 if (td->hcsplt != 0) 1155 goto receive_spkt; 1156 else 1157 goto receive_pkt; 1158 } 1159 break; 1160 1161 case DWC_CHAN_ST_WAIT_S_ANE: 1162 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1163 if (!dwc_otg_host_channel_wait(td)) 1164 break; 1165 1166 td->did_nak = 1; 1167 goto receive_spkt; 1168 } 1169 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1170 if (!dwc_otg_host_channel_wait(td)) 1171 break; 1172 goto receive_pkt; 1173 } 1174 break; 1175 1176 case DWC_CHAN_ST_RX_PKT: 1177 goto receive_pkt; 1178 1179 case DWC_CHAN_ST_RX_SPKT: 1180 goto receive_spkt; 1181 1182 default: 1183 break; 1184 } 1185 goto busy; 1186 1187 receive_pkt: 1188 if (dwc_otg_host_rate_check(td, 1)) { 1189 td->state = DWC_CHAN_ST_RX_PKT; 1190 dwc_otg_host_channel_free(td); 1191 goto busy; 1192 } 1193 1194 if (td->hcsplt != 0) 1195 td->hcsplt |= HCSPLT_COMPSPLT; 1196 td->state = DWC_CHAN_ST_WAIT_ANE; 1197 1198 /* receive one packet */ 1199 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1200 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1201 (1 << HCTSIZ_PKTCNT_SHIFT) | 1202 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1203 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1204 1205 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1206 1207 hcchar = td->hcchar; 1208 hcchar |= HCCHAR_EPDIR_IN; 1209 1210 /* must enable channel before data can be received */ 1211 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1212 1213 goto busy; 1214 1215 receive_spkt: 1216 if (dwc_otg_host_rate_check(td, 0)) { 1217 td->state = DWC_CHAN_ST_RX_SPKT; 1218 dwc_otg_host_channel_free(td); 1219 goto busy; 1220 } 1221 1222 td->hcsplt &= ~HCSPLT_COMPSPLT; 1223 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1224 1225 /* receive one packet */ 1226 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1227 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1228 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1229 1230 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1231 1232 hcchar = td->hcchar; 1233 hcchar |= HCCHAR_EPDIR_IN; 1234 1235 /* must enable channel before data can be received */ 1236 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1237 1238 busy: 1239 return (1); /* busy */ 1240 } 1241 1242 static uint8_t 1243 dwc_otg_data_rx(struct dwc_otg_td *td) 1244 { 1245 struct dwc_otg_softc *sc; 1246 uint32_t temp; 1247 uint16_t count; 1248 uint8_t got_short; 1249 1250 got_short = 0; 1251 1252 /* get pointer to softc */ 1253 sc = DWC_OTG_PC2SC(td->pc); 1254 1255 /* check endpoint status */ 1256 if (sc->sc_last_rx_status == 0) 1257 goto not_complete; 1258 1259 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1260 goto not_complete; 1261 1262 /* check for SETUP packet */ 1263 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1264 GRXSTSRD_STP_DATA) { 1265 if (td->remainder == 0) { 1266 /* 1267 * We are actually complete and have 1268 * received the next SETUP 1269 */ 1270 DPRINTFN(5, "faking complete\n"); 1271 return (0); /* complete */ 1272 } 1273 /* 1274 * USB Host Aborted the transfer. 1275 */ 1276 td->error_any = 1; 1277 return (0); /* complete */ 1278 } 1279 1280 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1281 GRXSTSRD_OUT_DATA) { 1282 /* release FIFO */ 1283 dwc_otg_common_rx_ack(sc); 1284 goto not_complete; 1285 } 1286 1287 /* get the packet byte count */ 1288 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1289 1290 /* verify the packet byte count */ 1291 if (count != td->max_packet_size) { 1292 if (count < td->max_packet_size) { 1293 /* we have a short packet */ 1294 td->short_pkt = 1; 1295 got_short = 1; 1296 } else { 1297 /* invalid USB packet */ 1298 td->error_any = 1; 1299 1300 /* release FIFO */ 1301 dwc_otg_common_rx_ack(sc); 1302 return (0); /* we are complete */ 1303 } 1304 } 1305 /* verify the packet byte count */ 1306 if (count > td->remainder) { 1307 /* invalid USB packet */ 1308 td->error_any = 1; 1309 1310 /* release FIFO */ 1311 dwc_otg_common_rx_ack(sc); 1312 return (0); /* we are complete */ 1313 } 1314 1315 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1316 td->remainder -= count; 1317 td->offset += count; 1318 1319 /* release FIFO */ 1320 dwc_otg_common_rx_ack(sc); 1321 1322 /* check if we are complete */ 1323 if ((td->remainder == 0) || got_short) { 1324 if (td->short_pkt) { 1325 /* we are complete */ 1326 return (0); 1327 } 1328 /* else need to receive a zero length packet */ 1329 } 1330 1331 not_complete: 1332 1333 temp = sc->sc_out_ctl[td->ep_no]; 1334 1335 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1336 1337 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1338 1339 /* enable SETUP and transfer complete interrupt */ 1340 if (td->ep_no == 0) { 1341 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1342 DXEPTSIZ_SET_NPKT(1) | 1343 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1344 } else { 1345 /* allow reception of multiple packets */ 1346 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1347 DXEPTSIZ_SET_MULTI(1) | 1348 DXEPTSIZ_SET_NPKT(4) | 1349 DXEPTSIZ_SET_NBYTES(4 * 1350 ((td->max_packet_size + 3) & ~3))); 1351 } 1352 return (1); /* not complete */ 1353 } 1354 1355 static uint8_t 1356 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1357 { 1358 struct dwc_otg_softc *sc; 1359 uint32_t count; 1360 uint32_t hcint; 1361 uint32_t hcchar; 1362 uint8_t ep_type; 1363 1364 if (dwc_otg_host_channel_alloc(td)) 1365 return (1); /* busy */ 1366 1367 /* get pointer to softc */ 1368 sc = DWC_OTG_PC2SC(td->pc); 1369 1370 ep_type = ((td->hcchar & 1371 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1372 1373 hcint = sc->sc_chan_state[td->channel].hcint; 1374 1375 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1376 td->channel, td->state, hcint, 1377 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1378 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1379 1380 if (hcint & HCINT_STALL) { 1381 DPRINTF("CH=%d STALL\n", td->channel); 1382 td->error_stall = 1; 1383 td->error_any = 1; 1384 return (0); /* complete */ 1385 } 1386 1387 if (hcint & HCINT_ERRORS) { 1388 DPRINTF("CH=%d ERROR\n", td->channel); 1389 td->errcnt++; 1390 if (td->hcsplt != 0 || td->errcnt >= 3) { 1391 td->error_any = 1; 1392 return (0); /* complete */ 1393 } 1394 } 1395 1396 /* channel must be disabled before we can complete the transfer */ 1397 1398 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1399 HCINT_ACK | HCINT_NYET)) { 1400 1401 dwc_otg_host_channel_disable(sc, td->channel); 1402 1403 if (!(hcint & HCINT_ERRORS)) 1404 td->errcnt = 0; 1405 } 1406 1407 switch (td->state) { 1408 case DWC_CHAN_ST_START: 1409 goto send_pkt; 1410 1411 case DWC_CHAN_ST_WAIT_ANE: 1412 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1413 if (!dwc_otg_host_channel_wait(td)) 1414 break; 1415 td->did_nak = 1; 1416 goto send_pkt; 1417 } 1418 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1419 if (!dwc_otg_host_channel_wait(td)) 1420 break; 1421 1422 td->offset += td->tx_bytes; 1423 td->remainder -= td->tx_bytes; 1424 td->toggle ^= 1; 1425 1426 /* check remainder */ 1427 if (td->remainder == 0) { 1428 if (td->short_pkt) 1429 return (0); /* complete */ 1430 1431 /* 1432 * Else we need to transmit a short 1433 * packet: 1434 */ 1435 } 1436 goto send_pkt; 1437 } 1438 break; 1439 case DWC_CHAN_ST_WAIT_S_ANE: 1440 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1441 if (!dwc_otg_host_channel_wait(td)) 1442 break; 1443 td->did_nak = 1; 1444 goto send_pkt; 1445 } 1446 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1447 if (!dwc_otg_host_channel_wait(td)) 1448 break; 1449 goto send_cpkt; 1450 } 1451 break; 1452 case DWC_CHAN_ST_WAIT_C_ANE: 1453 if (hcint & HCINT_NYET) { 1454 if (!dwc_otg_host_channel_wait(td)) 1455 break; 1456 goto send_cpkt; 1457 } 1458 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1459 if (!dwc_otg_host_channel_wait(td)) 1460 break; 1461 td->did_nak = 1; 1462 goto send_pkt; 1463 } 1464 if (hcint & HCINT_ACK) { 1465 if (!dwc_otg_host_channel_wait(td)) 1466 break; 1467 td->offset += td->tx_bytes; 1468 td->remainder -= td->tx_bytes; 1469 td->toggle ^= 1; 1470 1471 /* check remainder */ 1472 if (td->remainder == 0) { 1473 if (td->short_pkt) 1474 return (0); /* complete */ 1475 1476 /* else we need to transmit a short packet */ 1477 } 1478 goto send_pkt; 1479 } 1480 break; 1481 1482 case DWC_CHAN_ST_TX_PKT: 1483 goto send_pkt; 1484 1485 case DWC_CHAN_ST_TX_CPKT: 1486 goto send_cpkt; 1487 1488 default: 1489 break; 1490 } 1491 goto busy; 1492 1493 send_pkt: 1494 if (dwc_otg_host_rate_check(td, 1)) { 1495 td->state = DWC_CHAN_ST_TX_PKT; 1496 dwc_otg_host_channel_free(td); 1497 goto busy; 1498 } 1499 1500 if (td->hcsplt != 0) { 1501 td->hcsplt &= ~HCSPLT_COMPSPLT; 1502 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1503 } else { 1504 td->state = DWC_CHAN_ST_WAIT_ANE; 1505 } 1506 1507 /* send one packet at a time */ 1508 count = td->max_packet_size; 1509 if (td->remainder < count) { 1510 /* we have a short packet */ 1511 td->short_pkt = 1; 1512 count = td->remainder; 1513 } 1514 1515 /* TODO: HCTSIZ_DOPNG */ 1516 1517 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1518 (count << HCTSIZ_XFERSIZE_SHIFT) | 1519 (1 << HCTSIZ_PKTCNT_SHIFT) | 1520 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1521 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1522 1523 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1524 1525 hcchar = td->hcchar; 1526 hcchar &= ~HCCHAR_EPDIR_IN; 1527 1528 /* must enable before writing data to FIFO */ 1529 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1530 1531 if (count != 0) { 1532 1533 /* clear topmost word before copy */ 1534 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1535 1536 /* copy out data */ 1537 usbd_copy_out(td->pc, td->offset, 1538 sc->sc_tx_bounce_buffer, count); 1539 1540 /* transfer data into FIFO */ 1541 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1542 DOTG_DFIFO(td->channel), 1543 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1544 } 1545 1546 /* store number of bytes transmitted */ 1547 td->tx_bytes = count; 1548 1549 goto busy; 1550 1551 send_cpkt: 1552 td->hcsplt |= HCSPLT_COMPSPLT; 1553 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1554 1555 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1556 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1557 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1558 1559 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1560 1561 hcchar = td->hcchar; 1562 hcchar &= ~HCCHAR_EPDIR_IN; 1563 1564 /* must enable channel before writing data to FIFO */ 1565 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1566 1567 busy: 1568 return (1); /* busy */ 1569 } 1570 1571 static uint8_t 1572 dwc_otg_data_tx(struct dwc_otg_td *td) 1573 { 1574 struct dwc_otg_softc *sc; 1575 uint32_t max_buffer; 1576 uint32_t count; 1577 uint32_t fifo_left; 1578 uint32_t mpkt; 1579 uint32_t temp; 1580 uint8_t to; 1581 1582 to = 3; /* don't loop forever! */ 1583 1584 /* get pointer to softc */ 1585 sc = DWC_OTG_PC2SC(td->pc); 1586 1587 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1588 1589 repeat: 1590 /* check for for endpoint 0 data */ 1591 1592 temp = sc->sc_last_rx_status; 1593 1594 if ((td->ep_no == 0) && (temp != 0) && 1595 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1596 1597 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1598 GRXSTSRD_STP_DATA) { 1599 1600 /* dump data - wrong direction */ 1601 dwc_otg_common_rx_ack(sc); 1602 } else { 1603 /* 1604 * The current transfer was cancelled 1605 * by the USB Host: 1606 */ 1607 td->error_any = 1; 1608 return (0); /* complete */ 1609 } 1610 } 1611 1612 /* fill in more TX data, if possible */ 1613 if (td->tx_bytes != 0) { 1614 1615 uint16_t cpkt; 1616 1617 /* check if packets have been transferred */ 1618 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1619 1620 /* get current packet number */ 1621 cpkt = DXEPTSIZ_GET_NPKT(temp); 1622 1623 if (cpkt >= td->npkt) { 1624 fifo_left = 0; 1625 } else { 1626 if (max_buffer != 0) { 1627 fifo_left = (td->npkt - cpkt) * 1628 td->max_packet_size; 1629 1630 if (fifo_left > max_buffer) 1631 fifo_left = max_buffer; 1632 } else { 1633 fifo_left = td->max_packet_size; 1634 } 1635 } 1636 1637 count = td->tx_bytes; 1638 if (count > fifo_left) 1639 count = fifo_left; 1640 1641 if (count != 0) { 1642 1643 /* clear topmost word before copy */ 1644 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1645 1646 /* copy out data */ 1647 usbd_copy_out(td->pc, td->offset, 1648 sc->sc_tx_bounce_buffer, count); 1649 1650 /* transfer data into FIFO */ 1651 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1652 DOTG_DFIFO(td->ep_no), 1653 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1654 1655 td->tx_bytes -= count; 1656 td->remainder -= count; 1657 td->offset += count; 1658 td->npkt = cpkt; 1659 } 1660 if (td->tx_bytes != 0) 1661 goto not_complete; 1662 1663 /* check remainder */ 1664 if (td->remainder == 0) { 1665 if (td->short_pkt) 1666 return (0); /* complete */ 1667 1668 /* else we need to transmit a short packet */ 1669 } 1670 } 1671 1672 if (!to--) 1673 goto not_complete; 1674 1675 /* check if not all packets have been transferred */ 1676 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1677 1678 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1679 1680 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 1681 "DIEPCTL=0x%08x\n", td->ep_no, 1682 DXEPTSIZ_GET_NPKT(temp), 1683 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 1684 1685 goto not_complete; 1686 } 1687 1688 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 1689 1690 /* try to optimise by sending more data */ 1691 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 1692 1693 /* send multiple packets at the same time */ 1694 mpkt = max_buffer / td->max_packet_size; 1695 1696 if (mpkt > 0x3FE) 1697 mpkt = 0x3FE; 1698 1699 count = td->remainder; 1700 if (count > 0x7FFFFF) 1701 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 1702 1703 td->npkt = count / td->max_packet_size; 1704 1705 /* 1706 * NOTE: We could use 0x3FE instead of "mpkt" in the 1707 * check below to get more throughput, but then we 1708 * have a dependency towards non-generic chip features 1709 * to disable the TX-FIFO-EMPTY interrupts on a per 1710 * endpoint basis. Increase the maximum buffer size of 1711 * the IN endpoint to increase the performance. 1712 */ 1713 if (td->npkt > mpkt) { 1714 td->npkt = mpkt; 1715 count = td->max_packet_size * mpkt; 1716 } else if ((count == 0) || (count % td->max_packet_size)) { 1717 /* we are transmitting a short packet */ 1718 td->npkt++; 1719 td->short_pkt = 1; 1720 } 1721 } else { 1722 /* send one packet at a time */ 1723 mpkt = 1; 1724 count = td->max_packet_size; 1725 if (td->remainder < count) { 1726 /* we have a short packet */ 1727 td->short_pkt = 1; 1728 count = td->remainder; 1729 } 1730 td->npkt = 1; 1731 } 1732 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 1733 DXEPTSIZ_SET_MULTI(1) | 1734 DXEPTSIZ_SET_NPKT(td->npkt) | 1735 DXEPTSIZ_SET_NBYTES(count)); 1736 1737 /* make room for buffering */ 1738 td->npkt += mpkt; 1739 1740 temp = sc->sc_in_ctl[td->ep_no]; 1741 1742 /* must enable before writing data to FIFO */ 1743 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 1744 DIEPCTL_EPENA | 1745 DIEPCTL_CNAK); 1746 1747 td->tx_bytes = count; 1748 1749 /* check remainder */ 1750 if (td->tx_bytes == 0 && 1751 td->remainder == 0) { 1752 if (td->short_pkt) 1753 return (0); /* complete */ 1754 1755 /* else we need to transmit a short packet */ 1756 } 1757 goto repeat; 1758 1759 not_complete: 1760 return (1); /* not complete */ 1761 } 1762 1763 static uint8_t 1764 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 1765 { 1766 struct dwc_otg_softc *sc; 1767 uint32_t temp; 1768 1769 /* get pointer to softc */ 1770 sc = DWC_OTG_PC2SC(td->pc); 1771 1772 /* 1773 * If all packets are transferred we are complete: 1774 */ 1775 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1776 1777 /* check that all packets have been transferred */ 1778 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1779 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 1780 goto not_complete; 1781 } 1782 return (0); 1783 1784 not_complete: 1785 1786 /* we only want to know if there is a SETUP packet or free IN packet */ 1787 1788 temp = sc->sc_last_rx_status; 1789 1790 if ((td->ep_no == 0) && (temp != 0) && 1791 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1792 1793 if ((temp & GRXSTSRD_PKTSTS_MASK) == 1794 GRXSTSRD_STP_DATA) { 1795 DPRINTFN(5, "faking complete\n"); 1796 /* 1797 * Race condition: We are complete! 1798 */ 1799 return (0); 1800 } else { 1801 /* dump data - wrong direction */ 1802 dwc_otg_common_rx_ack(sc); 1803 } 1804 } 1805 return (1); /* not complete */ 1806 } 1807 1808 static uint8_t 1809 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 1810 { 1811 struct dwc_otg_td *td; 1812 uint8_t toggle; 1813 uint8_t channel; 1814 uint8_t tmr_val; 1815 uint8_t tmr_res; 1816 1817 DPRINTFN(9, "\n"); 1818 1819 td = xfer->td_transfer_cache; 1820 1821 /* 1822 * If we are suspended in host mode and no channel is 1823 * allocated, simply return: 1824 */ 1825 if (xfer->xroot->udev->flags.self_suspended != 0 && 1826 xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST && 1827 td->channel >= DWC_OTG_MAX_CHANNELS) { 1828 return (1); /* not complete */ 1829 } 1830 while (1) { 1831 if ((td->func) (td)) { 1832 /* operation in progress */ 1833 break; 1834 } 1835 if (((void *)td) == xfer->td_transfer_last) { 1836 goto done; 1837 } 1838 if (td->error_any) { 1839 goto done; 1840 } else if (td->remainder > 0) { 1841 /* 1842 * We had a short transfer. If there is no alternate 1843 * next, stop processing ! 1844 */ 1845 if (!td->alt_next) 1846 goto done; 1847 } 1848 1849 /* 1850 * Fetch the next transfer descriptor and transfer 1851 * some flags to the next transfer descriptor 1852 */ 1853 tmr_res = td->tmr_res; 1854 tmr_val = td->tmr_val; 1855 toggle = td->toggle; 1856 channel = td->channel; 1857 td = td->obj_next; 1858 xfer->td_transfer_cache = td; 1859 td->toggle = toggle; /* transfer toggle */ 1860 td->channel = channel; /* transfer channel */ 1861 td->tmr_res = tmr_res; 1862 td->tmr_val = tmr_val; 1863 } 1864 return (1); /* not complete */ 1865 1866 done: 1867 /* compute all actual lengths */ 1868 1869 dwc_otg_standard_done(xfer); 1870 return (0); /* complete */ 1871 } 1872 1873 static void 1874 dwc_otg_timer(void *_sc) 1875 { 1876 struct dwc_otg_softc *sc = _sc; 1877 struct usb_xfer *xfer; 1878 struct dwc_otg_td *td; 1879 1880 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1881 1882 DPRINTF("\n"); 1883 1884 /* increment timer value */ 1885 sc->sc_tmr_val++; 1886 1887 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1888 td = xfer->td_transfer_cache; 1889 if (td != NULL) 1890 td->did_nak = 0; 1891 } 1892 1893 /* poll jobs */ 1894 dwc_otg_interrupt_poll(sc); 1895 1896 if (sc->sc_timer_active) { 1897 /* restart timer */ 1898 usb_callout_reset(&sc->sc_timer, 1899 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 1900 &dwc_otg_timer, sc); 1901 } 1902 } 1903 1904 static void 1905 dwc_otg_timer_start(struct dwc_otg_softc *sc) 1906 { 1907 if (sc->sc_timer_active != 0) 1908 return; 1909 1910 sc->sc_timer_active = 1; 1911 1912 /* restart timer */ 1913 usb_callout_reset(&sc->sc_timer, 1914 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 1915 &dwc_otg_timer, sc); 1916 } 1917 1918 static void 1919 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 1920 { 1921 if (sc->sc_timer_active == 0) 1922 return; 1923 1924 sc->sc_timer_active = 0; 1925 1926 /* stop timer */ 1927 usb_callout_stop(&sc->sc_timer); 1928 } 1929 1930 static void 1931 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 1932 { 1933 struct usb_xfer *xfer; 1934 uint32_t temp; 1935 uint8_t got_rx_status; 1936 uint8_t x; 1937 1938 repeat: 1939 /* get all channel interrupts */ 1940 for (x = 0; x != sc->sc_host_ch_max; x++) { 1941 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 1942 if (temp != 0) { 1943 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 1944 temp &= ~HCINT_SOFTWARE_ONLY; 1945 sc->sc_chan_state[x].hcint |= temp; 1946 } 1947 } 1948 1949 if (sc->sc_last_rx_status == 0) { 1950 1951 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 1952 if (temp & GINTSTS_RXFLVL) { 1953 /* pop current status */ 1954 sc->sc_last_rx_status = 1955 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 1956 } 1957 1958 if (sc->sc_last_rx_status != 0) { 1959 1960 uint8_t ep_no; 1961 1962 temp = sc->sc_last_rx_status & 1963 GRXSTSRD_PKTSTS_MASK; 1964 1965 /* non-data messages we simply skip */ 1966 if (temp != GRXSTSRD_STP_DATA && 1967 temp != GRXSTSRD_OUT_DATA) { 1968 dwc_otg_common_rx_ack(sc); 1969 goto repeat; 1970 } 1971 1972 temp = GRXSTSRD_BCNT_GET( 1973 sc->sc_last_rx_status); 1974 ep_no = GRXSTSRD_CHNUM_GET( 1975 sc->sc_last_rx_status); 1976 1977 /* receive data, if any */ 1978 if (temp != 0) { 1979 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 1980 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1981 DOTG_DFIFO(ep_no), 1982 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 1983 } 1984 1985 /* check if we should dump the data */ 1986 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 1987 dwc_otg_common_rx_ack(sc); 1988 goto repeat; 1989 } 1990 1991 got_rx_status = 1; 1992 1993 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 1994 sc->sc_last_rx_status, ep_no, 1995 (sc->sc_last_rx_status >> 15) & 3, 1996 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 1997 (sc->sc_last_rx_status >> 17) & 15); 1998 } else { 1999 got_rx_status = 0; 2000 } 2001 } else { 2002 uint8_t ep_no; 2003 2004 ep_no = GRXSTSRD_CHNUM_GET( 2005 sc->sc_last_rx_status); 2006 2007 /* check if we should dump the data */ 2008 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2009 dwc_otg_common_rx_ack(sc); 2010 goto repeat; 2011 } 2012 2013 got_rx_status = 1; 2014 } 2015 2016 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2017 if (!dwc_otg_xfer_do_fifo(xfer)) { 2018 /* queue has been modified */ 2019 goto repeat; 2020 } 2021 } 2022 2023 if (got_rx_status) { 2024 /* check if data was consumed */ 2025 if (sc->sc_last_rx_status == 0) 2026 goto repeat; 2027 2028 /* disable RX FIFO level interrupt */ 2029 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 2030 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2031 } 2032 } 2033 2034 static void 2035 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2036 { 2037 DPRINTFN(5, "vbus = %u\n", is_on); 2038 2039 if (is_on) { 2040 if (!sc->sc_flags.status_vbus) { 2041 sc->sc_flags.status_vbus = 1; 2042 2043 /* complete root HUB interrupt endpoint */ 2044 2045 dwc_otg_root_intr(sc); 2046 } 2047 } else { 2048 if (sc->sc_flags.status_vbus) { 2049 sc->sc_flags.status_vbus = 0; 2050 sc->sc_flags.status_bus_reset = 0; 2051 sc->sc_flags.status_suspend = 0; 2052 sc->sc_flags.change_suspend = 0; 2053 sc->sc_flags.change_connect = 1; 2054 2055 /* complete root HUB interrupt endpoint */ 2056 2057 dwc_otg_root_intr(sc); 2058 } 2059 } 2060 } 2061 2062 void 2063 dwc_otg_interrupt(struct dwc_otg_softc *sc) 2064 { 2065 uint32_t status; 2066 2067 USB_BUS_LOCK(&sc->sc_bus); 2068 2069 /* read and clear interrupt status */ 2070 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2071 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 2072 2073 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2074 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2075 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2076 2077 if (status & GINTSTS_USBRST) { 2078 2079 /* set correct state */ 2080 sc->sc_flags.status_device_mode = 1; 2081 sc->sc_flags.status_bus_reset = 0; 2082 sc->sc_flags.status_suspend = 0; 2083 sc->sc_flags.change_suspend = 0; 2084 sc->sc_flags.change_connect = 1; 2085 2086 /* complete root HUB interrupt endpoint */ 2087 dwc_otg_root_intr(sc); 2088 } 2089 2090 /* check for any bus state change interrupts */ 2091 if (status & GINTSTS_ENUMDONE) { 2092 2093 uint32_t temp; 2094 2095 DPRINTFN(5, "end of reset\n"); 2096 2097 /* set correct state */ 2098 sc->sc_flags.status_device_mode = 1; 2099 sc->sc_flags.status_bus_reset = 1; 2100 sc->sc_flags.status_suspend = 0; 2101 sc->sc_flags.change_suspend = 0; 2102 sc->sc_flags.change_connect = 1; 2103 sc->sc_flags.status_low_speed = 0; 2104 sc->sc_flags.port_enabled = 1; 2105 2106 /* reset FIFOs */ 2107 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2108 2109 /* reset function address */ 2110 dwc_otg_set_address(sc, 0); 2111 2112 /* figure out enumeration speed */ 2113 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2114 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2115 sc->sc_flags.status_high_speed = 1; 2116 else 2117 sc->sc_flags.status_high_speed = 0; 2118 2119 /* disable resume interrupt and enable suspend interrupt */ 2120 2121 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 2122 sc->sc_irq_mask |= GINTSTS_USBSUSP; 2123 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2124 2125 /* complete root HUB interrupt endpoint */ 2126 dwc_otg_root_intr(sc); 2127 } 2128 2129 if (status & GINTSTS_PRTINT) { 2130 uint32_t hprt; 2131 2132 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2133 2134 /* clear change bits */ 2135 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2136 HPRT_PRTPWR | HPRT_PRTENCHNG | 2137 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2138 sc->sc_hprt_val); 2139 2140 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2141 2142 sc->sc_flags.status_device_mode = 0; 2143 2144 if (hprt & HPRT_PRTCONNSTS) 2145 sc->sc_flags.status_bus_reset = 1; 2146 else 2147 sc->sc_flags.status_bus_reset = 0; 2148 2149 if (hprt & HPRT_PRTENCHNG) 2150 sc->sc_flags.change_enabled = 1; 2151 2152 if (hprt & HPRT_PRTENA) 2153 sc->sc_flags.port_enabled = 1; 2154 else 2155 sc->sc_flags.port_enabled = 0; 2156 2157 if (hprt & HPRT_PRTOVRCURRCHNG) 2158 sc->sc_flags.change_over_current = 1; 2159 2160 if (hprt & HPRT_PRTOVRCURRACT) 2161 sc->sc_flags.port_over_current = 1; 2162 else 2163 sc->sc_flags.port_over_current = 0; 2164 2165 if (hprt & HPRT_PRTPWR) 2166 sc->sc_flags.port_powered = 1; 2167 else 2168 sc->sc_flags.port_powered = 0; 2169 2170 if (((hprt & HPRT_PRTSPD_MASK) 2171 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2172 sc->sc_flags.status_low_speed = 1; 2173 else 2174 sc->sc_flags.status_low_speed = 0; 2175 2176 if (((hprt & HPRT_PRTSPD_MASK) 2177 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2178 sc->sc_flags.status_high_speed = 1; 2179 else 2180 sc->sc_flags.status_high_speed = 0; 2181 2182 if (hprt & HPRT_PRTCONNDET) 2183 sc->sc_flags.change_connect = 1; 2184 2185 if (hprt & HPRT_PRTSUSP) 2186 dwc_otg_suspend_irq(sc); 2187 else 2188 dwc_otg_resume_irq(sc); 2189 2190 /* complete root HUB interrupt endpoint */ 2191 dwc_otg_root_intr(sc); 2192 } 2193 2194 /* 2195 * If resume and suspend is set at the same time we interpret 2196 * that like RESUME. Resume is set when there is at least 3 2197 * milliseconds of inactivity on the USB BUS. 2198 */ 2199 if (status & GINTSTS_WKUPINT) { 2200 2201 DPRINTFN(5, "resume interrupt\n"); 2202 2203 dwc_otg_resume_irq(sc); 2204 2205 } else if (status & GINTSTS_USBSUSP) { 2206 2207 DPRINTFN(5, "suspend interrupt\n"); 2208 2209 dwc_otg_suspend_irq(sc); 2210 } 2211 /* check VBUS */ 2212 if (status & (GINTSTS_USBSUSP | 2213 GINTSTS_USBRST | 2214 GINTMSK_OTGINTMSK | 2215 GINTSTS_SESSREQINT)) { 2216 uint32_t temp; 2217 2218 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2219 2220 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2221 2222 dwc_otg_vbus_interrupt(sc, 2223 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2224 } 2225 2226 /* clear all IN endpoint interrupts */ 2227 if (status & GINTSTS_IEPINT) { 2228 uint32_t temp; 2229 uint8_t x; 2230 2231 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2232 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2233 if (temp & DIEPMSK_XFERCOMPLMSK) { 2234 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2235 DIEPMSK_XFERCOMPLMSK); 2236 } 2237 } 2238 } 2239 2240 /* check for SOF interrupt */ 2241 if (status & GINTSTS_SOF) { 2242 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2243 uint8_t x; 2244 uint8_t y; 2245 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 2246 if (sc->sc_chan_state[x].wait_sof != 0) { 2247 if (--(sc->sc_chan_state[x].wait_sof) != 0) 2248 y = 1; 2249 } 2250 } 2251 if (y == 0) { 2252 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2253 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2254 } 2255 } 2256 } 2257 2258 /* poll FIFO(s) */ 2259 dwc_otg_interrupt_poll(sc); 2260 2261 USB_BUS_UNLOCK(&sc->sc_bus); 2262 } 2263 2264 static void 2265 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2266 { 2267 struct dwc_otg_td *td; 2268 2269 /* get current Transfer Descriptor */ 2270 td = temp->td_next; 2271 temp->td = td; 2272 2273 /* prepare for next TD */ 2274 temp->td_next = td->obj_next; 2275 2276 /* fill out the Transfer Descriptor */ 2277 td->func = temp->func; 2278 td->pc = temp->pc; 2279 td->offset = temp->offset; 2280 td->remainder = temp->len; 2281 td->tx_bytes = 0; 2282 td->error_any = 0; 2283 td->npkt = 0; 2284 td->did_stall = temp->did_stall; 2285 td->short_pkt = temp->short_pkt; 2286 td->alt_next = temp->setup_alt_next; 2287 td->set_toggle = 0; 2288 td->got_short = 0; 2289 td->did_nak = 0; 2290 td->channel = DWC_OTG_MAX_CHANNELS; 2291 td->state = 0; 2292 td->errcnt = 0; 2293 } 2294 2295 static void 2296 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2297 { 2298 struct dwc_otg_std_temp temp; 2299 struct dwc_otg_td *td; 2300 uint32_t x; 2301 uint8_t need_sync; 2302 uint8_t is_host; 2303 2304 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2305 xfer->address, UE_GET_ADDR(xfer->endpointno), 2306 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2307 2308 temp.max_frame_size = xfer->max_frame_size; 2309 2310 td = xfer->td_start[0]; 2311 xfer->td_transfer_first = td; 2312 xfer->td_transfer_cache = td; 2313 2314 /* setup temp */ 2315 2316 temp.pc = NULL; 2317 temp.td = NULL; 2318 temp.td_next = xfer->td_start[0]; 2319 temp.offset = 0; 2320 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2321 temp.did_stall = !xfer->flags_int.control_stall; 2322 2323 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2324 2325 /* check if we should prepend a setup message */ 2326 2327 if (xfer->flags_int.control_xfr) { 2328 if (xfer->flags_int.control_hdr) { 2329 2330 if (is_host) 2331 temp.func = &dwc_otg_host_setup_tx; 2332 else 2333 temp.func = &dwc_otg_setup_rx; 2334 2335 temp.len = xfer->frlengths[0]; 2336 temp.pc = xfer->frbuffers + 0; 2337 temp.short_pkt = temp.len ? 1 : 0; 2338 2339 /* check for last frame */ 2340 if (xfer->nframes == 1) { 2341 /* no STATUS stage yet, SETUP is last */ 2342 if (xfer->flags_int.control_act) 2343 temp.setup_alt_next = 0; 2344 } 2345 2346 dwc_otg_setup_standard_chain_sub(&temp); 2347 } 2348 x = 1; 2349 } else { 2350 x = 0; 2351 } 2352 2353 if (x != xfer->nframes) { 2354 if (xfer->endpointno & UE_DIR_IN) { 2355 if (is_host) { 2356 temp.func = &dwc_otg_host_data_rx; 2357 need_sync = 0; 2358 } else { 2359 temp.func = &dwc_otg_data_tx; 2360 need_sync = 1; 2361 } 2362 } else { 2363 if (is_host) { 2364 temp.func = &dwc_otg_host_data_tx; 2365 need_sync = 0; 2366 } else { 2367 temp.func = &dwc_otg_data_rx; 2368 need_sync = 0; 2369 } 2370 } 2371 2372 /* setup "pc" pointer */ 2373 temp.pc = xfer->frbuffers + x; 2374 } else { 2375 need_sync = 0; 2376 } 2377 while (x != xfer->nframes) { 2378 2379 /* DATA0 / DATA1 message */ 2380 2381 temp.len = xfer->frlengths[x]; 2382 2383 x++; 2384 2385 if (x == xfer->nframes) { 2386 if (xfer->flags_int.control_xfr) { 2387 if (xfer->flags_int.control_act) { 2388 temp.setup_alt_next = 0; 2389 } 2390 } else { 2391 temp.setup_alt_next = 0; 2392 } 2393 } 2394 if (temp.len == 0) { 2395 2396 /* make sure that we send an USB packet */ 2397 2398 temp.short_pkt = 0; 2399 2400 } else { 2401 2402 /* regular data transfer */ 2403 2404 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2405 } 2406 2407 dwc_otg_setup_standard_chain_sub(&temp); 2408 2409 if (xfer->flags_int.isochronous_xfr) { 2410 temp.offset += temp.len; 2411 } else { 2412 /* get next Page Cache pointer */ 2413 temp.pc = xfer->frbuffers + x; 2414 } 2415 } 2416 2417 if (xfer->flags_int.control_xfr) { 2418 2419 /* always setup a valid "pc" pointer for status and sync */ 2420 temp.pc = xfer->frbuffers + 0; 2421 temp.len = 0; 2422 temp.short_pkt = 0; 2423 temp.setup_alt_next = 0; 2424 2425 /* check if we need to sync */ 2426 if (need_sync) { 2427 /* we need a SYNC point after TX */ 2428 temp.func = &dwc_otg_data_tx_sync; 2429 dwc_otg_setup_standard_chain_sub(&temp); 2430 } 2431 2432 /* check if we should append a status stage */ 2433 if (!xfer->flags_int.control_act) { 2434 2435 /* 2436 * Send a DATA1 message and invert the current 2437 * endpoint direction. 2438 */ 2439 if (xfer->endpointno & UE_DIR_IN) { 2440 if (is_host) { 2441 temp.func = &dwc_otg_host_data_tx; 2442 need_sync = 0; 2443 } else { 2444 temp.func = &dwc_otg_data_rx; 2445 need_sync = 0; 2446 } 2447 } else { 2448 if (is_host) { 2449 temp.func = &dwc_otg_host_data_rx; 2450 need_sync = 0; 2451 } else { 2452 temp.func = &dwc_otg_data_tx; 2453 need_sync = 1; 2454 } 2455 } 2456 2457 dwc_otg_setup_standard_chain_sub(&temp); 2458 2459 /* data toggle should be DATA1 */ 2460 td = temp.td; 2461 td->set_toggle = 1; 2462 2463 if (need_sync) { 2464 /* we need a SYNC point after TX */ 2465 temp.func = &dwc_otg_data_tx_sync; 2466 dwc_otg_setup_standard_chain_sub(&temp); 2467 } 2468 } 2469 } else { 2470 /* check if we need to sync */ 2471 if (need_sync) { 2472 2473 temp.pc = xfer->frbuffers + 0; 2474 temp.len = 0; 2475 temp.short_pkt = 0; 2476 temp.setup_alt_next = 0; 2477 2478 /* we need a SYNC point after TX */ 2479 temp.func = &dwc_otg_data_tx_sync; 2480 dwc_otg_setup_standard_chain_sub(&temp); 2481 } 2482 } 2483 2484 /* must have at least one frame! */ 2485 td = temp.td; 2486 xfer->td_transfer_last = td; 2487 2488 if (is_host) { 2489 2490 struct dwc_otg_softc *sc; 2491 uint32_t hcchar; 2492 uint32_t hcsplt; 2493 uint8_t xfer_type; 2494 2495 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2496 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2497 2498 /* get first again */ 2499 td = xfer->td_transfer_first; 2500 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 2501 2502 hcchar = 2503 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 2504 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 2505 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 2506 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 2507 HCCHAR_CHENA; 2508 2509 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 2510 hcchar |= HCCHAR_LSPDDEV; 2511 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2512 hcchar |= HCCHAR_EPDIR_IN; 2513 2514 switch (xfer->xroot->udev->speed) { 2515 case USB_SPEED_FULL: 2516 case USB_SPEED_LOW: 2517 /* check if root HUB port is running High Speed */ 2518 if (sc->sc_flags.status_high_speed != 0) { 2519 hcsplt = HCSPLT_SPLTENA | 2520 (xfer->xroot->udev->hs_port_no << 2521 HCSPLT_PRTADDR_SHIFT) | 2522 (xfer->xroot->udev->hs_hub_addr << 2523 HCSPLT_HUBADDR_SHIFT); 2524 if (xfer_type == UE_ISOCHRONOUS) /* XXX */ 2525 hcsplt |= (3 << HCSPLT_XACTPOS_SHIFT); 2526 } else { 2527 hcsplt = 0; 2528 } 2529 if (xfer_type == UE_INTERRUPT) { 2530 uint32_t ival; 2531 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2532 if (ival == 0) 2533 ival = 1; 2534 else if (ival > 255) 2535 ival = 255; 2536 td->tmr_val = sc->sc_tmr_val + ival; 2537 td->tmr_res = ival; 2538 } 2539 break; 2540 case USB_SPEED_HIGH: 2541 hcsplt = 0; 2542 if (xfer_type == UE_ISOCHRONOUS || 2543 xfer_type == UE_INTERRUPT) { 2544 hcchar |= ((xfer->max_packet_count & 3) 2545 << HCCHAR_MC_SHIFT); 2546 } 2547 if (xfer_type == UE_INTERRUPT) { 2548 uint32_t ival; 2549 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2550 if (ival == 0) 2551 ival = 1; 2552 else if (ival > 255) 2553 ival = 255; 2554 td->tmr_val = sc->sc_tmr_val + ival; 2555 td->tmr_res = ival; 2556 } 2557 break; 2558 default: 2559 hcsplt = 0; 2560 break; 2561 } 2562 2563 if (xfer_type == UE_ISOCHRONOUS) { 2564 td->tmr_val = xfer->endpoint->isoc_next & 0xFF; 2565 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 2566 } else if (xfer_type != UE_INTERRUPT) { 2567 td->tmr_val = 0; 2568 td->tmr_res = 0; 2569 } 2570 2571 /* store configuration in all TD's */ 2572 while (1) { 2573 td->hcchar = hcchar; 2574 td->hcsplt = hcsplt; 2575 2576 if (((void *)td) == xfer->td_transfer_last) 2577 break; 2578 2579 td = td->obj_next; 2580 } 2581 } 2582 } 2583 2584 static void 2585 dwc_otg_timeout(void *arg) 2586 { 2587 struct usb_xfer *xfer = arg; 2588 2589 DPRINTF("xfer=%p\n", xfer); 2590 2591 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2592 2593 /* transfer is transferred */ 2594 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 2595 } 2596 2597 static void 2598 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 2599 { 2600 DPRINTFN(9, "\n"); 2601 2602 /* poll one time - will turn on interrupts */ 2603 if (dwc_otg_xfer_do_fifo(xfer)) { 2604 2605 /* put transfer on interrupt queue */ 2606 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2607 2608 /* start timeout, if any */ 2609 if (xfer->timeout != 0) { 2610 usbd_transfer_timeout_ms(xfer, 2611 &dwc_otg_timeout, xfer->timeout); 2612 } 2613 } 2614 } 2615 2616 static void 2617 dwc_otg_root_intr(struct dwc_otg_softc *sc) 2618 { 2619 DPRINTFN(9, "\n"); 2620 2621 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2622 2623 /* set port bit */ 2624 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2625 2626 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2627 sizeof(sc->sc_hub_idata)); 2628 } 2629 2630 static usb_error_t 2631 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 2632 { 2633 struct dwc_otg_td *td; 2634 uint32_t len; 2635 usb_error_t error; 2636 2637 DPRINTFN(9, "\n"); 2638 2639 td = xfer->td_transfer_cache; 2640 2641 do { 2642 len = td->remainder; 2643 2644 /* store last data toggle */ 2645 xfer->endpoint->toggle_next = td->toggle; 2646 2647 if (xfer->aframes != xfer->nframes) { 2648 /* 2649 * Verify the length and subtract 2650 * the remainder from "frlengths[]": 2651 */ 2652 if (len > xfer->frlengths[xfer->aframes]) { 2653 td->error_any = 1; 2654 } else { 2655 xfer->frlengths[xfer->aframes] -= len; 2656 } 2657 } 2658 /* Check for transfer error */ 2659 if (td->error_any) { 2660 /* the transfer is finished */ 2661 error = (td->error_stall ? 2662 USB_ERR_STALLED : USB_ERR_IOERROR); 2663 td = NULL; 2664 break; 2665 } 2666 /* Check for short transfer */ 2667 if (len > 0) { 2668 if (xfer->flags_int.short_frames_ok) { 2669 /* follow alt next */ 2670 if (td->alt_next) { 2671 td = td->obj_next; 2672 } else { 2673 td = NULL; 2674 } 2675 } else { 2676 /* the transfer is finished */ 2677 td = NULL; 2678 } 2679 error = 0; 2680 break; 2681 } 2682 td = td->obj_next; 2683 2684 /* this USB frame is complete */ 2685 error = 0; 2686 break; 2687 2688 } while (0); 2689 2690 /* update transfer cache */ 2691 2692 xfer->td_transfer_cache = td; 2693 2694 return (error); 2695 } 2696 2697 static void 2698 dwc_otg_standard_done(struct usb_xfer *xfer) 2699 { 2700 usb_error_t err = 0; 2701 2702 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2703 xfer, xfer->endpoint); 2704 2705 /* reset scanner */ 2706 2707 xfer->td_transfer_cache = xfer->td_transfer_first; 2708 2709 if (xfer->flags_int.control_xfr) { 2710 2711 if (xfer->flags_int.control_hdr) { 2712 2713 err = dwc_otg_standard_done_sub(xfer); 2714 } 2715 xfer->aframes = 1; 2716 2717 if (xfer->td_transfer_cache == NULL) { 2718 goto done; 2719 } 2720 } 2721 while (xfer->aframes != xfer->nframes) { 2722 2723 err = dwc_otg_standard_done_sub(xfer); 2724 xfer->aframes++; 2725 2726 if (xfer->td_transfer_cache == NULL) { 2727 goto done; 2728 } 2729 } 2730 2731 if (xfer->flags_int.control_xfr && 2732 !xfer->flags_int.control_act) { 2733 2734 err = dwc_otg_standard_done_sub(xfer); 2735 } 2736 done: 2737 dwc_otg_device_done(xfer, err); 2738 } 2739 2740 /*------------------------------------------------------------------------* 2741 * dwc_otg_device_done 2742 * 2743 * NOTE: this function can be called more than one time on the 2744 * same USB transfer! 2745 *------------------------------------------------------------------------*/ 2746 static void 2747 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 2748 { 2749 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 2750 xfer, xfer->endpoint, error); 2751 2752 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 2753 DPRINTFN(15, "disabled interrupts!\n"); 2754 } else { 2755 struct dwc_otg_td *td; 2756 2757 td = xfer->td_transfer_first; 2758 2759 if (td != NULL) 2760 dwc_otg_host_channel_free(td); 2761 } 2762 /* dequeue transfer and start next transfer */ 2763 usbd_transfer_done(xfer, error); 2764 } 2765 2766 static void 2767 dwc_otg_xfer_stall(struct usb_xfer *xfer) 2768 { 2769 dwc_otg_device_done(xfer, USB_ERR_STALLED); 2770 } 2771 2772 static void 2773 dwc_otg_set_stall(struct usb_device *udev, 2774 struct usb_endpoint *ep, uint8_t *did_stall) 2775 { 2776 struct dwc_otg_softc *sc; 2777 uint32_t temp; 2778 uint32_t reg; 2779 uint8_t ep_no; 2780 2781 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2782 2783 /* check mode */ 2784 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2785 /* not supported */ 2786 return; 2787 } 2788 2789 sc = DWC_OTG_BUS2SC(udev->bus); 2790 2791 /* get endpoint address */ 2792 ep_no = ep->edesc->bEndpointAddress; 2793 2794 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 2795 2796 if (ep_no & UE_DIR_IN) { 2797 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 2798 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 2799 } else { 2800 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 2801 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 2802 } 2803 2804 /* disable and stall endpoint */ 2805 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2806 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 2807 2808 /* clear active OUT ep */ 2809 if (!(ep_no & UE_DIR_IN)) { 2810 2811 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 2812 2813 if (sc->sc_last_rx_status != 0 && 2814 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 2815 sc->sc_last_rx_status)) { 2816 /* dump data */ 2817 dwc_otg_common_rx_ack(sc); 2818 /* poll interrupt */ 2819 dwc_otg_interrupt_poll(sc); 2820 } 2821 } 2822 } 2823 2824 static void 2825 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 2826 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2827 { 2828 uint32_t reg; 2829 uint32_t temp; 2830 2831 if (ep_type == UE_CONTROL) { 2832 /* clearing stall is not needed */ 2833 return; 2834 } 2835 2836 if (ep_dir) { 2837 reg = DOTG_DIEPCTL(ep_no); 2838 } else { 2839 reg = DOTG_DOEPCTL(ep_no); 2840 sc->sc_active_rx_ep |= (1U << ep_no); 2841 } 2842 2843 /* round up and mask away the multiplier count */ 2844 mps = (mps + 3) & 0x7FC; 2845 2846 if (ep_type == UE_BULK) { 2847 temp = DIEPCTL_EPTYPE_SET( 2848 DIEPCTL_EPTYPE_BULK) | 2849 DIEPCTL_USBACTEP; 2850 } else if (ep_type == UE_INTERRUPT) { 2851 temp = DIEPCTL_EPTYPE_SET( 2852 DIEPCTL_EPTYPE_INTERRUPT) | 2853 DIEPCTL_USBACTEP; 2854 } else { 2855 temp = DIEPCTL_EPTYPE_SET( 2856 DIEPCTL_EPTYPE_ISOC) | 2857 DIEPCTL_USBACTEP; 2858 } 2859 2860 temp |= DIEPCTL_MPS_SET(mps); 2861 temp |= DIEPCTL_TXFNUM_SET(ep_no); 2862 2863 if (ep_dir) 2864 sc->sc_in_ctl[ep_no] = temp; 2865 else 2866 sc->sc_out_ctl[ep_no] = temp; 2867 2868 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2869 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 2870 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 2871 2872 /* we only reset the transmit FIFO */ 2873 if (ep_dir) { 2874 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2875 GRSTCTL_TXFIFO(ep_no) | 2876 GRSTCTL_TXFFLSH); 2877 2878 DWC_OTG_WRITE_4(sc, 2879 DOTG_DIEPTSIZ(ep_no), 0); 2880 } 2881 2882 /* poll interrupt */ 2883 dwc_otg_interrupt_poll(sc); 2884 } 2885 2886 static void 2887 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 2888 { 2889 struct dwc_otg_softc *sc; 2890 struct usb_endpoint_descriptor *ed; 2891 2892 DPRINTFN(5, "endpoint=%p\n", ep); 2893 2894 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2895 2896 /* check mode */ 2897 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2898 /* not supported */ 2899 return; 2900 } 2901 /* get softc */ 2902 sc = DWC_OTG_BUS2SC(udev->bus); 2903 2904 /* get endpoint descriptor */ 2905 ed = ep->edesc; 2906 2907 /* reset endpoint */ 2908 dwc_otg_clear_stall_sub(sc, 2909 UGETW(ed->wMaxPacketSize), 2910 (ed->bEndpointAddress & UE_ADDR), 2911 (ed->bmAttributes & UE_XFERTYPE), 2912 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 2913 } 2914 2915 static void 2916 dwc_otg_device_state_change(struct usb_device *udev) 2917 { 2918 struct dwc_otg_softc *sc; 2919 uint8_t x; 2920 2921 /* check mode */ 2922 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2923 /* not supported */ 2924 return; 2925 } 2926 2927 /* get softc */ 2928 sc = DWC_OTG_BUS2SC(udev->bus); 2929 2930 /* deactivate all other endpoint but the control endpoint */ 2931 if (udev->state == USB_STATE_CONFIGURED || 2932 udev->state == USB_STATE_ADDRESSED) { 2933 2934 USB_BUS_LOCK(&sc->sc_bus); 2935 2936 for (x = 1; x != sc->sc_dev_ep_max; x++) { 2937 2938 if (x < sc->sc_dev_in_ep_max) { 2939 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 2940 DIEPCTL_EPDIS); 2941 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 2942 } 2943 2944 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 2945 DOEPCTL_EPDIS); 2946 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 2947 } 2948 USB_BUS_UNLOCK(&sc->sc_bus); 2949 } 2950 } 2951 2952 int 2953 dwc_otg_init(struct dwc_otg_softc *sc) 2954 { 2955 uint32_t temp; 2956 2957 DPRINTF("start\n"); 2958 2959 /* set up the bus structure */ 2960 sc->sc_bus.usbrev = USB_REV_2_0; 2961 sc->sc_bus.methods = &dwc_otg_bus_methods; 2962 2963 usb_callout_init_mtx(&sc->sc_timer, 2964 &sc->sc_bus.bus_mtx, 0); 2965 2966 USB_BUS_LOCK(&sc->sc_bus); 2967 2968 /* turn on clocks */ 2969 dwc_otg_clocks_on(sc); 2970 2971 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 2972 DPRINTF("Version = 0x%08x\n", temp); 2973 2974 /* disconnect */ 2975 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 2976 DCTL_SFTDISCON); 2977 2978 /* wait for host to detect disconnect */ 2979 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 2980 2981 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2982 GRSTCTL_CSFTRST); 2983 2984 /* wait a little bit for block to reset */ 2985 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 2986 2987 switch (sc->sc_mode) { 2988 case DWC_MODE_DEVICE: 2989 temp = GUSBCFG_FORCEDEVMODE; 2990 break; 2991 case DWC_MODE_HOST: 2992 temp = GUSBCFG_FORCEHOSTMODE; 2993 break; 2994 default: 2995 temp = 0; 2996 break; 2997 } 2998 2999 /* select HSIC or non-HSIC mode */ 3000 if (dwc_otg_use_hsic) { 3001 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3002 GUSBCFG_PHYIF | 3003 GUSBCFG_TRD_TIM_SET(5) | temp); 3004 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3005 0x000000EC); 3006 3007 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3008 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3009 temp & ~GLPMCFG_HSIC_CONN); 3010 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3011 temp | GLPMCFG_HSIC_CONN); 3012 } else { 3013 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3014 GUSBCFG_ULPI_UTMI_SEL | 3015 GUSBCFG_TRD_TIM_SET(5) | temp); 3016 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3017 3018 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3019 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3020 temp & ~GLPMCFG_HSIC_CONN); 3021 } 3022 3023 /* clear global nak */ 3024 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3025 DCTL_CGOUTNAK | 3026 DCTL_CGNPINNAK); 3027 3028 /* disable USB port */ 3029 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3030 3031 /* wait 10ms */ 3032 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3033 3034 /* enable USB port */ 3035 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3036 3037 /* wait 10ms */ 3038 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3039 3040 /* pull up D+ */ 3041 dwc_otg_pull_up(sc); 3042 3043 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3044 3045 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3046 3047 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3048 3049 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3050 3051 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3052 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3053 3054 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3055 3056 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3057 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3058 3059 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3060 3061 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3062 3063 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3064 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3065 sc->sc_host_ch_max); 3066 3067 /* setup FIFO */ 3068 if (dwc_otg_init_fifo(sc, DWC_MODE_OTG)) 3069 return (EINVAL); 3070 3071 /* enable interrupts */ 3072 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3073 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3074 3075 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3076 3077 /* enable all endpoint interrupts */ 3078 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3079 if (temp & GHWCFG2_MPI) { 3080 uint8_t x; 3081 3082 DPRINTF("Multi Process Interrupts\n"); 3083 3084 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3085 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3086 DIEPMSK_XFERCOMPLMSK); 3087 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3088 } 3089 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3090 } else { 3091 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3092 DIEPMSK_XFERCOMPLMSK); 3093 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3094 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3095 } 3096 } 3097 3098 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3099 /* setup clocks */ 3100 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3101 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3102 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3103 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3104 } 3105 3106 /* only enable global IRQ */ 3107 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3108 GAHBCFG_GLBLINTRMSK); 3109 3110 /* turn off clocks */ 3111 dwc_otg_clocks_off(sc); 3112 3113 /* read initial VBUS state */ 3114 3115 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3116 3117 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3118 3119 dwc_otg_vbus_interrupt(sc, 3120 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3121 3122 USB_BUS_UNLOCK(&sc->sc_bus); 3123 3124 /* catch any lost interrupts */ 3125 3126 dwc_otg_do_poll(&sc->sc_bus); 3127 3128 return (0); /* success */ 3129 } 3130 3131 void 3132 dwc_otg_uninit(struct dwc_otg_softc *sc) 3133 { 3134 USB_BUS_LOCK(&sc->sc_bus); 3135 3136 /* stop host timer */ 3137 dwc_otg_timer_stop(sc); 3138 3139 /* set disconnect */ 3140 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3141 DCTL_SFTDISCON); 3142 3143 /* turn off global IRQ */ 3144 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3145 3146 sc->sc_flags.port_enabled = 0; 3147 sc->sc_flags.port_powered = 0; 3148 sc->sc_flags.status_vbus = 0; 3149 sc->sc_flags.status_bus_reset = 0; 3150 sc->sc_flags.status_suspend = 0; 3151 sc->sc_flags.change_suspend = 0; 3152 sc->sc_flags.change_connect = 1; 3153 3154 dwc_otg_pull_down(sc); 3155 dwc_otg_clocks_off(sc); 3156 3157 USB_BUS_UNLOCK(&sc->sc_bus); 3158 3159 usb_callout_drain(&sc->sc_timer); 3160 } 3161 3162 static void 3163 dwc_otg_suspend(struct dwc_otg_softc *sc) 3164 { 3165 return; 3166 } 3167 3168 static void 3169 dwc_otg_resume(struct dwc_otg_softc *sc) 3170 { 3171 return; 3172 } 3173 3174 static void 3175 dwc_otg_do_poll(struct usb_bus *bus) 3176 { 3177 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3178 3179 USB_BUS_LOCK(&sc->sc_bus); 3180 dwc_otg_interrupt_poll(sc); 3181 USB_BUS_UNLOCK(&sc->sc_bus); 3182 } 3183 3184 /*------------------------------------------------------------------------* 3185 * DWC OTG bulk support 3186 * DWC OTG control support 3187 * DWC OTG interrupt support 3188 *------------------------------------------------------------------------*/ 3189 static void 3190 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3191 { 3192 } 3193 3194 static void 3195 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3196 { 3197 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3198 } 3199 3200 static void 3201 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3202 { 3203 } 3204 3205 static void 3206 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3207 { 3208 /* setup TDs */ 3209 dwc_otg_setup_standard_chain(xfer); 3210 dwc_otg_start_standard_chain(xfer); 3211 } 3212 3213 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3214 { 3215 .open = dwc_otg_device_non_isoc_open, 3216 .close = dwc_otg_device_non_isoc_close, 3217 .enter = dwc_otg_device_non_isoc_enter, 3218 .start = dwc_otg_device_non_isoc_start, 3219 }; 3220 3221 /*------------------------------------------------------------------------* 3222 * DWC OTG full speed isochronous support 3223 *------------------------------------------------------------------------*/ 3224 static void 3225 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3226 { 3227 } 3228 3229 static void 3230 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3231 { 3232 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3233 } 3234 3235 static void 3236 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3237 { 3238 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3239 uint32_t temp; 3240 uint32_t nframes; 3241 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3242 3243 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3244 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3245 3246 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3247 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3248 3249 /* get the current frame index */ 3250 nframes = (temp & HFNUM_FRNUM_MASK); 3251 } else { 3252 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3253 3254 /* get the current frame index */ 3255 nframes = DSTS_SOFFN_GET(temp); 3256 } 3257 3258 if (sc->sc_flags.status_high_speed) 3259 nframes /= 8; 3260 3261 nframes &= DWC_OTG_FRAME_MASK; 3262 3263 /* 3264 * check if the frame index is within the window where the frames 3265 * will be inserted 3266 */ 3267 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3268 3269 if ((xfer->endpoint->is_synced == 0) || 3270 (temp < (((xfer->nframes << shift) + 7) / 8))) { 3271 /* 3272 * If there is data underflow or the pipe queue is 3273 * empty we schedule the transfer a few frames ahead 3274 * of the current frame position. Else two isochronous 3275 * transfers might overlap. 3276 */ 3277 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 3278 xfer->endpoint->is_synced = 1; 3279 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3280 } 3281 /* 3282 * compute how many milliseconds the insertion is ahead of the 3283 * current frame position: 3284 */ 3285 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 3286 3287 /* 3288 * pre-compute when the isochronous transfer will be finished: 3289 */ 3290 xfer->isoc_time_complete = 3291 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3292 (((xfer->nframes << shift) + 7) / 8); 3293 3294 /* setup TDs */ 3295 dwc_otg_setup_standard_chain(xfer); 3296 3297 /* compute frame number for next insertion */ 3298 xfer->endpoint->isoc_next += (xfer->nframes << shift); 3299 } 3300 3301 static void 3302 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3303 { 3304 /* start TD chain */ 3305 dwc_otg_start_standard_chain(xfer); 3306 } 3307 3308 struct usb_pipe_methods dwc_otg_device_isoc_methods = 3309 { 3310 .open = dwc_otg_device_isoc_open, 3311 .close = dwc_otg_device_isoc_close, 3312 .enter = dwc_otg_device_isoc_enter, 3313 .start = dwc_otg_device_isoc_start, 3314 }; 3315 3316 /*------------------------------------------------------------------------* 3317 * DWC OTG root control support 3318 *------------------------------------------------------------------------* 3319 * Simulate a hardware HUB by handling all the necessary requests. 3320 *------------------------------------------------------------------------*/ 3321 3322 static const struct usb_device_descriptor dwc_otg_devd = { 3323 .bLength = sizeof(struct usb_device_descriptor), 3324 .bDescriptorType = UDESC_DEVICE, 3325 .bcdUSB = {0x00, 0x02}, 3326 .bDeviceClass = UDCLASS_HUB, 3327 .bDeviceSubClass = UDSUBCLASS_HUB, 3328 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3329 .bMaxPacketSize = 64, 3330 .bcdDevice = {0x00, 0x01}, 3331 .iManufacturer = 1, 3332 .iProduct = 2, 3333 .bNumConfigurations = 1, 3334 }; 3335 3336 static const struct dwc_otg_config_desc dwc_otg_confd = { 3337 .confd = { 3338 .bLength = sizeof(struct usb_config_descriptor), 3339 .bDescriptorType = UDESC_CONFIG, 3340 .wTotalLength[0] = sizeof(dwc_otg_confd), 3341 .bNumInterface = 1, 3342 .bConfigurationValue = 1, 3343 .iConfiguration = 0, 3344 .bmAttributes = UC_SELF_POWERED, 3345 .bMaxPower = 0, 3346 }, 3347 .ifcd = { 3348 .bLength = sizeof(struct usb_interface_descriptor), 3349 .bDescriptorType = UDESC_INTERFACE, 3350 .bNumEndpoints = 1, 3351 .bInterfaceClass = UICLASS_HUB, 3352 .bInterfaceSubClass = UISUBCLASS_HUB, 3353 .bInterfaceProtocol = 0, 3354 }, 3355 .endpd = { 3356 .bLength = sizeof(struct usb_endpoint_descriptor), 3357 .bDescriptorType = UDESC_ENDPOINT, 3358 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 3359 .bmAttributes = UE_INTERRUPT, 3360 .wMaxPacketSize[0] = 8, 3361 .bInterval = 255, 3362 }, 3363 }; 3364 3365 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3366 3367 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 3368 .bDescLength = sizeof(dwc_otg_hubd), 3369 .bDescriptorType = UDESC_HUB, 3370 .bNbrPorts = 1, 3371 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3372 .bPwrOn2PwrGood = 50, 3373 .bHubContrCurrent = 0, 3374 .DeviceRemovable = {0}, /* port is removable */ 3375 }; 3376 3377 #define STRING_LANG \ 3378 0x09, 0x04, /* American English */ 3379 3380 #define STRING_VENDOR \ 3381 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 3382 3383 #define STRING_PRODUCT \ 3384 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 3385 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 3386 'U', 0, 'B', 0, 3387 3388 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 3389 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 3390 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 3391 3392 static usb_error_t 3393 dwc_otg_roothub_exec(struct usb_device *udev, 3394 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3395 { 3396 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3397 const void *ptr; 3398 uint16_t len; 3399 uint16_t value; 3400 uint16_t index; 3401 usb_error_t err; 3402 3403 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3404 3405 /* buffer reset */ 3406 ptr = (const void *)&sc->sc_hub_temp; 3407 len = 0; 3408 err = 0; 3409 3410 value = UGETW(req->wValue); 3411 index = UGETW(req->wIndex); 3412 3413 /* demultiplex the control request */ 3414 3415 switch (req->bmRequestType) { 3416 case UT_READ_DEVICE: 3417 switch (req->bRequest) { 3418 case UR_GET_DESCRIPTOR: 3419 goto tr_handle_get_descriptor; 3420 case UR_GET_CONFIG: 3421 goto tr_handle_get_config; 3422 case UR_GET_STATUS: 3423 goto tr_handle_get_status; 3424 default: 3425 goto tr_stalled; 3426 } 3427 break; 3428 3429 case UT_WRITE_DEVICE: 3430 switch (req->bRequest) { 3431 case UR_SET_ADDRESS: 3432 goto tr_handle_set_address; 3433 case UR_SET_CONFIG: 3434 goto tr_handle_set_config; 3435 case UR_CLEAR_FEATURE: 3436 goto tr_valid; /* nop */ 3437 case UR_SET_DESCRIPTOR: 3438 goto tr_valid; /* nop */ 3439 case UR_SET_FEATURE: 3440 default: 3441 goto tr_stalled; 3442 } 3443 break; 3444 3445 case UT_WRITE_ENDPOINT: 3446 switch (req->bRequest) { 3447 case UR_CLEAR_FEATURE: 3448 switch (UGETW(req->wValue)) { 3449 case UF_ENDPOINT_HALT: 3450 goto tr_handle_clear_halt; 3451 case UF_DEVICE_REMOTE_WAKEUP: 3452 goto tr_handle_clear_wakeup; 3453 default: 3454 goto tr_stalled; 3455 } 3456 break; 3457 case UR_SET_FEATURE: 3458 switch (UGETW(req->wValue)) { 3459 case UF_ENDPOINT_HALT: 3460 goto tr_handle_set_halt; 3461 case UF_DEVICE_REMOTE_WAKEUP: 3462 goto tr_handle_set_wakeup; 3463 default: 3464 goto tr_stalled; 3465 } 3466 break; 3467 case UR_SYNCH_FRAME: 3468 goto tr_valid; /* nop */ 3469 default: 3470 goto tr_stalled; 3471 } 3472 break; 3473 3474 case UT_READ_ENDPOINT: 3475 switch (req->bRequest) { 3476 case UR_GET_STATUS: 3477 goto tr_handle_get_ep_status; 3478 default: 3479 goto tr_stalled; 3480 } 3481 break; 3482 3483 case UT_WRITE_INTERFACE: 3484 switch (req->bRequest) { 3485 case UR_SET_INTERFACE: 3486 goto tr_handle_set_interface; 3487 case UR_CLEAR_FEATURE: 3488 goto tr_valid; /* nop */ 3489 case UR_SET_FEATURE: 3490 default: 3491 goto tr_stalled; 3492 } 3493 break; 3494 3495 case UT_READ_INTERFACE: 3496 switch (req->bRequest) { 3497 case UR_GET_INTERFACE: 3498 goto tr_handle_get_interface; 3499 case UR_GET_STATUS: 3500 goto tr_handle_get_iface_status; 3501 default: 3502 goto tr_stalled; 3503 } 3504 break; 3505 3506 case UT_WRITE_CLASS_INTERFACE: 3507 case UT_WRITE_VENDOR_INTERFACE: 3508 /* XXX forward */ 3509 break; 3510 3511 case UT_READ_CLASS_INTERFACE: 3512 case UT_READ_VENDOR_INTERFACE: 3513 /* XXX forward */ 3514 break; 3515 3516 case UT_WRITE_CLASS_DEVICE: 3517 switch (req->bRequest) { 3518 case UR_CLEAR_FEATURE: 3519 goto tr_valid; 3520 case UR_SET_DESCRIPTOR: 3521 case UR_SET_FEATURE: 3522 break; 3523 default: 3524 goto tr_stalled; 3525 } 3526 break; 3527 3528 case UT_WRITE_CLASS_OTHER: 3529 switch (req->bRequest) { 3530 case UR_CLEAR_FEATURE: 3531 goto tr_handle_clear_port_feature; 3532 case UR_SET_FEATURE: 3533 goto tr_handle_set_port_feature; 3534 case UR_CLEAR_TT_BUFFER: 3535 case UR_RESET_TT: 3536 case UR_STOP_TT: 3537 goto tr_valid; 3538 3539 default: 3540 goto tr_stalled; 3541 } 3542 break; 3543 3544 case UT_READ_CLASS_OTHER: 3545 switch (req->bRequest) { 3546 case UR_GET_TT_STATE: 3547 goto tr_handle_get_tt_state; 3548 case UR_GET_STATUS: 3549 goto tr_handle_get_port_status; 3550 default: 3551 goto tr_stalled; 3552 } 3553 break; 3554 3555 case UT_READ_CLASS_DEVICE: 3556 switch (req->bRequest) { 3557 case UR_GET_DESCRIPTOR: 3558 goto tr_handle_get_class_descriptor; 3559 case UR_GET_STATUS: 3560 goto tr_handle_get_class_status; 3561 3562 default: 3563 goto tr_stalled; 3564 } 3565 break; 3566 default: 3567 goto tr_stalled; 3568 } 3569 goto tr_valid; 3570 3571 tr_handle_get_descriptor: 3572 switch (value >> 8) { 3573 case UDESC_DEVICE: 3574 if (value & 0xff) { 3575 goto tr_stalled; 3576 } 3577 len = sizeof(dwc_otg_devd); 3578 ptr = (const void *)&dwc_otg_devd; 3579 goto tr_valid; 3580 case UDESC_CONFIG: 3581 if (value & 0xff) { 3582 goto tr_stalled; 3583 } 3584 len = sizeof(dwc_otg_confd); 3585 ptr = (const void *)&dwc_otg_confd; 3586 goto tr_valid; 3587 case UDESC_STRING: 3588 switch (value & 0xff) { 3589 case 0: /* Language table */ 3590 len = sizeof(dwc_otg_langtab); 3591 ptr = (const void *)&dwc_otg_langtab; 3592 goto tr_valid; 3593 3594 case 1: /* Vendor */ 3595 len = sizeof(dwc_otg_vendor); 3596 ptr = (const void *)&dwc_otg_vendor; 3597 goto tr_valid; 3598 3599 case 2: /* Product */ 3600 len = sizeof(dwc_otg_product); 3601 ptr = (const void *)&dwc_otg_product; 3602 goto tr_valid; 3603 default: 3604 break; 3605 } 3606 break; 3607 default: 3608 goto tr_stalled; 3609 } 3610 goto tr_stalled; 3611 3612 tr_handle_get_config: 3613 len = 1; 3614 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3615 goto tr_valid; 3616 3617 tr_handle_get_status: 3618 len = 2; 3619 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3620 goto tr_valid; 3621 3622 tr_handle_set_address: 3623 if (value & 0xFF00) { 3624 goto tr_stalled; 3625 } 3626 sc->sc_rt_addr = value; 3627 goto tr_valid; 3628 3629 tr_handle_set_config: 3630 if (value >= 2) { 3631 goto tr_stalled; 3632 } 3633 sc->sc_conf = value; 3634 goto tr_valid; 3635 3636 tr_handle_get_interface: 3637 len = 1; 3638 sc->sc_hub_temp.wValue[0] = 0; 3639 goto tr_valid; 3640 3641 tr_handle_get_tt_state: 3642 tr_handle_get_class_status: 3643 tr_handle_get_iface_status: 3644 tr_handle_get_ep_status: 3645 len = 2; 3646 USETW(sc->sc_hub_temp.wValue, 0); 3647 goto tr_valid; 3648 3649 tr_handle_set_halt: 3650 tr_handle_set_interface: 3651 tr_handle_set_wakeup: 3652 tr_handle_clear_wakeup: 3653 tr_handle_clear_halt: 3654 goto tr_valid; 3655 3656 tr_handle_clear_port_feature: 3657 if (index != 1) 3658 goto tr_stalled; 3659 3660 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3661 3662 switch (value) { 3663 case UHF_PORT_SUSPEND: 3664 dwc_otg_wakeup_peer(sc); 3665 break; 3666 3667 case UHF_PORT_ENABLE: 3668 if (sc->sc_flags.status_device_mode == 0) { 3669 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 3670 sc->sc_hprt_val | HPRT_PRTENA); 3671 } 3672 sc->sc_flags.port_enabled = 0; 3673 break; 3674 3675 case UHF_C_PORT_RESET: 3676 sc->sc_flags.change_reset = 0; 3677 break; 3678 3679 case UHF_C_PORT_ENABLE: 3680 sc->sc_flags.change_enabled = 0; 3681 break; 3682 3683 case UHF_C_PORT_OVER_CURRENT: 3684 sc->sc_flags.change_over_current = 0; 3685 break; 3686 3687 case UHF_PORT_TEST: 3688 case UHF_PORT_INDICATOR: 3689 /* nops */ 3690 break; 3691 3692 case UHF_PORT_POWER: 3693 sc->sc_flags.port_powered = 0; 3694 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3695 sc->sc_hprt_val = 0; 3696 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 3697 } 3698 dwc_otg_pull_down(sc); 3699 dwc_otg_clocks_off(sc); 3700 break; 3701 3702 case UHF_C_PORT_CONNECTION: 3703 /* clear connect change flag */ 3704 sc->sc_flags.change_connect = 0; 3705 break; 3706 3707 case UHF_C_PORT_SUSPEND: 3708 sc->sc_flags.change_suspend = 0; 3709 break; 3710 3711 default: 3712 err = USB_ERR_IOERROR; 3713 goto done; 3714 } 3715 goto tr_valid; 3716 3717 tr_handle_set_port_feature: 3718 if (index != 1) { 3719 goto tr_stalled; 3720 } 3721 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 3722 3723 switch (value) { 3724 case UHF_PORT_ENABLE: 3725 break; 3726 3727 case UHF_PORT_SUSPEND: 3728 if (sc->sc_flags.status_device_mode == 0) { 3729 /* set suspend BIT */ 3730 sc->sc_hprt_val |= HPRT_PRTSUSP; 3731 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3732 3733 /* generate HUB suspend event */ 3734 dwc_otg_suspend_irq(sc); 3735 } 3736 break; 3737 3738 case UHF_PORT_RESET: 3739 if (sc->sc_flags.status_device_mode == 0) { 3740 3741 DPRINTF("PORT RESET\n"); 3742 3743 /* enable PORT reset */ 3744 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 3745 3746 /* Wait 62.5ms for reset to complete */ 3747 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3748 3749 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3750 3751 /* Wait 62.5ms for reset to complete */ 3752 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3753 3754 /* reset FIFOs */ 3755 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 3756 3757 sc->sc_flags.change_reset = 1; 3758 } else { 3759 err = USB_ERR_IOERROR; 3760 } 3761 break; 3762 3763 case UHF_PORT_TEST: 3764 case UHF_PORT_INDICATOR: 3765 /* nops */ 3766 break; 3767 case UHF_PORT_POWER: 3768 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3769 sc->sc_hprt_val |= HPRT_PRTPWR; 3770 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3771 } 3772 sc->sc_flags.port_powered = 1; 3773 break; 3774 default: 3775 err = USB_ERR_IOERROR; 3776 goto done; 3777 } 3778 goto tr_valid; 3779 3780 tr_handle_get_port_status: 3781 3782 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 3783 3784 if (index != 1) 3785 goto tr_stalled; 3786 3787 if (sc->sc_flags.status_vbus) 3788 dwc_otg_clocks_on(sc); 3789 else 3790 dwc_otg_clocks_off(sc); 3791 3792 /* Select Device Side Mode */ 3793 3794 if (sc->sc_flags.status_device_mode) { 3795 value = UPS_PORT_MODE_DEVICE; 3796 dwc_otg_timer_stop(sc); 3797 } else { 3798 value = 0; 3799 dwc_otg_timer_start(sc); 3800 } 3801 3802 if (sc->sc_flags.status_high_speed) 3803 value |= UPS_HIGH_SPEED; 3804 else if (sc->sc_flags.status_low_speed) 3805 value |= UPS_LOW_SPEED; 3806 3807 if (sc->sc_flags.port_powered) 3808 value |= UPS_PORT_POWER; 3809 3810 if (sc->sc_flags.port_enabled) 3811 value |= UPS_PORT_ENABLED; 3812 3813 if (sc->sc_flags.port_over_current) 3814 value |= UPS_OVERCURRENT_INDICATOR; 3815 3816 if (sc->sc_flags.status_vbus && 3817 sc->sc_flags.status_bus_reset) 3818 value |= UPS_CURRENT_CONNECT_STATUS; 3819 3820 if (sc->sc_flags.status_suspend) 3821 value |= UPS_SUSPEND; 3822 3823 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3824 3825 value = 0; 3826 3827 if (sc->sc_flags.change_connect) 3828 value |= UPS_C_CONNECT_STATUS; 3829 if (sc->sc_flags.change_suspend) 3830 value |= UPS_C_SUSPEND; 3831 if (sc->sc_flags.change_reset) 3832 value |= UPS_C_PORT_RESET; 3833 if (sc->sc_flags.change_over_current) 3834 value |= UPS_C_OVERCURRENT_INDICATOR; 3835 3836 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3837 len = sizeof(sc->sc_hub_temp.ps); 3838 goto tr_valid; 3839 3840 tr_handle_get_class_descriptor: 3841 if (value & 0xFF) { 3842 goto tr_stalled; 3843 } 3844 ptr = (const void *)&dwc_otg_hubd; 3845 len = sizeof(dwc_otg_hubd); 3846 goto tr_valid; 3847 3848 tr_stalled: 3849 err = USB_ERR_STALLED; 3850 tr_valid: 3851 done: 3852 *plength = len; 3853 *pptr = ptr; 3854 return (err); 3855 } 3856 3857 static void 3858 dwc_otg_xfer_setup(struct usb_setup_params *parm) 3859 { 3860 const struct usb_hw_ep_profile *pf; 3861 struct usb_xfer *xfer; 3862 void *last_obj; 3863 uint32_t ntd; 3864 uint32_t n; 3865 uint8_t ep_no; 3866 3867 xfer = parm->curr_xfer; 3868 3869 /* 3870 * NOTE: This driver does not use any of the parameters that 3871 * are computed from the following values. Just set some 3872 * reasonable dummies: 3873 */ 3874 parm->hc_max_packet_size = 0x500; 3875 parm->hc_max_packet_count = 1; 3876 parm->hc_max_frame_size = 0x500; 3877 3878 usbd_transfer_setup_sub(parm); 3879 3880 /* 3881 * compute maximum number of TDs 3882 */ 3883 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 3884 3885 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 3886 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 3887 } else { 3888 3889 ntd = xfer->nframes + 1 /* SYNC */ ; 3890 } 3891 3892 /* 3893 * check if "usbd_transfer_setup_sub" set an error 3894 */ 3895 if (parm->err) 3896 return; 3897 3898 /* 3899 * allocate transfer descriptors 3900 */ 3901 last_obj = NULL; 3902 3903 /* 3904 * get profile stuff 3905 */ 3906 ep_no = xfer->endpointno & UE_ADDR; 3907 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 3908 3909 if (pf == NULL) { 3910 /* should not happen */ 3911 parm->err = USB_ERR_INVAL; 3912 return; 3913 } 3914 3915 /* align data */ 3916 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 3917 3918 for (n = 0; n != ntd; n++) { 3919 3920 struct dwc_otg_td *td; 3921 3922 if (parm->buf) { 3923 3924 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 3925 3926 /* init TD */ 3927 td->max_packet_size = xfer->max_packet_size; 3928 td->ep_no = ep_no; 3929 td->obj_next = last_obj; 3930 3931 last_obj = td; 3932 } 3933 parm->size[0] += sizeof(*td); 3934 } 3935 3936 xfer->td_start[0] = last_obj; 3937 } 3938 3939 static void 3940 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 3941 { 3942 return; 3943 } 3944 3945 static void 3946 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3947 struct usb_endpoint *ep) 3948 { 3949 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3950 3951 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 3952 ep, udev->address, 3953 edesc->bEndpointAddress, udev->flags.usb_mode, 3954 sc->sc_rt_addr, udev->device_index); 3955 3956 if (udev->device_index != sc->sc_rt_addr) { 3957 3958 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 3959 if (udev->speed != USB_SPEED_FULL && 3960 udev->speed != USB_SPEED_HIGH) { 3961 /* not supported */ 3962 return; 3963 } 3964 } else { 3965 uint16_t mps; 3966 3967 mps = UGETW(edesc->wMaxPacketSize); 3968 3969 /* Apply limitations of our USB host driver */ 3970 3971 switch (udev->speed) { 3972 case USB_SPEED_HIGH: 3973 if (mps > 512) { 3974 DPRINTF("wMaxPacketSize=0x%04x" 3975 "is not supported\n", (int)mps); 3976 /* not supported */ 3977 return; 3978 } 3979 break; 3980 3981 case USB_SPEED_FULL: 3982 case USB_SPEED_LOW: 3983 if (mps > 188) { 3984 DPRINTF("wMaxPacketSize=0x%04x" 3985 "is not supported\n", (int)mps); 3986 /* not supported */ 3987 return; 3988 } 3989 break; 3990 3991 default: 3992 DPRINTF("Invalid device speed\n"); 3993 /* not supported */ 3994 return; 3995 } 3996 } 3997 3998 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 3999 ep->methods = &dwc_otg_device_isoc_methods; 4000 else 4001 ep->methods = &dwc_otg_device_non_isoc_methods; 4002 } 4003 } 4004 4005 static void 4006 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4007 { 4008 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4009 4010 switch (state) { 4011 case USB_HW_POWER_SUSPEND: 4012 dwc_otg_suspend(sc); 4013 break; 4014 case USB_HW_POWER_SHUTDOWN: 4015 dwc_otg_uninit(sc); 4016 break; 4017 case USB_HW_POWER_RESUME: 4018 dwc_otg_resume(sc); 4019 break; 4020 default: 4021 break; 4022 } 4023 } 4024 4025 static void 4026 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4027 { 4028 /* DMA delay - wait until any use of memory is finished */ 4029 *pus = (2125); /* microseconds */ 4030 } 4031 4032 static void 4033 dwc_otg_device_resume(struct usb_device *udev) 4034 { 4035 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4036 struct usb_xfer *xfer; 4037 struct dwc_otg_td *td; 4038 4039 DPRINTF("\n"); 4040 4041 /* Enable relevant Host channels before resuming */ 4042 4043 USB_BUS_LOCK(udev->bus); 4044 4045 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4046 4047 if (xfer->xroot->udev == udev) { 4048 4049 td = xfer->td_transfer_cache; 4050 if (td != NULL && 4051 td->channel < DWC_OTG_MAX_CHANNELS) 4052 sc->sc_chan_state[td->channel].suspended = 0; 4053 } 4054 } 4055 4056 USB_BUS_UNLOCK(udev->bus); 4057 4058 /* poll all transfers again to restart resumed ones */ 4059 dwc_otg_do_poll(udev->bus); 4060 } 4061 4062 static void 4063 dwc_otg_device_suspend(struct usb_device *udev) 4064 { 4065 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4066 struct usb_xfer *xfer; 4067 struct dwc_otg_td *td; 4068 4069 DPRINTF("\n"); 4070 4071 /* Disable relevant Host channels before going to suspend */ 4072 4073 USB_BUS_LOCK(udev->bus); 4074 4075 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4076 4077 if (xfer->xroot->udev == udev) { 4078 4079 td = xfer->td_transfer_cache; 4080 if (td != NULL && 4081 td->channel < DWC_OTG_MAX_CHANNELS) 4082 sc->sc_chan_state[td->channel].suspended = 1; 4083 } 4084 } 4085 4086 USB_BUS_UNLOCK(udev->bus); 4087 } 4088 4089 struct usb_bus_methods dwc_otg_bus_methods = 4090 { 4091 .endpoint_init = &dwc_otg_ep_init, 4092 .xfer_setup = &dwc_otg_xfer_setup, 4093 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4094 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4095 .xfer_stall = &dwc_otg_xfer_stall, 4096 .set_stall = &dwc_otg_set_stall, 4097 .clear_stall = &dwc_otg_clear_stall, 4098 .roothub_exec = &dwc_otg_roothub_exec, 4099 .xfer_poll = &dwc_otg_do_poll, 4100 .device_state_change = &dwc_otg_device_state_change, 4101 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4102 .get_dma_delay = &dwc_otg_get_dma_delay, 4103 .device_resume = &dwc_otg_device_resume, 4104 .device_suspend = &dwc_otg_device_suspend, 4105 }; 4106