1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2SC(pc) \ 93 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_OTGINTMSK | \ 102 GINTMSK_PRTINTMSK) 103 104 static int dwc_otg_use_hsic; 105 106 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 107 108 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 109 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 110 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 111 112 #ifdef USB_DEBUG 113 static int dwc_otg_debug; 114 115 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 116 &dwc_otg_debug, 0, "DWC OTG debug level"); 117 #endif 118 119 #define DWC_OTG_INTR_ENDPT 1 120 121 /* prototypes */ 122 123 static const struct usb_bus_methods dwc_otg_bus_methods; 124 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 125 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 126 127 static dwc_otg_cmd_t dwc_otg_setup_rx; 128 static dwc_otg_cmd_t dwc_otg_data_rx; 129 static dwc_otg_cmd_t dwc_otg_data_tx; 130 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 131 132 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 133 static dwc_otg_cmd_t dwc_otg_host_data_tx; 134 static dwc_otg_cmd_t dwc_otg_host_data_rx; 135 136 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 137 static void dwc_otg_do_poll(struct usb_bus *); 138 static void dwc_otg_standard_done(struct usb_xfer *); 139 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 140 static void dwc_otg_interrupt_poll(struct dwc_otg_softc *sc); 141 142 /* 143 * Here is a configuration that the chip supports. 144 */ 145 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 146 147 [0] = { 148 .max_in_frame_size = 64,/* fixed */ 149 .max_out_frame_size = 64, /* fixed */ 150 .is_simplex = 1, 151 .support_control = 1, 152 } 153 }; 154 155 static void 156 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 157 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 158 { 159 struct dwc_otg_softc *sc; 160 161 sc = DWC_OTG_BUS2SC(udev->bus); 162 163 if (ep_addr < sc->sc_dev_ep_max) 164 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 165 else 166 *ppf = NULL; 167 } 168 169 static int 170 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 171 { 172 struct dwc_otg_profile *pf; 173 uint32_t fifo_size; 174 uint32_t fifo_regs; 175 uint32_t tx_start; 176 uint8_t x; 177 178 fifo_size = sc->sc_fifo_size; 179 180 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 181 182 if (fifo_size >= fifo_regs) 183 fifo_size -= fifo_regs; 184 else 185 fifo_size = 0; 186 187 /* split equally for IN and OUT */ 188 fifo_size /= 2; 189 190 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 191 192 /* align to 4-bytes */ 193 fifo_size &= ~3; 194 195 tx_start = fifo_size; 196 197 if (fifo_size < 0x40) { 198 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 199 USB_BUS_UNLOCK(&sc->sc_bus); 200 return (EINVAL); 201 } 202 203 if (mode == DWC_MODE_HOST) { 204 205 /* reset active endpoints */ 206 sc->sc_active_rx_ep = 0; 207 208 /* reset TX size */ 209 sc->sc_tx_cur_size = 0; 210 211 /* reset TT info */ 212 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 213 214 fifo_size /= 2; 215 216 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 217 ((fifo_size / 4) << 16) | 218 (tx_start / 4)); 219 220 tx_start += fifo_size; 221 222 for (x = 0; x != sc->sc_host_ch_max; x++) { 223 /* disable all host interrupts */ 224 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 0); 225 } 226 227 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 228 ((fifo_size / 4) << 16) | 229 (tx_start / 4)); 230 231 /* store maximum TX FIFO size */ 232 sc->sc_tx_max_size = fifo_size; 233 234 /* disable all host channel interrupts */ 235 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 0); 236 } 237 238 if (mode == DWC_MODE_DEVICE) { 239 240 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 241 (0x10 << 16) | (tx_start / 4)); 242 fifo_size -= 0x40; 243 tx_start += 0x40; 244 245 /* setup control endpoint profile */ 246 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 247 248 /* reset active endpoints */ 249 sc->sc_active_rx_ep = 1; 250 251 for (x = 1; x != sc->sc_dev_ep_max; x++) { 252 253 pf = sc->sc_hw_ep_profile + x; 254 255 pf->usb.max_out_frame_size = 1024 * 3; 256 pf->usb.is_simplex = 0; /* assume duplex */ 257 pf->usb.support_bulk = 1; 258 pf->usb.support_interrupt = 1; 259 pf->usb.support_isochronous = 1; 260 pf->usb.support_out = 1; 261 262 if (x < sc->sc_dev_in_ep_max) { 263 uint32_t limit; 264 265 limit = (x == 1) ? DWC_OTG_MAX_TXN : 266 (DWC_OTG_MAX_TXN / 2); 267 268 if (fifo_size >= limit) { 269 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 270 ((limit / 4) << 16) | 271 (tx_start / 4)); 272 tx_start += limit; 273 fifo_size -= limit; 274 pf->usb.max_in_frame_size = 0x200; 275 pf->usb.support_in = 1; 276 pf->max_buffer = limit; 277 278 } else if (fifo_size >= 0x80) { 279 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 280 ((0x80 / 4) << 16) | (tx_start / 4)); 281 tx_start += 0x80; 282 fifo_size -= 0x80; 283 pf->usb.max_in_frame_size = 0x40; 284 pf->usb.support_in = 1; 285 286 } else { 287 pf->usb.is_simplex = 1; 288 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 289 (0x0 << 16) | (tx_start / 4)); 290 } 291 } else { 292 pf->usb.is_simplex = 1; 293 } 294 295 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 296 pf->usb.max_in_frame_size, 297 pf->usb.max_out_frame_size); 298 } 299 } 300 301 /* reset RX FIFO */ 302 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 303 GRSTCTL_RXFFLSH); 304 305 if (mode != DWC_MODE_OTG) { 306 /* reset all TX FIFOs */ 307 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 308 GRSTCTL_TXFIFO(0x10) | 309 GRSTCTL_TXFFLSH); 310 } else { 311 /* reset active endpoints */ 312 sc->sc_active_rx_ep = 0; 313 314 /* reset TX size */ 315 sc->sc_tx_cur_size = 0; 316 317 /* reset TT info */ 318 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 319 } 320 return (0); 321 } 322 323 static void 324 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 325 { 326 uint32_t temp; 327 328 /* setup HOST frame interval register, based on existing value */ 329 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 330 if (temp >= 10000) 331 temp /= 1000; 332 else 333 temp /= 125; 334 335 /* figure out nearest X-tal value */ 336 if (temp >= 54) 337 temp = 60; /* MHz */ 338 else if (temp >= 39) 339 temp = 48; /* MHz */ 340 else 341 temp = 30; /* MHz */ 342 343 if (sc->sc_flags.status_high_speed) 344 temp *= 125; 345 else 346 temp *= 1000; 347 348 DPRINTF("HFIR=0x%08x\n", temp); 349 350 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 351 } 352 353 static void 354 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 355 { 356 if (sc->sc_flags.clocks_off && 357 sc->sc_flags.port_powered) { 358 359 DPRINTFN(5, "\n"); 360 361 /* TODO - platform specific */ 362 363 sc->sc_flags.clocks_off = 0; 364 } 365 } 366 367 static void 368 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 369 { 370 if (!sc->sc_flags.clocks_off) { 371 372 DPRINTFN(5, "\n"); 373 374 /* TODO - platform specific */ 375 376 sc->sc_flags.clocks_off = 1; 377 } 378 } 379 380 static void 381 dwc_otg_pull_up(struct dwc_otg_softc *sc) 382 { 383 uint32_t temp; 384 385 /* pullup D+, if possible */ 386 387 if (!sc->sc_flags.d_pulled_up && 388 sc->sc_flags.port_powered) { 389 sc->sc_flags.d_pulled_up = 1; 390 391 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 392 temp &= ~DCTL_SFTDISCON; 393 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 394 } 395 } 396 397 static void 398 dwc_otg_pull_down(struct dwc_otg_softc *sc) 399 { 400 uint32_t temp; 401 402 /* pulldown D+, if possible */ 403 404 if (sc->sc_flags.d_pulled_up) { 405 sc->sc_flags.d_pulled_up = 0; 406 407 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 408 temp |= DCTL_SFTDISCON; 409 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 410 } 411 } 412 413 static void 414 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 415 { 416 /* In device mode we don't use the SOF interrupt */ 417 if (sc->sc_flags.status_device_mode != 0 || 418 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 419 return; 420 sc->sc_irq_mask |= GINTMSK_SOFMSK; 421 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 422 } 423 424 static void 425 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 426 { 427 if (sc->sc_flags.status_suspend) { 428 /* update status bits */ 429 sc->sc_flags.status_suspend = 0; 430 sc->sc_flags.change_suspend = 1; 431 432 if (sc->sc_flags.status_device_mode) { 433 /* 434 * Disable resume interrupt and enable suspend 435 * interrupt: 436 */ 437 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 438 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 439 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 440 } 441 442 /* complete root HUB interrupt endpoint */ 443 dwc_otg_root_intr(sc); 444 } 445 } 446 447 static void 448 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 449 { 450 if (!sc->sc_flags.status_suspend) { 451 /* update status bits */ 452 sc->sc_flags.status_suspend = 1; 453 sc->sc_flags.change_suspend = 1; 454 455 if (sc->sc_flags.status_device_mode) { 456 /* 457 * Disable suspend interrupt and enable resume 458 * interrupt: 459 */ 460 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 461 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 462 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 463 } 464 465 /* complete root HUB interrupt endpoint */ 466 dwc_otg_root_intr(sc); 467 } 468 } 469 470 static void 471 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 472 { 473 if (!sc->sc_flags.status_suspend) 474 return; 475 476 DPRINTFN(5, "Remote wakeup\n"); 477 478 if (sc->sc_flags.status_device_mode) { 479 uint32_t temp; 480 481 /* enable remote wakeup signalling */ 482 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 483 temp |= DCTL_RMTWKUPSIG; 484 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 485 486 /* Wait 8ms for remote wakeup to complete. */ 487 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 488 489 temp &= ~DCTL_RMTWKUPSIG; 490 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 491 } else { 492 /* enable USB port */ 493 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 494 495 /* wait 10ms */ 496 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 497 498 /* resume port */ 499 sc->sc_hprt_val |= HPRT_PRTRES; 500 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 501 502 /* Wait 100ms for resume signalling to complete. */ 503 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 504 505 /* clear suspend and resume */ 506 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 507 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 508 509 /* Wait 4ms */ 510 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 511 } 512 513 /* need to fake resume IRQ */ 514 dwc_otg_resume_irq(sc); 515 } 516 517 static void 518 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 519 { 520 uint32_t temp; 521 522 DPRINTFN(5, "addr=%d\n", addr); 523 524 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 525 temp &= ~DCFG_DEVADDR_SET(0x7F); 526 temp |= DCFG_DEVADDR_SET(addr); 527 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 528 } 529 530 static void 531 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 532 { 533 DPRINTFN(5, "RX status clear\n"); 534 535 if (sc->sc_flags.status_device_mode != 0) { 536 /* enable RX FIFO level interrupt */ 537 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 538 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 539 } 540 541 /* clear cached status */ 542 sc->sc_last_rx_status = 0; 543 } 544 545 static void 546 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 547 { 548 uint32_t hcint; 549 550 /* clear all pending interrupts */ 551 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 552 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 553 554 /* clear buffered interrupts */ 555 sc->sc_chan_state[x].hcint = 0; 556 } 557 558 /* 559 * This function waits until a DWC OTG host channel is ready to be 560 * used again: 561 */ 562 static uint8_t 563 dwc_otg_host_channel_wait(struct dwc_otg_td *td) 564 { 565 struct dwc_otg_softc *sc; 566 uint8_t x; 567 568 x = td->channel; 569 570 DPRINTF("CH=%d\n", x); 571 572 /* get pointer to softc */ 573 sc = DWC_OTG_PC2SC(td->pc); 574 575 if (sc->sc_chan_state[x].wait_sof == 0) { 576 dwc_otg_clear_hcint(sc, x); 577 return (1); /* done */ 578 } 579 580 if (x == 0) 581 return (0); /* wait */ 582 583 /* find new disabled channel */ 584 for (x = 1; x != sc->sc_host_ch_max; x++) { 585 586 if (sc->sc_chan_state[x].allocated) 587 continue; 588 if (sc->sc_chan_state[x].wait_sof != 0) 589 continue; 590 591 sc->sc_chan_state[td->channel].allocated = 0; 592 sc->sc_chan_state[x].allocated = 1; 593 594 sc->sc_chan_state[x].tx_size = 595 sc->sc_chan_state[td->channel].tx_size; 596 597 if (sc->sc_chan_state[td->channel].suspended) { 598 sc->sc_chan_state[td->channel].suspended = 0; 599 sc->sc_chan_state[x].suspended = 1; 600 } 601 602 /* clear interrupts */ 603 dwc_otg_clear_hcint(sc, x); 604 605 DPRINTF("CH=%d HCCHAR=0x%08x " 606 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 607 608 /* ack any pending messages */ 609 if (sc->sc_last_rx_status != 0 && 610 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == td->channel) { 611 /* get rid of message */ 612 dwc_otg_common_rx_ack(sc); 613 } 614 615 /* move active channel */ 616 sc->sc_active_rx_ep &= ~(1 << td->channel); 617 sc->sc_active_rx_ep |= (1 << x); 618 619 /* set channel */ 620 td->channel = x; 621 622 return (1); /* new channel allocated */ 623 } 624 return (0); /* wait */ 625 } 626 627 static uint8_t 628 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 629 { 630 struct dwc_otg_softc *sc; 631 uint32_t tx_size; 632 uint8_t x; 633 uint8_t max_channel; 634 635 if (td->channel < DWC_OTG_MAX_CHANNELS) 636 return (0); /* already allocated */ 637 638 /* get pointer to softc */ 639 sc = DWC_OTG_PC2SC(td->pc); 640 641 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 642 max_channel = 1; 643 x = 0; 644 tx_size = td->max_packet_size; 645 if ((sc->sc_tx_cur_size + tx_size) > sc->sc_tx_max_size) { 646 DPRINTF("Too little FIFO space\n"); 647 return (1); /* too little FIFO */ 648 } 649 } else { 650 max_channel = sc->sc_host_ch_max; 651 x = 1; 652 if ((td->hcchar & HCCHAR_EPDIR) == HCCHAR_EPDIR_OUT) { 653 tx_size = td->max_packet_size; 654 if (td->hcsplt != 0 && tx_size > HCSPLT_XACTLEN_MAX) 655 tx_size = HCSPLT_XACTLEN_MAX; 656 if ((sc->sc_tx_cur_size + tx_size) > sc->sc_tx_max_size) { 657 DPRINTF("Too little FIFO space\n"); 658 return (1); /* too little FIFO */ 659 } 660 } else { 661 tx_size = 0; 662 } 663 } 664 665 for (; x != max_channel; x++) { 666 667 if (sc->sc_chan_state[x].allocated) 668 continue; 669 if (sc->sc_chan_state[x].wait_sof != 0) 670 continue; 671 672 sc->sc_chan_state[x].allocated = 1; 673 sc->sc_chan_state[x].tx_size = tx_size; 674 675 /* keep track of used FIFO */ 676 sc->sc_tx_cur_size += tx_size; 677 678 /* clear interrupts */ 679 dwc_otg_clear_hcint(sc, x); 680 681 DPRINTF("CH=%d HCCHAR=0x%08x " 682 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 683 684 /* set active channel */ 685 sc->sc_active_rx_ep |= (1 << x); 686 687 /* set channel */ 688 td->channel = x; 689 690 return (0); /* allocated */ 691 } 692 return (1); /* busy */ 693 } 694 695 static void 696 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 697 { 698 uint32_t hcchar; 699 if (sc->sc_chan_state[x].wait_sof != 0) 700 return; 701 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 702 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 703 /* disable channel */ 704 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 705 HCCHAR_CHENA | HCCHAR_CHDIS); 706 /* don't re-use channel until next SOF is transmitted */ 707 sc->sc_chan_state[x].wait_sof = 2; 708 } 709 } 710 711 static void 712 dwc_otg_host_channel_free(struct dwc_otg_td *td) 713 { 714 struct dwc_otg_softc *sc; 715 uint8_t x; 716 717 if (td->channel >= DWC_OTG_MAX_CHANNELS) 718 return; /* already freed */ 719 720 /* free channel */ 721 x = td->channel; 722 td->channel = DWC_OTG_MAX_CHANNELS; 723 724 DPRINTF("CH=%d\n", x); 725 726 /* get pointer to softc */ 727 sc = DWC_OTG_PC2SC(td->pc); 728 729 dwc_otg_host_channel_disable(sc, x); 730 731 sc->sc_chan_state[x].allocated = 0; 732 sc->sc_chan_state[x].suspended = 0; 733 734 /* keep track of used FIFO */ 735 sc->sc_tx_cur_size -= sc->sc_chan_state[x].tx_size; 736 737 /* ack any pending messages */ 738 if (sc->sc_last_rx_status != 0 && 739 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 740 dwc_otg_common_rx_ack(sc); 741 } 742 743 /* clear active channel */ 744 sc->sc_active_rx_ep &= ~(1 << x); 745 } 746 747 static uint8_t 748 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 749 { 750 struct usb_device_request req __aligned(4); 751 struct dwc_otg_softc *sc; 752 uint32_t hcint; 753 uint32_t hcchar; 754 755 if (dwc_otg_host_channel_alloc(td)) 756 goto busy; 757 758 /* get pointer to softc */ 759 sc = DWC_OTG_PC2SC(td->pc); 760 761 hcint = sc->sc_chan_state[td->channel].hcint; 762 763 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 764 td->channel, td->state, hcint, 765 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 766 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 767 768 if (hcint & (HCINT_RETRY | 769 HCINT_ACK | HCINT_NYET)) { 770 /* give success bits priority over failure bits */ 771 } else if (hcint & HCINT_STALL) { 772 DPRINTF("CH=%d STALL\n", td->channel); 773 td->error_stall = 1; 774 td->error_any = 1; 775 goto complete; 776 } else if (hcint & HCINT_ERRORS) { 777 DPRINTF("CH=%d ERROR\n", td->channel); 778 td->errcnt++; 779 if (td->hcsplt != 0 || td->errcnt >= 3) { 780 td->error_any = 1; 781 goto complete; 782 } 783 } 784 785 /* channel must be disabled before we can complete the transfer */ 786 787 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 788 HCINT_ACK | HCINT_NYET)) { 789 790 dwc_otg_host_channel_disable(sc, td->channel); 791 792 if (!(hcint & HCINT_ERRORS)) 793 td->errcnt = 0; 794 } 795 796 switch (td->state) { 797 case DWC_CHAN_ST_START: 798 if (!dwc_otg_host_channel_wait(td)) 799 break; 800 goto send_pkt; 801 802 case DWC_CHAN_ST_WAIT_ANE: 803 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 804 if (!dwc_otg_host_channel_wait(td)) 805 break; 806 td->did_nak = 1; 807 td->tt_scheduled = 0; 808 goto send_pkt; 809 } 810 if (hcint & (HCINT_ACK | HCINT_NYET)) { 811 if (!dwc_otg_host_channel_wait(td)) 812 break; 813 td->offset += td->tx_bytes; 814 td->remainder -= td->tx_bytes; 815 td->toggle = 1; 816 td->tt_scheduled = 0; 817 goto complete; 818 } 819 break; 820 821 case DWC_CHAN_ST_WAIT_S_ANE: 822 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 823 if (!dwc_otg_host_channel_wait(td)) 824 break; 825 td->did_nak = 1; 826 td->tt_scheduled = 0; 827 goto send_pkt; 828 } 829 if (hcint & (HCINT_ACK | HCINT_NYET)) { 830 if (!dwc_otg_host_channel_wait(td)) 831 break; 832 goto send_cpkt; 833 } 834 break; 835 836 case DWC_CHAN_ST_WAIT_C_ANE: 837 if (hcint & HCINT_NYET) { 838 if (!dwc_otg_host_channel_wait(td)) 839 break; 840 goto send_cpkt; 841 } 842 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 843 if (!dwc_otg_host_channel_wait(td)) 844 break; 845 td->did_nak = 1; 846 td->tt_scheduled = 0; 847 goto send_pkt; 848 } 849 if (hcint & HCINT_ACK) { 850 if (!dwc_otg_host_channel_wait(td)) 851 break; 852 td->offset += td->tx_bytes; 853 td->remainder -= td->tx_bytes; 854 td->toggle = 1; 855 goto complete; 856 } 857 break; 858 859 case DWC_CHAN_ST_WAIT_C_PKT: 860 if (!dwc_otg_host_channel_wait(td)) 861 break; 862 goto send_cpkt; 863 864 default: 865 break; 866 } 867 goto busy; 868 869 send_pkt: 870 if (sizeof(req) != td->remainder) { 871 td->error_any = 1; 872 goto complete; 873 } 874 875 if (td->hcsplt != 0) { 876 /* Wait for our turn, if TT transfer */ 877 if (td->tt_scheduled == 0 || 878 (sc->sc_last_frame_num & 7) < td->tt_start_slot) { 879 /* set return state */ 880 td->state = DWC_CHAN_ST_START; 881 goto tt_wait; 882 } 883 884 td->hcsplt &= ~HCSPLT_COMPSPLT; 885 td->state = DWC_CHAN_ST_WAIT_S_ANE; 886 } else { 887 td->state = DWC_CHAN_ST_WAIT_ANE; 888 } 889 890 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 891 892 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 893 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 894 (1 << HCTSIZ_PKTCNT_SHIFT) | 895 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 896 897 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 898 899 hcchar = td->hcchar; 900 hcchar &= ~HCCHAR_EPDIR_IN; 901 902 /* must enable channel before writing data to FIFO */ 903 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 904 905 /* transfer data into FIFO */ 906 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 907 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 908 909 /* store number of bytes transmitted */ 910 td->tx_bytes = sizeof(req); 911 912 goto busy; 913 914 send_cpkt: 915 /* Wait for our turn, if TT transfer */ 916 if (td->tt_scheduled == 0 || 917 (sc->sc_last_frame_num & 7) < td->tt_complete_slot) { 918 /* set return state */ 919 td->state = DWC_CHAN_ST_WAIT_C_PKT; 920 goto tt_wait; 921 } 922 /* wait until next slot before trying again */ 923 td->tt_complete_slot++; 924 925 td->hcsplt |= HCSPLT_COMPSPLT; 926 td->state = DWC_CHAN_ST_WAIT_C_ANE; 927 928 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 929 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 930 931 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 932 933 hcchar = td->hcchar; 934 hcchar &= ~HCCHAR_EPDIR_IN; 935 936 /* must enable channel before writing data to FIFO */ 937 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 938 goto busy; 939 940 tt_wait: 941 /* free allocated channel */ 942 dwc_otg_host_channel_free(td); 943 busy: 944 return (1); /* busy */ 945 complete: 946 return (0); /* complete */ 947 } 948 949 static uint8_t 950 dwc_otg_setup_rx(struct dwc_otg_td *td) 951 { 952 struct dwc_otg_softc *sc; 953 struct usb_device_request req __aligned(4); 954 uint32_t temp; 955 uint16_t count; 956 957 /* get pointer to softc */ 958 sc = DWC_OTG_PC2SC(td->pc); 959 960 /* check endpoint status */ 961 962 if (sc->sc_last_rx_status == 0) 963 goto not_complete; 964 965 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 966 goto not_complete; 967 968 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 969 GRXSTSRD_DPID_DATA0) { 970 /* release FIFO */ 971 dwc_otg_common_rx_ack(sc); 972 goto not_complete; 973 } 974 975 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 976 GRXSTSRD_STP_DATA) { 977 /* release FIFO */ 978 dwc_otg_common_rx_ack(sc); 979 goto not_complete; 980 } 981 982 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 983 984 /* clear did stall */ 985 td->did_stall = 0; 986 987 /* get the packet byte count */ 988 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 989 990 /* verify data length */ 991 if (count != td->remainder) { 992 DPRINTFN(0, "Invalid SETUP packet " 993 "length, %d bytes\n", count); 994 /* release FIFO */ 995 dwc_otg_common_rx_ack(sc); 996 goto not_complete; 997 } 998 if (count != sizeof(req)) { 999 DPRINTFN(0, "Unsupported SETUP packet " 1000 "length, %d bytes\n", count); 1001 /* release FIFO */ 1002 dwc_otg_common_rx_ack(sc); 1003 goto not_complete; 1004 } 1005 1006 /* copy in control request */ 1007 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 1008 1009 /* copy data into real buffer */ 1010 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 1011 1012 td->offset = sizeof(req); 1013 td->remainder = 0; 1014 1015 /* sneak peek the set address */ 1016 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1017 (req.bRequest == UR_SET_ADDRESS)) { 1018 /* must write address before ZLP */ 1019 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1020 } 1021 1022 /* don't send any data by default */ 1023 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 1024 DXEPTSIZ_SET_NPKT(0) | 1025 DXEPTSIZ_SET_NBYTES(0)); 1026 1027 temp = sc->sc_in_ctl[0]; 1028 1029 /* enable IN endpoint */ 1030 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1031 temp | DIEPCTL_EPENA); 1032 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1033 temp | DIEPCTL_SNAK); 1034 1035 /* reset IN endpoint buffer */ 1036 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1037 GRSTCTL_TXFIFO(0) | 1038 GRSTCTL_TXFFLSH); 1039 1040 /* acknowledge RX status */ 1041 dwc_otg_common_rx_ack(sc); 1042 return (0); /* complete */ 1043 1044 not_complete: 1045 /* abort any ongoing transfer, before enabling again */ 1046 1047 temp = sc->sc_out_ctl[0]; 1048 1049 temp |= DOEPCTL_EPENA | 1050 DOEPCTL_SNAK; 1051 1052 /* enable OUT endpoint */ 1053 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1054 1055 if (!td->did_stall) { 1056 td->did_stall = 1; 1057 1058 DPRINTFN(5, "stalling IN and OUT direction\n"); 1059 1060 /* set stall after enabling endpoint */ 1061 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1062 temp | DOEPCTL_STALL); 1063 1064 temp = sc->sc_in_ctl[0]; 1065 1066 /* set stall assuming endpoint is enabled */ 1067 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1068 temp | DIEPCTL_STALL); 1069 } 1070 1071 /* setup number of buffers to receive */ 1072 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1073 DXEPTSIZ_SET_MULTI(3) | 1074 DXEPTSIZ_SET_NPKT(1) | 1075 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1076 1077 return (1); /* not complete */ 1078 } 1079 1080 static uint8_t 1081 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1082 { 1083 uint8_t delta; 1084 1085 delta = sc->sc_tmr_val - td->tmr_val; 1086 if (delta >= 128) 1087 return (1); /* busy */ 1088 1089 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1090 1091 /* set toggle, if any */ 1092 if (td->set_toggle) { 1093 td->set_toggle = 0; 1094 td->toggle = 1; 1095 } 1096 return (0); 1097 } 1098 1099 static uint8_t 1100 dwc_otg_host_rate_check(struct dwc_otg_td *td) 1101 { 1102 struct dwc_otg_softc *sc; 1103 uint8_t ep_type; 1104 1105 /* get pointer to softc */ 1106 sc = DWC_OTG_PC2SC(td->pc); 1107 1108 if (td->channel < DWC_OTG_MAX_CHANNELS && 1109 sc->sc_chan_state[td->channel].suspended) 1110 goto busy; 1111 1112 ep_type = ((td->hcchar & 1113 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1114 1115 if (ep_type == UE_ISOCHRONOUS) { 1116 1117 /* non TT isochronous traffic */ 1118 if ((td->tmr_val != 0) || 1119 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1120 goto busy; 1121 } 1122 td->tmr_val = 1; /* executed */ 1123 td->toggle = 0; 1124 1125 } else if (ep_type == UE_INTERRUPT) { 1126 if (!td->tt_scheduled) 1127 goto busy; 1128 td->tt_scheduled = 0; 1129 } else if (td->did_nak != 0) { 1130 goto busy; 1131 } else if (td->set_toggle) { 1132 td->set_toggle = 0; 1133 td->toggle = 1; 1134 } 1135 return (0); 1136 busy: 1137 return (1); 1138 } 1139 1140 static uint8_t 1141 dwc_otg_host_data_rx(struct dwc_otg_td *td) 1142 { 1143 struct dwc_otg_softc *sc; 1144 uint32_t hcint; 1145 uint32_t hcchar; 1146 uint32_t count; 1147 uint8_t ep_type; 1148 1149 if (dwc_otg_host_channel_alloc(td)) 1150 goto busy; 1151 1152 /* get pointer to softc */ 1153 sc = DWC_OTG_PC2SC(td->pc); 1154 1155 ep_type = ((td->hcchar & 1156 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1157 1158 hcint = sc->sc_chan_state[td->channel].hcint; 1159 1160 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1161 td->channel, td->state, hcint, 1162 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1163 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1164 1165 /* check interrupt bits */ 1166 1167 if (hcint & (HCINT_RETRY | 1168 HCINT_ACK | HCINT_NYET)) { 1169 /* give success bits priority over failure bits */ 1170 } else if (hcint & HCINT_STALL) { 1171 DPRINTF("CH=%d STALL\n", td->channel); 1172 td->error_stall = 1; 1173 td->error_any = 1; 1174 goto complete; 1175 } else if (hcint & HCINT_ERRORS) { 1176 DPRINTF("CH=%d ERROR\n", td->channel); 1177 td->errcnt++; 1178 if (td->hcsplt != 0 || td->errcnt >= 3) { 1179 if (ep_type != UE_ISOCHRONOUS) { 1180 td->error_any = 1; 1181 goto complete; 1182 } 1183 } 1184 } 1185 1186 /* channel must be disabled before we can complete the transfer */ 1187 1188 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1189 HCINT_ACK | HCINT_NYET)) { 1190 1191 dwc_otg_host_channel_disable(sc, td->channel); 1192 1193 if (!(hcint & HCINT_ERRORS)) 1194 td->errcnt = 0; 1195 } 1196 1197 /* check endpoint status */ 1198 if (sc->sc_last_rx_status == 0) 1199 goto check_state; 1200 1201 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 1202 goto check_state; 1203 1204 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1205 case GRXSTSRH_IN_DATA: 1206 1207 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1208 (int)td->state, (int)sc->sc_last_rx_status); 1209 1210 if (hcint & HCINT_SOFTWARE_ONLY) { 1211 /* 1212 * When using SPLIT transactions on interrupt 1213 * endpoints, sometimes data occurs twice. 1214 */ 1215 DPRINTF("Data already received\n"); 1216 break; 1217 } 1218 1219 /* get the packet byte count */ 1220 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1221 1222 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1223 if (ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1224 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1225 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1226 } else { 1227 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1228 1229 /* verify the packet byte count */ 1230 if (count < td->max_packet_size) { 1231 /* we have a short packet */ 1232 td->short_pkt = 1; 1233 td->got_short = 1; 1234 } 1235 } 1236 td->toggle = 0; 1237 } else { 1238 /* verify the packet byte count */ 1239 if (count != td->max_packet_size) { 1240 if (count < td->max_packet_size) { 1241 /* we have a short packet */ 1242 td->short_pkt = 1; 1243 td->got_short = 1; 1244 } else { 1245 /* invalid USB packet */ 1246 td->error_any = 1; 1247 1248 /* release FIFO */ 1249 dwc_otg_common_rx_ack(sc); 1250 goto complete; 1251 } 1252 } 1253 td->toggle ^= 1; 1254 td->tt_scheduled = 0; 1255 } 1256 1257 /* verify the packet byte count */ 1258 if (count > td->remainder) { 1259 /* invalid USB packet */ 1260 td->error_any = 1; 1261 1262 /* release FIFO */ 1263 dwc_otg_common_rx_ack(sc); 1264 goto complete; 1265 } 1266 1267 usbd_copy_in(td->pc, td->offset, 1268 sc->sc_rx_bounce_buffer, count); 1269 1270 td->remainder -= count; 1271 td->offset += count; 1272 hcint |= HCINT_SOFTWARE_ONLY | HCINT_ACK; 1273 sc->sc_chan_state[td->channel].hcint = hcint; 1274 break; 1275 1276 default: 1277 break; 1278 } 1279 /* release FIFO */ 1280 dwc_otg_common_rx_ack(sc); 1281 1282 check_state: 1283 switch (td->state) { 1284 case DWC_CHAN_ST_START: 1285 if (!dwc_otg_host_channel_wait(td)) 1286 break; 1287 if (td->hcsplt != 0) 1288 goto receive_spkt; 1289 else 1290 goto receive_pkt; 1291 1292 case DWC_CHAN_ST_WAIT_ANE: 1293 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1294 if (!dwc_otg_host_channel_wait(td)) 1295 break; 1296 1297 td->did_nak = 1; 1298 td->tt_scheduled = 0; 1299 if (td->hcsplt != 0) 1300 goto receive_spkt; 1301 else 1302 goto receive_pkt; 1303 } 1304 if (!(hcint & HCINT_SOFTWARE_ONLY)) { 1305 if (hcint & HCINT_NYET) { 1306 if (ep_type == UE_ISOCHRONOUS) { 1307 /* we missed the service interval */ 1308 goto complete; 1309 } 1310 if (!dwc_otg_host_channel_wait(td)) 1311 break; 1312 goto receive_pkt; 1313 } 1314 break; 1315 } 1316 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1317 if (!dwc_otg_host_channel_wait(td)) 1318 break; 1319 1320 if (ep_type == UE_ISOCHRONOUS) { 1321 /* check if we are complete */ 1322 if ((td->remainder == 0) || 1323 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) 1324 goto complete; 1325 1326 goto receive_pkt; 1327 } else { 1328 /* check if we are complete */ 1329 if ((td->remainder == 0) || (td->got_short != 0)) { 1330 if (td->short_pkt) 1331 goto complete; 1332 1333 /* 1334 * Else need to receive a zero length 1335 * packet. 1336 */ 1337 } 1338 td->tt_scheduled = 0; 1339 if (td->hcsplt != 0) 1340 goto receive_spkt; 1341 else 1342 goto receive_pkt; 1343 } 1344 } 1345 break; 1346 1347 case DWC_CHAN_ST_WAIT_S_ANE: 1348 /* 1349 * NOTE: The DWC OTG hardware provides a fake ACK in 1350 * case of interrupt and isochronous transfers: 1351 */ 1352 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1353 if (!dwc_otg_host_channel_wait(td)) 1354 break; 1355 1356 td->did_nak = 1; 1357 td->tt_scheduled = 0; 1358 goto receive_spkt; 1359 } 1360 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1361 if (!dwc_otg_host_channel_wait(td)) 1362 break; 1363 goto receive_pkt; 1364 } 1365 break; 1366 1367 case DWC_CHAN_ST_WAIT_C_PKT: 1368 if (!dwc_otg_host_channel_wait(td)) 1369 break; 1370 goto receive_pkt; 1371 1372 default: 1373 break; 1374 } 1375 goto busy; 1376 1377 receive_pkt: 1378 if (td->hcsplt != 0) { 1379 /* Wait for our turn, if TT transfer */ 1380 if (td->tt_scheduled == 0 || 1381 (sc->sc_last_frame_num & 7) < td->tt_complete_slot) { 1382 /* set return state */ 1383 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1384 goto tt_wait; 1385 } 1386 /* wait until next slot before trying again */ 1387 td->tt_complete_slot++; 1388 1389 /* set toggle, if any */ 1390 if (td->set_toggle) { 1391 td->set_toggle = 0; 1392 td->toggle = 1; 1393 } 1394 td->hcsplt |= HCSPLT_COMPSPLT; 1395 count = HCSPLT_XACTLEN_MAX; 1396 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1397 dwc_otg_host_rate_check(td)) { 1398 td->state = DWC_CHAN_ST_START; 1399 dwc_otg_host_channel_free(td); 1400 goto busy; 1401 } else { 1402 count = td->max_packet_size; 1403 } 1404 td->state = DWC_CHAN_ST_WAIT_ANE; 1405 1406 /* receive one packet */ 1407 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1408 (count << HCTSIZ_XFERSIZE_SHIFT) | 1409 (1 << HCTSIZ_PKTCNT_SHIFT) | 1410 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1411 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1412 1413 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1414 1415 /* send ASAP */ 1416 if ((ep_type == UE_ISOCHRONOUS) && !(sc->sc_last_frame_num & 1)) 1417 td->hcchar |= HCCHAR_ODDFRM; 1418 else 1419 td->hcchar &= ~HCCHAR_ODDFRM; 1420 1421 hcchar = td->hcchar; 1422 hcchar |= HCCHAR_EPDIR_IN; 1423 1424 /* must enable channel before data can be received */ 1425 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1426 goto busy; 1427 1428 receive_spkt: 1429 /* Wait for our turn, if TT transfer */ 1430 if (td->tt_scheduled == 0) { 1431 if (ep_type == UE_INTERRUPT) { 1432 td->state = DWC_CHAN_ST_START; 1433 dwc_otg_host_channel_free(td); 1434 goto busy; 1435 } 1436 /* set return state */ 1437 td->state = DWC_CHAN_ST_START; 1438 goto tt_wait; 1439 } 1440 if ((sc->sc_last_frame_num & 7) < td->tt_start_slot) { 1441 /* set return state */ 1442 td->state = DWC_CHAN_ST_START; 1443 goto tt_wait; 1444 } 1445 1446 /* send ASAP */ 1447 if ((ep_type == UE_ISOCHRONOUS) && !(sc->sc_last_frame_num & 1)) 1448 td->hcchar |= HCCHAR_ODDFRM; 1449 else 1450 td->hcchar &= ~HCCHAR_ODDFRM; 1451 1452 td->hcsplt &= ~HCSPLT_COMPSPLT; 1453 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1454 1455 /* receive one packet */ 1456 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1457 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1458 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1459 1460 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1461 1462 hcchar = td->hcchar; 1463 hcchar |= HCCHAR_EPDIR_IN; 1464 1465 /* must enable channel before data can be received */ 1466 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1467 goto busy; 1468 1469 tt_wait: 1470 /* free allocated channel */ 1471 dwc_otg_host_channel_free(td); 1472 busy: 1473 return (1); /* busy */ 1474 complete: 1475 return (0); /* complete */ 1476 } 1477 1478 static uint8_t 1479 dwc_otg_data_rx(struct dwc_otg_td *td) 1480 { 1481 struct dwc_otg_softc *sc; 1482 uint32_t temp; 1483 uint16_t count; 1484 uint8_t got_short; 1485 1486 got_short = 0; 1487 1488 /* get pointer to softc */ 1489 sc = DWC_OTG_PC2SC(td->pc); 1490 1491 /* check endpoint status */ 1492 if (sc->sc_last_rx_status == 0) 1493 goto not_complete; 1494 1495 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1496 goto not_complete; 1497 1498 /* check for SETUP packet */ 1499 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1500 GRXSTSRD_STP_DATA) { 1501 if (td->remainder == 0) { 1502 /* 1503 * We are actually complete and have 1504 * received the next SETUP 1505 */ 1506 DPRINTFN(5, "faking complete\n"); 1507 return (0); /* complete */ 1508 } 1509 /* 1510 * USB Host Aborted the transfer. 1511 */ 1512 td->error_any = 1; 1513 return (0); /* complete */ 1514 } 1515 1516 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1517 GRXSTSRD_OUT_DATA) { 1518 /* release FIFO */ 1519 dwc_otg_common_rx_ack(sc); 1520 goto not_complete; 1521 } 1522 1523 /* get the packet byte count */ 1524 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1525 1526 /* verify the packet byte count */ 1527 if (count != td->max_packet_size) { 1528 if (count < td->max_packet_size) { 1529 /* we have a short packet */ 1530 td->short_pkt = 1; 1531 got_short = 1; 1532 } else { 1533 /* invalid USB packet */ 1534 td->error_any = 1; 1535 1536 /* release FIFO */ 1537 dwc_otg_common_rx_ack(sc); 1538 return (0); /* we are complete */ 1539 } 1540 } 1541 /* verify the packet byte count */ 1542 if (count > td->remainder) { 1543 /* invalid USB packet */ 1544 td->error_any = 1; 1545 1546 /* release FIFO */ 1547 dwc_otg_common_rx_ack(sc); 1548 return (0); /* we are complete */ 1549 } 1550 1551 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1552 td->remainder -= count; 1553 td->offset += count; 1554 1555 /* release FIFO */ 1556 dwc_otg_common_rx_ack(sc); 1557 1558 /* check if we are complete */ 1559 if ((td->remainder == 0) || got_short) { 1560 if (td->short_pkt) { 1561 /* we are complete */ 1562 return (0); 1563 } 1564 /* else need to receive a zero length packet */ 1565 } 1566 1567 not_complete: 1568 1569 temp = sc->sc_out_ctl[td->ep_no]; 1570 1571 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1572 1573 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1574 1575 /* enable SETUP and transfer complete interrupt */ 1576 if (td->ep_no == 0) { 1577 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1578 DXEPTSIZ_SET_NPKT(1) | 1579 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1580 } else { 1581 /* allow reception of multiple packets */ 1582 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1583 DXEPTSIZ_SET_MULTI(1) | 1584 DXEPTSIZ_SET_NPKT(4) | 1585 DXEPTSIZ_SET_NBYTES(4 * 1586 ((td->max_packet_size + 3) & ~3))); 1587 } 1588 return (1); /* not complete */ 1589 } 1590 1591 static uint8_t 1592 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1593 { 1594 struct dwc_otg_softc *sc; 1595 uint32_t count; 1596 uint32_t hcint; 1597 uint32_t hcchar; 1598 uint8_t ep_type; 1599 1600 if (dwc_otg_host_channel_alloc(td)) 1601 goto busy; 1602 1603 /* get pointer to softc */ 1604 sc = DWC_OTG_PC2SC(td->pc); 1605 1606 ep_type = ((td->hcchar & 1607 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1608 1609 hcint = sc->sc_chan_state[td->channel].hcint; 1610 1611 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1612 td->channel, td->state, hcint, 1613 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1614 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1615 1616 if (hcint & (HCINT_RETRY | 1617 HCINT_ACK | HCINT_NYET)) { 1618 /* give success bits priority over failure bits */ 1619 } else if (hcint & HCINT_STALL) { 1620 DPRINTF("CH=%d STALL\n", td->channel); 1621 td->error_stall = 1; 1622 td->error_any = 1; 1623 goto complete; 1624 } else if (hcint & HCINT_ERRORS) { 1625 DPRINTF("CH=%d ERROR\n", td->channel); 1626 td->errcnt++; 1627 if (td->hcsplt != 0 || td->errcnt >= 3) { 1628 td->error_any = 1; 1629 goto complete; 1630 } 1631 } 1632 1633 /* channel must be disabled before we can complete the transfer */ 1634 1635 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1636 HCINT_ACK | HCINT_NYET)) { 1637 1638 dwc_otg_host_channel_disable(sc, td->channel); 1639 1640 if (!(hcint & HCINT_ERRORS)) 1641 td->errcnt = 0; 1642 } 1643 1644 switch (td->state) { 1645 case DWC_CHAN_ST_START: 1646 if (!dwc_otg_host_channel_wait(td)) 1647 break; 1648 goto send_pkt; 1649 1650 case DWC_CHAN_ST_WAIT_ANE: 1651 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1652 if (!dwc_otg_host_channel_wait(td)) 1653 break; 1654 td->did_nak = 1; 1655 td->tt_scheduled = 0; 1656 goto send_pkt; 1657 } 1658 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1659 if (!dwc_otg_host_channel_wait(td)) 1660 break; 1661 1662 td->offset += td->tx_bytes; 1663 td->remainder -= td->tx_bytes; 1664 td->toggle ^= 1; 1665 td->tt_scheduled = 0; 1666 1667 /* check remainder */ 1668 if (td->remainder == 0) { 1669 if (td->short_pkt) 1670 goto complete; 1671 1672 /* 1673 * Else we need to transmit a short 1674 * packet: 1675 */ 1676 } 1677 goto send_pkt; 1678 } 1679 break; 1680 1681 case DWC_CHAN_ST_WAIT_S_ANE: 1682 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1683 if (!dwc_otg_host_channel_wait(td)) 1684 break; 1685 td->did_nak = 1; 1686 td->tt_scheduled = 0; 1687 goto send_pkt; 1688 } 1689 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1690 if (!dwc_otg_host_channel_wait(td)) 1691 break; 1692 goto send_cpkt; 1693 } 1694 break; 1695 1696 case DWC_CHAN_ST_WAIT_C_ANE: 1697 if (hcint & HCINT_NYET) { 1698 if (!dwc_otg_host_channel_wait(td)) 1699 break; 1700 goto send_cpkt; 1701 } 1702 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1703 if (!dwc_otg_host_channel_wait(td)) 1704 break; 1705 td->did_nak = 1; 1706 td->tt_scheduled = 0; 1707 goto send_pkt; 1708 } 1709 if (hcint & HCINT_ACK) { 1710 if (!dwc_otg_host_channel_wait(td)) 1711 break; 1712 td->offset += td->tx_bytes; 1713 td->remainder -= td->tx_bytes; 1714 td->toggle ^= 1; 1715 td->tt_scheduled = 0; 1716 1717 /* check remainder */ 1718 if (td->remainder == 0) { 1719 if (td->short_pkt) 1720 goto complete; 1721 1722 /* else we need to transmit a short packet */ 1723 } 1724 goto send_pkt; 1725 } 1726 break; 1727 1728 case DWC_CHAN_ST_WAIT_C_PKT: 1729 if (!dwc_otg_host_channel_wait(td)) 1730 break; 1731 goto send_cpkt; 1732 1733 case DWC_CHAN_ST_TX_WAIT_ISOC: 1734 1735 /* Check if isochronous OUT traffic is complete */ 1736 if ((hcint & HCINT_ACK) == 0) 1737 break; 1738 1739 td->offset += td->tx_bytes; 1740 td->remainder -= td->tx_bytes; 1741 1742 /* Update split token according to specification */ 1743 if (td->hcsplt != 0) { 1744 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) 1745 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1746 } else if (td->max_packet_count > 1) { 1747 td->tt_xactpos++; 1748 } 1749 1750 dwc_otg_host_channel_disable(sc, td->channel); 1751 1752 if (td->remainder == 0) 1753 goto complete; 1754 1755 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1756 1757 /* FALLTHROUGH */ 1758 1759 case DWC_CHAN_ST_TX_PKT_ISOC: 1760 if (!dwc_otg_host_channel_wait(td)) 1761 break; 1762 1763 if (td->hcsplt != 0) { 1764 if ((sc->sc_last_frame_num & 7) < td->tt_start_slot) 1765 goto tt_wait; 1766 /* packets must be 125us apart */ 1767 td->tt_start_slot++; 1768 } 1769 goto send_isoc_pkt; 1770 default: 1771 break; 1772 } 1773 goto busy; 1774 1775 send_pkt: 1776 if (td->hcsplt != 0) { 1777 /* Wait for our turn, if TT transfer */ 1778 if (td->tt_scheduled == 0) { 1779 if (ep_type == UE_INTERRUPT) { 1780 td->state = DWC_CHAN_ST_START; 1781 dwc_otg_host_channel_free(td); 1782 goto busy; 1783 } 1784 /* set return state */ 1785 td->state = DWC_CHAN_ST_START; 1786 goto tt_wait; 1787 } 1788 if ((sc->sc_last_frame_num & 7) < td->tt_start_slot) { 1789 /* set return state */ 1790 td->state = DWC_CHAN_ST_START; 1791 goto tt_wait; 1792 } 1793 1794 /* packets must be 125us apart */ 1795 td->tt_start_slot++; 1796 1797 /* set toggle, if any */ 1798 if (td->set_toggle) { 1799 td->set_toggle = 0; 1800 td->toggle = 1; 1801 } 1802 } else if (dwc_otg_host_rate_check(td)) { 1803 td->state = DWC_CHAN_ST_START; 1804 dwc_otg_host_channel_free(td); 1805 goto busy; 1806 } 1807 1808 if (ep_type == UE_ISOCHRONOUS) { 1809 send_isoc_pkt: 1810 /* Isochronous OUT transfers don't have any ACKs */ 1811 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1812 td->hcsplt &= ~HCSPLT_COMPSPLT; 1813 if (td->hcsplt != 0) { 1814 /* get maximum transfer length */ 1815 count = td->remainder; 1816 1817 /* Update split token according to specification */ 1818 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1819 if (count <= HCSPLT_XACTLEN_MAX) 1820 td->tt_xactpos = HCSPLT_XACTPOS_ALL; 1821 else 1822 count = HCSPLT_XACTLEN_MAX; 1823 } else if (td->tt_xactpos == HCSPLT_XACTPOS_MIDDLE) { 1824 if (count <= HCSPLT_XACTLEN_MAX) 1825 td->tt_xactpos = HCSPLT_XACTPOS_LAST; 1826 else 1827 count = HCSPLT_XACTLEN_MAX; 1828 } 1829 1830 /* Update transaction position */ 1831 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1832 td->hcsplt |= ((uint32_t)td->tt_xactpos << HCSPLT_XACTPOS_SHIFT); 1833 } else { 1834 /* send one packet at a time */ 1835 count = td->max_packet_size; 1836 if (td->remainder < count) { 1837 /* we have a short packet */ 1838 td->short_pkt = 1; 1839 count = td->remainder; 1840 } 1841 } 1842 } else if (td->hcsplt != 0) { 1843 1844 td->hcsplt &= ~HCSPLT_COMPSPLT; 1845 1846 /* Wait for ACK/NAK/ERR from TT */ 1847 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1848 1849 /* send one packet at a time */ 1850 count = td->max_packet_size; 1851 if (td->remainder < count) { 1852 /* we have a short packet */ 1853 td->short_pkt = 1; 1854 count = td->remainder; 1855 } 1856 } else { 1857 /* Wait for ACK/NAK/STALL from device */ 1858 td->state = DWC_CHAN_ST_WAIT_ANE; 1859 1860 /* send one packet at a time */ 1861 count = td->max_packet_size; 1862 if (td->remainder < count) { 1863 /* we have a short packet */ 1864 td->short_pkt = 1; 1865 count = td->remainder; 1866 } 1867 } 1868 1869 /* check for High-Speed multi-packets */ 1870 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1871 if (td->npkt == 0) { 1872 if (td->remainder >= (3 * td->max_packet_size)) 1873 td->npkt = 3; 1874 else if (td->remainder >= (2 * td->max_packet_size)) 1875 td->npkt = 2; 1876 else 1877 td->npkt = 1; 1878 1879 if (td->npkt > td->max_packet_count) 1880 td->npkt = td->max_packet_count; 1881 1882 td->tt_xactpos = 1; /* overload */ 1883 } 1884 if (td->tt_xactpos == td->npkt) { 1885 if (td->npkt == 1) { 1886 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1887 (count << HCTSIZ_XFERSIZE_SHIFT) | 1888 (1 << HCTSIZ_PKTCNT_SHIFT) | 1889 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1890 } else if (td->npkt == 2) { 1891 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1892 (count << HCTSIZ_XFERSIZE_SHIFT) | 1893 (1 << HCTSIZ_PKTCNT_SHIFT) | 1894 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1895 } else { 1896 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1897 (count << HCTSIZ_XFERSIZE_SHIFT) | 1898 (1 << HCTSIZ_PKTCNT_SHIFT) | 1899 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1900 } 1901 td->npkt = 0; 1902 } else { 1903 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1904 (count << HCTSIZ_XFERSIZE_SHIFT) | 1905 (1 << HCTSIZ_PKTCNT_SHIFT) | 1906 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1907 } 1908 } else { 1909 /* TODO: HCTSIZ_DOPNG */ 1910 1911 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1912 (count << HCTSIZ_XFERSIZE_SHIFT) | 1913 (1 << HCTSIZ_PKTCNT_SHIFT) | 1914 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1915 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1916 } 1917 1918 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1919 1920 /* send ASAP */ 1921 if ((ep_type == UE_ISOCHRONOUS) && !(sc->sc_last_frame_num & 1)) 1922 td->hcchar |= HCCHAR_ODDFRM; 1923 else 1924 td->hcchar &= ~HCCHAR_ODDFRM; 1925 1926 hcchar = td->hcchar; 1927 hcchar &= ~HCCHAR_EPDIR_IN; 1928 1929 /* must enable before writing data to FIFO */ 1930 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1931 1932 if (count != 0) { 1933 1934 /* clear topmost word before copy */ 1935 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1936 1937 /* copy out data */ 1938 usbd_copy_out(td->pc, td->offset, 1939 sc->sc_tx_bounce_buffer, count); 1940 1941 /* transfer data into FIFO */ 1942 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1943 DOTG_DFIFO(td->channel), 1944 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1945 } 1946 1947 /* store number of bytes transmitted */ 1948 td->tx_bytes = count; 1949 goto busy; 1950 1951 send_cpkt: 1952 /* Wait for our turn, if TT transfer */ 1953 if (td->tt_scheduled == 0 || 1954 (sc->sc_last_frame_num & 7) < td->tt_complete_slot) { 1955 /* set return state */ 1956 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1957 goto tt_wait; 1958 } 1959 /* wait until next slot before trying again */ 1960 td->tt_complete_slot++; 1961 1962 td->hcsplt |= HCSPLT_COMPSPLT; 1963 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1964 1965 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1966 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1967 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1968 1969 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1970 1971 hcchar = td->hcchar; 1972 hcchar &= ~HCCHAR_EPDIR_IN; 1973 1974 /* must enable channel before writing data to FIFO */ 1975 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1976 goto busy; 1977 1978 tt_wait: 1979 /* free allocated channel */ 1980 dwc_otg_host_channel_free(td); 1981 busy: 1982 return (1); /* busy */ 1983 complete: 1984 return (0); /* complete */ 1985 } 1986 1987 static uint8_t 1988 dwc_otg_data_tx(struct dwc_otg_td *td) 1989 { 1990 struct dwc_otg_softc *sc; 1991 uint32_t max_buffer; 1992 uint32_t count; 1993 uint32_t fifo_left; 1994 uint32_t mpkt; 1995 uint32_t temp; 1996 uint8_t to; 1997 1998 to = 3; /* don't loop forever! */ 1999 2000 /* get pointer to softc */ 2001 sc = DWC_OTG_PC2SC(td->pc); 2002 2003 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2004 2005 repeat: 2006 /* check for for endpoint 0 data */ 2007 2008 temp = sc->sc_last_rx_status; 2009 2010 if ((td->ep_no == 0) && (temp != 0) && 2011 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2012 2013 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2014 GRXSTSRD_STP_DATA) { 2015 2016 /* dump data - wrong direction */ 2017 dwc_otg_common_rx_ack(sc); 2018 } else { 2019 /* 2020 * The current transfer was cancelled 2021 * by the USB Host: 2022 */ 2023 td->error_any = 1; 2024 return (0); /* complete */ 2025 } 2026 } 2027 2028 /* fill in more TX data, if possible */ 2029 if (td->tx_bytes != 0) { 2030 2031 uint16_t cpkt; 2032 2033 /* check if packets have been transferred */ 2034 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2035 2036 /* get current packet number */ 2037 cpkt = DXEPTSIZ_GET_NPKT(temp); 2038 2039 if (cpkt >= td->npkt) { 2040 fifo_left = 0; 2041 } else { 2042 if (max_buffer != 0) { 2043 fifo_left = (td->npkt - cpkt) * 2044 td->max_packet_size; 2045 2046 if (fifo_left > max_buffer) 2047 fifo_left = max_buffer; 2048 } else { 2049 fifo_left = td->max_packet_size; 2050 } 2051 } 2052 2053 count = td->tx_bytes; 2054 if (count > fifo_left) 2055 count = fifo_left; 2056 2057 if (count != 0) { 2058 2059 /* clear topmost word before copy */ 2060 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2061 2062 /* copy out data */ 2063 usbd_copy_out(td->pc, td->offset, 2064 sc->sc_tx_bounce_buffer, count); 2065 2066 /* transfer data into FIFO */ 2067 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2068 DOTG_DFIFO(td->ep_no), 2069 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2070 2071 td->tx_bytes -= count; 2072 td->remainder -= count; 2073 td->offset += count; 2074 td->npkt = cpkt; 2075 } 2076 if (td->tx_bytes != 0) 2077 goto not_complete; 2078 2079 /* check remainder */ 2080 if (td->remainder == 0) { 2081 if (td->short_pkt) 2082 return (0); /* complete */ 2083 2084 /* else we need to transmit a short packet */ 2085 } 2086 } 2087 2088 if (!to--) 2089 goto not_complete; 2090 2091 /* check if not all packets have been transferred */ 2092 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2093 2094 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2095 2096 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2097 "DIEPCTL=0x%08x\n", td->ep_no, 2098 DXEPTSIZ_GET_NPKT(temp), 2099 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2100 2101 goto not_complete; 2102 } 2103 2104 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2105 2106 /* try to optimise by sending more data */ 2107 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2108 2109 /* send multiple packets at the same time */ 2110 mpkt = max_buffer / td->max_packet_size; 2111 2112 if (mpkt > 0x3FE) 2113 mpkt = 0x3FE; 2114 2115 count = td->remainder; 2116 if (count > 0x7FFFFF) 2117 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2118 2119 td->npkt = count / td->max_packet_size; 2120 2121 /* 2122 * NOTE: We could use 0x3FE instead of "mpkt" in the 2123 * check below to get more throughput, but then we 2124 * have a dependency towards non-generic chip features 2125 * to disable the TX-FIFO-EMPTY interrupts on a per 2126 * endpoint basis. Increase the maximum buffer size of 2127 * the IN endpoint to increase the performance. 2128 */ 2129 if (td->npkt > mpkt) { 2130 td->npkt = mpkt; 2131 count = td->max_packet_size * mpkt; 2132 } else if ((count == 0) || (count % td->max_packet_size)) { 2133 /* we are transmitting a short packet */ 2134 td->npkt++; 2135 td->short_pkt = 1; 2136 } 2137 } else { 2138 /* send one packet at a time */ 2139 mpkt = 1; 2140 count = td->max_packet_size; 2141 if (td->remainder < count) { 2142 /* we have a short packet */ 2143 td->short_pkt = 1; 2144 count = td->remainder; 2145 } 2146 td->npkt = 1; 2147 } 2148 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2149 DXEPTSIZ_SET_MULTI(1) | 2150 DXEPTSIZ_SET_NPKT(td->npkt) | 2151 DXEPTSIZ_SET_NBYTES(count)); 2152 2153 /* make room for buffering */ 2154 td->npkt += mpkt; 2155 2156 temp = sc->sc_in_ctl[td->ep_no]; 2157 2158 /* must enable before writing data to FIFO */ 2159 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2160 DIEPCTL_EPENA | 2161 DIEPCTL_CNAK); 2162 2163 td->tx_bytes = count; 2164 2165 /* check remainder */ 2166 if (td->tx_bytes == 0 && 2167 td->remainder == 0) { 2168 if (td->short_pkt) 2169 return (0); /* complete */ 2170 2171 /* else we need to transmit a short packet */ 2172 } 2173 goto repeat; 2174 2175 not_complete: 2176 return (1); /* not complete */ 2177 } 2178 2179 static uint8_t 2180 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 2181 { 2182 struct dwc_otg_softc *sc; 2183 uint32_t temp; 2184 2185 /* get pointer to softc */ 2186 sc = DWC_OTG_PC2SC(td->pc); 2187 2188 /* 2189 * If all packets are transferred we are complete: 2190 */ 2191 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2192 2193 /* check that all packets have been transferred */ 2194 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2195 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2196 goto not_complete; 2197 } 2198 return (0); 2199 2200 not_complete: 2201 2202 /* we only want to know if there is a SETUP packet or free IN packet */ 2203 2204 temp = sc->sc_last_rx_status; 2205 2206 if ((td->ep_no == 0) && (temp != 0) && 2207 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2208 2209 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2210 GRXSTSRD_STP_DATA) { 2211 DPRINTFN(5, "faking complete\n"); 2212 /* 2213 * Race condition: We are complete! 2214 */ 2215 return (0); 2216 } else { 2217 /* dump data - wrong direction */ 2218 dwc_otg_common_rx_ack(sc); 2219 } 2220 } 2221 return (1); /* not complete */ 2222 } 2223 2224 static uint8_t 2225 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 2226 { 2227 struct dwc_otg_td *td; 2228 uint8_t toggle; 2229 uint8_t channel; 2230 uint8_t tmr_val; 2231 uint8_t tmr_res; 2232 2233 DPRINTFN(9, "\n"); 2234 2235 td = xfer->td_transfer_cache; 2236 2237 /* 2238 * If we are suspended in host mode and no channel is 2239 * allocated, simply return: 2240 */ 2241 if (xfer->xroot->udev->flags.self_suspended != 0 && 2242 xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST && 2243 td->channel >= DWC_OTG_MAX_CHANNELS) { 2244 return (1); /* not complete */ 2245 } 2246 while (1) { 2247 if ((td->func) (td)) { 2248 /* operation in progress */ 2249 break; 2250 } 2251 if (((void *)td) == xfer->td_transfer_last) { 2252 goto done; 2253 } 2254 if (td->error_any) { 2255 goto done; 2256 } else if (td->remainder > 0) { 2257 /* 2258 * We had a short transfer. If there is no alternate 2259 * next, stop processing ! 2260 */ 2261 if (!td->alt_next) 2262 goto done; 2263 } 2264 2265 /* 2266 * Fetch the next transfer descriptor and transfer 2267 * some flags to the next transfer descriptor 2268 */ 2269 tmr_res = td->tmr_res; 2270 tmr_val = td->tmr_val; 2271 toggle = td->toggle; 2272 channel = td->channel; 2273 td = td->obj_next; 2274 xfer->td_transfer_cache = td; 2275 td->toggle = toggle; /* transfer toggle */ 2276 td->channel = channel; /* transfer channel */ 2277 td->tmr_res = tmr_res; 2278 td->tmr_val = tmr_val; 2279 } 2280 return (1); /* not complete */ 2281 2282 done: 2283 /* compute all actual lengths */ 2284 2285 dwc_otg_standard_done(xfer); 2286 return (0); /* complete */ 2287 } 2288 2289 static void 2290 dwc_otg_timer(void *_sc) 2291 { 2292 struct dwc_otg_softc *sc = _sc; 2293 struct usb_xfer *xfer; 2294 struct dwc_otg_td *td; 2295 2296 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2297 2298 DPRINTF("\n"); 2299 2300 /* increment timer value */ 2301 sc->sc_tmr_val++; 2302 2303 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2304 td = xfer->td_transfer_cache; 2305 if (td != NULL) 2306 td->did_nak = 0; 2307 } 2308 2309 /* enable SOF interrupt, which will poll jobs */ 2310 dwc_otg_enable_sof_irq(sc); 2311 2312 if (sc->sc_timer_active) { 2313 /* restart timer */ 2314 usb_callout_reset(&sc->sc_timer, 2315 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2316 &dwc_otg_timer, sc); 2317 } 2318 } 2319 2320 static void 2321 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2322 { 2323 if (sc->sc_timer_active != 0) 2324 return; 2325 2326 sc->sc_timer_active = 1; 2327 2328 /* restart timer */ 2329 usb_callout_reset(&sc->sc_timer, 2330 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2331 &dwc_otg_timer, sc); 2332 } 2333 2334 static void 2335 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2336 { 2337 if (sc->sc_timer_active == 0) 2338 return; 2339 2340 sc->sc_timer_active = 0; 2341 2342 /* stop timer */ 2343 usb_callout_stop(&sc->sc_timer); 2344 } 2345 2346 static void 2347 dwc_otg_update_host_transfer_schedule(struct dwc_otg_softc *sc) 2348 { 2349 TAILQ_HEAD(, usb_xfer) head; 2350 struct usb_xfer *xfer; 2351 struct usb_xfer *xfer_next; 2352 struct dwc_otg_td *td; 2353 uint8_t needsof; 2354 uint16_t temp; 2355 2356 /* FS/LS TT frames are one behind, so add one here */ 2357 temp = (DWC_OTG_READ_4(sc, DOTG_HFNUM) + 1) & HFNUM_FRNUM_MASK; 2358 2359 if (sc->sc_last_frame_num == temp) 2360 return; 2361 2362 sc->sc_last_frame_num = temp; 2363 2364 needsof = 0; 2365 2366 TAILQ_INIT(&head); 2367 2368 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2369 uint8_t x; 2370 2371 for (x = 0; x != sc->sc_host_ch_max; x++) { 2372 if (sc->sc_chan_state[x].wait_sof != 0) { 2373 if (--(sc->sc_chan_state[x].wait_sof) != 0) 2374 needsof = 1; 2375 } 2376 } 2377 } 2378 2379 if ((temp & 7) == 0) { 2380 2381 /* reset TT info */ 2382 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2383 2384 /* 2385 * Plan ahead FULL speed transfers going through the 2386 * transaction translator, according to the USB 2387 * specified priority: 2388 */ 2389 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2390 struct dwc_otg_tt_info *pinfo; 2391 2392 td = xfer->td_transfer_cache; 2393 if (td == NULL || td->did_nak != 0 || 2394 (td->hcchar & HCCHAR_EPTYPE_MASK) != 2395 (UE_CONTROL << HCCHAR_EPTYPE_SHIFT)) 2396 continue; 2397 2398 needsof = 1; 2399 2400 if (td->hcsplt == 0) 2401 continue; 2402 2403 /* Reset state if stuck waiting for complete split */ 2404 if (td->state == DWC_CHAN_ST_WAIT_C_PKT) 2405 td->state = DWC_CHAN_ST_START; 2406 2407 pinfo = sc->sc_tt_info + td->tt_index; 2408 2409 td->tt_start_slot = pinfo->slot_index; 2410 pinfo->bytes_used += td->max_packet_size; 2411 while (pinfo->bytes_used >= HCSPLT_XACTLEN_MAX) { 2412 pinfo->bytes_used -= HCSPLT_XACTLEN_MAX; 2413 pinfo->slot_index ++; 2414 } 2415 2416 td->tt_complete_slot = pinfo->slot_index + 2; 2417 if (td->tt_complete_slot < 8) { 2418 td->tt_scheduled = 1; 2419 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2420 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2421 } else { 2422 td->tt_scheduled = 0; 2423 } 2424 } 2425 2426 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2427 struct dwc_otg_tt_info *pinfo; 2428 2429 td = xfer->td_transfer_cache; 2430 if (td == NULL || 2431 (td->hcchar & HCCHAR_EPTYPE_MASK) != 2432 (UE_ISOCHRONOUS << HCCHAR_EPTYPE_SHIFT)) 2433 continue; 2434 2435 /* execute more frames */ 2436 td->tmr_val = 0; 2437 2438 needsof = 1; 2439 2440 if (td->hcsplt == 0) 2441 continue; 2442 2443 /* Reset state if stuck waiting for complete split */ 2444 if (td->state == DWC_CHAN_ST_WAIT_C_PKT) 2445 td->state = DWC_CHAN_ST_START; 2446 2447 pinfo = sc->sc_tt_info + td->tt_index; 2448 2449 td->tt_start_slot = pinfo->slot_index; 2450 pinfo->bytes_used += td->remainder; 2451 while (pinfo->bytes_used >= HCSPLT_XACTLEN_MAX) { 2452 pinfo->bytes_used -= HCSPLT_XACTLEN_MAX; 2453 pinfo->slot_index ++; 2454 } 2455 2456 td->tt_complete_slot = pinfo->slot_index + 2; 2457 if (td->tt_complete_slot < 8) { 2458 td->tt_scheduled = 1; 2459 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2460 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2461 } else { 2462 td->tt_scheduled = 0; 2463 } 2464 } 2465 2466 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2467 struct dwc_otg_tt_info *pinfo; 2468 2469 td = xfer->td_transfer_cache; 2470 if (td == NULL || 2471 (td->hcchar & HCCHAR_EPTYPE_MASK) != 2472 (UE_INTERRUPT << HCCHAR_EPTYPE_SHIFT)) { 2473 continue; 2474 } 2475 2476 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2477 continue; 2478 2479 needsof = 1; 2480 2481 if (td->hcsplt == 0) { 2482 td->tt_scheduled = 1; 2483 continue; 2484 } 2485 2486 /* Reset state if stuck waiting for complete split */ 2487 if (td->state == DWC_CHAN_ST_WAIT_C_PKT) 2488 td->state = DWC_CHAN_ST_START; 2489 2490 pinfo = sc->sc_tt_info + td->tt_index; 2491 2492 td->tt_start_slot = pinfo->slot_index; 2493 pinfo->bytes_used += td->remainder; 2494 while (pinfo->bytes_used >= HCSPLT_XACTLEN_MAX) { 2495 pinfo->bytes_used -= HCSPLT_XACTLEN_MAX; 2496 pinfo->slot_index ++; 2497 } 2498 2499 td->tt_complete_slot = pinfo->slot_index + 2; 2500 if (td->tt_complete_slot < 8) { 2501 td->tt_scheduled = 1; 2502 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2503 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2504 } else { 2505 td->tt_scheduled = 0; 2506 } 2507 } 2508 } 2509 2510 if ((temp & 7) < 6) { 2511 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2512 struct dwc_otg_tt_info *pinfo; 2513 2514 td = xfer->td_transfer_cache; 2515 if (td == NULL || td->did_nak != 0 || 2516 (td->hcchar & HCCHAR_EPTYPE_MASK) != 2517 (UE_BULK << HCCHAR_EPTYPE_SHIFT)) { 2518 continue; 2519 } 2520 2521 needsof = 1; 2522 2523 if (td->hcsplt == 0) 2524 continue; 2525 2526 if ((temp & 7) == 0) { 2527 /* Reset state if stuck waiting for complete split */ 2528 if (td->state == DWC_CHAN_ST_WAIT_C_PKT) 2529 td->state = DWC_CHAN_ST_START; 2530 } else if (td->tt_scheduled != 0) 2531 continue; /* already scheduled */ 2532 2533 pinfo = sc->sc_tt_info + td->tt_index; 2534 2535 td->tt_start_slot = pinfo->slot_index; 2536 pinfo->bytes_used += td->remainder; 2537 while (pinfo->bytes_used >= HCSPLT_XACTLEN_MAX) { 2538 pinfo->bytes_used -= HCSPLT_XACTLEN_MAX; 2539 pinfo->slot_index ++; 2540 } 2541 2542 td->tt_complete_slot = pinfo->slot_index + 2; 2543 if (td->tt_complete_slot < 8) { 2544 td->tt_scheduled = 1; 2545 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2546 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2547 } else { 2548 td->tt_scheduled = 0; 2549 } 2550 } 2551 } 2552 2553 /* TT transfers need to be executed in a specific order */ 2554 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2555 2556 /* Put TT transfers first in the queue */ 2557 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2558 2559 if ((temp & 7) == 0) { 2560 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2561 (int)temp, (int)needsof); 2562 2563 /* update SOF IRQ mask */ 2564 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2565 if (needsof == 0) { 2566 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2567 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2568 } 2569 } else { 2570 if (needsof != 0) { 2571 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2572 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2573 } 2574 } 2575 } 2576 } 2577 2578 static void 2579 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 2580 { 2581 struct usb_xfer *xfer; 2582 uint32_t temp; 2583 uint8_t got_rx_status; 2584 uint8_t x; 2585 2586 repeat: 2587 /* get all channel interrupts */ 2588 for (x = 0; x != sc->sc_host_ch_max; x++) { 2589 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2590 if (temp != 0) { 2591 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2592 temp &= ~HCINT_SOFTWARE_ONLY; 2593 sc->sc_chan_state[x].hcint |= temp; 2594 } 2595 } 2596 2597 if (sc->sc_last_rx_status == 0) { 2598 2599 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2600 if (temp & GINTSTS_RXFLVL) { 2601 /* pop current status */ 2602 sc->sc_last_rx_status = 2603 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2604 } 2605 2606 if (sc->sc_last_rx_status != 0) { 2607 2608 uint8_t ep_no; 2609 2610 temp = sc->sc_last_rx_status & 2611 GRXSTSRD_PKTSTS_MASK; 2612 2613 /* non-data messages we simply skip */ 2614 if (temp != GRXSTSRD_STP_DATA && 2615 temp != GRXSTSRD_OUT_DATA) { 2616 dwc_otg_common_rx_ack(sc); 2617 goto repeat; 2618 } 2619 2620 temp = GRXSTSRD_BCNT_GET( 2621 sc->sc_last_rx_status); 2622 ep_no = GRXSTSRD_CHNUM_GET( 2623 sc->sc_last_rx_status); 2624 2625 /* receive data, if any */ 2626 if (temp != 0) { 2627 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2628 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2629 DOTG_DFIFO(ep_no), 2630 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2631 } 2632 2633 /* check if we should dump the data */ 2634 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2635 dwc_otg_common_rx_ack(sc); 2636 goto repeat; 2637 } 2638 2639 got_rx_status = 1; 2640 2641 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2642 sc->sc_last_rx_status, ep_no, 2643 (sc->sc_last_rx_status >> 15) & 3, 2644 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2645 (sc->sc_last_rx_status >> 17) & 15); 2646 } else { 2647 got_rx_status = 0; 2648 } 2649 } else { 2650 uint8_t ep_no; 2651 2652 ep_no = GRXSTSRD_CHNUM_GET( 2653 sc->sc_last_rx_status); 2654 2655 /* check if we should dump the data */ 2656 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2657 dwc_otg_common_rx_ack(sc); 2658 goto repeat; 2659 } 2660 2661 got_rx_status = 1; 2662 } 2663 2664 /* scan for completion events first */ 2665 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2666 if (!dwc_otg_xfer_do_fifo(xfer)) { 2667 /* queue has been modified */ 2668 goto repeat; 2669 } 2670 } 2671 2672 if (sc->sc_flags.status_device_mode == 0) { 2673 /* update host transfer schedule, so that new transfers can be issued */ 2674 dwc_otg_update_host_transfer_schedule(sc); 2675 2676 /* start re-scheduled transfers */ 2677 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2678 if (!dwc_otg_xfer_do_fifo(xfer)) { 2679 /* queue has been modified */ 2680 goto repeat; 2681 } 2682 } 2683 } 2684 2685 if (got_rx_status) { 2686 /* check if data was consumed */ 2687 if (sc->sc_last_rx_status == 0) 2688 goto repeat; 2689 2690 /* disable RX FIFO level interrupt */ 2691 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2692 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2693 } 2694 } 2695 2696 static void 2697 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2698 { 2699 DPRINTFN(5, "vbus = %u\n", is_on); 2700 2701 /* 2702 * If the USB host mode is forced, then assume VBUS is always 2703 * present else rely on the input to this function: 2704 */ 2705 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2706 2707 if (!sc->sc_flags.status_vbus) { 2708 sc->sc_flags.status_vbus = 1; 2709 2710 /* complete root HUB interrupt endpoint */ 2711 2712 dwc_otg_root_intr(sc); 2713 } 2714 } else { 2715 if (sc->sc_flags.status_vbus) { 2716 sc->sc_flags.status_vbus = 0; 2717 sc->sc_flags.status_bus_reset = 0; 2718 sc->sc_flags.status_suspend = 0; 2719 sc->sc_flags.change_suspend = 0; 2720 sc->sc_flags.change_connect = 1; 2721 2722 /* complete root HUB interrupt endpoint */ 2723 2724 dwc_otg_root_intr(sc); 2725 } 2726 } 2727 } 2728 2729 void 2730 dwc_otg_interrupt(struct dwc_otg_softc *sc) 2731 { 2732 uint32_t status; 2733 2734 USB_BUS_LOCK(&sc->sc_bus); 2735 2736 /* read and clear interrupt status */ 2737 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2738 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 2739 2740 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2741 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2742 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2743 2744 if (status & GINTSTS_USBRST) { 2745 2746 /* set correct state */ 2747 sc->sc_flags.status_device_mode = 1; 2748 sc->sc_flags.status_bus_reset = 0; 2749 sc->sc_flags.status_suspend = 0; 2750 sc->sc_flags.change_suspend = 0; 2751 sc->sc_flags.change_connect = 1; 2752 2753 /* Disable SOF interrupt */ 2754 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2755 /* Enable RX frame interrupt */ 2756 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 2757 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2758 2759 /* complete root HUB interrupt endpoint */ 2760 dwc_otg_root_intr(sc); 2761 } 2762 2763 /* check for any bus state change interrupts */ 2764 if (status & GINTSTS_ENUMDONE) { 2765 2766 uint32_t temp; 2767 2768 DPRINTFN(5, "end of reset\n"); 2769 2770 /* set correct state */ 2771 sc->sc_flags.status_device_mode = 1; 2772 sc->sc_flags.status_bus_reset = 1; 2773 sc->sc_flags.status_suspend = 0; 2774 sc->sc_flags.change_suspend = 0; 2775 sc->sc_flags.change_connect = 1; 2776 sc->sc_flags.status_low_speed = 0; 2777 sc->sc_flags.port_enabled = 1; 2778 2779 /* reset FIFOs */ 2780 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2781 2782 /* reset function address */ 2783 dwc_otg_set_address(sc, 0); 2784 2785 /* figure out enumeration speed */ 2786 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2787 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2788 sc->sc_flags.status_high_speed = 1; 2789 else 2790 sc->sc_flags.status_high_speed = 0; 2791 2792 /* 2793 * Disable resume and SOF interrupt, and enable 2794 * suspend and RX frame interrupt: 2795 */ 2796 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2797 sc->sc_irq_mask |= (GINTMSK_USBSUSPMSK | GINTMSK_RXFLVLMSK); 2798 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2799 2800 /* complete root HUB interrupt endpoint */ 2801 dwc_otg_root_intr(sc); 2802 } 2803 2804 if (status & GINTSTS_PRTINT) { 2805 uint32_t hprt; 2806 2807 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2808 2809 /* clear change bits */ 2810 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2811 HPRT_PRTPWR | HPRT_PRTENCHNG | 2812 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2813 sc->sc_hprt_val); 2814 2815 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2816 2817 sc->sc_flags.status_device_mode = 0; 2818 2819 if (hprt & HPRT_PRTCONNSTS) 2820 sc->sc_flags.status_bus_reset = 1; 2821 else 2822 sc->sc_flags.status_bus_reset = 0; 2823 2824 if (hprt & HPRT_PRTENCHNG) 2825 sc->sc_flags.change_enabled = 1; 2826 2827 if (hprt & HPRT_PRTENA) 2828 sc->sc_flags.port_enabled = 1; 2829 else 2830 sc->sc_flags.port_enabled = 0; 2831 2832 if (hprt & HPRT_PRTOVRCURRCHNG) 2833 sc->sc_flags.change_over_current = 1; 2834 2835 if (hprt & HPRT_PRTOVRCURRACT) 2836 sc->sc_flags.port_over_current = 1; 2837 else 2838 sc->sc_flags.port_over_current = 0; 2839 2840 if (hprt & HPRT_PRTPWR) 2841 sc->sc_flags.port_powered = 1; 2842 else 2843 sc->sc_flags.port_powered = 0; 2844 2845 if (((hprt & HPRT_PRTSPD_MASK) 2846 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2847 sc->sc_flags.status_low_speed = 1; 2848 else 2849 sc->sc_flags.status_low_speed = 0; 2850 2851 if (((hprt & HPRT_PRTSPD_MASK) 2852 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2853 sc->sc_flags.status_high_speed = 1; 2854 else 2855 sc->sc_flags.status_high_speed = 0; 2856 2857 if (hprt & HPRT_PRTCONNDET) 2858 sc->sc_flags.change_connect = 1; 2859 2860 if (hprt & HPRT_PRTSUSP) 2861 dwc_otg_suspend_irq(sc); 2862 else 2863 dwc_otg_resume_irq(sc); 2864 2865 /* complete root HUB interrupt endpoint */ 2866 dwc_otg_root_intr(sc); 2867 2868 /* disable RX FIFO level interrupt */ 2869 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2870 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2871 2872 /* update host frame interval */ 2873 dwc_otg_update_host_frame_interval(sc); 2874 } 2875 2876 /* 2877 * If resume and suspend is set at the same time we interpret 2878 * that like RESUME. Resume is set when there is at least 3 2879 * milliseconds of inactivity on the USB BUS. 2880 */ 2881 if (status & GINTSTS_WKUPINT) { 2882 2883 DPRINTFN(5, "resume interrupt\n"); 2884 2885 dwc_otg_resume_irq(sc); 2886 2887 } else if (status & GINTSTS_USBSUSP) { 2888 2889 DPRINTFN(5, "suspend interrupt\n"); 2890 2891 dwc_otg_suspend_irq(sc); 2892 } 2893 /* check VBUS */ 2894 if (status & (GINTSTS_USBSUSP | 2895 GINTSTS_USBRST | 2896 GINTMSK_OTGINTMSK | 2897 GINTSTS_SESSREQINT)) { 2898 uint32_t temp; 2899 2900 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2901 2902 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2903 2904 dwc_otg_vbus_interrupt(sc, 2905 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2906 } 2907 2908 /* clear all IN endpoint interrupts */ 2909 if (status & GINTSTS_IEPINT) { 2910 uint32_t temp; 2911 uint8_t x; 2912 2913 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2914 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2915 if (temp & DIEPMSK_XFERCOMPLMSK) { 2916 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2917 DIEPMSK_XFERCOMPLMSK); 2918 } 2919 } 2920 } 2921 2922 /* poll FIFO(s) */ 2923 dwc_otg_interrupt_poll(sc); 2924 2925 USB_BUS_UNLOCK(&sc->sc_bus); 2926 } 2927 2928 static void 2929 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2930 { 2931 struct dwc_otg_td *td; 2932 2933 /* get current Transfer Descriptor */ 2934 td = temp->td_next; 2935 temp->td = td; 2936 2937 /* prepare for next TD */ 2938 temp->td_next = td->obj_next; 2939 2940 /* fill out the Transfer Descriptor */ 2941 td->func = temp->func; 2942 td->pc = temp->pc; 2943 td->offset = temp->offset; 2944 td->remainder = temp->len; 2945 td->tx_bytes = 0; 2946 td->error_any = 0; 2947 td->error_stall = 0; 2948 td->npkt = 0; 2949 td->did_stall = temp->did_stall; 2950 td->short_pkt = temp->short_pkt; 2951 td->alt_next = temp->setup_alt_next; 2952 td->set_toggle = 0; 2953 td->got_short = 0; 2954 td->did_nak = 0; 2955 td->channel = DWC_OTG_MAX_CHANNELS; 2956 td->state = 0; 2957 td->errcnt = 0; 2958 td->tt_scheduled = 0; 2959 td->tt_index = temp->tt_index; 2960 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 2961 } 2962 2963 static void 2964 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2965 { 2966 struct dwc_otg_std_temp temp; 2967 struct dwc_otg_td *td; 2968 struct usb_device *udev; 2969 uint32_t x; 2970 uint8_t need_sync; 2971 uint8_t is_host; 2972 2973 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2974 xfer->address, UE_GET_ADDR(xfer->endpointno), 2975 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2976 2977 temp.max_frame_size = xfer->max_frame_size; 2978 2979 udev = xfer->xroot->udev; 2980 if (udev->parent_hs_hub != NULL && udev->speed != USB_SPEED_HIGH) { 2981 if (udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 2982 temp.tt_index = udev->device_index; 2983 else 2984 temp.tt_index = udev->parent_hs_hub->device_index; 2985 } else { 2986 temp.tt_index = udev->device_index; 2987 } 2988 2989 td = xfer->td_start[0]; 2990 xfer->td_transfer_first = td; 2991 xfer->td_transfer_cache = td; 2992 2993 /* setup temp */ 2994 2995 temp.pc = NULL; 2996 temp.td = NULL; 2997 temp.td_next = xfer->td_start[0]; 2998 temp.offset = 0; 2999 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3000 xfer->flags_int.isochronous_xfr; 3001 temp.did_stall = !xfer->flags_int.control_stall; 3002 3003 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3004 3005 /* check if we should prepend a setup message */ 3006 3007 if (xfer->flags_int.control_xfr) { 3008 if (xfer->flags_int.control_hdr) { 3009 3010 if (is_host) 3011 temp.func = &dwc_otg_host_setup_tx; 3012 else 3013 temp.func = &dwc_otg_setup_rx; 3014 3015 temp.len = xfer->frlengths[0]; 3016 temp.pc = xfer->frbuffers + 0; 3017 temp.short_pkt = temp.len ? 1 : 0; 3018 3019 /* check for last frame */ 3020 if (xfer->nframes == 1) { 3021 /* no STATUS stage yet, SETUP is last */ 3022 if (xfer->flags_int.control_act) 3023 temp.setup_alt_next = 0; 3024 } 3025 3026 dwc_otg_setup_standard_chain_sub(&temp); 3027 } 3028 x = 1; 3029 } else { 3030 x = 0; 3031 } 3032 3033 if (x != xfer->nframes) { 3034 if (xfer->endpointno & UE_DIR_IN) { 3035 if (is_host) { 3036 temp.func = &dwc_otg_host_data_rx; 3037 need_sync = 0; 3038 } else { 3039 temp.func = &dwc_otg_data_tx; 3040 need_sync = 1; 3041 } 3042 } else { 3043 if (is_host) { 3044 temp.func = &dwc_otg_host_data_tx; 3045 need_sync = 0; 3046 } else { 3047 temp.func = &dwc_otg_data_rx; 3048 need_sync = 0; 3049 } 3050 } 3051 3052 /* setup "pc" pointer */ 3053 temp.pc = xfer->frbuffers + x; 3054 } else { 3055 need_sync = 0; 3056 } 3057 while (x != xfer->nframes) { 3058 3059 /* DATA0 / DATA1 message */ 3060 3061 temp.len = xfer->frlengths[x]; 3062 3063 x++; 3064 3065 if (x == xfer->nframes) { 3066 if (xfer->flags_int.control_xfr) { 3067 if (xfer->flags_int.control_act) { 3068 temp.setup_alt_next = 0; 3069 } 3070 } else { 3071 temp.setup_alt_next = 0; 3072 } 3073 } 3074 if (temp.len == 0) { 3075 3076 /* make sure that we send an USB packet */ 3077 3078 temp.short_pkt = 0; 3079 3080 } else { 3081 3082 /* regular data transfer */ 3083 3084 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3085 } 3086 3087 dwc_otg_setup_standard_chain_sub(&temp); 3088 3089 if (xfer->flags_int.isochronous_xfr) { 3090 temp.offset += temp.len; 3091 } else { 3092 /* get next Page Cache pointer */ 3093 temp.pc = xfer->frbuffers + x; 3094 } 3095 } 3096 3097 if (xfer->flags_int.control_xfr) { 3098 3099 /* always setup a valid "pc" pointer for status and sync */ 3100 temp.pc = xfer->frbuffers + 0; 3101 temp.len = 0; 3102 temp.short_pkt = 0; 3103 temp.setup_alt_next = 0; 3104 3105 /* check if we need to sync */ 3106 if (need_sync) { 3107 /* we need a SYNC point after TX */ 3108 temp.func = &dwc_otg_data_tx_sync; 3109 dwc_otg_setup_standard_chain_sub(&temp); 3110 } 3111 3112 /* check if we should append a status stage */ 3113 if (!xfer->flags_int.control_act) { 3114 3115 /* 3116 * Send a DATA1 message and invert the current 3117 * endpoint direction. 3118 */ 3119 if (xfer->endpointno & UE_DIR_IN) { 3120 if (is_host) { 3121 temp.func = &dwc_otg_host_data_tx; 3122 need_sync = 0; 3123 } else { 3124 temp.func = &dwc_otg_data_rx; 3125 need_sync = 0; 3126 } 3127 } else { 3128 if (is_host) { 3129 temp.func = &dwc_otg_host_data_rx; 3130 need_sync = 0; 3131 } else { 3132 temp.func = &dwc_otg_data_tx; 3133 need_sync = 1; 3134 } 3135 } 3136 3137 dwc_otg_setup_standard_chain_sub(&temp); 3138 3139 /* data toggle should be DATA1 */ 3140 td = temp.td; 3141 td->set_toggle = 1; 3142 3143 if (need_sync) { 3144 /* we need a SYNC point after TX */ 3145 temp.func = &dwc_otg_data_tx_sync; 3146 dwc_otg_setup_standard_chain_sub(&temp); 3147 } 3148 } 3149 } else { 3150 /* check if we need to sync */ 3151 if (need_sync) { 3152 3153 temp.pc = xfer->frbuffers + 0; 3154 temp.len = 0; 3155 temp.short_pkt = 0; 3156 temp.setup_alt_next = 0; 3157 3158 /* we need a SYNC point after TX */ 3159 temp.func = &dwc_otg_data_tx_sync; 3160 dwc_otg_setup_standard_chain_sub(&temp); 3161 } 3162 } 3163 3164 /* must have at least one frame! */ 3165 td = temp.td; 3166 xfer->td_transfer_last = td; 3167 3168 if (is_host) { 3169 3170 struct dwc_otg_softc *sc; 3171 uint32_t hcchar; 3172 uint32_t hcsplt; 3173 uint8_t xfer_type; 3174 3175 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3176 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 3177 3178 /* get first again */ 3179 td = xfer->td_transfer_first; 3180 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3181 3182 hcchar = 3183 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3184 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 3185 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3186 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3187 HCCHAR_CHENA; 3188 3189 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3190 hcchar |= HCCHAR_LSPDDEV; 3191 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3192 hcchar |= HCCHAR_EPDIR_IN; 3193 3194 switch (xfer->xroot->udev->speed) { 3195 case USB_SPEED_FULL: 3196 case USB_SPEED_LOW: 3197 /* check if root HUB port is running High Speed */ 3198 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3199 hcsplt = HCSPLT_SPLTENA | 3200 (xfer->xroot->udev->hs_port_no << 3201 HCSPLT_PRTADDR_SHIFT) | 3202 (xfer->xroot->udev->hs_hub_addr << 3203 HCSPLT_HUBADDR_SHIFT); 3204 } else { 3205 hcsplt = 0; 3206 } 3207 if (xfer_type == UE_INTERRUPT) { 3208 uint32_t ival; 3209 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3210 if (ival == 0) 3211 ival = 1; 3212 else if (ival > 127) 3213 ival = 127; 3214 td->tmr_val = sc->sc_tmr_val + ival; 3215 td->tmr_res = ival; 3216 } else if (xfer_type == UE_ISOCHRONOUS) { 3217 td->tmr_val = 0; 3218 td->tmr_res = 1; 3219 } else { 3220 td->tmr_val = 0; 3221 td->tmr_res = 0; 3222 } 3223 break; 3224 case USB_SPEED_HIGH: 3225 hcsplt = 0; 3226 if (xfer_type == UE_ISOCHRONOUS || 3227 xfer_type == UE_INTERRUPT) { 3228 hcchar |= ((xfer->max_packet_count & 3) 3229 << HCCHAR_MC_SHIFT); 3230 } 3231 if (xfer_type == UE_INTERRUPT) { 3232 uint32_t ival; 3233 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3234 if (ival == 0) 3235 ival = 1; 3236 else if (ival > 127) 3237 ival = 127; 3238 td->tmr_val = sc->sc_tmr_val + ival; 3239 td->tmr_res = ival; 3240 } else if (xfer_type == UE_ISOCHRONOUS) { 3241 td->tmr_val = 0; 3242 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3243 } else { 3244 td->tmr_val = 0; 3245 td->tmr_res = 0; 3246 } 3247 break; 3248 default: 3249 hcsplt = 0; 3250 td->tmr_val = 0; 3251 td->tmr_res = 0; 3252 break; 3253 } 3254 3255 /* store configuration in all TD's */ 3256 while (1) { 3257 td->hcchar = hcchar; 3258 td->hcsplt = hcsplt; 3259 3260 if (((void *)td) == xfer->td_transfer_last) 3261 break; 3262 3263 td = td->obj_next; 3264 } 3265 } 3266 } 3267 3268 static void 3269 dwc_otg_timeout(void *arg) 3270 { 3271 struct usb_xfer *xfer = arg; 3272 3273 DPRINTF("xfer=%p\n", xfer); 3274 3275 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3276 3277 /* transfer is transferred */ 3278 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3279 } 3280 3281 static void 3282 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3283 { 3284 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3285 3286 DPRINTFN(9, "\n"); 3287 3288 /* poll one time - will turn on interrupts */ 3289 if (dwc_otg_xfer_do_fifo(xfer)) { 3290 3291 /* put transfer on interrupt queue */ 3292 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3293 3294 /* start timeout, if any */ 3295 if (xfer->timeout != 0) { 3296 usbd_transfer_timeout_ms(xfer, 3297 &dwc_otg_timeout, xfer->timeout); 3298 } 3299 3300 /* enable SOF interrupt, if any */ 3301 dwc_otg_enable_sof_irq(sc); 3302 } 3303 } 3304 3305 static void 3306 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3307 { 3308 DPRINTFN(9, "\n"); 3309 3310 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3311 3312 /* set port bit */ 3313 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3314 3315 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3316 sizeof(sc->sc_hub_idata)); 3317 } 3318 3319 static usb_error_t 3320 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3321 { 3322 struct dwc_otg_td *td; 3323 uint32_t len; 3324 usb_error_t error; 3325 3326 DPRINTFN(9, "\n"); 3327 3328 td = xfer->td_transfer_cache; 3329 3330 do { 3331 len = td->remainder; 3332 3333 /* store last data toggle */ 3334 xfer->endpoint->toggle_next = td->toggle; 3335 3336 if (xfer->aframes != xfer->nframes) { 3337 /* 3338 * Verify the length and subtract 3339 * the remainder from "frlengths[]": 3340 */ 3341 if (len > xfer->frlengths[xfer->aframes]) { 3342 td->error_any = 1; 3343 } else { 3344 xfer->frlengths[xfer->aframes] -= len; 3345 } 3346 } 3347 /* Check for transfer error */ 3348 if (td->error_any) { 3349 /* the transfer is finished */ 3350 error = (td->error_stall ? 3351 USB_ERR_STALLED : USB_ERR_IOERROR); 3352 td = NULL; 3353 break; 3354 } 3355 /* Check for short transfer */ 3356 if (len > 0) { 3357 if (xfer->flags_int.short_frames_ok || 3358 xfer->flags_int.isochronous_xfr) { 3359 /* follow alt next */ 3360 if (td->alt_next) { 3361 td = td->obj_next; 3362 } else { 3363 td = NULL; 3364 } 3365 } else { 3366 /* the transfer is finished */ 3367 td = NULL; 3368 } 3369 error = 0; 3370 break; 3371 } 3372 td = td->obj_next; 3373 3374 /* this USB frame is complete */ 3375 error = 0; 3376 break; 3377 3378 } while (0); 3379 3380 /* update transfer cache */ 3381 3382 xfer->td_transfer_cache = td; 3383 3384 return (error); 3385 } 3386 3387 static void 3388 dwc_otg_standard_done(struct usb_xfer *xfer) 3389 { 3390 usb_error_t err = 0; 3391 3392 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3393 xfer, xfer->endpoint); 3394 3395 /* reset scanner */ 3396 3397 xfer->td_transfer_cache = xfer->td_transfer_first; 3398 3399 if (xfer->flags_int.control_xfr) { 3400 3401 if (xfer->flags_int.control_hdr) { 3402 3403 err = dwc_otg_standard_done_sub(xfer); 3404 } 3405 xfer->aframes = 1; 3406 3407 if (xfer->td_transfer_cache == NULL) { 3408 goto done; 3409 } 3410 } 3411 while (xfer->aframes != xfer->nframes) { 3412 3413 err = dwc_otg_standard_done_sub(xfer); 3414 xfer->aframes++; 3415 3416 if (xfer->td_transfer_cache == NULL) { 3417 goto done; 3418 } 3419 } 3420 3421 if (xfer->flags_int.control_xfr && 3422 !xfer->flags_int.control_act) { 3423 3424 err = dwc_otg_standard_done_sub(xfer); 3425 } 3426 done: 3427 dwc_otg_device_done(xfer, err); 3428 } 3429 3430 /*------------------------------------------------------------------------* 3431 * dwc_otg_device_done 3432 * 3433 * NOTE: this function can be called more than one time on the 3434 * same USB transfer! 3435 *------------------------------------------------------------------------*/ 3436 static void 3437 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3438 { 3439 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3440 xfer, xfer->endpoint, error); 3441 3442 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3443 DPRINTFN(15, "disabled interrupts!\n"); 3444 } else { 3445 struct dwc_otg_td *td; 3446 3447 td = xfer->td_transfer_first; 3448 3449 if (td != NULL) 3450 dwc_otg_host_channel_free(td); 3451 } 3452 /* dequeue transfer and start next transfer */ 3453 usbd_transfer_done(xfer, error); 3454 } 3455 3456 static void 3457 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3458 { 3459 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3460 } 3461 3462 static void 3463 dwc_otg_set_stall(struct usb_device *udev, 3464 struct usb_endpoint *ep, uint8_t *did_stall) 3465 { 3466 struct dwc_otg_softc *sc; 3467 uint32_t temp; 3468 uint32_t reg; 3469 uint8_t ep_no; 3470 3471 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3472 3473 /* check mode */ 3474 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3475 /* not supported */ 3476 return; 3477 } 3478 3479 sc = DWC_OTG_BUS2SC(udev->bus); 3480 3481 /* get endpoint address */ 3482 ep_no = ep->edesc->bEndpointAddress; 3483 3484 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3485 3486 if (ep_no & UE_DIR_IN) { 3487 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3488 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3489 } else { 3490 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3491 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3492 } 3493 3494 /* disable and stall endpoint */ 3495 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3496 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3497 3498 /* clear active OUT ep */ 3499 if (!(ep_no & UE_DIR_IN)) { 3500 3501 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3502 3503 if (sc->sc_last_rx_status != 0 && 3504 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3505 sc->sc_last_rx_status)) { 3506 /* dump data */ 3507 dwc_otg_common_rx_ack(sc); 3508 /* poll interrupt */ 3509 dwc_otg_interrupt_poll(sc); 3510 } 3511 } 3512 } 3513 3514 static void 3515 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 3516 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3517 { 3518 uint32_t reg; 3519 uint32_t temp; 3520 3521 if (ep_type == UE_CONTROL) { 3522 /* clearing stall is not needed */ 3523 return; 3524 } 3525 3526 if (ep_dir) { 3527 reg = DOTG_DIEPCTL(ep_no); 3528 } else { 3529 reg = DOTG_DOEPCTL(ep_no); 3530 sc->sc_active_rx_ep |= (1U << ep_no); 3531 } 3532 3533 /* round up and mask away the multiplier count */ 3534 mps = (mps + 3) & 0x7FC; 3535 3536 if (ep_type == UE_BULK) { 3537 temp = DIEPCTL_EPTYPE_SET( 3538 DIEPCTL_EPTYPE_BULK) | 3539 DIEPCTL_USBACTEP; 3540 } else if (ep_type == UE_INTERRUPT) { 3541 temp = DIEPCTL_EPTYPE_SET( 3542 DIEPCTL_EPTYPE_INTERRUPT) | 3543 DIEPCTL_USBACTEP; 3544 } else { 3545 temp = DIEPCTL_EPTYPE_SET( 3546 DIEPCTL_EPTYPE_ISOC) | 3547 DIEPCTL_USBACTEP; 3548 } 3549 3550 temp |= DIEPCTL_MPS_SET(mps); 3551 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3552 3553 if (ep_dir) 3554 sc->sc_in_ctl[ep_no] = temp; 3555 else 3556 sc->sc_out_ctl[ep_no] = temp; 3557 3558 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3559 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3560 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3561 3562 /* we only reset the transmit FIFO */ 3563 if (ep_dir) { 3564 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3565 GRSTCTL_TXFIFO(ep_no) | 3566 GRSTCTL_TXFFLSH); 3567 3568 DWC_OTG_WRITE_4(sc, 3569 DOTG_DIEPTSIZ(ep_no), 0); 3570 } 3571 3572 /* poll interrupt */ 3573 dwc_otg_interrupt_poll(sc); 3574 } 3575 3576 static void 3577 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3578 { 3579 struct dwc_otg_softc *sc; 3580 struct usb_endpoint_descriptor *ed; 3581 3582 DPRINTFN(5, "endpoint=%p\n", ep); 3583 3584 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3585 3586 /* check mode */ 3587 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3588 /* not supported */ 3589 return; 3590 } 3591 /* get softc */ 3592 sc = DWC_OTG_BUS2SC(udev->bus); 3593 3594 /* get endpoint descriptor */ 3595 ed = ep->edesc; 3596 3597 /* reset endpoint */ 3598 dwc_otg_clear_stall_sub(sc, 3599 UGETW(ed->wMaxPacketSize), 3600 (ed->bEndpointAddress & UE_ADDR), 3601 (ed->bmAttributes & UE_XFERTYPE), 3602 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3603 } 3604 3605 static void 3606 dwc_otg_device_state_change(struct usb_device *udev) 3607 { 3608 struct dwc_otg_softc *sc; 3609 uint8_t x; 3610 3611 /* check mode */ 3612 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3613 /* not supported */ 3614 return; 3615 } 3616 3617 /* get softc */ 3618 sc = DWC_OTG_BUS2SC(udev->bus); 3619 3620 /* deactivate all other endpoint but the control endpoint */ 3621 if (udev->state == USB_STATE_CONFIGURED || 3622 udev->state == USB_STATE_ADDRESSED) { 3623 3624 USB_BUS_LOCK(&sc->sc_bus); 3625 3626 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3627 3628 if (x < sc->sc_dev_in_ep_max) { 3629 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3630 DIEPCTL_EPDIS); 3631 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3632 } 3633 3634 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3635 DOEPCTL_EPDIS); 3636 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3637 } 3638 USB_BUS_UNLOCK(&sc->sc_bus); 3639 } 3640 } 3641 3642 int 3643 dwc_otg_init(struct dwc_otg_softc *sc) 3644 { 3645 uint32_t temp; 3646 3647 DPRINTF("start\n"); 3648 3649 /* set up the bus structure */ 3650 sc->sc_bus.usbrev = USB_REV_2_0; 3651 sc->sc_bus.methods = &dwc_otg_bus_methods; 3652 3653 usb_callout_init_mtx(&sc->sc_timer, 3654 &sc->sc_bus.bus_mtx, 0); 3655 3656 USB_BUS_LOCK(&sc->sc_bus); 3657 3658 /* turn on clocks */ 3659 dwc_otg_clocks_on(sc); 3660 3661 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3662 DPRINTF("Version = 0x%08x\n", temp); 3663 3664 /* disconnect */ 3665 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3666 DCTL_SFTDISCON); 3667 3668 /* wait for host to detect disconnect */ 3669 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3670 3671 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3672 GRSTCTL_CSFTRST); 3673 3674 /* wait a little bit for block to reset */ 3675 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3676 3677 switch (sc->sc_mode) { 3678 case DWC_MODE_DEVICE: 3679 temp = GUSBCFG_FORCEDEVMODE; 3680 break; 3681 case DWC_MODE_HOST: 3682 temp = GUSBCFG_FORCEHOSTMODE; 3683 break; 3684 default: 3685 temp = 0; 3686 break; 3687 } 3688 3689 /* select HSIC or non-HSIC mode */ 3690 if (dwc_otg_use_hsic) { 3691 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3692 GUSBCFG_PHYIF | 3693 GUSBCFG_TRD_TIM_SET(5) | temp); 3694 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3695 0x000000EC); 3696 3697 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3698 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3699 temp & ~GLPMCFG_HSIC_CONN); 3700 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3701 temp | GLPMCFG_HSIC_CONN); 3702 } else { 3703 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3704 GUSBCFG_ULPI_UTMI_SEL | 3705 GUSBCFG_TRD_TIM_SET(5) | temp); 3706 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3707 3708 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3709 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3710 temp & ~GLPMCFG_HSIC_CONN); 3711 } 3712 3713 /* clear global nak */ 3714 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3715 DCTL_CGOUTNAK | 3716 DCTL_CGNPINNAK); 3717 3718 /* disable USB port */ 3719 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3720 3721 /* wait 10ms */ 3722 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3723 3724 /* enable USB port */ 3725 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3726 3727 /* wait 10ms */ 3728 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3729 3730 /* pull up D+ */ 3731 dwc_otg_pull_up(sc); 3732 3733 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3734 3735 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3736 3737 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3738 3739 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3740 3741 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3742 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3743 3744 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3745 3746 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3747 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3748 3749 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3750 3751 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3752 3753 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3754 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3755 sc->sc_host_ch_max); 3756 3757 /* setup FIFO */ 3758 if (dwc_otg_init_fifo(sc, sc->sc_mode)) 3759 return (EINVAL); 3760 3761 /* enable interrupts */ 3762 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3763 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3764 3765 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3766 3767 /* enable all endpoint interrupts */ 3768 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3769 if (temp & GHWCFG2_MPI) { 3770 uint8_t x; 3771 3772 DPRINTF("Multi Process Interrupts\n"); 3773 3774 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3775 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3776 DIEPMSK_XFERCOMPLMSK); 3777 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3778 } 3779 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3780 } else { 3781 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3782 DIEPMSK_XFERCOMPLMSK); 3783 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3784 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3785 } 3786 } 3787 3788 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3789 /* setup clocks */ 3790 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3791 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3792 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3793 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3794 } 3795 3796 /* only enable global IRQ */ 3797 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3798 GAHBCFG_GLBLINTRMSK); 3799 3800 /* turn off clocks */ 3801 dwc_otg_clocks_off(sc); 3802 3803 /* read initial VBUS state */ 3804 3805 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3806 3807 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3808 3809 dwc_otg_vbus_interrupt(sc, 3810 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3811 3812 USB_BUS_UNLOCK(&sc->sc_bus); 3813 3814 /* catch any lost interrupts */ 3815 3816 dwc_otg_do_poll(&sc->sc_bus); 3817 3818 return (0); /* success */ 3819 } 3820 3821 void 3822 dwc_otg_uninit(struct dwc_otg_softc *sc) 3823 { 3824 USB_BUS_LOCK(&sc->sc_bus); 3825 3826 /* stop host timer */ 3827 dwc_otg_timer_stop(sc); 3828 3829 /* set disconnect */ 3830 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3831 DCTL_SFTDISCON); 3832 3833 /* turn off global IRQ */ 3834 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3835 3836 sc->sc_flags.port_enabled = 0; 3837 sc->sc_flags.port_powered = 0; 3838 sc->sc_flags.status_vbus = 0; 3839 sc->sc_flags.status_bus_reset = 0; 3840 sc->sc_flags.status_suspend = 0; 3841 sc->sc_flags.change_suspend = 0; 3842 sc->sc_flags.change_connect = 1; 3843 3844 dwc_otg_pull_down(sc); 3845 dwc_otg_clocks_off(sc); 3846 3847 USB_BUS_UNLOCK(&sc->sc_bus); 3848 3849 usb_callout_drain(&sc->sc_timer); 3850 } 3851 3852 static void 3853 dwc_otg_suspend(struct dwc_otg_softc *sc) 3854 { 3855 return; 3856 } 3857 3858 static void 3859 dwc_otg_resume(struct dwc_otg_softc *sc) 3860 { 3861 return; 3862 } 3863 3864 static void 3865 dwc_otg_do_poll(struct usb_bus *bus) 3866 { 3867 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3868 3869 USB_BUS_LOCK(&sc->sc_bus); 3870 dwc_otg_interrupt_poll(sc); 3871 USB_BUS_UNLOCK(&sc->sc_bus); 3872 } 3873 3874 /*------------------------------------------------------------------------* 3875 * DWC OTG bulk support 3876 * DWC OTG control support 3877 * DWC OTG interrupt support 3878 *------------------------------------------------------------------------*/ 3879 static void 3880 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3881 { 3882 } 3883 3884 static void 3885 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3886 { 3887 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3888 } 3889 3890 static void 3891 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3892 { 3893 } 3894 3895 static void 3896 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3897 { 3898 /* setup TDs */ 3899 dwc_otg_setup_standard_chain(xfer); 3900 dwc_otg_start_standard_chain(xfer); 3901 } 3902 3903 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3904 { 3905 .open = dwc_otg_device_non_isoc_open, 3906 .close = dwc_otg_device_non_isoc_close, 3907 .enter = dwc_otg_device_non_isoc_enter, 3908 .start = dwc_otg_device_non_isoc_start, 3909 }; 3910 3911 /*------------------------------------------------------------------------* 3912 * DWC OTG full speed isochronous support 3913 *------------------------------------------------------------------------*/ 3914 static void 3915 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3916 { 3917 } 3918 3919 static void 3920 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3921 { 3922 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3923 } 3924 3925 static void 3926 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3927 { 3928 } 3929 3930 static void 3931 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3932 { 3933 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3934 uint32_t temp; 3935 uint32_t msframes; 3936 uint32_t framenum; 3937 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3938 3939 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3940 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3941 3942 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3943 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3944 3945 /* get the current frame index */ 3946 framenum = (temp & HFNUM_FRNUM_MASK); 3947 } else { 3948 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3949 3950 /* get the current frame index */ 3951 framenum = DSTS_SOFFN_GET(temp); 3952 } 3953 3954 if (xfer->xroot->udev->parent_hs_hub != NULL) 3955 framenum /= 8; 3956 3957 framenum &= DWC_OTG_FRAME_MASK; 3958 3959 /* 3960 * Compute number of milliseconds worth of data traffic for 3961 * this USB transfer: 3962 */ 3963 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 3964 msframes = ((xfer->nframes << shift) + 7) / 8; 3965 else 3966 msframes = xfer->nframes; 3967 3968 /* 3969 * check if the frame index is within the window where the frames 3970 * will be inserted 3971 */ 3972 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3973 3974 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 3975 /* 3976 * If there is data underflow or the pipe queue is 3977 * empty we schedule the transfer a few frames ahead 3978 * of the current frame position. Else two isochronous 3979 * transfers might overlap. 3980 */ 3981 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 3982 xfer->endpoint->is_synced = 1; 3983 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3984 } 3985 /* 3986 * compute how many milliseconds the insertion is ahead of the 3987 * current frame position: 3988 */ 3989 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 3990 3991 /* 3992 * pre-compute when the isochronous transfer will be finished: 3993 */ 3994 xfer->isoc_time_complete = 3995 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 3996 3997 /* setup TDs */ 3998 dwc_otg_setup_standard_chain(xfer); 3999 4000 /* compute frame number for next insertion */ 4001 xfer->endpoint->isoc_next += msframes; 4002 4003 /* start TD chain */ 4004 dwc_otg_start_standard_chain(xfer); 4005 } 4006 4007 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4008 { 4009 .open = dwc_otg_device_isoc_open, 4010 .close = dwc_otg_device_isoc_close, 4011 .enter = dwc_otg_device_isoc_enter, 4012 .start = dwc_otg_device_isoc_start, 4013 }; 4014 4015 /*------------------------------------------------------------------------* 4016 * DWC OTG root control support 4017 *------------------------------------------------------------------------* 4018 * Simulate a hardware HUB by handling all the necessary requests. 4019 *------------------------------------------------------------------------*/ 4020 4021 static const struct usb_device_descriptor dwc_otg_devd = { 4022 .bLength = sizeof(struct usb_device_descriptor), 4023 .bDescriptorType = UDESC_DEVICE, 4024 .bcdUSB = {0x00, 0x02}, 4025 .bDeviceClass = UDCLASS_HUB, 4026 .bDeviceSubClass = UDSUBCLASS_HUB, 4027 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4028 .bMaxPacketSize = 64, 4029 .bcdDevice = {0x00, 0x01}, 4030 .iManufacturer = 1, 4031 .iProduct = 2, 4032 .bNumConfigurations = 1, 4033 }; 4034 4035 static const struct dwc_otg_config_desc dwc_otg_confd = { 4036 .confd = { 4037 .bLength = sizeof(struct usb_config_descriptor), 4038 .bDescriptorType = UDESC_CONFIG, 4039 .wTotalLength[0] = sizeof(dwc_otg_confd), 4040 .bNumInterface = 1, 4041 .bConfigurationValue = 1, 4042 .iConfiguration = 0, 4043 .bmAttributes = UC_SELF_POWERED, 4044 .bMaxPower = 0, 4045 }, 4046 .ifcd = { 4047 .bLength = sizeof(struct usb_interface_descriptor), 4048 .bDescriptorType = UDESC_INTERFACE, 4049 .bNumEndpoints = 1, 4050 .bInterfaceClass = UICLASS_HUB, 4051 .bInterfaceSubClass = UISUBCLASS_HUB, 4052 .bInterfaceProtocol = 0, 4053 }, 4054 .endpd = { 4055 .bLength = sizeof(struct usb_endpoint_descriptor), 4056 .bDescriptorType = UDESC_ENDPOINT, 4057 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4058 .bmAttributes = UE_INTERRUPT, 4059 .wMaxPacketSize[0] = 8, 4060 .bInterval = 255, 4061 }, 4062 }; 4063 4064 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4065 4066 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4067 .bDescLength = sizeof(dwc_otg_hubd), 4068 .bDescriptorType = UDESC_HUB, 4069 .bNbrPorts = 1, 4070 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4071 .bPwrOn2PwrGood = 50, 4072 .bHubContrCurrent = 0, 4073 .DeviceRemovable = {0}, /* port is removable */ 4074 }; 4075 4076 #define STRING_VENDOR \ 4077 "D\0W\0C\0O\0T\0G" 4078 4079 #define STRING_PRODUCT \ 4080 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4081 4082 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4083 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4084 4085 static usb_error_t 4086 dwc_otg_roothub_exec(struct usb_device *udev, 4087 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4088 { 4089 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4090 const void *ptr; 4091 uint16_t len; 4092 uint16_t value; 4093 uint16_t index; 4094 usb_error_t err; 4095 4096 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4097 4098 /* buffer reset */ 4099 ptr = (const void *)&sc->sc_hub_temp; 4100 len = 0; 4101 err = 0; 4102 4103 value = UGETW(req->wValue); 4104 index = UGETW(req->wIndex); 4105 4106 /* demultiplex the control request */ 4107 4108 switch (req->bmRequestType) { 4109 case UT_READ_DEVICE: 4110 switch (req->bRequest) { 4111 case UR_GET_DESCRIPTOR: 4112 goto tr_handle_get_descriptor; 4113 case UR_GET_CONFIG: 4114 goto tr_handle_get_config; 4115 case UR_GET_STATUS: 4116 goto tr_handle_get_status; 4117 default: 4118 goto tr_stalled; 4119 } 4120 break; 4121 4122 case UT_WRITE_DEVICE: 4123 switch (req->bRequest) { 4124 case UR_SET_ADDRESS: 4125 goto tr_handle_set_address; 4126 case UR_SET_CONFIG: 4127 goto tr_handle_set_config; 4128 case UR_CLEAR_FEATURE: 4129 goto tr_valid; /* nop */ 4130 case UR_SET_DESCRIPTOR: 4131 goto tr_valid; /* nop */ 4132 case UR_SET_FEATURE: 4133 default: 4134 goto tr_stalled; 4135 } 4136 break; 4137 4138 case UT_WRITE_ENDPOINT: 4139 switch (req->bRequest) { 4140 case UR_CLEAR_FEATURE: 4141 switch (UGETW(req->wValue)) { 4142 case UF_ENDPOINT_HALT: 4143 goto tr_handle_clear_halt; 4144 case UF_DEVICE_REMOTE_WAKEUP: 4145 goto tr_handle_clear_wakeup; 4146 default: 4147 goto tr_stalled; 4148 } 4149 break; 4150 case UR_SET_FEATURE: 4151 switch (UGETW(req->wValue)) { 4152 case UF_ENDPOINT_HALT: 4153 goto tr_handle_set_halt; 4154 case UF_DEVICE_REMOTE_WAKEUP: 4155 goto tr_handle_set_wakeup; 4156 default: 4157 goto tr_stalled; 4158 } 4159 break; 4160 case UR_SYNCH_FRAME: 4161 goto tr_valid; /* nop */ 4162 default: 4163 goto tr_stalled; 4164 } 4165 break; 4166 4167 case UT_READ_ENDPOINT: 4168 switch (req->bRequest) { 4169 case UR_GET_STATUS: 4170 goto tr_handle_get_ep_status; 4171 default: 4172 goto tr_stalled; 4173 } 4174 break; 4175 4176 case UT_WRITE_INTERFACE: 4177 switch (req->bRequest) { 4178 case UR_SET_INTERFACE: 4179 goto tr_handle_set_interface; 4180 case UR_CLEAR_FEATURE: 4181 goto tr_valid; /* nop */ 4182 case UR_SET_FEATURE: 4183 default: 4184 goto tr_stalled; 4185 } 4186 break; 4187 4188 case UT_READ_INTERFACE: 4189 switch (req->bRequest) { 4190 case UR_GET_INTERFACE: 4191 goto tr_handle_get_interface; 4192 case UR_GET_STATUS: 4193 goto tr_handle_get_iface_status; 4194 default: 4195 goto tr_stalled; 4196 } 4197 break; 4198 4199 case UT_WRITE_CLASS_INTERFACE: 4200 case UT_WRITE_VENDOR_INTERFACE: 4201 /* XXX forward */ 4202 break; 4203 4204 case UT_READ_CLASS_INTERFACE: 4205 case UT_READ_VENDOR_INTERFACE: 4206 /* XXX forward */ 4207 break; 4208 4209 case UT_WRITE_CLASS_DEVICE: 4210 switch (req->bRequest) { 4211 case UR_CLEAR_FEATURE: 4212 goto tr_valid; 4213 case UR_SET_DESCRIPTOR: 4214 case UR_SET_FEATURE: 4215 break; 4216 default: 4217 goto tr_stalled; 4218 } 4219 break; 4220 4221 case UT_WRITE_CLASS_OTHER: 4222 switch (req->bRequest) { 4223 case UR_CLEAR_FEATURE: 4224 goto tr_handle_clear_port_feature; 4225 case UR_SET_FEATURE: 4226 goto tr_handle_set_port_feature; 4227 case UR_CLEAR_TT_BUFFER: 4228 case UR_RESET_TT: 4229 case UR_STOP_TT: 4230 goto tr_valid; 4231 4232 default: 4233 goto tr_stalled; 4234 } 4235 break; 4236 4237 case UT_READ_CLASS_OTHER: 4238 switch (req->bRequest) { 4239 case UR_GET_TT_STATE: 4240 goto tr_handle_get_tt_state; 4241 case UR_GET_STATUS: 4242 goto tr_handle_get_port_status; 4243 default: 4244 goto tr_stalled; 4245 } 4246 break; 4247 4248 case UT_READ_CLASS_DEVICE: 4249 switch (req->bRequest) { 4250 case UR_GET_DESCRIPTOR: 4251 goto tr_handle_get_class_descriptor; 4252 case UR_GET_STATUS: 4253 goto tr_handle_get_class_status; 4254 4255 default: 4256 goto tr_stalled; 4257 } 4258 break; 4259 default: 4260 goto tr_stalled; 4261 } 4262 goto tr_valid; 4263 4264 tr_handle_get_descriptor: 4265 switch (value >> 8) { 4266 case UDESC_DEVICE: 4267 if (value & 0xff) { 4268 goto tr_stalled; 4269 } 4270 len = sizeof(dwc_otg_devd); 4271 ptr = (const void *)&dwc_otg_devd; 4272 goto tr_valid; 4273 case UDESC_CONFIG: 4274 if (value & 0xff) { 4275 goto tr_stalled; 4276 } 4277 len = sizeof(dwc_otg_confd); 4278 ptr = (const void *)&dwc_otg_confd; 4279 goto tr_valid; 4280 case UDESC_STRING: 4281 switch (value & 0xff) { 4282 case 0: /* Language table */ 4283 len = sizeof(usb_string_lang_en); 4284 ptr = (const void *)&usb_string_lang_en; 4285 goto tr_valid; 4286 4287 case 1: /* Vendor */ 4288 len = sizeof(dwc_otg_vendor); 4289 ptr = (const void *)&dwc_otg_vendor; 4290 goto tr_valid; 4291 4292 case 2: /* Product */ 4293 len = sizeof(dwc_otg_product); 4294 ptr = (const void *)&dwc_otg_product; 4295 goto tr_valid; 4296 default: 4297 break; 4298 } 4299 break; 4300 default: 4301 goto tr_stalled; 4302 } 4303 goto tr_stalled; 4304 4305 tr_handle_get_config: 4306 len = 1; 4307 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4308 goto tr_valid; 4309 4310 tr_handle_get_status: 4311 len = 2; 4312 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4313 goto tr_valid; 4314 4315 tr_handle_set_address: 4316 if (value & 0xFF00) { 4317 goto tr_stalled; 4318 } 4319 sc->sc_rt_addr = value; 4320 goto tr_valid; 4321 4322 tr_handle_set_config: 4323 if (value >= 2) { 4324 goto tr_stalled; 4325 } 4326 sc->sc_conf = value; 4327 goto tr_valid; 4328 4329 tr_handle_get_interface: 4330 len = 1; 4331 sc->sc_hub_temp.wValue[0] = 0; 4332 goto tr_valid; 4333 4334 tr_handle_get_tt_state: 4335 tr_handle_get_class_status: 4336 tr_handle_get_iface_status: 4337 tr_handle_get_ep_status: 4338 len = 2; 4339 USETW(sc->sc_hub_temp.wValue, 0); 4340 goto tr_valid; 4341 4342 tr_handle_set_halt: 4343 tr_handle_set_interface: 4344 tr_handle_set_wakeup: 4345 tr_handle_clear_wakeup: 4346 tr_handle_clear_halt: 4347 goto tr_valid; 4348 4349 tr_handle_clear_port_feature: 4350 if (index != 1) 4351 goto tr_stalled; 4352 4353 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4354 4355 switch (value) { 4356 case UHF_PORT_SUSPEND: 4357 dwc_otg_wakeup_peer(sc); 4358 break; 4359 4360 case UHF_PORT_ENABLE: 4361 if (sc->sc_flags.status_device_mode == 0) { 4362 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4363 sc->sc_hprt_val | HPRT_PRTENA); 4364 } 4365 sc->sc_flags.port_enabled = 0; 4366 break; 4367 4368 case UHF_C_PORT_RESET: 4369 sc->sc_flags.change_reset = 0; 4370 break; 4371 4372 case UHF_C_PORT_ENABLE: 4373 sc->sc_flags.change_enabled = 0; 4374 break; 4375 4376 case UHF_C_PORT_OVER_CURRENT: 4377 sc->sc_flags.change_over_current = 0; 4378 break; 4379 4380 case UHF_PORT_TEST: 4381 case UHF_PORT_INDICATOR: 4382 /* nops */ 4383 break; 4384 4385 case UHF_PORT_POWER: 4386 sc->sc_flags.port_powered = 0; 4387 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4388 sc->sc_hprt_val = 0; 4389 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4390 } 4391 dwc_otg_pull_down(sc); 4392 dwc_otg_clocks_off(sc); 4393 break; 4394 4395 case UHF_C_PORT_CONNECTION: 4396 /* clear connect change flag */ 4397 sc->sc_flags.change_connect = 0; 4398 break; 4399 4400 case UHF_C_PORT_SUSPEND: 4401 sc->sc_flags.change_suspend = 0; 4402 break; 4403 4404 default: 4405 err = USB_ERR_IOERROR; 4406 goto done; 4407 } 4408 goto tr_valid; 4409 4410 tr_handle_set_port_feature: 4411 if (index != 1) { 4412 goto tr_stalled; 4413 } 4414 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4415 4416 switch (value) { 4417 case UHF_PORT_ENABLE: 4418 break; 4419 4420 case UHF_PORT_SUSPEND: 4421 if (sc->sc_flags.status_device_mode == 0) { 4422 /* set suspend BIT */ 4423 sc->sc_hprt_val |= HPRT_PRTSUSP; 4424 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4425 4426 /* generate HUB suspend event */ 4427 dwc_otg_suspend_irq(sc); 4428 } 4429 break; 4430 4431 case UHF_PORT_RESET: 4432 if (sc->sc_flags.status_device_mode == 0) { 4433 4434 DPRINTF("PORT RESET\n"); 4435 4436 /* enable PORT reset */ 4437 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4438 4439 /* Wait 62.5ms for reset to complete */ 4440 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4441 4442 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4443 4444 /* Wait 62.5ms for reset to complete */ 4445 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4446 4447 /* reset FIFOs */ 4448 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4449 4450 sc->sc_flags.change_reset = 1; 4451 } else { 4452 err = USB_ERR_IOERROR; 4453 } 4454 break; 4455 4456 case UHF_PORT_TEST: 4457 case UHF_PORT_INDICATOR: 4458 /* nops */ 4459 break; 4460 case UHF_PORT_POWER: 4461 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4462 sc->sc_hprt_val |= HPRT_PRTPWR; 4463 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4464 } 4465 sc->sc_flags.port_powered = 1; 4466 break; 4467 default: 4468 err = USB_ERR_IOERROR; 4469 goto done; 4470 } 4471 goto tr_valid; 4472 4473 tr_handle_get_port_status: 4474 4475 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4476 4477 if (index != 1) 4478 goto tr_stalled; 4479 4480 if (sc->sc_flags.status_vbus) 4481 dwc_otg_clocks_on(sc); 4482 else 4483 dwc_otg_clocks_off(sc); 4484 4485 /* Select Device Side Mode */ 4486 4487 if (sc->sc_flags.status_device_mode) { 4488 value = UPS_PORT_MODE_DEVICE; 4489 dwc_otg_timer_stop(sc); 4490 } else { 4491 value = 0; 4492 dwc_otg_timer_start(sc); 4493 } 4494 4495 if (sc->sc_flags.status_high_speed) 4496 value |= UPS_HIGH_SPEED; 4497 else if (sc->sc_flags.status_low_speed) 4498 value |= UPS_LOW_SPEED; 4499 4500 if (sc->sc_flags.port_powered) 4501 value |= UPS_PORT_POWER; 4502 4503 if (sc->sc_flags.port_enabled) 4504 value |= UPS_PORT_ENABLED; 4505 4506 if (sc->sc_flags.port_over_current) 4507 value |= UPS_OVERCURRENT_INDICATOR; 4508 4509 if (sc->sc_flags.status_vbus && 4510 sc->sc_flags.status_bus_reset) 4511 value |= UPS_CURRENT_CONNECT_STATUS; 4512 4513 if (sc->sc_flags.status_suspend) 4514 value |= UPS_SUSPEND; 4515 4516 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4517 4518 value = 0; 4519 4520 if (sc->sc_flags.change_connect) 4521 value |= UPS_C_CONNECT_STATUS; 4522 if (sc->sc_flags.change_suspend) 4523 value |= UPS_C_SUSPEND; 4524 if (sc->sc_flags.change_reset) 4525 value |= UPS_C_PORT_RESET; 4526 if (sc->sc_flags.change_over_current) 4527 value |= UPS_C_OVERCURRENT_INDICATOR; 4528 4529 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4530 len = sizeof(sc->sc_hub_temp.ps); 4531 goto tr_valid; 4532 4533 tr_handle_get_class_descriptor: 4534 if (value & 0xFF) { 4535 goto tr_stalled; 4536 } 4537 ptr = (const void *)&dwc_otg_hubd; 4538 len = sizeof(dwc_otg_hubd); 4539 goto tr_valid; 4540 4541 tr_stalled: 4542 err = USB_ERR_STALLED; 4543 tr_valid: 4544 done: 4545 *plength = len; 4546 *pptr = ptr; 4547 return (err); 4548 } 4549 4550 static void 4551 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4552 { 4553 struct usb_xfer *xfer; 4554 void *last_obj; 4555 uint32_t ntd; 4556 uint32_t n; 4557 uint8_t ep_no; 4558 4559 xfer = parm->curr_xfer; 4560 4561 /* 4562 * NOTE: This driver does not use any of the parameters that 4563 * are computed from the following values. Just set some 4564 * reasonable dummies: 4565 */ 4566 parm->hc_max_packet_size = 0x500; 4567 parm->hc_max_packet_count = 3; 4568 parm->hc_max_frame_size = 3 * 0x500; 4569 4570 usbd_transfer_setup_sub(parm); 4571 4572 /* 4573 * compute maximum number of TDs 4574 */ 4575 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 4576 4577 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4578 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4579 } else { 4580 4581 ntd = xfer->nframes + 1 /* SYNC */ ; 4582 } 4583 4584 /* 4585 * check if "usbd_transfer_setup_sub" set an error 4586 */ 4587 if (parm->err) 4588 return; 4589 4590 /* 4591 * allocate transfer descriptors 4592 */ 4593 last_obj = NULL; 4594 4595 ep_no = xfer->endpointno & UE_ADDR; 4596 4597 /* 4598 * Check for a valid endpoint profile in USB device mode: 4599 */ 4600 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4601 const struct usb_hw_ep_profile *pf; 4602 4603 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4604 4605 if (pf == NULL) { 4606 /* should not happen */ 4607 parm->err = USB_ERR_INVAL; 4608 return; 4609 } 4610 } 4611 4612 /* align data */ 4613 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4614 4615 for (n = 0; n != ntd; n++) { 4616 4617 struct dwc_otg_td *td; 4618 4619 if (parm->buf) { 4620 4621 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4622 4623 /* init TD */ 4624 td->max_packet_size = xfer->max_packet_size; 4625 td->max_packet_count = xfer->max_packet_count; 4626 td->ep_no = ep_no; 4627 td->obj_next = last_obj; 4628 4629 last_obj = td; 4630 } 4631 parm->size[0] += sizeof(*td); 4632 } 4633 4634 xfer->td_start[0] = last_obj; 4635 } 4636 4637 static void 4638 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4639 { 4640 return; 4641 } 4642 4643 static void 4644 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4645 struct usb_endpoint *ep) 4646 { 4647 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4648 4649 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4650 ep, udev->address, 4651 edesc->bEndpointAddress, udev->flags.usb_mode, 4652 sc->sc_rt_addr, udev->device_index); 4653 4654 if (udev->device_index != sc->sc_rt_addr) { 4655 4656 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4657 if (udev->speed != USB_SPEED_FULL && 4658 udev->speed != USB_SPEED_HIGH) { 4659 /* not supported */ 4660 return; 4661 } 4662 } 4663 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4664 ep->methods = &dwc_otg_device_isoc_methods; 4665 else 4666 ep->methods = &dwc_otg_device_non_isoc_methods; 4667 } 4668 } 4669 4670 static void 4671 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4672 { 4673 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4674 4675 switch (state) { 4676 case USB_HW_POWER_SUSPEND: 4677 dwc_otg_suspend(sc); 4678 break; 4679 case USB_HW_POWER_SHUTDOWN: 4680 dwc_otg_uninit(sc); 4681 break; 4682 case USB_HW_POWER_RESUME: 4683 dwc_otg_resume(sc); 4684 break; 4685 default: 4686 break; 4687 } 4688 } 4689 4690 static void 4691 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4692 { 4693 /* DMA delay - wait until any use of memory is finished */ 4694 *pus = (2125); /* microseconds */ 4695 } 4696 4697 static void 4698 dwc_otg_device_resume(struct usb_device *udev) 4699 { 4700 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4701 struct usb_xfer *xfer; 4702 struct dwc_otg_td *td; 4703 4704 DPRINTF("\n"); 4705 4706 /* Enable relevant Host channels before resuming */ 4707 4708 USB_BUS_LOCK(udev->bus); 4709 4710 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4711 4712 if (xfer->xroot->udev == udev) { 4713 4714 td = xfer->td_transfer_cache; 4715 if (td != NULL && 4716 td->channel < DWC_OTG_MAX_CHANNELS) 4717 sc->sc_chan_state[td->channel].suspended = 0; 4718 } 4719 } 4720 4721 USB_BUS_UNLOCK(udev->bus); 4722 4723 /* poll all transfers again to restart resumed ones */ 4724 dwc_otg_do_poll(udev->bus); 4725 } 4726 4727 static void 4728 dwc_otg_device_suspend(struct usb_device *udev) 4729 { 4730 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4731 struct usb_xfer *xfer; 4732 struct dwc_otg_td *td; 4733 4734 DPRINTF("\n"); 4735 4736 /* Disable relevant Host channels before going to suspend */ 4737 4738 USB_BUS_LOCK(udev->bus); 4739 4740 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4741 4742 if (xfer->xroot->udev == udev) { 4743 4744 td = xfer->td_transfer_cache; 4745 if (td != NULL && 4746 td->channel < DWC_OTG_MAX_CHANNELS) 4747 sc->sc_chan_state[td->channel].suspended = 1; 4748 } 4749 } 4750 4751 USB_BUS_UNLOCK(udev->bus); 4752 } 4753 4754 static const struct usb_bus_methods dwc_otg_bus_methods = 4755 { 4756 .endpoint_init = &dwc_otg_ep_init, 4757 .xfer_setup = &dwc_otg_xfer_setup, 4758 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4759 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4760 .xfer_stall = &dwc_otg_xfer_stall, 4761 .set_stall = &dwc_otg_set_stall, 4762 .clear_stall = &dwc_otg_clear_stall, 4763 .roothub_exec = &dwc_otg_roothub_exec, 4764 .xfer_poll = &dwc_otg_do_poll, 4765 .device_state_change = &dwc_otg_device_state_change, 4766 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4767 .get_dma_delay = &dwc_otg_get_dma_delay, 4768 .device_resume = &dwc_otg_device_resume, 4769 .device_suspend = &dwc_otg_device_suspend, 4770 }; 4771