1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the DesignWare series USB 2.0 OTG 29 * Controller. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 #include <dev/usb/controller/dwc_otgreg.h> 85 86 #define DWC_OTG_BUS2SC(bus) \ 87 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 89 90 #define DWC_OTG_PC2SC(pc) \ 91 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 92 93 #define DWC_OTG_MSK_GINT_ENABLED \ 94 (GINTSTS_ENUMDONE | \ 95 GINTSTS_USBRST | \ 96 GINTSTS_USBSUSP | \ 97 GINTSTS_IEPINT | \ 98 GINTSTS_RXFLVL | \ 99 GINTSTS_SESSREQINT | \ 100 GINTMSK_OTGINTMSK | \ 101 GINTMSK_HCHINTMSK | \ 102 GINTSTS_PRTINT) 103 104 static int dwc_otg_use_hsic; 105 106 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 107 108 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 109 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 110 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 111 112 #ifdef USB_DEBUG 113 static int dwc_otg_debug; 114 115 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 116 &dwc_otg_debug, 0, "DWC OTG debug level"); 117 #endif 118 119 #define DWC_OTG_INTR_ENDPT 1 120 121 /* prototypes */ 122 123 struct usb_bus_methods dwc_otg_bus_methods; 124 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 125 struct usb_pipe_methods dwc_otg_device_isoc_methods; 126 127 static dwc_otg_cmd_t dwc_otg_setup_rx; 128 static dwc_otg_cmd_t dwc_otg_data_rx; 129 static dwc_otg_cmd_t dwc_otg_data_tx; 130 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 131 132 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 133 static dwc_otg_cmd_t dwc_otg_host_data_tx; 134 static dwc_otg_cmd_t dwc_otg_host_data_rx; 135 136 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 137 static void dwc_otg_do_poll(struct usb_bus *); 138 static void dwc_otg_standard_done(struct usb_xfer *); 139 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 140 static void dwc_otg_interrupt_poll(struct dwc_otg_softc *sc); 141 142 /* 143 * Here is a configuration that the chip supports. 144 */ 145 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 146 147 [0] = { 148 .max_in_frame_size = 64,/* fixed */ 149 .max_out_frame_size = 64, /* fixed */ 150 .is_simplex = 1, 151 .support_control = 1, 152 } 153 }; 154 155 static void 156 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 157 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 158 { 159 struct dwc_otg_softc *sc; 160 161 sc = DWC_OTG_BUS2SC(udev->bus); 162 163 if (ep_addr < sc->sc_dev_ep_max) 164 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 165 else 166 *ppf = NULL; 167 } 168 169 static int 170 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 171 { 172 struct dwc_otg_profile *pf; 173 uint32_t fifo_size; 174 uint32_t fifo_regs; 175 uint32_t tx_start; 176 uint8_t x; 177 178 fifo_size = sc->sc_fifo_size; 179 180 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 181 182 if (fifo_size >= fifo_regs) 183 fifo_size -= fifo_regs; 184 else 185 fifo_size = 0; 186 187 /* split equally for IN and OUT */ 188 fifo_size /= 2; 189 190 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 191 192 /* align to 4-bytes */ 193 fifo_size &= ~3; 194 195 tx_start = fifo_size; 196 197 if (fifo_size < 0x40) { 198 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 199 USB_BUS_UNLOCK(&sc->sc_bus); 200 return (EINVAL); 201 } 202 203 if (mode == DWC_MODE_HOST) { 204 205 /* reset active endpoints */ 206 sc->sc_active_rx_ep = 0; 207 208 fifo_size /= 2; 209 210 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 211 ((fifo_size / 4) << 16) | 212 (tx_start / 4)); 213 214 tx_start += fifo_size; 215 216 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 217 ((fifo_size / 4) << 16) | 218 (tx_start / 4)); 219 220 for (x = 0; x != sc->sc_host_ch_max; x++) { 221 /* enable interrupts */ 222 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 223 HCINT_STALL | HCINT_BBLERR | 224 HCINT_XACTERR | 225 HCINT_NAK | HCINT_ACK | HCINT_NYET | 226 HCINT_CHHLTD | HCINT_FRMOVRUN | 227 HCINT_DATATGLERR); 228 } 229 230 /* enable host channel interrupts */ 231 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 232 (1U << sc->sc_host_ch_max) - 1U); 233 } 234 235 if (mode == DWC_MODE_DEVICE) { 236 237 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 238 (0x10 << 16) | (tx_start / 4)); 239 fifo_size -= 0x40; 240 tx_start += 0x40; 241 242 /* setup control endpoint profile */ 243 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 244 245 /* reset active endpoints */ 246 sc->sc_active_rx_ep = 1; 247 248 for (x = 1; x != sc->sc_dev_ep_max; x++) { 249 250 pf = sc->sc_hw_ep_profile + x; 251 252 pf->usb.max_out_frame_size = 1024 * 3; 253 pf->usb.is_simplex = 0; /* assume duplex */ 254 pf->usb.support_bulk = 1; 255 pf->usb.support_interrupt = 1; 256 pf->usb.support_isochronous = 1; 257 pf->usb.support_out = 1; 258 259 if (x < sc->sc_dev_in_ep_max) { 260 uint32_t limit; 261 262 limit = (x == 1) ? DWC_OTG_MAX_TXN : 263 (DWC_OTG_MAX_TXN / 2); 264 265 if (fifo_size >= limit) { 266 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 267 ((limit / 4) << 16) | 268 (tx_start / 4)); 269 tx_start += limit; 270 fifo_size -= limit; 271 pf->usb.max_in_frame_size = 0x200; 272 pf->usb.support_in = 1; 273 pf->max_buffer = limit; 274 275 } else if (fifo_size >= 0x80) { 276 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 277 ((0x80 / 4) << 16) | (tx_start / 4)); 278 tx_start += 0x80; 279 fifo_size -= 0x80; 280 pf->usb.max_in_frame_size = 0x40; 281 pf->usb.support_in = 1; 282 283 } else { 284 pf->usb.is_simplex = 1; 285 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 286 (0x0 << 16) | (tx_start / 4)); 287 } 288 } else { 289 pf->usb.is_simplex = 1; 290 } 291 292 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 293 pf->usb.max_in_frame_size, 294 pf->usb.max_out_frame_size); 295 } 296 } 297 298 /* reset RX FIFO */ 299 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 300 GRSTCTL_RXFFLSH); 301 302 if (mode != DWC_MODE_OTG) { 303 /* reset all TX FIFOs */ 304 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 305 GRSTCTL_TXFIFO(0x10) | 306 GRSTCTL_TXFFLSH); 307 } else { 308 /* reset active endpoints */ 309 sc->sc_active_rx_ep = 0; 310 } 311 return (0); 312 } 313 314 static void 315 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 316 { 317 if (sc->sc_flags.clocks_off && 318 sc->sc_flags.port_powered) { 319 320 DPRINTFN(5, "\n"); 321 322 /* TODO - platform specific */ 323 324 sc->sc_flags.clocks_off = 0; 325 } 326 } 327 328 static void 329 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 330 { 331 if (!sc->sc_flags.clocks_off) { 332 333 DPRINTFN(5, "\n"); 334 335 /* TODO - platform specific */ 336 337 sc->sc_flags.clocks_off = 1; 338 } 339 } 340 341 static void 342 dwc_otg_pull_up(struct dwc_otg_softc *sc) 343 { 344 uint32_t temp; 345 346 /* pullup D+, if possible */ 347 348 if (!sc->sc_flags.d_pulled_up && 349 sc->sc_flags.port_powered) { 350 sc->sc_flags.d_pulled_up = 1; 351 352 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 353 temp &= ~DCTL_SFTDISCON; 354 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 355 } 356 } 357 358 static void 359 dwc_otg_pull_down(struct dwc_otg_softc *sc) 360 { 361 uint32_t temp; 362 363 /* pulldown D+, if possible */ 364 365 if (sc->sc_flags.d_pulled_up) { 366 sc->sc_flags.d_pulled_up = 0; 367 368 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 369 temp |= DCTL_SFTDISCON; 370 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 371 } 372 } 373 374 static void 375 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 376 { 377 if (sc->sc_irq_mask & GINTSTS_SOF) 378 return; 379 sc->sc_irq_mask |= GINTSTS_SOF; 380 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 381 } 382 383 static void 384 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 385 { 386 if (sc->sc_flags.status_suspend) { 387 /* update status bits */ 388 sc->sc_flags.status_suspend = 0; 389 sc->sc_flags.change_suspend = 1; 390 391 if (sc->sc_flags.status_device_mode) { 392 /* 393 * Disable resume interrupt and enable suspend 394 * interrupt: 395 */ 396 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 397 sc->sc_irq_mask |= GINTSTS_USBSUSP; 398 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 399 } 400 401 /* complete root HUB interrupt endpoint */ 402 dwc_otg_root_intr(sc); 403 } 404 } 405 406 static void 407 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 408 { 409 if (!sc->sc_flags.status_suspend) { 410 /* update status bits */ 411 sc->sc_flags.status_suspend = 1; 412 sc->sc_flags.change_suspend = 1; 413 414 if (sc->sc_flags.status_device_mode) { 415 /* 416 * Disable suspend interrupt and enable resume 417 * interrupt: 418 */ 419 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 420 sc->sc_irq_mask |= GINTSTS_WKUPINT; 421 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 422 } 423 424 /* complete root HUB interrupt endpoint */ 425 dwc_otg_root_intr(sc); 426 } 427 } 428 429 static void 430 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 431 { 432 if (!sc->sc_flags.status_suspend) 433 return; 434 435 DPRINTFN(5, "Remote wakeup\n"); 436 437 if (sc->sc_flags.status_device_mode) { 438 uint32_t temp; 439 440 /* enable remote wakeup signalling */ 441 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 442 temp |= DCTL_RMTWKUPSIG; 443 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 444 445 /* Wait 8ms for remote wakeup to complete. */ 446 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 447 448 temp &= ~DCTL_RMTWKUPSIG; 449 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 450 } else { 451 /* enable USB port */ 452 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 453 454 /* wait 10ms */ 455 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 456 457 /* resume port */ 458 sc->sc_hprt_val |= HPRT_PRTRES; 459 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 460 461 /* Wait 100ms for resume signalling to complete. */ 462 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 463 464 /* clear suspend and resume */ 465 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 466 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 467 468 /* Wait 4ms */ 469 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 470 } 471 472 /* need to fake resume IRQ */ 473 dwc_otg_resume_irq(sc); 474 } 475 476 static void 477 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 478 { 479 uint32_t temp; 480 481 DPRINTFN(5, "addr=%d\n", addr); 482 483 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 484 temp &= ~DCFG_DEVADDR_SET(0x7F); 485 temp |= DCFG_DEVADDR_SET(addr); 486 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 487 } 488 489 static void 490 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 491 { 492 DPRINTFN(5, "RX status clear\n"); 493 494 /* enable RX FIFO level interrupt */ 495 sc->sc_irq_mask |= GINTSTS_RXFLVL; 496 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 497 498 /* clear cached status */ 499 sc->sc_last_rx_status = 0; 500 } 501 502 static void 503 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 504 { 505 uint32_t hcint; 506 507 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 508 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 509 510 /* clear buffered interrupts */ 511 sc->sc_chan_state[x].hcint = 0; 512 } 513 514 static uint8_t 515 dwc_otg_host_channel_wait(struct dwc_otg_td *td) 516 { 517 struct dwc_otg_softc *sc; 518 uint8_t x; 519 520 x = td->channel; 521 522 DPRINTF("CH=%d\n", x); 523 524 /* get pointer to softc */ 525 sc = DWC_OTG_PC2SC(td->pc); 526 527 if (sc->sc_chan_state[x].wait_sof == 0) { 528 dwc_otg_clear_hcint(sc, x); 529 return (1); /* done */ 530 } 531 532 if (x == 0) 533 return (0); /* wait */ 534 535 /* find new disabled channel */ 536 for (x = 1; x != sc->sc_host_ch_max; x++) { 537 538 if (sc->sc_chan_state[x].allocated) 539 continue; 540 if (sc->sc_chan_state[x].wait_sof != 0) 541 continue; 542 543 sc->sc_chan_state[td->channel].allocated = 0; 544 sc->sc_chan_state[x].allocated = 1; 545 546 if (sc->sc_chan_state[td->channel].suspended) { 547 sc->sc_chan_state[td->channel].suspended = 0; 548 sc->sc_chan_state[x].suspended = 1; 549 } 550 551 /* clear interrupts */ 552 dwc_otg_clear_hcint(sc, x); 553 554 DPRINTF("CH=%d HCCHAR=0x%08x " 555 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 556 557 /* ack any pending messages */ 558 if (sc->sc_last_rx_status != 0 && 559 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == td->channel) { 560 /* get rid of message */ 561 dwc_otg_common_rx_ack(sc); 562 } 563 564 /* move active channel */ 565 sc->sc_active_rx_ep &= ~(1 << td->channel); 566 sc->sc_active_rx_ep |= (1 << x); 567 568 /* set channel */ 569 td->channel = x; 570 571 return (1); /* new channel allocated */ 572 } 573 return (0); /* wait */ 574 } 575 576 static uint8_t 577 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 578 { 579 struct dwc_otg_softc *sc; 580 uint8_t x; 581 uint8_t max_channel; 582 583 if (td->channel < DWC_OTG_MAX_CHANNELS) 584 return (0); /* already allocated */ 585 586 /* get pointer to softc */ 587 sc = DWC_OTG_PC2SC(td->pc); 588 589 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 590 max_channel = 1; 591 x = 0; 592 } else { 593 max_channel = sc->sc_host_ch_max; 594 x = 1; 595 } 596 597 for (; x != max_channel; x++) { 598 599 if (sc->sc_chan_state[x].allocated) 600 continue; 601 if (sc->sc_chan_state[x].wait_sof != 0) 602 continue; 603 604 sc->sc_chan_state[x].allocated = 1; 605 606 /* clear interrupts */ 607 dwc_otg_clear_hcint(sc, x); 608 609 DPRINTF("CH=%d HCCHAR=0x%08x " 610 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 611 612 /* set active channel */ 613 sc->sc_active_rx_ep |= (1 << x); 614 615 /* set channel */ 616 td->channel = x; 617 618 return (0); /* allocated */ 619 } 620 return (1); /* busy */ 621 } 622 623 static void 624 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 625 { 626 uint32_t hcchar; 627 if (sc->sc_chan_state[x].wait_sof != 0) 628 return; 629 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 630 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 631 /* disable channel */ 632 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 633 HCCHAR_CHENA | HCCHAR_CHDIS); 634 /* don't re-use channel until next SOF is transmitted */ 635 sc->sc_chan_state[x].wait_sof = 2; 636 /* enable SOF interrupt */ 637 dwc_otg_enable_sof_irq(sc); 638 } 639 } 640 641 static void 642 dwc_otg_host_channel_free(struct dwc_otg_td *td) 643 { 644 struct dwc_otg_softc *sc; 645 uint8_t x; 646 647 if (td->channel >= DWC_OTG_MAX_CHANNELS) 648 return; /* already freed */ 649 650 /* free channel */ 651 x = td->channel; 652 td->channel = DWC_OTG_MAX_CHANNELS; 653 654 DPRINTF("CH=%d\n", x); 655 656 /* get pointer to softc */ 657 sc = DWC_OTG_PC2SC(td->pc); 658 659 dwc_otg_host_channel_disable(sc, x); 660 661 sc->sc_chan_state[x].allocated = 0; 662 sc->sc_chan_state[x].suspended = 0; 663 664 /* ack any pending messages */ 665 if (sc->sc_last_rx_status != 0 && 666 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 667 dwc_otg_common_rx_ack(sc); 668 } 669 670 /* clear active channel */ 671 sc->sc_active_rx_ep &= ~(1 << x); 672 } 673 674 static uint8_t 675 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 676 { 677 struct usb_device_request req __aligned(4); 678 struct dwc_otg_softc *sc; 679 uint32_t hcint; 680 uint32_t hcchar; 681 682 if (dwc_otg_host_channel_alloc(td)) 683 return (1); /* busy */ 684 685 /* get pointer to softc */ 686 sc = DWC_OTG_PC2SC(td->pc); 687 688 hcint = sc->sc_chan_state[td->channel].hcint; 689 690 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 691 td->channel, td->state, hcint, 692 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 693 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 694 695 if (hcint & (HCINT_RETRY | 696 HCINT_ACK | HCINT_NYET)) { 697 /* give success bits priority over failure bits */ 698 } else if (hcint & HCINT_STALL) { 699 DPRINTF("CH=%d STALL\n", td->channel); 700 td->error_stall = 1; 701 td->error_any = 1; 702 return (0); /* complete */ 703 } else if (hcint & HCINT_ERRORS) { 704 DPRINTF("CH=%d ERROR\n", td->channel); 705 td->errcnt++; 706 if (td->hcsplt != 0 || td->errcnt >= 3) { 707 td->error_any = 1; 708 return (0); /* complete */ 709 } 710 } 711 712 /* channel must be disabled before we can complete the transfer */ 713 714 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 715 HCINT_ACK | HCINT_NYET)) { 716 717 dwc_otg_host_channel_disable(sc, td->channel); 718 719 if (!(hcint & HCINT_ERRORS)) 720 td->errcnt = 0; 721 } 722 723 switch (td->state) { 724 case DWC_CHAN_ST_START: 725 goto send_pkt; 726 727 case DWC_CHAN_ST_WAIT_ANE: 728 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 729 if (!dwc_otg_host_channel_wait(td)) 730 break; 731 td->did_nak = 1; 732 goto send_pkt; 733 } 734 if (hcint & (HCINT_ACK | HCINT_NYET)) { 735 if (!dwc_otg_host_channel_wait(td)) 736 break; 737 td->offset += td->tx_bytes; 738 td->remainder -= td->tx_bytes; 739 td->toggle = 1; 740 return (0); /* complete */ 741 } 742 break; 743 case DWC_CHAN_ST_WAIT_S_ANE: 744 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 745 if (!dwc_otg_host_channel_wait(td)) 746 break; 747 td->did_nak = 1; 748 goto send_pkt; 749 } 750 if (hcint & (HCINT_ACK | HCINT_NYET)) { 751 if (!dwc_otg_host_channel_wait(td)) 752 break; 753 goto send_cpkt; 754 } 755 break; 756 case DWC_CHAN_ST_WAIT_C_ANE: 757 if (hcint & HCINT_NYET) { 758 if (!dwc_otg_host_channel_wait(td)) 759 break; 760 goto send_cpkt; 761 } 762 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 763 if (!dwc_otg_host_channel_wait(td)) 764 break; 765 td->did_nak = 1; 766 goto send_pkt; 767 } 768 if (hcint & HCINT_ACK) { 769 if (!dwc_otg_host_channel_wait(td)) 770 break; 771 td->offset += td->tx_bytes; 772 td->remainder -= td->tx_bytes; 773 td->toggle = 1; 774 return (0); /* complete */ 775 } 776 break; 777 case DWC_CHAN_ST_TX_PKT_SYNC: 778 goto send_pkt_sync; 779 default: 780 break; 781 } 782 return (1); /* busy */ 783 784 send_pkt: 785 if (sizeof(req) != td->remainder) { 786 td->error_any = 1; 787 return (0); /* complete */ 788 } 789 790 send_pkt_sync: 791 if (td->hcsplt != 0) { 792 uint32_t count; 793 794 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 795 /* check for not first microframe */ 796 if (count != 0) { 797 /* enable SOF interrupt */ 798 dwc_otg_enable_sof_irq(sc); 799 /* set state */ 800 td->state = DWC_CHAN_ST_TX_PKT_SYNC; 801 dwc_otg_host_channel_free(td); 802 return (1); /* busy */ 803 } 804 805 td->hcsplt &= ~HCSPLT_COMPSPLT; 806 td->state = DWC_CHAN_ST_WAIT_S_ANE; 807 } else { 808 td->state = DWC_CHAN_ST_WAIT_ANE; 809 } 810 811 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 812 813 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 814 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 815 (1 << HCTSIZ_PKTCNT_SHIFT) | 816 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 817 818 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 819 820 hcchar = td->hcchar; 821 hcchar &= ~HCCHAR_EPDIR_IN; 822 823 /* must enable channel before writing data to FIFO */ 824 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 825 826 /* transfer data into FIFO */ 827 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 828 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 829 830 /* store number of bytes transmitted */ 831 td->tx_bytes = sizeof(req); 832 833 return (1); /* busy */ 834 835 send_cpkt: 836 td->hcsplt |= HCSPLT_COMPSPLT; 837 td->state = DWC_CHAN_ST_WAIT_C_ANE; 838 839 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 840 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 841 842 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 843 844 hcchar = td->hcchar; 845 hcchar &= ~HCCHAR_EPDIR_IN; 846 847 /* must enable channel before writing data to FIFO */ 848 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 849 850 return (1); /* busy */ 851 } 852 853 static uint8_t 854 dwc_otg_setup_rx(struct dwc_otg_td *td) 855 { 856 struct dwc_otg_softc *sc; 857 struct usb_device_request req __aligned(4); 858 uint32_t temp; 859 uint16_t count; 860 861 /* get pointer to softc */ 862 sc = DWC_OTG_PC2SC(td->pc); 863 864 /* check endpoint status */ 865 866 if (sc->sc_last_rx_status == 0) 867 goto not_complete; 868 869 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 870 goto not_complete; 871 872 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 873 GRXSTSRD_DPID_DATA0) { 874 /* release FIFO */ 875 dwc_otg_common_rx_ack(sc); 876 goto not_complete; 877 } 878 879 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 880 GRXSTSRD_STP_DATA) { 881 /* release FIFO */ 882 dwc_otg_common_rx_ack(sc); 883 goto not_complete; 884 } 885 886 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 887 888 /* clear did stall */ 889 td->did_stall = 0; 890 891 /* get the packet byte count */ 892 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 893 894 /* verify data length */ 895 if (count != td->remainder) { 896 DPRINTFN(0, "Invalid SETUP packet " 897 "length, %d bytes\n", count); 898 /* release FIFO */ 899 dwc_otg_common_rx_ack(sc); 900 goto not_complete; 901 } 902 if (count != sizeof(req)) { 903 DPRINTFN(0, "Unsupported SETUP packet " 904 "length, %d bytes\n", count); 905 /* release FIFO */ 906 dwc_otg_common_rx_ack(sc); 907 goto not_complete; 908 } 909 910 /* copy in control request */ 911 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 912 913 /* copy data into real buffer */ 914 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 915 916 td->offset = sizeof(req); 917 td->remainder = 0; 918 919 /* sneak peek the set address */ 920 if ((req.bmRequestType == UT_WRITE_DEVICE) && 921 (req.bRequest == UR_SET_ADDRESS)) { 922 /* must write address before ZLP */ 923 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 924 } 925 926 /* don't send any data by default */ 927 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 928 DXEPTSIZ_SET_NPKT(0) | 929 DXEPTSIZ_SET_NBYTES(0)); 930 931 temp = sc->sc_in_ctl[0]; 932 933 /* enable IN endpoint */ 934 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 935 temp | DIEPCTL_EPENA); 936 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 937 temp | DIEPCTL_SNAK); 938 939 /* reset IN endpoint buffer */ 940 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 941 GRSTCTL_TXFIFO(0) | 942 GRSTCTL_TXFFLSH); 943 944 /* acknowledge RX status */ 945 dwc_otg_common_rx_ack(sc); 946 return (0); /* complete */ 947 948 not_complete: 949 /* abort any ongoing transfer, before enabling again */ 950 951 temp = sc->sc_out_ctl[0]; 952 953 temp |= DOEPCTL_EPENA | 954 DOEPCTL_SNAK; 955 956 /* enable OUT endpoint */ 957 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 958 959 if (!td->did_stall) { 960 td->did_stall = 1; 961 962 DPRINTFN(5, "stalling IN and OUT direction\n"); 963 964 /* set stall after enabling endpoint */ 965 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 966 temp | DOEPCTL_STALL); 967 968 temp = sc->sc_in_ctl[0]; 969 970 /* set stall assuming endpoint is enabled */ 971 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 972 temp | DIEPCTL_STALL); 973 } 974 975 /* setup number of buffers to receive */ 976 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 977 DXEPTSIZ_SET_MULTI(3) | 978 DXEPTSIZ_SET_NPKT(1) | 979 DXEPTSIZ_SET_NBYTES(sizeof(req))); 980 981 return (1); /* not complete */ 982 } 983 984 static uint8_t 985 dwc_otg_host_rate_check(struct dwc_otg_td *td) 986 { 987 struct dwc_otg_softc *sc; 988 uint8_t ep_type; 989 990 /* get pointer to softc */ 991 sc = DWC_OTG_PC2SC(td->pc); 992 993 ep_type = ((td->hcchar & 994 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 995 996 if (sc->sc_chan_state[td->channel].suspended) 997 goto busy; 998 999 if (ep_type == UE_ISOCHRONOUS) { 1000 if (td->tmr_val & 1) 1001 td->hcchar |= HCCHAR_ODDFRM; 1002 else 1003 td->hcchar &= ~HCCHAR_ODDFRM; 1004 td->tmr_val += td->tmr_res; 1005 } else if (ep_type == UE_INTERRUPT) { 1006 uint8_t delta; 1007 1008 delta = sc->sc_tmr_val - td->tmr_val; 1009 if (delta >= 128) 1010 goto busy; 1011 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1012 } else if (td->did_nak != 0) { 1013 goto busy; 1014 } 1015 1016 if (ep_type == UE_ISOCHRONOUS) { 1017 td->toggle = 0; 1018 } else if (td->set_toggle) { 1019 td->set_toggle = 0; 1020 td->toggle = 1; 1021 } 1022 return (0); 1023 busy: 1024 return (1); 1025 } 1026 1027 static uint8_t 1028 dwc_otg_host_data_rx(struct dwc_otg_td *td) 1029 { 1030 struct dwc_otg_softc *sc; 1031 uint32_t hcint; 1032 uint32_t hcchar; 1033 uint32_t count; 1034 uint8_t ep_type; 1035 1036 if (dwc_otg_host_channel_alloc(td)) 1037 return (1); /* busy */ 1038 1039 /* get pointer to softc */ 1040 sc = DWC_OTG_PC2SC(td->pc); 1041 1042 ep_type = ((td->hcchar & 1043 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1044 1045 hcint = sc->sc_chan_state[td->channel].hcint; 1046 1047 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1048 td->channel, td->state, hcint, 1049 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1050 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1051 1052 /* check interrupt bits */ 1053 1054 if (hcint & (HCINT_RETRY | 1055 HCINT_ACK | HCINT_NYET)) { 1056 /* give success bits priority over failure bits */ 1057 } else if (hcint & HCINT_STALL) { 1058 DPRINTF("CH=%d STALL\n", td->channel); 1059 td->error_stall = 1; 1060 td->error_any = 1; 1061 return (0); /* complete */ 1062 } else if (hcint & HCINT_ERRORS) { 1063 DPRINTF("CH=%d ERROR\n", td->channel); 1064 td->errcnt++; 1065 if (td->hcsplt != 0 || td->errcnt >= 3) { 1066 td->error_any = 1; 1067 return (0); /* complete */ 1068 } 1069 } 1070 1071 /* channel must be disabled before we can complete the transfer */ 1072 1073 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1074 HCINT_ACK | HCINT_NYET)) { 1075 1076 dwc_otg_host_channel_disable(sc, td->channel); 1077 1078 if (!(hcint & HCINT_ERRORS)) 1079 td->errcnt = 0; 1080 } 1081 1082 /* check endpoint status */ 1083 if (sc->sc_last_rx_status == 0) 1084 goto check_state; 1085 1086 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 1087 goto check_state; 1088 1089 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1090 case GRXSTSRH_IN_DATA: 1091 1092 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1093 (int)td->state, (int)sc->sc_last_rx_status); 1094 1095 if (hcint & HCINT_SOFTWARE_ONLY) { 1096 /* 1097 * When using SPLIT transactions on interrupt 1098 * endpoints, sometimes data occurs twice. 1099 */ 1100 DPRINTF("Data already received\n"); 1101 break; 1102 } 1103 1104 td->toggle ^= 1; 1105 1106 /* get the packet byte count */ 1107 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1108 1109 /* verify the packet byte count */ 1110 if (count != td->max_packet_size) { 1111 if (count < td->max_packet_size) { 1112 /* we have a short packet */ 1113 td->short_pkt = 1; 1114 td->got_short = 1; 1115 } else { 1116 /* invalid USB packet */ 1117 td->error_any = 1; 1118 1119 /* release FIFO */ 1120 dwc_otg_common_rx_ack(sc); 1121 return (0); /* we are complete */ 1122 } 1123 } 1124 1125 /* verify the packet byte count */ 1126 if (count > td->remainder) { 1127 /* invalid USB packet */ 1128 td->error_any = 1; 1129 1130 /* release FIFO */ 1131 dwc_otg_common_rx_ack(sc); 1132 return (0); /* we are complete */ 1133 } 1134 1135 usbd_copy_in(td->pc, td->offset, 1136 sc->sc_rx_bounce_buffer, count); 1137 1138 td->remainder -= count; 1139 td->offset += count; 1140 hcint |= HCINT_SOFTWARE_ONLY | HCINT_ACK; 1141 sc->sc_chan_state[td->channel].hcint = hcint; 1142 break; 1143 1144 default: 1145 DPRINTF("OTHER\n"); 1146 break; 1147 } 1148 /* release FIFO */ 1149 dwc_otg_common_rx_ack(sc); 1150 1151 check_state: 1152 switch (td->state) { 1153 case DWC_CHAN_ST_START: 1154 if (td->hcsplt != 0) 1155 goto receive_spkt; 1156 else 1157 goto receive_pkt; 1158 1159 case DWC_CHAN_ST_WAIT_ANE: 1160 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1161 if (!dwc_otg_host_channel_wait(td)) 1162 break; 1163 1164 td->did_nak = 1; 1165 if (td->hcsplt != 0) 1166 goto receive_spkt; 1167 else 1168 goto receive_pkt; 1169 } 1170 if (!(hcint & HCINT_SOFTWARE_ONLY)) { 1171 if (hcint & HCINT_NYET) { 1172 if (td->hcsplt != 0) { 1173 if (!dwc_otg_host_channel_wait(td)) 1174 break; 1175 goto receive_pkt; 1176 } 1177 } 1178 break; 1179 } 1180 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1181 if (!dwc_otg_host_channel_wait(td)) 1182 break; 1183 1184 /* check if we are complete */ 1185 if ((td->remainder == 0) || (td->got_short != 0)) { 1186 if (td->short_pkt) 1187 return (0); /* complete */ 1188 1189 /* 1190 * Else need to receive a zero length 1191 * packet. 1192 */ 1193 } 1194 if (td->hcsplt != 0) 1195 goto receive_spkt; 1196 else 1197 goto receive_pkt; 1198 } 1199 break; 1200 1201 case DWC_CHAN_ST_WAIT_S_ANE: 1202 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1203 if (!dwc_otg_host_channel_wait(td)) 1204 break; 1205 1206 td->did_nak = 1; 1207 goto receive_spkt; 1208 } 1209 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1210 if (!dwc_otg_host_channel_wait(td)) 1211 break; 1212 goto receive_pkt; 1213 } 1214 break; 1215 1216 case DWC_CHAN_ST_RX_PKT: 1217 goto receive_pkt; 1218 1219 case DWC_CHAN_ST_RX_SPKT: 1220 goto receive_spkt; 1221 1222 case DWC_CHAN_ST_RX_SPKT_SYNC: 1223 goto receive_spkt_sync; 1224 1225 default: 1226 break; 1227 } 1228 goto busy; 1229 1230 receive_pkt: 1231 if (td->hcsplt != 0) { 1232 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1233 1234 /* check for even microframes */ 1235 if (count == td->curr_frame) { 1236 td->state = DWC_CHAN_ST_RX_PKT; 1237 dwc_otg_host_channel_free(td); 1238 /* enable SOF interrupt */ 1239 dwc_otg_enable_sof_irq(sc); 1240 goto busy; 1241 } else if (count == 0) { 1242 /* check for start split timeout */ 1243 goto receive_spkt; 1244 } 1245 1246 td->curr_frame = count; 1247 td->hcsplt |= HCSPLT_COMPSPLT; 1248 } else if (dwc_otg_host_rate_check(td)) { 1249 td->state = DWC_CHAN_ST_RX_PKT; 1250 dwc_otg_host_channel_free(td); 1251 goto busy; 1252 } 1253 1254 td->state = DWC_CHAN_ST_WAIT_ANE; 1255 1256 /* receive one packet */ 1257 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1258 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1259 (1 << HCTSIZ_PKTCNT_SHIFT) | 1260 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1261 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1262 1263 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1264 1265 hcchar = td->hcchar; 1266 hcchar |= HCCHAR_EPDIR_IN; 1267 1268 /* must enable channel before data can be received */ 1269 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1270 1271 goto busy; 1272 1273 receive_spkt: 1274 if (dwc_otg_host_rate_check(td)) { 1275 td->state = DWC_CHAN_ST_RX_SPKT; 1276 dwc_otg_host_channel_free(td); 1277 goto busy; 1278 } 1279 1280 receive_spkt_sync: 1281 if (ep_type == UE_INTERRUPT || 1282 ep_type == UE_ISOCHRONOUS) { 1283 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1284 td->curr_frame = count; 1285 1286 /* check for non-zero microframe */ 1287 if (count != 0) { 1288 /* enable SOF interrupt */ 1289 dwc_otg_enable_sof_irq(sc); 1290 /* set state */ 1291 td->state = DWC_CHAN_ST_RX_SPKT_SYNC; 1292 dwc_otg_host_channel_free(td); 1293 goto busy; 1294 } 1295 } else { 1296 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1297 td->curr_frame = count; 1298 1299 /* check for two last frames */ 1300 if (count >= 6) { 1301 /* enable SOF interrupt */ 1302 dwc_otg_enable_sof_irq(sc); 1303 /* set state */ 1304 td->state = DWC_CHAN_ST_RX_SPKT_SYNC; 1305 dwc_otg_host_channel_free(td); 1306 goto busy; 1307 } 1308 } 1309 1310 td->hcsplt &= ~HCSPLT_COMPSPLT; 1311 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1312 1313 /* receive one packet */ 1314 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1315 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1316 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1317 1318 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1319 1320 hcchar = td->hcchar; 1321 hcchar |= HCCHAR_EPDIR_IN; 1322 1323 /* must enable channel before data can be received */ 1324 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1325 1326 busy: 1327 return (1); /* busy */ 1328 } 1329 1330 static uint8_t 1331 dwc_otg_data_rx(struct dwc_otg_td *td) 1332 { 1333 struct dwc_otg_softc *sc; 1334 uint32_t temp; 1335 uint16_t count; 1336 uint8_t got_short; 1337 1338 got_short = 0; 1339 1340 /* get pointer to softc */ 1341 sc = DWC_OTG_PC2SC(td->pc); 1342 1343 /* check endpoint status */ 1344 if (sc->sc_last_rx_status == 0) 1345 goto not_complete; 1346 1347 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1348 goto not_complete; 1349 1350 /* check for SETUP packet */ 1351 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1352 GRXSTSRD_STP_DATA) { 1353 if (td->remainder == 0) { 1354 /* 1355 * We are actually complete and have 1356 * received the next SETUP 1357 */ 1358 DPRINTFN(5, "faking complete\n"); 1359 return (0); /* complete */ 1360 } 1361 /* 1362 * USB Host Aborted the transfer. 1363 */ 1364 td->error_any = 1; 1365 return (0); /* complete */ 1366 } 1367 1368 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1369 GRXSTSRD_OUT_DATA) { 1370 /* release FIFO */ 1371 dwc_otg_common_rx_ack(sc); 1372 goto not_complete; 1373 } 1374 1375 /* get the packet byte count */ 1376 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1377 1378 /* verify the packet byte count */ 1379 if (count != td->max_packet_size) { 1380 if (count < td->max_packet_size) { 1381 /* we have a short packet */ 1382 td->short_pkt = 1; 1383 got_short = 1; 1384 } else { 1385 /* invalid USB packet */ 1386 td->error_any = 1; 1387 1388 /* release FIFO */ 1389 dwc_otg_common_rx_ack(sc); 1390 return (0); /* we are complete */ 1391 } 1392 } 1393 /* verify the packet byte count */ 1394 if (count > td->remainder) { 1395 /* invalid USB packet */ 1396 td->error_any = 1; 1397 1398 /* release FIFO */ 1399 dwc_otg_common_rx_ack(sc); 1400 return (0); /* we are complete */ 1401 } 1402 1403 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1404 td->remainder -= count; 1405 td->offset += count; 1406 1407 /* release FIFO */ 1408 dwc_otg_common_rx_ack(sc); 1409 1410 /* check if we are complete */ 1411 if ((td->remainder == 0) || got_short) { 1412 if (td->short_pkt) { 1413 /* we are complete */ 1414 return (0); 1415 } 1416 /* else need to receive a zero length packet */ 1417 } 1418 1419 not_complete: 1420 1421 temp = sc->sc_out_ctl[td->ep_no]; 1422 1423 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1424 1425 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1426 1427 /* enable SETUP and transfer complete interrupt */ 1428 if (td->ep_no == 0) { 1429 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1430 DXEPTSIZ_SET_NPKT(1) | 1431 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1432 } else { 1433 /* allow reception of multiple packets */ 1434 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1435 DXEPTSIZ_SET_MULTI(1) | 1436 DXEPTSIZ_SET_NPKT(4) | 1437 DXEPTSIZ_SET_NBYTES(4 * 1438 ((td->max_packet_size + 3) & ~3))); 1439 } 1440 return (1); /* not complete */ 1441 } 1442 1443 static uint8_t 1444 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1445 { 1446 struct dwc_otg_softc *sc; 1447 uint32_t count; 1448 uint32_t hcint; 1449 uint32_t hcchar; 1450 uint8_t ep_type; 1451 1452 if (dwc_otg_host_channel_alloc(td)) 1453 return (1); /* busy */ 1454 1455 /* get pointer to softc */ 1456 sc = DWC_OTG_PC2SC(td->pc); 1457 1458 ep_type = ((td->hcchar & 1459 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1460 1461 hcint = sc->sc_chan_state[td->channel].hcint; 1462 1463 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1464 td->channel, td->state, hcint, 1465 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1466 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1467 1468 if (hcint & (HCINT_RETRY | 1469 HCINT_ACK | HCINT_NYET)) { 1470 /* give success bits priority over failure bits */ 1471 } else if (hcint & HCINT_STALL) { 1472 DPRINTF("CH=%d STALL\n", td->channel); 1473 td->error_stall = 1; 1474 td->error_any = 1; 1475 return (0); /* complete */ 1476 } else if (hcint & HCINT_ERRORS) { 1477 DPRINTF("CH=%d ERROR\n", td->channel); 1478 td->errcnt++; 1479 if (td->hcsplt != 0 || td->errcnt >= 3) { 1480 td->error_any = 1; 1481 return (0); /* complete */ 1482 } 1483 } 1484 1485 /* channel must be disabled before we can complete the transfer */ 1486 1487 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1488 HCINT_ACK | HCINT_NYET)) { 1489 1490 dwc_otg_host_channel_disable(sc, td->channel); 1491 1492 if (!(hcint & HCINT_ERRORS)) 1493 td->errcnt = 0; 1494 } 1495 1496 switch (td->state) { 1497 case DWC_CHAN_ST_START: 1498 goto send_pkt; 1499 1500 case DWC_CHAN_ST_WAIT_ANE: 1501 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1502 if (!dwc_otg_host_channel_wait(td)) 1503 break; 1504 td->did_nak = 1; 1505 goto send_pkt; 1506 } 1507 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1508 if (!dwc_otg_host_channel_wait(td)) 1509 break; 1510 1511 td->offset += td->tx_bytes; 1512 td->remainder -= td->tx_bytes; 1513 td->toggle ^= 1; 1514 1515 /* check remainder */ 1516 if (td->remainder == 0) { 1517 if (td->short_pkt) 1518 return (0); /* complete */ 1519 1520 /* 1521 * Else we need to transmit a short 1522 * packet: 1523 */ 1524 } 1525 goto send_pkt; 1526 } 1527 break; 1528 case DWC_CHAN_ST_WAIT_S_ANE: 1529 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1530 if (!dwc_otg_host_channel_wait(td)) 1531 break; 1532 td->did_nak = 1; 1533 goto send_pkt; 1534 } 1535 if (hcint & (HCINT_ACK | HCINT_NYET)) { 1536 if (!dwc_otg_host_channel_wait(td)) 1537 break; 1538 goto send_cpkt; 1539 } 1540 break; 1541 case DWC_CHAN_ST_WAIT_C_ANE: 1542 if (hcint & HCINT_NYET) { 1543 if (!dwc_otg_host_channel_wait(td)) 1544 break; 1545 goto send_cpkt; 1546 } 1547 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1548 if (!dwc_otg_host_channel_wait(td)) 1549 break; 1550 td->did_nak = 1; 1551 goto send_pkt; 1552 } 1553 if (hcint & HCINT_ACK) { 1554 if (!dwc_otg_host_channel_wait(td)) 1555 break; 1556 td->offset += td->tx_bytes; 1557 td->remainder -= td->tx_bytes; 1558 td->toggle ^= 1; 1559 1560 /* check remainder */ 1561 if (td->remainder == 0) { 1562 if (td->short_pkt) 1563 return (0); /* complete */ 1564 1565 /* else we need to transmit a short packet */ 1566 } 1567 goto send_pkt; 1568 } 1569 break; 1570 1571 case DWC_CHAN_ST_TX_PKT: 1572 goto send_pkt; 1573 1574 case DWC_CHAN_ST_TX_PKT_SYNC: 1575 goto send_pkt_sync; 1576 1577 case DWC_CHAN_ST_TX_CPKT: 1578 goto send_cpkt; 1579 1580 default: 1581 break; 1582 } 1583 goto busy; 1584 1585 send_pkt: 1586 if (dwc_otg_host_rate_check(td)) { 1587 td->state = DWC_CHAN_ST_TX_PKT; 1588 dwc_otg_host_channel_free(td); 1589 goto busy; 1590 } 1591 1592 send_pkt_sync: 1593 if (td->hcsplt != 0) { 1594 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1595 /* check for first or last microframe */ 1596 if (count == 7 || count == 0) { 1597 /* enable SOF interrupt */ 1598 dwc_otg_enable_sof_irq(sc); 1599 /* set state */ 1600 td->state = DWC_CHAN_ST_TX_PKT_SYNC; 1601 dwc_otg_host_channel_free(td); 1602 goto busy; 1603 } 1604 1605 td->hcsplt &= ~HCSPLT_COMPSPLT; 1606 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1607 } else { 1608 td->state = DWC_CHAN_ST_WAIT_ANE; 1609 } 1610 1611 /* send one packet at a time */ 1612 count = td->max_packet_size; 1613 if (td->remainder < count) { 1614 /* we have a short packet */ 1615 td->short_pkt = 1; 1616 count = td->remainder; 1617 } 1618 1619 /* TODO: HCTSIZ_DOPNG */ 1620 1621 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1622 (count << HCTSIZ_XFERSIZE_SHIFT) | 1623 (1 << HCTSIZ_PKTCNT_SHIFT) | 1624 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1625 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1626 1627 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1628 1629 hcchar = td->hcchar; 1630 hcchar &= ~HCCHAR_EPDIR_IN; 1631 1632 /* must enable before writing data to FIFO */ 1633 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1634 1635 if (count != 0) { 1636 1637 /* clear topmost word before copy */ 1638 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1639 1640 /* copy out data */ 1641 usbd_copy_out(td->pc, td->offset, 1642 sc->sc_tx_bounce_buffer, count); 1643 1644 /* transfer data into FIFO */ 1645 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1646 DOTG_DFIFO(td->channel), 1647 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1648 } 1649 1650 /* store number of bytes transmitted */ 1651 td->tx_bytes = count; 1652 1653 goto busy; 1654 1655 send_cpkt: 1656 count = DWC_OTG_READ_4(sc, DOTG_HFNUM) & 7; 1657 /* check for first microframe */ 1658 if (count == 0) { 1659 /* send packet again */ 1660 goto send_pkt; 1661 } 1662 1663 td->hcsplt |= HCSPLT_COMPSPLT; 1664 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1665 1666 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1667 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1668 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1669 1670 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 1671 1672 hcchar = td->hcchar; 1673 hcchar &= ~HCCHAR_EPDIR_IN; 1674 1675 /* must enable channel before writing data to FIFO */ 1676 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 1677 1678 busy: 1679 return (1); /* busy */ 1680 } 1681 1682 static uint8_t 1683 dwc_otg_data_tx(struct dwc_otg_td *td) 1684 { 1685 struct dwc_otg_softc *sc; 1686 uint32_t max_buffer; 1687 uint32_t count; 1688 uint32_t fifo_left; 1689 uint32_t mpkt; 1690 uint32_t temp; 1691 uint8_t to; 1692 1693 to = 3; /* don't loop forever! */ 1694 1695 /* get pointer to softc */ 1696 sc = DWC_OTG_PC2SC(td->pc); 1697 1698 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1699 1700 repeat: 1701 /* check for for endpoint 0 data */ 1702 1703 temp = sc->sc_last_rx_status; 1704 1705 if ((td->ep_no == 0) && (temp != 0) && 1706 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1707 1708 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1709 GRXSTSRD_STP_DATA) { 1710 1711 /* dump data - wrong direction */ 1712 dwc_otg_common_rx_ack(sc); 1713 } else { 1714 /* 1715 * The current transfer was cancelled 1716 * by the USB Host: 1717 */ 1718 td->error_any = 1; 1719 return (0); /* complete */ 1720 } 1721 } 1722 1723 /* fill in more TX data, if possible */ 1724 if (td->tx_bytes != 0) { 1725 1726 uint16_t cpkt; 1727 1728 /* check if packets have been transferred */ 1729 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1730 1731 /* get current packet number */ 1732 cpkt = DXEPTSIZ_GET_NPKT(temp); 1733 1734 if (cpkt >= td->npkt) { 1735 fifo_left = 0; 1736 } else { 1737 if (max_buffer != 0) { 1738 fifo_left = (td->npkt - cpkt) * 1739 td->max_packet_size; 1740 1741 if (fifo_left > max_buffer) 1742 fifo_left = max_buffer; 1743 } else { 1744 fifo_left = td->max_packet_size; 1745 } 1746 } 1747 1748 count = td->tx_bytes; 1749 if (count > fifo_left) 1750 count = fifo_left; 1751 1752 if (count != 0) { 1753 1754 /* clear topmost word before copy */ 1755 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1756 1757 /* copy out data */ 1758 usbd_copy_out(td->pc, td->offset, 1759 sc->sc_tx_bounce_buffer, count); 1760 1761 /* transfer data into FIFO */ 1762 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1763 DOTG_DFIFO(td->ep_no), 1764 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1765 1766 td->tx_bytes -= count; 1767 td->remainder -= count; 1768 td->offset += count; 1769 td->npkt = cpkt; 1770 } 1771 if (td->tx_bytes != 0) 1772 goto not_complete; 1773 1774 /* check remainder */ 1775 if (td->remainder == 0) { 1776 if (td->short_pkt) 1777 return (0); /* complete */ 1778 1779 /* else we need to transmit a short packet */ 1780 } 1781 } 1782 1783 if (!to--) 1784 goto not_complete; 1785 1786 /* check if not all packets have been transferred */ 1787 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1788 1789 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1790 1791 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 1792 "DIEPCTL=0x%08x\n", td->ep_no, 1793 DXEPTSIZ_GET_NPKT(temp), 1794 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 1795 1796 goto not_complete; 1797 } 1798 1799 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 1800 1801 /* try to optimise by sending more data */ 1802 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 1803 1804 /* send multiple packets at the same time */ 1805 mpkt = max_buffer / td->max_packet_size; 1806 1807 if (mpkt > 0x3FE) 1808 mpkt = 0x3FE; 1809 1810 count = td->remainder; 1811 if (count > 0x7FFFFF) 1812 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 1813 1814 td->npkt = count / td->max_packet_size; 1815 1816 /* 1817 * NOTE: We could use 0x3FE instead of "mpkt" in the 1818 * check below to get more throughput, but then we 1819 * have a dependency towards non-generic chip features 1820 * to disable the TX-FIFO-EMPTY interrupts on a per 1821 * endpoint basis. Increase the maximum buffer size of 1822 * the IN endpoint to increase the performance. 1823 */ 1824 if (td->npkt > mpkt) { 1825 td->npkt = mpkt; 1826 count = td->max_packet_size * mpkt; 1827 } else if ((count == 0) || (count % td->max_packet_size)) { 1828 /* we are transmitting a short packet */ 1829 td->npkt++; 1830 td->short_pkt = 1; 1831 } 1832 } else { 1833 /* send one packet at a time */ 1834 mpkt = 1; 1835 count = td->max_packet_size; 1836 if (td->remainder < count) { 1837 /* we have a short packet */ 1838 td->short_pkt = 1; 1839 count = td->remainder; 1840 } 1841 td->npkt = 1; 1842 } 1843 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 1844 DXEPTSIZ_SET_MULTI(1) | 1845 DXEPTSIZ_SET_NPKT(td->npkt) | 1846 DXEPTSIZ_SET_NBYTES(count)); 1847 1848 /* make room for buffering */ 1849 td->npkt += mpkt; 1850 1851 temp = sc->sc_in_ctl[td->ep_no]; 1852 1853 /* must enable before writing data to FIFO */ 1854 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 1855 DIEPCTL_EPENA | 1856 DIEPCTL_CNAK); 1857 1858 td->tx_bytes = count; 1859 1860 /* check remainder */ 1861 if (td->tx_bytes == 0 && 1862 td->remainder == 0) { 1863 if (td->short_pkt) 1864 return (0); /* complete */ 1865 1866 /* else we need to transmit a short packet */ 1867 } 1868 goto repeat; 1869 1870 not_complete: 1871 return (1); /* not complete */ 1872 } 1873 1874 static uint8_t 1875 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 1876 { 1877 struct dwc_otg_softc *sc; 1878 uint32_t temp; 1879 1880 /* get pointer to softc */ 1881 sc = DWC_OTG_PC2SC(td->pc); 1882 1883 /* 1884 * If all packets are transferred we are complete: 1885 */ 1886 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1887 1888 /* check that all packets have been transferred */ 1889 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1890 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 1891 goto not_complete; 1892 } 1893 return (0); 1894 1895 not_complete: 1896 1897 /* we only want to know if there is a SETUP packet or free IN packet */ 1898 1899 temp = sc->sc_last_rx_status; 1900 1901 if ((td->ep_no == 0) && (temp != 0) && 1902 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1903 1904 if ((temp & GRXSTSRD_PKTSTS_MASK) == 1905 GRXSTSRD_STP_DATA) { 1906 DPRINTFN(5, "faking complete\n"); 1907 /* 1908 * Race condition: We are complete! 1909 */ 1910 return (0); 1911 } else { 1912 /* dump data - wrong direction */ 1913 dwc_otg_common_rx_ack(sc); 1914 } 1915 } 1916 return (1); /* not complete */ 1917 } 1918 1919 static uint8_t 1920 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 1921 { 1922 struct dwc_otg_td *td; 1923 uint8_t toggle; 1924 uint8_t channel; 1925 uint8_t tmr_val; 1926 uint8_t tmr_res; 1927 1928 DPRINTFN(9, "\n"); 1929 1930 td = xfer->td_transfer_cache; 1931 1932 /* 1933 * If we are suspended in host mode and no channel is 1934 * allocated, simply return: 1935 */ 1936 if (xfer->xroot->udev->flags.self_suspended != 0 && 1937 xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST && 1938 td->channel >= DWC_OTG_MAX_CHANNELS) { 1939 return (1); /* not complete */ 1940 } 1941 while (1) { 1942 if ((td->func) (td)) { 1943 /* operation in progress */ 1944 break; 1945 } 1946 if (((void *)td) == xfer->td_transfer_last) { 1947 goto done; 1948 } 1949 if (td->error_any) { 1950 goto done; 1951 } else if (td->remainder > 0) { 1952 /* 1953 * We had a short transfer. If there is no alternate 1954 * next, stop processing ! 1955 */ 1956 if (!td->alt_next) 1957 goto done; 1958 } 1959 1960 /* 1961 * Fetch the next transfer descriptor and transfer 1962 * some flags to the next transfer descriptor 1963 */ 1964 tmr_res = td->tmr_res; 1965 tmr_val = td->tmr_val; 1966 toggle = td->toggle; 1967 channel = td->channel; 1968 td = td->obj_next; 1969 xfer->td_transfer_cache = td; 1970 td->toggle = toggle; /* transfer toggle */ 1971 td->channel = channel; /* transfer channel */ 1972 td->tmr_res = tmr_res; 1973 td->tmr_val = tmr_val; 1974 } 1975 return (1); /* not complete */ 1976 1977 done: 1978 /* compute all actual lengths */ 1979 1980 dwc_otg_standard_done(xfer); 1981 return (0); /* complete */ 1982 } 1983 1984 static void 1985 dwc_otg_timer(void *_sc) 1986 { 1987 struct dwc_otg_softc *sc = _sc; 1988 struct usb_xfer *xfer; 1989 struct dwc_otg_td *td; 1990 1991 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1992 1993 DPRINTF("\n"); 1994 1995 /* increment timer value */ 1996 sc->sc_tmr_val++; 1997 1998 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1999 td = xfer->td_transfer_cache; 2000 if (td != NULL) 2001 td->did_nak = 0; 2002 } 2003 2004 /* poll jobs */ 2005 dwc_otg_interrupt_poll(sc); 2006 2007 if (sc->sc_timer_active) { 2008 /* restart timer */ 2009 usb_callout_reset(&sc->sc_timer, 2010 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2011 &dwc_otg_timer, sc); 2012 } 2013 } 2014 2015 static void 2016 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2017 { 2018 if (sc->sc_timer_active != 0) 2019 return; 2020 2021 sc->sc_timer_active = 1; 2022 2023 /* restart timer */ 2024 usb_callout_reset(&sc->sc_timer, 2025 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2026 &dwc_otg_timer, sc); 2027 } 2028 2029 static void 2030 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2031 { 2032 if (sc->sc_timer_active == 0) 2033 return; 2034 2035 sc->sc_timer_active = 0; 2036 2037 /* stop timer */ 2038 usb_callout_stop(&sc->sc_timer); 2039 } 2040 2041 static void 2042 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 2043 { 2044 struct usb_xfer *xfer; 2045 uint32_t temp; 2046 uint8_t got_rx_status; 2047 uint8_t x; 2048 2049 repeat: 2050 /* get all channel interrupts */ 2051 for (x = 0; x != sc->sc_host_ch_max; x++) { 2052 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2053 if (temp != 0) { 2054 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2055 temp &= ~HCINT_SOFTWARE_ONLY; 2056 sc->sc_chan_state[x].hcint |= temp; 2057 } 2058 } 2059 2060 if (sc->sc_last_rx_status == 0) { 2061 2062 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2063 if (temp & GINTSTS_RXFLVL) { 2064 /* pop current status */ 2065 sc->sc_last_rx_status = 2066 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2067 } 2068 2069 if (sc->sc_last_rx_status != 0) { 2070 2071 uint8_t ep_no; 2072 2073 temp = sc->sc_last_rx_status & 2074 GRXSTSRD_PKTSTS_MASK; 2075 2076 /* non-data messages we simply skip */ 2077 if (temp != GRXSTSRD_STP_DATA && 2078 temp != GRXSTSRD_OUT_DATA) { 2079 dwc_otg_common_rx_ack(sc); 2080 goto repeat; 2081 } 2082 2083 temp = GRXSTSRD_BCNT_GET( 2084 sc->sc_last_rx_status); 2085 ep_no = GRXSTSRD_CHNUM_GET( 2086 sc->sc_last_rx_status); 2087 2088 /* receive data, if any */ 2089 if (temp != 0) { 2090 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2091 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2092 DOTG_DFIFO(ep_no), 2093 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2094 } 2095 2096 /* check if we should dump the data */ 2097 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2098 dwc_otg_common_rx_ack(sc); 2099 goto repeat; 2100 } 2101 2102 got_rx_status = 1; 2103 2104 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2105 sc->sc_last_rx_status, ep_no, 2106 (sc->sc_last_rx_status >> 15) & 3, 2107 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2108 (sc->sc_last_rx_status >> 17) & 15); 2109 } else { 2110 got_rx_status = 0; 2111 } 2112 } else { 2113 uint8_t ep_no; 2114 2115 ep_no = GRXSTSRD_CHNUM_GET( 2116 sc->sc_last_rx_status); 2117 2118 /* check if we should dump the data */ 2119 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2120 dwc_otg_common_rx_ack(sc); 2121 goto repeat; 2122 } 2123 2124 got_rx_status = 1; 2125 } 2126 2127 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2128 if (!dwc_otg_xfer_do_fifo(xfer)) { 2129 /* queue has been modified */ 2130 goto repeat; 2131 } 2132 } 2133 2134 if (got_rx_status) { 2135 /* check if data was consumed */ 2136 if (sc->sc_last_rx_status == 0) 2137 goto repeat; 2138 2139 /* disable RX FIFO level interrupt */ 2140 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 2141 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2142 } 2143 } 2144 2145 static void 2146 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2147 { 2148 DPRINTFN(5, "vbus = %u\n", is_on); 2149 2150 if (is_on) { 2151 if (!sc->sc_flags.status_vbus) { 2152 sc->sc_flags.status_vbus = 1; 2153 2154 /* complete root HUB interrupt endpoint */ 2155 2156 dwc_otg_root_intr(sc); 2157 } 2158 } else { 2159 if (sc->sc_flags.status_vbus) { 2160 sc->sc_flags.status_vbus = 0; 2161 sc->sc_flags.status_bus_reset = 0; 2162 sc->sc_flags.status_suspend = 0; 2163 sc->sc_flags.change_suspend = 0; 2164 sc->sc_flags.change_connect = 1; 2165 2166 /* complete root HUB interrupt endpoint */ 2167 2168 dwc_otg_root_intr(sc); 2169 } 2170 } 2171 } 2172 2173 void 2174 dwc_otg_interrupt(struct dwc_otg_softc *sc) 2175 { 2176 uint32_t status; 2177 2178 USB_BUS_LOCK(&sc->sc_bus); 2179 2180 /* read and clear interrupt status */ 2181 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2182 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 2183 2184 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2185 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2186 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2187 2188 if (status & GINTSTS_USBRST) { 2189 2190 /* set correct state */ 2191 sc->sc_flags.status_device_mode = 1; 2192 sc->sc_flags.status_bus_reset = 0; 2193 sc->sc_flags.status_suspend = 0; 2194 sc->sc_flags.change_suspend = 0; 2195 sc->sc_flags.change_connect = 1; 2196 2197 /* complete root HUB interrupt endpoint */ 2198 dwc_otg_root_intr(sc); 2199 } 2200 2201 /* check for any bus state change interrupts */ 2202 if (status & GINTSTS_ENUMDONE) { 2203 2204 uint32_t temp; 2205 2206 DPRINTFN(5, "end of reset\n"); 2207 2208 /* set correct state */ 2209 sc->sc_flags.status_device_mode = 1; 2210 sc->sc_flags.status_bus_reset = 1; 2211 sc->sc_flags.status_suspend = 0; 2212 sc->sc_flags.change_suspend = 0; 2213 sc->sc_flags.change_connect = 1; 2214 sc->sc_flags.status_low_speed = 0; 2215 sc->sc_flags.port_enabled = 1; 2216 2217 /* reset FIFOs */ 2218 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2219 2220 /* reset function address */ 2221 dwc_otg_set_address(sc, 0); 2222 2223 /* figure out enumeration speed */ 2224 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2225 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2226 sc->sc_flags.status_high_speed = 1; 2227 else 2228 sc->sc_flags.status_high_speed = 0; 2229 2230 /* disable resume interrupt and enable suspend interrupt */ 2231 2232 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 2233 sc->sc_irq_mask |= GINTSTS_USBSUSP; 2234 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2235 2236 /* complete root HUB interrupt endpoint */ 2237 dwc_otg_root_intr(sc); 2238 } 2239 2240 if (status & GINTSTS_PRTINT) { 2241 uint32_t hprt; 2242 2243 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2244 2245 /* clear change bits */ 2246 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2247 HPRT_PRTPWR | HPRT_PRTENCHNG | 2248 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2249 sc->sc_hprt_val); 2250 2251 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2252 2253 sc->sc_flags.status_device_mode = 0; 2254 2255 if (hprt & HPRT_PRTCONNSTS) 2256 sc->sc_flags.status_bus_reset = 1; 2257 else 2258 sc->sc_flags.status_bus_reset = 0; 2259 2260 if (hprt & HPRT_PRTENCHNG) 2261 sc->sc_flags.change_enabled = 1; 2262 2263 if (hprt & HPRT_PRTENA) 2264 sc->sc_flags.port_enabled = 1; 2265 else 2266 sc->sc_flags.port_enabled = 0; 2267 2268 if (hprt & HPRT_PRTOVRCURRCHNG) 2269 sc->sc_flags.change_over_current = 1; 2270 2271 if (hprt & HPRT_PRTOVRCURRACT) 2272 sc->sc_flags.port_over_current = 1; 2273 else 2274 sc->sc_flags.port_over_current = 0; 2275 2276 if (hprt & HPRT_PRTPWR) 2277 sc->sc_flags.port_powered = 1; 2278 else 2279 sc->sc_flags.port_powered = 0; 2280 2281 if (((hprt & HPRT_PRTSPD_MASK) 2282 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2283 sc->sc_flags.status_low_speed = 1; 2284 else 2285 sc->sc_flags.status_low_speed = 0; 2286 2287 if (((hprt & HPRT_PRTSPD_MASK) 2288 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2289 sc->sc_flags.status_high_speed = 1; 2290 else 2291 sc->sc_flags.status_high_speed = 0; 2292 2293 if (hprt & HPRT_PRTCONNDET) 2294 sc->sc_flags.change_connect = 1; 2295 2296 if (hprt & HPRT_PRTSUSP) 2297 dwc_otg_suspend_irq(sc); 2298 else 2299 dwc_otg_resume_irq(sc); 2300 2301 /* complete root HUB interrupt endpoint */ 2302 dwc_otg_root_intr(sc); 2303 } 2304 2305 /* 2306 * If resume and suspend is set at the same time we interpret 2307 * that like RESUME. Resume is set when there is at least 3 2308 * milliseconds of inactivity on the USB BUS. 2309 */ 2310 if (status & GINTSTS_WKUPINT) { 2311 2312 DPRINTFN(5, "resume interrupt\n"); 2313 2314 dwc_otg_resume_irq(sc); 2315 2316 } else if (status & GINTSTS_USBSUSP) { 2317 2318 DPRINTFN(5, "suspend interrupt\n"); 2319 2320 dwc_otg_suspend_irq(sc); 2321 } 2322 /* check VBUS */ 2323 if (status & (GINTSTS_USBSUSP | 2324 GINTSTS_USBRST | 2325 GINTMSK_OTGINTMSK | 2326 GINTSTS_SESSREQINT)) { 2327 uint32_t temp; 2328 2329 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2330 2331 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2332 2333 dwc_otg_vbus_interrupt(sc, 2334 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2335 } 2336 2337 /* clear all IN endpoint interrupts */ 2338 if (status & GINTSTS_IEPINT) { 2339 uint32_t temp; 2340 uint8_t x; 2341 2342 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2343 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2344 if (temp & DIEPMSK_XFERCOMPLMSK) { 2345 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2346 DIEPMSK_XFERCOMPLMSK); 2347 } 2348 } 2349 } 2350 2351 /* check for SOF interrupt */ 2352 if (status & GINTSTS_SOF) { 2353 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2354 uint8_t x; 2355 uint8_t y; 2356 2357 DPRINTFN(12, "SOF interrupt\n"); 2358 2359 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 2360 if (sc->sc_chan_state[x].wait_sof != 0) { 2361 if (--(sc->sc_chan_state[x].wait_sof) != 0) 2362 y = 1; 2363 } 2364 } 2365 if (y == 0) { 2366 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2367 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2368 } 2369 } 2370 } 2371 2372 /* poll FIFO(s) */ 2373 dwc_otg_interrupt_poll(sc); 2374 2375 USB_BUS_UNLOCK(&sc->sc_bus); 2376 } 2377 2378 static void 2379 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2380 { 2381 struct dwc_otg_td *td; 2382 2383 /* get current Transfer Descriptor */ 2384 td = temp->td_next; 2385 temp->td = td; 2386 2387 /* prepare for next TD */ 2388 temp->td_next = td->obj_next; 2389 2390 /* fill out the Transfer Descriptor */ 2391 td->func = temp->func; 2392 td->pc = temp->pc; 2393 td->offset = temp->offset; 2394 td->remainder = temp->len; 2395 td->tx_bytes = 0; 2396 td->error_any = 0; 2397 td->error_stall = 0; 2398 td->npkt = 0; 2399 td->did_stall = temp->did_stall; 2400 td->short_pkt = temp->short_pkt; 2401 td->alt_next = temp->setup_alt_next; 2402 td->set_toggle = 0; 2403 td->got_short = 0; 2404 td->did_nak = 0; 2405 td->channel = DWC_OTG_MAX_CHANNELS; 2406 td->state = 0; 2407 td->errcnt = 0; 2408 } 2409 2410 static void 2411 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2412 { 2413 struct dwc_otg_std_temp temp; 2414 struct dwc_otg_td *td; 2415 uint32_t x; 2416 uint8_t need_sync; 2417 uint8_t is_host; 2418 2419 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2420 xfer->address, UE_GET_ADDR(xfer->endpointno), 2421 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2422 2423 temp.max_frame_size = xfer->max_frame_size; 2424 2425 td = xfer->td_start[0]; 2426 xfer->td_transfer_first = td; 2427 xfer->td_transfer_cache = td; 2428 2429 /* setup temp */ 2430 2431 temp.pc = NULL; 2432 temp.td = NULL; 2433 temp.td_next = xfer->td_start[0]; 2434 temp.offset = 0; 2435 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2436 temp.did_stall = !xfer->flags_int.control_stall; 2437 2438 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2439 2440 /* check if we should prepend a setup message */ 2441 2442 if (xfer->flags_int.control_xfr) { 2443 if (xfer->flags_int.control_hdr) { 2444 2445 if (is_host) 2446 temp.func = &dwc_otg_host_setup_tx; 2447 else 2448 temp.func = &dwc_otg_setup_rx; 2449 2450 temp.len = xfer->frlengths[0]; 2451 temp.pc = xfer->frbuffers + 0; 2452 temp.short_pkt = temp.len ? 1 : 0; 2453 2454 /* check for last frame */ 2455 if (xfer->nframes == 1) { 2456 /* no STATUS stage yet, SETUP is last */ 2457 if (xfer->flags_int.control_act) 2458 temp.setup_alt_next = 0; 2459 } 2460 2461 dwc_otg_setup_standard_chain_sub(&temp); 2462 } 2463 x = 1; 2464 } else { 2465 x = 0; 2466 } 2467 2468 if (x != xfer->nframes) { 2469 if (xfer->endpointno & UE_DIR_IN) { 2470 if (is_host) { 2471 temp.func = &dwc_otg_host_data_rx; 2472 need_sync = 0; 2473 } else { 2474 temp.func = &dwc_otg_data_tx; 2475 need_sync = 1; 2476 } 2477 } else { 2478 if (is_host) { 2479 temp.func = &dwc_otg_host_data_tx; 2480 need_sync = 0; 2481 } else { 2482 temp.func = &dwc_otg_data_rx; 2483 need_sync = 0; 2484 } 2485 } 2486 2487 /* setup "pc" pointer */ 2488 temp.pc = xfer->frbuffers + x; 2489 } else { 2490 need_sync = 0; 2491 } 2492 while (x != xfer->nframes) { 2493 2494 /* DATA0 / DATA1 message */ 2495 2496 temp.len = xfer->frlengths[x]; 2497 2498 x++; 2499 2500 if (x == xfer->nframes) { 2501 if (xfer->flags_int.control_xfr) { 2502 if (xfer->flags_int.control_act) { 2503 temp.setup_alt_next = 0; 2504 } 2505 } else { 2506 temp.setup_alt_next = 0; 2507 } 2508 } 2509 if (temp.len == 0) { 2510 2511 /* make sure that we send an USB packet */ 2512 2513 temp.short_pkt = 0; 2514 2515 } else { 2516 2517 /* regular data transfer */ 2518 2519 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2520 } 2521 2522 dwc_otg_setup_standard_chain_sub(&temp); 2523 2524 if (xfer->flags_int.isochronous_xfr) { 2525 temp.offset += temp.len; 2526 } else { 2527 /* get next Page Cache pointer */ 2528 temp.pc = xfer->frbuffers + x; 2529 } 2530 } 2531 2532 if (xfer->flags_int.control_xfr) { 2533 2534 /* always setup a valid "pc" pointer for status and sync */ 2535 temp.pc = xfer->frbuffers + 0; 2536 temp.len = 0; 2537 temp.short_pkt = 0; 2538 temp.setup_alt_next = 0; 2539 2540 /* check if we need to sync */ 2541 if (need_sync) { 2542 /* we need a SYNC point after TX */ 2543 temp.func = &dwc_otg_data_tx_sync; 2544 dwc_otg_setup_standard_chain_sub(&temp); 2545 } 2546 2547 /* check if we should append a status stage */ 2548 if (!xfer->flags_int.control_act) { 2549 2550 /* 2551 * Send a DATA1 message and invert the current 2552 * endpoint direction. 2553 */ 2554 if (xfer->endpointno & UE_DIR_IN) { 2555 if (is_host) { 2556 temp.func = &dwc_otg_host_data_tx; 2557 need_sync = 0; 2558 } else { 2559 temp.func = &dwc_otg_data_rx; 2560 need_sync = 0; 2561 } 2562 } else { 2563 if (is_host) { 2564 temp.func = &dwc_otg_host_data_rx; 2565 need_sync = 0; 2566 } else { 2567 temp.func = &dwc_otg_data_tx; 2568 need_sync = 1; 2569 } 2570 } 2571 2572 dwc_otg_setup_standard_chain_sub(&temp); 2573 2574 /* data toggle should be DATA1 */ 2575 td = temp.td; 2576 td->set_toggle = 1; 2577 2578 if (need_sync) { 2579 /* we need a SYNC point after TX */ 2580 temp.func = &dwc_otg_data_tx_sync; 2581 dwc_otg_setup_standard_chain_sub(&temp); 2582 } 2583 } 2584 } else { 2585 /* check if we need to sync */ 2586 if (need_sync) { 2587 2588 temp.pc = xfer->frbuffers + 0; 2589 temp.len = 0; 2590 temp.short_pkt = 0; 2591 temp.setup_alt_next = 0; 2592 2593 /* we need a SYNC point after TX */ 2594 temp.func = &dwc_otg_data_tx_sync; 2595 dwc_otg_setup_standard_chain_sub(&temp); 2596 } 2597 } 2598 2599 /* must have at least one frame! */ 2600 td = temp.td; 2601 xfer->td_transfer_last = td; 2602 2603 if (is_host) { 2604 2605 struct dwc_otg_softc *sc; 2606 uint32_t hcchar; 2607 uint32_t hcsplt; 2608 uint8_t xfer_type; 2609 2610 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2611 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2612 2613 /* get first again */ 2614 td = xfer->td_transfer_first; 2615 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 2616 2617 hcchar = 2618 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 2619 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 2620 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 2621 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 2622 HCCHAR_CHENA; 2623 2624 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 2625 hcchar |= HCCHAR_LSPDDEV; 2626 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2627 hcchar |= HCCHAR_EPDIR_IN; 2628 2629 switch (xfer->xroot->udev->speed) { 2630 case USB_SPEED_FULL: 2631 case USB_SPEED_LOW: 2632 /* check if root HUB port is running High Speed */ 2633 if (sc->sc_flags.status_high_speed != 0) { 2634 hcsplt = HCSPLT_SPLTENA | 2635 (xfer->xroot->udev->hs_port_no << 2636 HCSPLT_PRTADDR_SHIFT) | 2637 (xfer->xroot->udev->hs_hub_addr << 2638 HCSPLT_HUBADDR_SHIFT); 2639 if (xfer_type == UE_ISOCHRONOUS) /* XXX */ 2640 hcsplt |= (3 << HCSPLT_XACTPOS_SHIFT); 2641 } else { 2642 hcsplt = 0; 2643 } 2644 if (xfer_type == UE_INTERRUPT) { 2645 uint32_t ival; 2646 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2647 if (ival == 0) 2648 ival = 1; 2649 else if (ival > 127) 2650 ival = 127; 2651 td->tmr_val = sc->sc_tmr_val + ival; 2652 td->tmr_res = ival; 2653 } 2654 break; 2655 case USB_SPEED_HIGH: 2656 hcsplt = 0; 2657 if (xfer_type == UE_ISOCHRONOUS || 2658 xfer_type == UE_INTERRUPT) { 2659 hcchar |= ((xfer->max_packet_count & 3) 2660 << HCCHAR_MC_SHIFT); 2661 } 2662 if (xfer_type == UE_INTERRUPT) { 2663 uint32_t ival; 2664 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 2665 if (ival == 0) 2666 ival = 1; 2667 else if (ival > 127) 2668 ival = 127; 2669 td->tmr_val = sc->sc_tmr_val + ival; 2670 td->tmr_res = ival; 2671 } 2672 break; 2673 default: 2674 hcsplt = 0; 2675 break; 2676 } 2677 2678 if (xfer_type == UE_ISOCHRONOUS) { 2679 td->tmr_val = xfer->endpoint->isoc_next & 0xFF; 2680 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 2681 } else if (xfer_type != UE_INTERRUPT) { 2682 td->tmr_val = 0; 2683 td->tmr_res = 0; 2684 } 2685 2686 /* store configuration in all TD's */ 2687 while (1) { 2688 td->hcchar = hcchar; 2689 td->hcsplt = hcsplt; 2690 2691 if (((void *)td) == xfer->td_transfer_last) 2692 break; 2693 2694 td = td->obj_next; 2695 } 2696 } 2697 } 2698 2699 static void 2700 dwc_otg_timeout(void *arg) 2701 { 2702 struct usb_xfer *xfer = arg; 2703 2704 DPRINTF("xfer=%p\n", xfer); 2705 2706 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2707 2708 /* transfer is transferred */ 2709 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 2710 } 2711 2712 static void 2713 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 2714 { 2715 DPRINTFN(9, "\n"); 2716 2717 /* poll one time - will turn on interrupts */ 2718 if (dwc_otg_xfer_do_fifo(xfer)) { 2719 2720 /* put transfer on interrupt queue */ 2721 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2722 2723 /* start timeout, if any */ 2724 if (xfer->timeout != 0) { 2725 usbd_transfer_timeout_ms(xfer, 2726 &dwc_otg_timeout, xfer->timeout); 2727 } 2728 } 2729 } 2730 2731 static void 2732 dwc_otg_root_intr(struct dwc_otg_softc *sc) 2733 { 2734 DPRINTFN(9, "\n"); 2735 2736 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2737 2738 /* set port bit */ 2739 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2740 2741 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2742 sizeof(sc->sc_hub_idata)); 2743 } 2744 2745 static usb_error_t 2746 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 2747 { 2748 struct dwc_otg_td *td; 2749 uint32_t len; 2750 usb_error_t error; 2751 2752 DPRINTFN(9, "\n"); 2753 2754 td = xfer->td_transfer_cache; 2755 2756 do { 2757 len = td->remainder; 2758 2759 /* store last data toggle */ 2760 xfer->endpoint->toggle_next = td->toggle; 2761 2762 if (xfer->aframes != xfer->nframes) { 2763 /* 2764 * Verify the length and subtract 2765 * the remainder from "frlengths[]": 2766 */ 2767 if (len > xfer->frlengths[xfer->aframes]) { 2768 td->error_any = 1; 2769 } else { 2770 xfer->frlengths[xfer->aframes] -= len; 2771 } 2772 } 2773 /* Check for transfer error */ 2774 if (td->error_any) { 2775 /* the transfer is finished */ 2776 error = (td->error_stall ? 2777 USB_ERR_STALLED : USB_ERR_IOERROR); 2778 td = NULL; 2779 break; 2780 } 2781 /* Check for short transfer */ 2782 if (len > 0) { 2783 if (xfer->flags_int.short_frames_ok) { 2784 /* follow alt next */ 2785 if (td->alt_next) { 2786 td = td->obj_next; 2787 } else { 2788 td = NULL; 2789 } 2790 } else { 2791 /* the transfer is finished */ 2792 td = NULL; 2793 } 2794 error = 0; 2795 break; 2796 } 2797 td = td->obj_next; 2798 2799 /* this USB frame is complete */ 2800 error = 0; 2801 break; 2802 2803 } while (0); 2804 2805 /* update transfer cache */ 2806 2807 xfer->td_transfer_cache = td; 2808 2809 return (error); 2810 } 2811 2812 static void 2813 dwc_otg_standard_done(struct usb_xfer *xfer) 2814 { 2815 usb_error_t err = 0; 2816 2817 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2818 xfer, xfer->endpoint); 2819 2820 /* reset scanner */ 2821 2822 xfer->td_transfer_cache = xfer->td_transfer_first; 2823 2824 if (xfer->flags_int.control_xfr) { 2825 2826 if (xfer->flags_int.control_hdr) { 2827 2828 err = dwc_otg_standard_done_sub(xfer); 2829 } 2830 xfer->aframes = 1; 2831 2832 if (xfer->td_transfer_cache == NULL) { 2833 goto done; 2834 } 2835 } 2836 while (xfer->aframes != xfer->nframes) { 2837 2838 err = dwc_otg_standard_done_sub(xfer); 2839 xfer->aframes++; 2840 2841 if (xfer->td_transfer_cache == NULL) { 2842 goto done; 2843 } 2844 } 2845 2846 if (xfer->flags_int.control_xfr && 2847 !xfer->flags_int.control_act) { 2848 2849 err = dwc_otg_standard_done_sub(xfer); 2850 } 2851 done: 2852 dwc_otg_device_done(xfer, err); 2853 } 2854 2855 /*------------------------------------------------------------------------* 2856 * dwc_otg_device_done 2857 * 2858 * NOTE: this function can be called more than one time on the 2859 * same USB transfer! 2860 *------------------------------------------------------------------------*/ 2861 static void 2862 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 2863 { 2864 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 2865 xfer, xfer->endpoint, error); 2866 2867 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 2868 DPRINTFN(15, "disabled interrupts!\n"); 2869 } else { 2870 struct dwc_otg_td *td; 2871 2872 td = xfer->td_transfer_first; 2873 2874 if (td != NULL) 2875 dwc_otg_host_channel_free(td); 2876 } 2877 /* dequeue transfer and start next transfer */ 2878 usbd_transfer_done(xfer, error); 2879 } 2880 2881 static void 2882 dwc_otg_xfer_stall(struct usb_xfer *xfer) 2883 { 2884 dwc_otg_device_done(xfer, USB_ERR_STALLED); 2885 } 2886 2887 static void 2888 dwc_otg_set_stall(struct usb_device *udev, 2889 struct usb_endpoint *ep, uint8_t *did_stall) 2890 { 2891 struct dwc_otg_softc *sc; 2892 uint32_t temp; 2893 uint32_t reg; 2894 uint8_t ep_no; 2895 2896 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2897 2898 /* check mode */ 2899 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2900 /* not supported */ 2901 return; 2902 } 2903 2904 sc = DWC_OTG_BUS2SC(udev->bus); 2905 2906 /* get endpoint address */ 2907 ep_no = ep->edesc->bEndpointAddress; 2908 2909 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 2910 2911 if (ep_no & UE_DIR_IN) { 2912 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 2913 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 2914 } else { 2915 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 2916 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 2917 } 2918 2919 /* disable and stall endpoint */ 2920 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2921 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 2922 2923 /* clear active OUT ep */ 2924 if (!(ep_no & UE_DIR_IN)) { 2925 2926 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 2927 2928 if (sc->sc_last_rx_status != 0 && 2929 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 2930 sc->sc_last_rx_status)) { 2931 /* dump data */ 2932 dwc_otg_common_rx_ack(sc); 2933 /* poll interrupt */ 2934 dwc_otg_interrupt_poll(sc); 2935 } 2936 } 2937 } 2938 2939 static void 2940 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 2941 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2942 { 2943 uint32_t reg; 2944 uint32_t temp; 2945 2946 if (ep_type == UE_CONTROL) { 2947 /* clearing stall is not needed */ 2948 return; 2949 } 2950 2951 if (ep_dir) { 2952 reg = DOTG_DIEPCTL(ep_no); 2953 } else { 2954 reg = DOTG_DOEPCTL(ep_no); 2955 sc->sc_active_rx_ep |= (1U << ep_no); 2956 } 2957 2958 /* round up and mask away the multiplier count */ 2959 mps = (mps + 3) & 0x7FC; 2960 2961 if (ep_type == UE_BULK) { 2962 temp = DIEPCTL_EPTYPE_SET( 2963 DIEPCTL_EPTYPE_BULK) | 2964 DIEPCTL_USBACTEP; 2965 } else if (ep_type == UE_INTERRUPT) { 2966 temp = DIEPCTL_EPTYPE_SET( 2967 DIEPCTL_EPTYPE_INTERRUPT) | 2968 DIEPCTL_USBACTEP; 2969 } else { 2970 temp = DIEPCTL_EPTYPE_SET( 2971 DIEPCTL_EPTYPE_ISOC) | 2972 DIEPCTL_USBACTEP; 2973 } 2974 2975 temp |= DIEPCTL_MPS_SET(mps); 2976 temp |= DIEPCTL_TXFNUM_SET(ep_no); 2977 2978 if (ep_dir) 2979 sc->sc_in_ctl[ep_no] = temp; 2980 else 2981 sc->sc_out_ctl[ep_no] = temp; 2982 2983 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2984 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 2985 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 2986 2987 /* we only reset the transmit FIFO */ 2988 if (ep_dir) { 2989 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2990 GRSTCTL_TXFIFO(ep_no) | 2991 GRSTCTL_TXFFLSH); 2992 2993 DWC_OTG_WRITE_4(sc, 2994 DOTG_DIEPTSIZ(ep_no), 0); 2995 } 2996 2997 /* poll interrupt */ 2998 dwc_otg_interrupt_poll(sc); 2999 } 3000 3001 static void 3002 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3003 { 3004 struct dwc_otg_softc *sc; 3005 struct usb_endpoint_descriptor *ed; 3006 3007 DPRINTFN(5, "endpoint=%p\n", ep); 3008 3009 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3010 3011 /* check mode */ 3012 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3013 /* not supported */ 3014 return; 3015 } 3016 /* get softc */ 3017 sc = DWC_OTG_BUS2SC(udev->bus); 3018 3019 /* get endpoint descriptor */ 3020 ed = ep->edesc; 3021 3022 /* reset endpoint */ 3023 dwc_otg_clear_stall_sub(sc, 3024 UGETW(ed->wMaxPacketSize), 3025 (ed->bEndpointAddress & UE_ADDR), 3026 (ed->bmAttributes & UE_XFERTYPE), 3027 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3028 } 3029 3030 static void 3031 dwc_otg_device_state_change(struct usb_device *udev) 3032 { 3033 struct dwc_otg_softc *sc; 3034 uint8_t x; 3035 3036 /* check mode */ 3037 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3038 /* not supported */ 3039 return; 3040 } 3041 3042 /* get softc */ 3043 sc = DWC_OTG_BUS2SC(udev->bus); 3044 3045 /* deactivate all other endpoint but the control endpoint */ 3046 if (udev->state == USB_STATE_CONFIGURED || 3047 udev->state == USB_STATE_ADDRESSED) { 3048 3049 USB_BUS_LOCK(&sc->sc_bus); 3050 3051 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3052 3053 if (x < sc->sc_dev_in_ep_max) { 3054 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3055 DIEPCTL_EPDIS); 3056 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3057 } 3058 3059 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3060 DOEPCTL_EPDIS); 3061 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3062 } 3063 USB_BUS_UNLOCK(&sc->sc_bus); 3064 } 3065 } 3066 3067 int 3068 dwc_otg_init(struct dwc_otg_softc *sc) 3069 { 3070 uint32_t temp; 3071 3072 DPRINTF("start\n"); 3073 3074 /* set up the bus structure */ 3075 sc->sc_bus.usbrev = USB_REV_2_0; 3076 sc->sc_bus.methods = &dwc_otg_bus_methods; 3077 3078 usb_callout_init_mtx(&sc->sc_timer, 3079 &sc->sc_bus.bus_mtx, 0); 3080 3081 USB_BUS_LOCK(&sc->sc_bus); 3082 3083 /* turn on clocks */ 3084 dwc_otg_clocks_on(sc); 3085 3086 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3087 DPRINTF("Version = 0x%08x\n", temp); 3088 3089 /* disconnect */ 3090 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3091 DCTL_SFTDISCON); 3092 3093 /* wait for host to detect disconnect */ 3094 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3095 3096 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3097 GRSTCTL_CSFTRST); 3098 3099 /* wait a little bit for block to reset */ 3100 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3101 3102 switch (sc->sc_mode) { 3103 case DWC_MODE_DEVICE: 3104 temp = GUSBCFG_FORCEDEVMODE; 3105 break; 3106 case DWC_MODE_HOST: 3107 temp = GUSBCFG_FORCEHOSTMODE; 3108 break; 3109 default: 3110 temp = 0; 3111 break; 3112 } 3113 3114 /* select HSIC or non-HSIC mode */ 3115 if (dwc_otg_use_hsic) { 3116 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3117 GUSBCFG_PHYIF | 3118 GUSBCFG_TRD_TIM_SET(5) | temp); 3119 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3120 0x000000EC); 3121 3122 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3123 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3124 temp & ~GLPMCFG_HSIC_CONN); 3125 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3126 temp | GLPMCFG_HSIC_CONN); 3127 } else { 3128 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3129 GUSBCFG_ULPI_UTMI_SEL | 3130 GUSBCFG_TRD_TIM_SET(5) | temp); 3131 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3132 3133 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3134 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3135 temp & ~GLPMCFG_HSIC_CONN); 3136 } 3137 3138 /* clear global nak */ 3139 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3140 DCTL_CGOUTNAK | 3141 DCTL_CGNPINNAK); 3142 3143 /* disable USB port */ 3144 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3145 3146 /* wait 10ms */ 3147 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3148 3149 /* enable USB port */ 3150 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3151 3152 /* wait 10ms */ 3153 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3154 3155 /* pull up D+ */ 3156 dwc_otg_pull_up(sc); 3157 3158 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3159 3160 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3161 3162 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3163 3164 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3165 3166 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3167 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3168 3169 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3170 3171 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3172 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3173 3174 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3175 3176 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3177 3178 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3179 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3180 sc->sc_host_ch_max); 3181 3182 /* setup FIFO */ 3183 if (dwc_otg_init_fifo(sc, DWC_MODE_OTG)) 3184 return (EINVAL); 3185 3186 /* enable interrupts */ 3187 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3188 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3189 3190 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3191 3192 /* enable all endpoint interrupts */ 3193 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3194 if (temp & GHWCFG2_MPI) { 3195 uint8_t x; 3196 3197 DPRINTF("Multi Process Interrupts\n"); 3198 3199 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3200 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3201 DIEPMSK_XFERCOMPLMSK); 3202 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3203 } 3204 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3205 } else { 3206 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3207 DIEPMSK_XFERCOMPLMSK); 3208 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3209 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3210 } 3211 } 3212 3213 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3214 /* setup clocks */ 3215 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3216 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3217 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3218 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3219 } 3220 3221 /* only enable global IRQ */ 3222 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3223 GAHBCFG_GLBLINTRMSK); 3224 3225 /* turn off clocks */ 3226 dwc_otg_clocks_off(sc); 3227 3228 /* read initial VBUS state */ 3229 3230 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3231 3232 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3233 3234 dwc_otg_vbus_interrupt(sc, 3235 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3236 3237 USB_BUS_UNLOCK(&sc->sc_bus); 3238 3239 /* catch any lost interrupts */ 3240 3241 dwc_otg_do_poll(&sc->sc_bus); 3242 3243 return (0); /* success */ 3244 } 3245 3246 void 3247 dwc_otg_uninit(struct dwc_otg_softc *sc) 3248 { 3249 USB_BUS_LOCK(&sc->sc_bus); 3250 3251 /* stop host timer */ 3252 dwc_otg_timer_stop(sc); 3253 3254 /* set disconnect */ 3255 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3256 DCTL_SFTDISCON); 3257 3258 /* turn off global IRQ */ 3259 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3260 3261 sc->sc_flags.port_enabled = 0; 3262 sc->sc_flags.port_powered = 0; 3263 sc->sc_flags.status_vbus = 0; 3264 sc->sc_flags.status_bus_reset = 0; 3265 sc->sc_flags.status_suspend = 0; 3266 sc->sc_flags.change_suspend = 0; 3267 sc->sc_flags.change_connect = 1; 3268 3269 dwc_otg_pull_down(sc); 3270 dwc_otg_clocks_off(sc); 3271 3272 USB_BUS_UNLOCK(&sc->sc_bus); 3273 3274 usb_callout_drain(&sc->sc_timer); 3275 } 3276 3277 static void 3278 dwc_otg_suspend(struct dwc_otg_softc *sc) 3279 { 3280 return; 3281 } 3282 3283 static void 3284 dwc_otg_resume(struct dwc_otg_softc *sc) 3285 { 3286 return; 3287 } 3288 3289 static void 3290 dwc_otg_do_poll(struct usb_bus *bus) 3291 { 3292 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3293 3294 USB_BUS_LOCK(&sc->sc_bus); 3295 dwc_otg_interrupt_poll(sc); 3296 USB_BUS_UNLOCK(&sc->sc_bus); 3297 } 3298 3299 /*------------------------------------------------------------------------* 3300 * DWC OTG bulk support 3301 * DWC OTG control support 3302 * DWC OTG interrupt support 3303 *------------------------------------------------------------------------*/ 3304 static void 3305 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3306 { 3307 } 3308 3309 static void 3310 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3311 { 3312 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3313 } 3314 3315 static void 3316 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3317 { 3318 } 3319 3320 static void 3321 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3322 { 3323 /* setup TDs */ 3324 dwc_otg_setup_standard_chain(xfer); 3325 dwc_otg_start_standard_chain(xfer); 3326 } 3327 3328 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3329 { 3330 .open = dwc_otg_device_non_isoc_open, 3331 .close = dwc_otg_device_non_isoc_close, 3332 .enter = dwc_otg_device_non_isoc_enter, 3333 .start = dwc_otg_device_non_isoc_start, 3334 }; 3335 3336 /*------------------------------------------------------------------------* 3337 * DWC OTG full speed isochronous support 3338 *------------------------------------------------------------------------*/ 3339 static void 3340 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3341 { 3342 } 3343 3344 static void 3345 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3346 { 3347 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3348 } 3349 3350 static void 3351 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3352 { 3353 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3354 uint32_t temp; 3355 uint32_t nframes; 3356 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3357 3358 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3359 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3360 3361 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3362 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 3363 3364 /* get the current frame index */ 3365 nframes = (temp & HFNUM_FRNUM_MASK); 3366 } else { 3367 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3368 3369 /* get the current frame index */ 3370 nframes = DSTS_SOFFN_GET(temp); 3371 } 3372 3373 if (sc->sc_flags.status_high_speed) 3374 nframes /= 8; 3375 3376 nframes &= DWC_OTG_FRAME_MASK; 3377 3378 /* 3379 * check if the frame index is within the window where the frames 3380 * will be inserted 3381 */ 3382 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3383 3384 if ((xfer->endpoint->is_synced == 0) || 3385 (temp < (((xfer->nframes << shift) + 7) / 8))) { 3386 /* 3387 * If there is data underflow or the pipe queue is 3388 * empty we schedule the transfer a few frames ahead 3389 * of the current frame position. Else two isochronous 3390 * transfers might overlap. 3391 */ 3392 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 3393 xfer->endpoint->is_synced = 1; 3394 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3395 } 3396 /* 3397 * compute how many milliseconds the insertion is ahead of the 3398 * current frame position: 3399 */ 3400 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 3401 3402 /* 3403 * pre-compute when the isochronous transfer will be finished: 3404 */ 3405 xfer->isoc_time_complete = 3406 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3407 (((xfer->nframes << shift) + 7) / 8); 3408 3409 /* setup TDs */ 3410 dwc_otg_setup_standard_chain(xfer); 3411 3412 /* compute frame number for next insertion */ 3413 xfer->endpoint->isoc_next += (xfer->nframes << shift); 3414 } 3415 3416 static void 3417 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3418 { 3419 /* start TD chain */ 3420 dwc_otg_start_standard_chain(xfer); 3421 } 3422 3423 struct usb_pipe_methods dwc_otg_device_isoc_methods = 3424 { 3425 .open = dwc_otg_device_isoc_open, 3426 .close = dwc_otg_device_isoc_close, 3427 .enter = dwc_otg_device_isoc_enter, 3428 .start = dwc_otg_device_isoc_start, 3429 }; 3430 3431 /*------------------------------------------------------------------------* 3432 * DWC OTG root control support 3433 *------------------------------------------------------------------------* 3434 * Simulate a hardware HUB by handling all the necessary requests. 3435 *------------------------------------------------------------------------*/ 3436 3437 static const struct usb_device_descriptor dwc_otg_devd = { 3438 .bLength = sizeof(struct usb_device_descriptor), 3439 .bDescriptorType = UDESC_DEVICE, 3440 .bcdUSB = {0x00, 0x02}, 3441 .bDeviceClass = UDCLASS_HUB, 3442 .bDeviceSubClass = UDSUBCLASS_HUB, 3443 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3444 .bMaxPacketSize = 64, 3445 .bcdDevice = {0x00, 0x01}, 3446 .iManufacturer = 1, 3447 .iProduct = 2, 3448 .bNumConfigurations = 1, 3449 }; 3450 3451 static const struct dwc_otg_config_desc dwc_otg_confd = { 3452 .confd = { 3453 .bLength = sizeof(struct usb_config_descriptor), 3454 .bDescriptorType = UDESC_CONFIG, 3455 .wTotalLength[0] = sizeof(dwc_otg_confd), 3456 .bNumInterface = 1, 3457 .bConfigurationValue = 1, 3458 .iConfiguration = 0, 3459 .bmAttributes = UC_SELF_POWERED, 3460 .bMaxPower = 0, 3461 }, 3462 .ifcd = { 3463 .bLength = sizeof(struct usb_interface_descriptor), 3464 .bDescriptorType = UDESC_INTERFACE, 3465 .bNumEndpoints = 1, 3466 .bInterfaceClass = UICLASS_HUB, 3467 .bInterfaceSubClass = UISUBCLASS_HUB, 3468 .bInterfaceProtocol = 0, 3469 }, 3470 .endpd = { 3471 .bLength = sizeof(struct usb_endpoint_descriptor), 3472 .bDescriptorType = UDESC_ENDPOINT, 3473 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 3474 .bmAttributes = UE_INTERRUPT, 3475 .wMaxPacketSize[0] = 8, 3476 .bInterval = 255, 3477 }, 3478 }; 3479 3480 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3481 3482 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 3483 .bDescLength = sizeof(dwc_otg_hubd), 3484 .bDescriptorType = UDESC_HUB, 3485 .bNbrPorts = 1, 3486 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3487 .bPwrOn2PwrGood = 50, 3488 .bHubContrCurrent = 0, 3489 .DeviceRemovable = {0}, /* port is removable */ 3490 }; 3491 3492 #define STRING_LANG \ 3493 0x09, 0x04, /* American English */ 3494 3495 #define STRING_VENDOR \ 3496 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 3497 3498 #define STRING_PRODUCT \ 3499 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 3500 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 3501 'U', 0, 'B', 0, 3502 3503 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 3504 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 3505 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 3506 3507 static usb_error_t 3508 dwc_otg_roothub_exec(struct usb_device *udev, 3509 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3510 { 3511 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3512 const void *ptr; 3513 uint16_t len; 3514 uint16_t value; 3515 uint16_t index; 3516 usb_error_t err; 3517 3518 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3519 3520 /* buffer reset */ 3521 ptr = (const void *)&sc->sc_hub_temp; 3522 len = 0; 3523 err = 0; 3524 3525 value = UGETW(req->wValue); 3526 index = UGETW(req->wIndex); 3527 3528 /* demultiplex the control request */ 3529 3530 switch (req->bmRequestType) { 3531 case UT_READ_DEVICE: 3532 switch (req->bRequest) { 3533 case UR_GET_DESCRIPTOR: 3534 goto tr_handle_get_descriptor; 3535 case UR_GET_CONFIG: 3536 goto tr_handle_get_config; 3537 case UR_GET_STATUS: 3538 goto tr_handle_get_status; 3539 default: 3540 goto tr_stalled; 3541 } 3542 break; 3543 3544 case UT_WRITE_DEVICE: 3545 switch (req->bRequest) { 3546 case UR_SET_ADDRESS: 3547 goto tr_handle_set_address; 3548 case UR_SET_CONFIG: 3549 goto tr_handle_set_config; 3550 case UR_CLEAR_FEATURE: 3551 goto tr_valid; /* nop */ 3552 case UR_SET_DESCRIPTOR: 3553 goto tr_valid; /* nop */ 3554 case UR_SET_FEATURE: 3555 default: 3556 goto tr_stalled; 3557 } 3558 break; 3559 3560 case UT_WRITE_ENDPOINT: 3561 switch (req->bRequest) { 3562 case UR_CLEAR_FEATURE: 3563 switch (UGETW(req->wValue)) { 3564 case UF_ENDPOINT_HALT: 3565 goto tr_handle_clear_halt; 3566 case UF_DEVICE_REMOTE_WAKEUP: 3567 goto tr_handle_clear_wakeup; 3568 default: 3569 goto tr_stalled; 3570 } 3571 break; 3572 case UR_SET_FEATURE: 3573 switch (UGETW(req->wValue)) { 3574 case UF_ENDPOINT_HALT: 3575 goto tr_handle_set_halt; 3576 case UF_DEVICE_REMOTE_WAKEUP: 3577 goto tr_handle_set_wakeup; 3578 default: 3579 goto tr_stalled; 3580 } 3581 break; 3582 case UR_SYNCH_FRAME: 3583 goto tr_valid; /* nop */ 3584 default: 3585 goto tr_stalled; 3586 } 3587 break; 3588 3589 case UT_READ_ENDPOINT: 3590 switch (req->bRequest) { 3591 case UR_GET_STATUS: 3592 goto tr_handle_get_ep_status; 3593 default: 3594 goto tr_stalled; 3595 } 3596 break; 3597 3598 case UT_WRITE_INTERFACE: 3599 switch (req->bRequest) { 3600 case UR_SET_INTERFACE: 3601 goto tr_handle_set_interface; 3602 case UR_CLEAR_FEATURE: 3603 goto tr_valid; /* nop */ 3604 case UR_SET_FEATURE: 3605 default: 3606 goto tr_stalled; 3607 } 3608 break; 3609 3610 case UT_READ_INTERFACE: 3611 switch (req->bRequest) { 3612 case UR_GET_INTERFACE: 3613 goto tr_handle_get_interface; 3614 case UR_GET_STATUS: 3615 goto tr_handle_get_iface_status; 3616 default: 3617 goto tr_stalled; 3618 } 3619 break; 3620 3621 case UT_WRITE_CLASS_INTERFACE: 3622 case UT_WRITE_VENDOR_INTERFACE: 3623 /* XXX forward */ 3624 break; 3625 3626 case UT_READ_CLASS_INTERFACE: 3627 case UT_READ_VENDOR_INTERFACE: 3628 /* XXX forward */ 3629 break; 3630 3631 case UT_WRITE_CLASS_DEVICE: 3632 switch (req->bRequest) { 3633 case UR_CLEAR_FEATURE: 3634 goto tr_valid; 3635 case UR_SET_DESCRIPTOR: 3636 case UR_SET_FEATURE: 3637 break; 3638 default: 3639 goto tr_stalled; 3640 } 3641 break; 3642 3643 case UT_WRITE_CLASS_OTHER: 3644 switch (req->bRequest) { 3645 case UR_CLEAR_FEATURE: 3646 goto tr_handle_clear_port_feature; 3647 case UR_SET_FEATURE: 3648 goto tr_handle_set_port_feature; 3649 case UR_CLEAR_TT_BUFFER: 3650 case UR_RESET_TT: 3651 case UR_STOP_TT: 3652 goto tr_valid; 3653 3654 default: 3655 goto tr_stalled; 3656 } 3657 break; 3658 3659 case UT_READ_CLASS_OTHER: 3660 switch (req->bRequest) { 3661 case UR_GET_TT_STATE: 3662 goto tr_handle_get_tt_state; 3663 case UR_GET_STATUS: 3664 goto tr_handle_get_port_status; 3665 default: 3666 goto tr_stalled; 3667 } 3668 break; 3669 3670 case UT_READ_CLASS_DEVICE: 3671 switch (req->bRequest) { 3672 case UR_GET_DESCRIPTOR: 3673 goto tr_handle_get_class_descriptor; 3674 case UR_GET_STATUS: 3675 goto tr_handle_get_class_status; 3676 3677 default: 3678 goto tr_stalled; 3679 } 3680 break; 3681 default: 3682 goto tr_stalled; 3683 } 3684 goto tr_valid; 3685 3686 tr_handle_get_descriptor: 3687 switch (value >> 8) { 3688 case UDESC_DEVICE: 3689 if (value & 0xff) { 3690 goto tr_stalled; 3691 } 3692 len = sizeof(dwc_otg_devd); 3693 ptr = (const void *)&dwc_otg_devd; 3694 goto tr_valid; 3695 case UDESC_CONFIG: 3696 if (value & 0xff) { 3697 goto tr_stalled; 3698 } 3699 len = sizeof(dwc_otg_confd); 3700 ptr = (const void *)&dwc_otg_confd; 3701 goto tr_valid; 3702 case UDESC_STRING: 3703 switch (value & 0xff) { 3704 case 0: /* Language table */ 3705 len = sizeof(dwc_otg_langtab); 3706 ptr = (const void *)&dwc_otg_langtab; 3707 goto tr_valid; 3708 3709 case 1: /* Vendor */ 3710 len = sizeof(dwc_otg_vendor); 3711 ptr = (const void *)&dwc_otg_vendor; 3712 goto tr_valid; 3713 3714 case 2: /* Product */ 3715 len = sizeof(dwc_otg_product); 3716 ptr = (const void *)&dwc_otg_product; 3717 goto tr_valid; 3718 default: 3719 break; 3720 } 3721 break; 3722 default: 3723 goto tr_stalled; 3724 } 3725 goto tr_stalled; 3726 3727 tr_handle_get_config: 3728 len = 1; 3729 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3730 goto tr_valid; 3731 3732 tr_handle_get_status: 3733 len = 2; 3734 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3735 goto tr_valid; 3736 3737 tr_handle_set_address: 3738 if (value & 0xFF00) { 3739 goto tr_stalled; 3740 } 3741 sc->sc_rt_addr = value; 3742 goto tr_valid; 3743 3744 tr_handle_set_config: 3745 if (value >= 2) { 3746 goto tr_stalled; 3747 } 3748 sc->sc_conf = value; 3749 goto tr_valid; 3750 3751 tr_handle_get_interface: 3752 len = 1; 3753 sc->sc_hub_temp.wValue[0] = 0; 3754 goto tr_valid; 3755 3756 tr_handle_get_tt_state: 3757 tr_handle_get_class_status: 3758 tr_handle_get_iface_status: 3759 tr_handle_get_ep_status: 3760 len = 2; 3761 USETW(sc->sc_hub_temp.wValue, 0); 3762 goto tr_valid; 3763 3764 tr_handle_set_halt: 3765 tr_handle_set_interface: 3766 tr_handle_set_wakeup: 3767 tr_handle_clear_wakeup: 3768 tr_handle_clear_halt: 3769 goto tr_valid; 3770 3771 tr_handle_clear_port_feature: 3772 if (index != 1) 3773 goto tr_stalled; 3774 3775 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3776 3777 switch (value) { 3778 case UHF_PORT_SUSPEND: 3779 dwc_otg_wakeup_peer(sc); 3780 break; 3781 3782 case UHF_PORT_ENABLE: 3783 if (sc->sc_flags.status_device_mode == 0) { 3784 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 3785 sc->sc_hprt_val | HPRT_PRTENA); 3786 } 3787 sc->sc_flags.port_enabled = 0; 3788 break; 3789 3790 case UHF_C_PORT_RESET: 3791 sc->sc_flags.change_reset = 0; 3792 break; 3793 3794 case UHF_C_PORT_ENABLE: 3795 sc->sc_flags.change_enabled = 0; 3796 break; 3797 3798 case UHF_C_PORT_OVER_CURRENT: 3799 sc->sc_flags.change_over_current = 0; 3800 break; 3801 3802 case UHF_PORT_TEST: 3803 case UHF_PORT_INDICATOR: 3804 /* nops */ 3805 break; 3806 3807 case UHF_PORT_POWER: 3808 sc->sc_flags.port_powered = 0; 3809 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3810 sc->sc_hprt_val = 0; 3811 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 3812 } 3813 dwc_otg_pull_down(sc); 3814 dwc_otg_clocks_off(sc); 3815 break; 3816 3817 case UHF_C_PORT_CONNECTION: 3818 /* clear connect change flag */ 3819 sc->sc_flags.change_connect = 0; 3820 break; 3821 3822 case UHF_C_PORT_SUSPEND: 3823 sc->sc_flags.change_suspend = 0; 3824 break; 3825 3826 default: 3827 err = USB_ERR_IOERROR; 3828 goto done; 3829 } 3830 goto tr_valid; 3831 3832 tr_handle_set_port_feature: 3833 if (index != 1) { 3834 goto tr_stalled; 3835 } 3836 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 3837 3838 switch (value) { 3839 case UHF_PORT_ENABLE: 3840 break; 3841 3842 case UHF_PORT_SUSPEND: 3843 if (sc->sc_flags.status_device_mode == 0) { 3844 /* set suspend BIT */ 3845 sc->sc_hprt_val |= HPRT_PRTSUSP; 3846 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3847 3848 /* generate HUB suspend event */ 3849 dwc_otg_suspend_irq(sc); 3850 } 3851 break; 3852 3853 case UHF_PORT_RESET: 3854 if (sc->sc_flags.status_device_mode == 0) { 3855 3856 DPRINTF("PORT RESET\n"); 3857 3858 /* enable PORT reset */ 3859 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 3860 3861 /* Wait 62.5ms for reset to complete */ 3862 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3863 3864 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3865 3866 /* Wait 62.5ms for reset to complete */ 3867 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3868 3869 /* reset FIFOs */ 3870 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 3871 3872 sc->sc_flags.change_reset = 1; 3873 } else { 3874 err = USB_ERR_IOERROR; 3875 } 3876 break; 3877 3878 case UHF_PORT_TEST: 3879 case UHF_PORT_INDICATOR: 3880 /* nops */ 3881 break; 3882 case UHF_PORT_POWER: 3883 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3884 sc->sc_hprt_val |= HPRT_PRTPWR; 3885 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3886 } 3887 sc->sc_flags.port_powered = 1; 3888 break; 3889 default: 3890 err = USB_ERR_IOERROR; 3891 goto done; 3892 } 3893 goto tr_valid; 3894 3895 tr_handle_get_port_status: 3896 3897 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 3898 3899 if (index != 1) 3900 goto tr_stalled; 3901 3902 if (sc->sc_flags.status_vbus) 3903 dwc_otg_clocks_on(sc); 3904 else 3905 dwc_otg_clocks_off(sc); 3906 3907 /* Select Device Side Mode */ 3908 3909 if (sc->sc_flags.status_device_mode) { 3910 value = UPS_PORT_MODE_DEVICE; 3911 dwc_otg_timer_stop(sc); 3912 } else { 3913 value = 0; 3914 dwc_otg_timer_start(sc); 3915 } 3916 3917 if (sc->sc_flags.status_high_speed) 3918 value |= UPS_HIGH_SPEED; 3919 else if (sc->sc_flags.status_low_speed) 3920 value |= UPS_LOW_SPEED; 3921 3922 if (sc->sc_flags.port_powered) 3923 value |= UPS_PORT_POWER; 3924 3925 if (sc->sc_flags.port_enabled) 3926 value |= UPS_PORT_ENABLED; 3927 3928 if (sc->sc_flags.port_over_current) 3929 value |= UPS_OVERCURRENT_INDICATOR; 3930 3931 if (sc->sc_flags.status_vbus && 3932 sc->sc_flags.status_bus_reset) 3933 value |= UPS_CURRENT_CONNECT_STATUS; 3934 3935 if (sc->sc_flags.status_suspend) 3936 value |= UPS_SUSPEND; 3937 3938 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3939 3940 value = 0; 3941 3942 if (sc->sc_flags.change_connect) 3943 value |= UPS_C_CONNECT_STATUS; 3944 if (sc->sc_flags.change_suspend) 3945 value |= UPS_C_SUSPEND; 3946 if (sc->sc_flags.change_reset) 3947 value |= UPS_C_PORT_RESET; 3948 if (sc->sc_flags.change_over_current) 3949 value |= UPS_C_OVERCURRENT_INDICATOR; 3950 3951 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3952 len = sizeof(sc->sc_hub_temp.ps); 3953 goto tr_valid; 3954 3955 tr_handle_get_class_descriptor: 3956 if (value & 0xFF) { 3957 goto tr_stalled; 3958 } 3959 ptr = (const void *)&dwc_otg_hubd; 3960 len = sizeof(dwc_otg_hubd); 3961 goto tr_valid; 3962 3963 tr_stalled: 3964 err = USB_ERR_STALLED; 3965 tr_valid: 3966 done: 3967 *plength = len; 3968 *pptr = ptr; 3969 return (err); 3970 } 3971 3972 static void 3973 dwc_otg_xfer_setup(struct usb_setup_params *parm) 3974 { 3975 const struct usb_hw_ep_profile *pf; 3976 struct usb_xfer *xfer; 3977 void *last_obj; 3978 uint32_t ntd; 3979 uint32_t n; 3980 uint8_t ep_no; 3981 3982 xfer = parm->curr_xfer; 3983 3984 /* 3985 * NOTE: This driver does not use any of the parameters that 3986 * are computed from the following values. Just set some 3987 * reasonable dummies: 3988 */ 3989 parm->hc_max_packet_size = 0x500; 3990 parm->hc_max_packet_count = 1; 3991 parm->hc_max_frame_size = 0x500; 3992 3993 usbd_transfer_setup_sub(parm); 3994 3995 /* 3996 * compute maximum number of TDs 3997 */ 3998 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 3999 4000 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4001 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4002 } else { 4003 4004 ntd = xfer->nframes + 1 /* SYNC */ ; 4005 } 4006 4007 /* 4008 * check if "usbd_transfer_setup_sub" set an error 4009 */ 4010 if (parm->err) 4011 return; 4012 4013 /* 4014 * allocate transfer descriptors 4015 */ 4016 last_obj = NULL; 4017 4018 /* 4019 * get profile stuff 4020 */ 4021 ep_no = xfer->endpointno & UE_ADDR; 4022 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4023 4024 if (pf == NULL) { 4025 /* should not happen */ 4026 parm->err = USB_ERR_INVAL; 4027 return; 4028 } 4029 4030 /* align data */ 4031 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4032 4033 for (n = 0; n != ntd; n++) { 4034 4035 struct dwc_otg_td *td; 4036 4037 if (parm->buf) { 4038 4039 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4040 4041 /* init TD */ 4042 td->max_packet_size = xfer->max_packet_size; 4043 td->ep_no = ep_no; 4044 td->obj_next = last_obj; 4045 4046 last_obj = td; 4047 } 4048 parm->size[0] += sizeof(*td); 4049 } 4050 4051 xfer->td_start[0] = last_obj; 4052 } 4053 4054 static void 4055 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4056 { 4057 return; 4058 } 4059 4060 static void 4061 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4062 struct usb_endpoint *ep) 4063 { 4064 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4065 4066 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4067 ep, udev->address, 4068 edesc->bEndpointAddress, udev->flags.usb_mode, 4069 sc->sc_rt_addr, udev->device_index); 4070 4071 if (udev->device_index != sc->sc_rt_addr) { 4072 4073 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4074 if (udev->speed != USB_SPEED_FULL && 4075 udev->speed != USB_SPEED_HIGH) { 4076 /* not supported */ 4077 return; 4078 } 4079 } else { 4080 uint16_t mps; 4081 4082 mps = UGETW(edesc->wMaxPacketSize); 4083 4084 /* Apply limitations of our USB host driver */ 4085 4086 switch (udev->speed) { 4087 case USB_SPEED_HIGH: 4088 if (mps > 512) { 4089 DPRINTF("wMaxPacketSize=0x%04x" 4090 "is not supported\n", (int)mps); 4091 /* not supported */ 4092 return; 4093 } 4094 break; 4095 4096 case USB_SPEED_FULL: 4097 case USB_SPEED_LOW: 4098 if (mps > 188) { 4099 DPRINTF("wMaxPacketSize=0x%04x" 4100 "is not supported\n", (int)mps); 4101 /* not supported */ 4102 return; 4103 } 4104 break; 4105 4106 default: 4107 DPRINTF("Invalid device speed\n"); 4108 /* not supported */ 4109 return; 4110 } 4111 } 4112 4113 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4114 ep->methods = &dwc_otg_device_isoc_methods; 4115 else 4116 ep->methods = &dwc_otg_device_non_isoc_methods; 4117 } 4118 } 4119 4120 static void 4121 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4122 { 4123 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4124 4125 switch (state) { 4126 case USB_HW_POWER_SUSPEND: 4127 dwc_otg_suspend(sc); 4128 break; 4129 case USB_HW_POWER_SHUTDOWN: 4130 dwc_otg_uninit(sc); 4131 break; 4132 case USB_HW_POWER_RESUME: 4133 dwc_otg_resume(sc); 4134 break; 4135 default: 4136 break; 4137 } 4138 } 4139 4140 static void 4141 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4142 { 4143 /* DMA delay - wait until any use of memory is finished */ 4144 *pus = (2125); /* microseconds */ 4145 } 4146 4147 static void 4148 dwc_otg_device_resume(struct usb_device *udev) 4149 { 4150 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4151 struct usb_xfer *xfer; 4152 struct dwc_otg_td *td; 4153 4154 DPRINTF("\n"); 4155 4156 /* Enable relevant Host channels before resuming */ 4157 4158 USB_BUS_LOCK(udev->bus); 4159 4160 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4161 4162 if (xfer->xroot->udev == udev) { 4163 4164 td = xfer->td_transfer_cache; 4165 if (td != NULL && 4166 td->channel < DWC_OTG_MAX_CHANNELS) 4167 sc->sc_chan_state[td->channel].suspended = 0; 4168 } 4169 } 4170 4171 USB_BUS_UNLOCK(udev->bus); 4172 4173 /* poll all transfers again to restart resumed ones */ 4174 dwc_otg_do_poll(udev->bus); 4175 } 4176 4177 static void 4178 dwc_otg_device_suspend(struct usb_device *udev) 4179 { 4180 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4181 struct usb_xfer *xfer; 4182 struct dwc_otg_td *td; 4183 4184 DPRINTF("\n"); 4185 4186 /* Disable relevant Host channels before going to suspend */ 4187 4188 USB_BUS_LOCK(udev->bus); 4189 4190 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 4191 4192 if (xfer->xroot->udev == udev) { 4193 4194 td = xfer->td_transfer_cache; 4195 if (td != NULL && 4196 td->channel < DWC_OTG_MAX_CHANNELS) 4197 sc->sc_chan_state[td->channel].suspended = 1; 4198 } 4199 } 4200 4201 USB_BUS_UNLOCK(udev->bus); 4202 } 4203 4204 struct usb_bus_methods dwc_otg_bus_methods = 4205 { 4206 .endpoint_init = &dwc_otg_ep_init, 4207 .xfer_setup = &dwc_otg_xfer_setup, 4208 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4209 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4210 .xfer_stall = &dwc_otg_xfer_stall, 4211 .set_stall = &dwc_otg_set_stall, 4212 .clear_stall = &dwc_otg_clear_stall, 4213 .roothub_exec = &dwc_otg_roothub_exec, 4214 .xfer_poll = &dwc_otg_do_poll, 4215 .device_state_change = &dwc_otg_device_state_change, 4216 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4217 .get_dma_delay = &dwc_otg_get_dma_delay, 4218 .device_resume = &dwc_otg_device_resume, 4219 .device_suspend = &dwc_otg_device_suspend, 4220 }; 4221