1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the DesignWare series USB 2.0 OTG 29 * Controller. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 #include <dev/usb/controller/dwc_otgreg.h> 85 86 #define DWC_OTG_BUS2SC(bus) \ 87 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 89 90 #define DWC_OTG_PC2SC(pc) \ 91 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 92 93 #define DWC_OTG_MSK_GINT_ENABLED \ 94 (GINTSTS_ENUMDONE | \ 95 GINTSTS_USBRST | \ 96 GINTSTS_USBSUSP | \ 97 GINTSTS_IEPINT | \ 98 GINTSTS_RXFLVL | \ 99 GINTSTS_SESSREQINT | \ 100 GINTMSK_OTGINTMSK | \ 101 GINTMSK_HCHINTMSK | \ 102 GINTSTS_PRTINT) 103 104 #define DWC_OTG_USE_HSIC 0 105 106 #ifdef USB_DEBUG 107 static int dwc_otg_debug = 0; 108 109 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 110 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 111 &dwc_otg_debug, 0, "DWC OTG debug level"); 112 #endif 113 114 #define DWC_OTG_INTR_ENDPT 1 115 116 /* prototypes */ 117 118 struct usb_bus_methods dwc_otg_bus_methods; 119 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 120 struct usb_pipe_methods dwc_otg_device_isoc_methods; 121 122 static dwc_otg_cmd_t dwc_otg_setup_rx; 123 static dwc_otg_cmd_t dwc_otg_data_rx; 124 static dwc_otg_cmd_t dwc_otg_data_tx; 125 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 126 127 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 128 static dwc_otg_cmd_t dwc_otg_host_data_tx; 129 static dwc_otg_cmd_t dwc_otg_host_data_rx; 130 131 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 132 static void dwc_otg_do_poll(struct usb_bus *); 133 static void dwc_otg_standard_done(struct usb_xfer *); 134 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 135 136 /* 137 * Here is a configuration that the chip supports. 138 */ 139 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 140 141 [0] = { 142 .max_in_frame_size = 64,/* fixed */ 143 .max_out_frame_size = 64, /* fixed */ 144 .is_simplex = 1, 145 .support_control = 1, 146 } 147 }; 148 149 static void 150 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 151 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 152 { 153 struct dwc_otg_softc *sc; 154 155 sc = DWC_OTG_BUS2SC(udev->bus); 156 157 if (ep_addr < sc->sc_dev_ep_max) 158 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 159 else 160 *ppf = NULL; 161 } 162 163 static void 164 dwc_otg_request_sof(struct dwc_otg_softc *sc) 165 { 166 sc->sc_sof_refs++; 167 sc->sc_irq_mask |= GINTMSK_SOFMSK; 168 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 169 } 170 171 static void 172 dwc_otg_release_sof(struct dwc_otg_softc *sc) 173 { 174 if (--(sc->sc_sof_refs) == 0) { 175 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 176 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 177 } 178 } 179 180 static int 181 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 182 { 183 struct dwc_otg_profile *pf; 184 uint32_t fifo_size; 185 uint32_t fifo_regs; 186 uint32_t tx_start; 187 uint8_t x; 188 189 fifo_size = sc->sc_fifo_size; 190 191 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 192 193 if (fifo_size >= fifo_regs) 194 fifo_size -= fifo_regs; 195 else 196 fifo_size = 0; 197 198 /* split equally for IN and OUT */ 199 fifo_size /= 2; 200 201 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 202 203 /* align to 4-bytes */ 204 fifo_size &= ~3; 205 206 tx_start = fifo_size; 207 208 if (fifo_size < 0x40) { 209 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 210 USB_BUS_UNLOCK(&sc->sc_bus); 211 return (EINVAL); 212 } 213 214 if (mode == DWC_MODE_HOST) { 215 216 /* reset active endpoints */ 217 sc->sc_active_rx_ep = 0; 218 219 fifo_size /= 2; 220 221 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 222 ((fifo_size / 4) << 16) | 223 (tx_start / 4)); 224 225 tx_start += fifo_size; 226 227 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 228 ((fifo_size / 4) << 16) | 229 (tx_start / 4)); 230 } 231 232 if (mode == DWC_MODE_DEVICE) { 233 234 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 235 (0x10 << 16) | (tx_start / 4)); 236 fifo_size -= 0x40; 237 tx_start += 0x40; 238 239 /* setup control endpoint profile */ 240 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 241 242 /* reset active endpoints */ 243 sc->sc_active_rx_ep = 1; 244 245 for (x = 1; x != sc->sc_dev_ep_max; x++) { 246 247 pf = sc->sc_hw_ep_profile + x; 248 249 pf->usb.max_out_frame_size = 1024 * 3; 250 pf->usb.is_simplex = 0; /* assume duplex */ 251 pf->usb.support_bulk = 1; 252 pf->usb.support_interrupt = 1; 253 pf->usb.support_isochronous = 1; 254 pf->usb.support_out = 1; 255 256 if (x < sc->sc_dev_in_ep_max) { 257 uint32_t limit; 258 259 limit = (x == 1) ? DWC_OTG_MAX_TXN : 260 (DWC_OTG_MAX_TXN / 2); 261 262 if (fifo_size >= limit) { 263 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 264 ((limit / 4) << 16) | 265 (tx_start / 4)); 266 tx_start += limit; 267 fifo_size -= limit; 268 pf->usb.max_in_frame_size = 0x200; 269 pf->usb.support_in = 1; 270 pf->max_buffer = limit; 271 272 } else if (fifo_size >= 0x80) { 273 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 274 ((0x80 / 4) << 16) | (tx_start / 4)); 275 tx_start += 0x80; 276 fifo_size -= 0x80; 277 pf->usb.max_in_frame_size = 0x40; 278 pf->usb.support_in = 1; 279 280 } else { 281 pf->usb.is_simplex = 1; 282 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 283 (0x0 << 16) | (tx_start / 4)); 284 } 285 } else { 286 pf->usb.is_simplex = 1; 287 } 288 289 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 290 pf->usb.max_in_frame_size, 291 pf->usb.max_out_frame_size); 292 } 293 } 294 295 /* reset RX FIFO */ 296 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 297 GRSTCTL_RXFFLSH); 298 299 if (mode != DWC_MODE_OTG) { 300 /* reset all TX FIFOs */ 301 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 302 GRSTCTL_TXFIFO(0x10) | 303 GRSTCTL_TXFFLSH); 304 } else { 305 /* reset active endpoints */ 306 sc->sc_active_rx_ep = 0; 307 } 308 return (0); 309 } 310 311 static void 312 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 313 { 314 if (sc->sc_flags.clocks_off && 315 sc->sc_flags.port_powered) { 316 317 DPRINTFN(5, "\n"); 318 319 /* TODO - platform specific */ 320 321 sc->sc_flags.clocks_off = 0; 322 } 323 } 324 325 static void 326 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 327 { 328 if (!sc->sc_flags.clocks_off) { 329 330 DPRINTFN(5, "\n"); 331 332 /* TODO - platform specific */ 333 334 sc->sc_flags.clocks_off = 1; 335 } 336 } 337 338 static void 339 dwc_otg_pull_up(struct dwc_otg_softc *sc) 340 { 341 uint32_t temp; 342 343 /* pullup D+, if possible */ 344 345 if (!sc->sc_flags.d_pulled_up && 346 sc->sc_flags.port_powered) { 347 sc->sc_flags.d_pulled_up = 1; 348 349 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 350 temp &= ~DCTL_SFTDISCON; 351 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 352 } 353 } 354 355 static void 356 dwc_otg_pull_down(struct dwc_otg_softc *sc) 357 { 358 uint32_t temp; 359 360 /* pulldown D+, if possible */ 361 362 if (sc->sc_flags.d_pulled_up) { 363 sc->sc_flags.d_pulled_up = 0; 364 365 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 366 temp |= DCTL_SFTDISCON; 367 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 368 } 369 } 370 371 static void 372 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 373 { 374 if (sc->sc_flags.status_suspend) { 375 /* update status bits */ 376 sc->sc_flags.status_suspend = 0; 377 sc->sc_flags.change_suspend = 1; 378 379 if (sc->sc_flags.status_device_mode) { 380 /* 381 * Disable resume interrupt and enable suspend 382 * interrupt: 383 */ 384 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 385 sc->sc_irq_mask |= GINTSTS_USBSUSP; 386 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 387 } 388 389 /* complete root HUB interrupt endpoint */ 390 dwc_otg_root_intr(sc); 391 } 392 } 393 394 static void 395 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 396 { 397 if (!sc->sc_flags.status_suspend) { 398 /* update status bits */ 399 sc->sc_flags.status_suspend = 1; 400 sc->sc_flags.change_suspend = 1; 401 402 if (sc->sc_flags.status_device_mode) { 403 /* 404 * Disable suspend interrupt and enable resume 405 * interrupt: 406 */ 407 sc->sc_irq_mask &= ~GINTSTS_USBSUSP; 408 sc->sc_irq_mask |= GINTSTS_WKUPINT; 409 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 410 } 411 412 /* complete root HUB interrupt endpoint */ 413 dwc_otg_root_intr(sc); 414 } 415 } 416 417 static void 418 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 419 { 420 if (!sc->sc_flags.status_suspend) 421 return; 422 423 DPRINTFN(5, "Remote wakeup\n"); 424 425 if (sc->sc_flags.status_device_mode) { 426 uint32_t temp; 427 428 /* enable remote wakeup signalling */ 429 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 430 temp |= DCTL_RMTWKUPSIG; 431 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 432 433 /* Wait 8ms for remote wakeup to complete. */ 434 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 435 436 temp &= ~DCTL_RMTWKUPSIG; 437 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 438 } else { 439 /* enable USB port */ 440 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 441 442 /* wait 10ms */ 443 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 444 445 /* resume port */ 446 sc->sc_hprt_val |= HPRT_PRTRES; 447 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 448 449 /* Wait 100ms for resume signalling to complete. */ 450 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 451 452 /* clear suspend and resume */ 453 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 454 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 455 456 /* Wait 4ms */ 457 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 458 } 459 460 /* need to fake resume IRQ */ 461 dwc_otg_resume_irq(sc); 462 } 463 464 static void 465 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 466 { 467 uint32_t temp; 468 469 DPRINTFN(5, "addr=%d\n", addr); 470 471 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 472 temp &= ~DCFG_DEVADDR_SET(0x7F); 473 temp |= DCFG_DEVADDR_SET(addr); 474 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 475 } 476 477 static void 478 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 479 { 480 DPRINTFN(5, "RX status clear\n"); 481 482 /* enable RX FIFO level interrupt */ 483 sc->sc_irq_mask |= GINTSTS_RXFLVL; 484 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 485 486 /* clear cached status */ 487 sc->sc_last_rx_status = 0; 488 } 489 490 static uint8_t 491 dwc_otg_host_channel_alloc(struct dwc_otg_td *td) 492 { 493 struct dwc_otg_softc *sc; 494 uint32_t temp; 495 uint8_t x; 496 uint8_t max_channel; 497 498 if (td->channel < DWC_OTG_MAX_CHANNELS) 499 return (0); /* already allocated */ 500 501 /* get pointer to softc */ 502 sc = DWC_OTG_PC2SC(td->pc); 503 504 if ((td->hcchar & HCCHAR_EPNUM_MASK) == 0) { 505 max_channel = 1; 506 x = 0; 507 } else { 508 max_channel = sc->sc_host_ch_max; 509 x = 1; 510 } 511 512 for (; x != max_channel; x++) { 513 if (sc->sc_chan_state[x].hcchar == 0) { 514 515 /* check if channel is enabled */ 516 temp = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 517 if (temp & HCCHAR_CHENA) { 518 DPRINTF("CH=%d is BUSY\n", x); 519 continue; 520 } 521 522 sc->sc_chan_state[x].hcchar = td->hcchar; 523 sc->sc_chan_state[x].hcsplt = td->hcsplt; 524 525 DPRINTF("HCCHAR=0x%08x(0x%08x) HCSPLT=0x%08x\n", 526 td->hcchar, temp, td->hcsplt); 527 528 /* clear leftover interrupts */ 529 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 530 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 531 532 /* clear buffered interrupts */ 533 sc->sc_chan_state[x].hcint = 0; 534 535 /* clear state */ 536 sc->sc_chan_state[x].state = 0; 537 538 /* we've requested SOF interrupt */ 539 sc->sc_chan_state[x].sof_requested = 1; 540 541 /* set channel */ 542 td->channel = x; 543 544 /* set active EP */ 545 sc->sc_active_rx_ep |= (1 << x); 546 547 /* request SOF's */ 548 dwc_otg_request_sof(sc); 549 550 return (0); /* allocated */ 551 } 552 } 553 return (1); /* busy */ 554 } 555 556 static uint8_t 557 dwc_otg_host_setup_tx(struct dwc_otg_td *td) 558 { 559 struct usb_device_request req __aligned(4); 560 struct dwc_otg_softc *sc; 561 uint32_t temp; 562 563 if (dwc_otg_host_channel_alloc(td)) 564 return (1); /* busy */ 565 566 /* get pointer to softc */ 567 sc = DWC_OTG_PC2SC(td->pc); 568 569 temp = sc->sc_chan_state[td->channel].hcint; 570 571 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 572 td->channel, sc->sc_chan_state[td->channel].state, temp, 573 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 574 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 575 576 if (temp & HCINT_STALL) { 577 td->error_stall = 1; 578 td->error_any = 1; 579 return (0); /* complete */ 580 } 581 582 if (temp & (HCINT_BBLERR | HCINT_XACTERR)) { 583 td->error_any = 1; 584 return (0); /* complete */ 585 } 586 587 if (temp & HCINT_NAK) { 588 if ((sc->sc_sof_val & 1) != (td->sof_val & 1)) 589 return (1); /* busy */ 590 td->sof_val += 1; 591 } 592 593 /* channel must be disabled before we can complete the transfer */ 594 595 if (temp & (HCINT_NAK | HCINT_ACK | HCINT_NYET)) { 596 uint32_t hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)); 597 if (hcchar & HCCHAR_CHENA) { 598 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), 599 HCCHAR_CHENA | HCCHAR_CHDIS); 600 } else { 601 sc->sc_chan_state[td->channel].hcint |= HCINT_CHHLTD; 602 } 603 } 604 605 switch (sc->sc_chan_state[td->channel].state) { 606 case DWC_CHAN_ST_START: 607 if (sc->sc_chan_state[td->channel].hcsplt != 0) { 608 sc->sc_chan_state[td->channel].hcsplt &= 609 ~HCSPLT_COMPSPLT; 610 sc->sc_chan_state[td->channel].state = 611 DWC_CHAN_ST_WAIT_S_ANE; 612 } else { 613 sc->sc_chan_state[td->channel].state = 614 DWC_CHAN_ST_WAIT_ANE; 615 } 616 goto send_pkt; 617 case DWC_CHAN_ST_WAIT_ANE: 618 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 619 break; 620 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 621 goto send_pkt; 622 if (sc->sc_chan_state[td->channel].hcint & 623 (HCINT_ACK | HCINT_NYET)) { 624 td->offset += td->tx_bytes; 625 td->remainder -= td->tx_bytes; 626 td->toggle = 1; 627 sc->sc_chan_state[td->channel].hcint = 0; 628 sc->sc_chan_state[td->channel].state = 0; 629 return (0); /* complete */ 630 } 631 break; 632 case DWC_CHAN_ST_WAIT_S_ANE: 633 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 634 break; 635 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 636 goto send_pkt; 637 if (sc->sc_chan_state[td->channel].hcint & 638 (HCINT_ACK | HCINT_NYET)) { 639 sc->sc_chan_state[td->channel].hcsplt |= HCSPLT_COMPSPLT; 640 sc->sc_chan_state[td->channel].state = 641 DWC_CHAN_ST_WAIT_C_ANE; 642 goto send_cpkt; 643 } 644 break; 645 case DWC_CHAN_ST_WAIT_C_ANE: 646 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 647 break; 648 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 649 goto send_cpkt; 650 if (sc->sc_chan_state[td->channel].hcint & 651 (HCINT_ACK | HCINT_NYET)) { 652 td->offset += td->tx_bytes; 653 td->remainder -= td->tx_bytes; 654 td->toggle = 1; 655 sc->sc_chan_state[td->channel].hcint = 0; 656 sc->sc_chan_state[td->channel].state = 0; 657 return (0); /* complete */ 658 } 659 break; 660 default: 661 break; 662 } 663 return (1); /* busy */ 664 665 send_pkt: 666 if (sizeof(req) != td->remainder) { 667 td->error_any = 1; 668 return (0); /* complete */ 669 } 670 671 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 672 673 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 674 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 675 (1 << HCTSIZ_PKTCNT_SHIFT) | 676 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 677 678 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 679 sc->sc_chan_state[td->channel].hcsplt); 680 681 temp = sc->sc_chan_state[td->channel].hcchar; 682 temp &= ~HCCHAR_EPDIR_IN; 683 684 /* must enable channel before writing data to FIFO */ 685 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 686 687 /* transfer data into FIFO */ 688 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 689 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 690 691 /* store number of bytes transmitted */ 692 td->tx_bytes = sizeof(req); 693 694 /* clear interrupts */ 695 sc->sc_chan_state[td->channel].hcint = 0; 696 697 return (1); /* busy */ 698 699 send_cpkt: 700 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 701 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 702 703 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 704 sc->sc_chan_state[td->channel].hcsplt); 705 706 temp = sc->sc_chan_state[td->channel].hcchar; 707 temp &= ~HCCHAR_EPDIR_IN; 708 709 /* must enable channel before writing data to FIFO */ 710 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 711 712 /* clear interrupts */ 713 sc->sc_chan_state[td->channel].hcint = 0; 714 715 return (1); /* busy */ 716 } 717 718 static uint8_t 719 dwc_otg_setup_rx(struct dwc_otg_td *td) 720 { 721 struct dwc_otg_softc *sc; 722 struct usb_device_request req __aligned(4); 723 uint32_t temp; 724 uint16_t count; 725 726 /* get pointer to softc */ 727 sc = DWC_OTG_PC2SC(td->pc); 728 729 /* check endpoint status */ 730 731 if (sc->sc_last_rx_status == 0) 732 goto not_complete; 733 734 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 735 goto not_complete; 736 737 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 738 GRXSTSRD_DPID_DATA0) { 739 /* release FIFO */ 740 dwc_otg_common_rx_ack(sc); 741 goto not_complete; 742 } 743 744 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 745 GRXSTSRD_STP_DATA) { 746 /* release FIFO */ 747 dwc_otg_common_rx_ack(sc); 748 goto not_complete; 749 } 750 751 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 752 753 /* clear did stall */ 754 td->did_stall = 0; 755 756 /* get the packet byte count */ 757 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 758 759 /* verify data length */ 760 if (count != td->remainder) { 761 DPRINTFN(0, "Invalid SETUP packet " 762 "length, %d bytes\n", count); 763 /* release FIFO */ 764 dwc_otg_common_rx_ack(sc); 765 goto not_complete; 766 } 767 if (count != sizeof(req)) { 768 DPRINTFN(0, "Unsupported SETUP packet " 769 "length, %d bytes\n", count); 770 /* release FIFO */ 771 dwc_otg_common_rx_ack(sc); 772 goto not_complete; 773 } 774 775 /* copy in control request */ 776 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 777 778 /* copy data into real buffer */ 779 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 780 781 td->offset = sizeof(req); 782 td->remainder = 0; 783 784 /* sneak peek the set address */ 785 if ((req.bmRequestType == UT_WRITE_DEVICE) && 786 (req.bRequest == UR_SET_ADDRESS)) { 787 /* must write address before ZLP */ 788 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 789 } 790 791 /* don't send any data by default */ 792 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 793 DXEPTSIZ_SET_NPKT(0) | 794 DXEPTSIZ_SET_NBYTES(0)); 795 796 temp = sc->sc_in_ctl[0]; 797 798 /* enable IN endpoint */ 799 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 800 temp | DIEPCTL_EPENA); 801 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 802 temp | DIEPCTL_SNAK); 803 804 /* reset IN endpoint buffer */ 805 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 806 GRSTCTL_TXFIFO(0) | 807 GRSTCTL_TXFFLSH); 808 809 /* acknowledge RX status */ 810 dwc_otg_common_rx_ack(sc); 811 return (0); /* complete */ 812 813 not_complete: 814 /* abort any ongoing transfer, before enabling again */ 815 816 temp = sc->sc_out_ctl[0]; 817 818 temp |= DOEPCTL_EPENA | 819 DOEPCTL_SNAK; 820 821 /* enable OUT endpoint */ 822 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 823 824 if (!td->did_stall) { 825 td->did_stall = 1; 826 827 DPRINTFN(5, "stalling IN and OUT direction\n"); 828 829 /* set stall after enabling endpoint */ 830 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 831 temp | DOEPCTL_STALL); 832 833 temp = sc->sc_in_ctl[0]; 834 835 /* set stall assuming endpoint is enabled */ 836 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 837 temp | DIEPCTL_STALL); 838 } 839 840 /* setup number of buffers to receive */ 841 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 842 DXEPTSIZ_SET_MULTI(3) | 843 DXEPTSIZ_SET_NPKT(1) | 844 DXEPTSIZ_SET_NBYTES(sizeof(req))); 845 846 return (1); /* not complete */ 847 } 848 849 static uint8_t 850 dwc_otg_host_data_rx(struct dwc_otg_td *td) 851 { 852 struct dwc_otg_softc *sc; 853 uint32_t temp; 854 uint16_t count; 855 uint8_t ep_type; 856 857 if (dwc_otg_host_channel_alloc(td)) 858 return (1); /* busy */ 859 860 /* get pointer to softc */ 861 sc = DWC_OTG_PC2SC(td->pc); 862 863 ep_type = ((sc->sc_chan_state[td->channel].hcchar & 864 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 865 866 temp = sc->sc_chan_state[td->channel].hcint; 867 868 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 869 td->channel, sc->sc_chan_state[td->channel].state, temp, 870 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 871 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 872 873 if (temp & HCINT_STALL) { 874 td->error_stall = 1; 875 td->error_any = 1; 876 return (0); /* complete */ 877 } 878 879 if (temp & (HCINT_BBLERR | HCINT_XACTERR)) { 880 td->error_any = 1; 881 return (0); /* complete */ 882 } 883 884 /* channel must be disabled before we can complete the transfer */ 885 886 if (temp & (HCINT_NAK | HCINT_ACK | HCINT_NYET)) { 887 uint32_t hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)); 888 if (hcchar & HCCHAR_CHENA) { 889 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), 890 HCCHAR_CHENA | HCCHAR_CHDIS); 891 } else { 892 sc->sc_chan_state[td->channel].hcint |= HCINT_CHHLTD; 893 } 894 } 895 896 /* check endpoint status */ 897 if (sc->sc_last_rx_status == 0) 898 goto not_complete; 899 900 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->channel) 901 goto not_complete; 902 903 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 904 case GRXSTSRH_IN_DATA: 905 906 DPRINTF("DATA\n"); 907 908 td->toggle ^= 1; 909 910 /* get the packet byte count */ 911 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 912 913 /* verify the packet byte count */ 914 if (count != td->max_packet_size) { 915 if (count < td->max_packet_size) { 916 /* we have a short packet */ 917 td->short_pkt = 1; 918 td->got_short = 1; 919 } else { 920 /* invalid USB packet */ 921 td->error_any = 1; 922 923 /* release FIFO */ 924 dwc_otg_common_rx_ack(sc); 925 return (0); /* we are complete */ 926 } 927 } 928 929 /* verify the packet byte count */ 930 if (count > td->remainder) { 931 /* invalid USB packet */ 932 td->error_any = 1; 933 934 /* release FIFO */ 935 dwc_otg_common_rx_ack(sc); 936 return (0); /* we are complete */ 937 } 938 939 usbd_copy_in(td->pc, td->offset, 940 sc->sc_rx_bounce_buffer, count); 941 942 td->remainder -= count; 943 td->offset += count; 944 sc->sc_chan_state[td->channel].hcint |= HCINT_SOFTWARE_ONLY; 945 break; 946 947 default: 948 DPRINTF("OTHER\n"); 949 break; 950 } 951 /* release FIFO */ 952 dwc_otg_common_rx_ack(sc); 953 954 not_complete: 955 if (temp & HCINT_SUSPEND_ONLY) 956 return (1); /* busy */ 957 958 if (ep_type == UE_ISOCHRONOUS) { 959 if ((sc->sc_sof_val & 0xFF) != td->sof_val) 960 return (1); /* busy */ 961 if (td->sof_val & 1) 962 sc->sc_chan_state[td->channel].hcchar |= HCCHAR_ODDFRM; 963 else 964 sc->sc_chan_state[td->channel].hcchar &= ~HCCHAR_ODDFRM; 965 td->sof_val += td->sof_res; 966 } else if (ep_type == UE_INTERRUPT) { 967 if ((sc->sc_sof_val & 0xFF) != td->sof_val) 968 return (1); /* busy */ 969 td->sof_val += td->sof_res; 970 } else if (temp & HCINT_NAK) { 971 if ((sc->sc_sof_val & 1) != (td->sof_val & 1)) 972 return (1); /* busy */ 973 td->sof_val += 1; 974 } 975 976 switch (sc->sc_chan_state[td->channel].state) { 977 case DWC_CHAN_ST_START: 978 if (sc->sc_chan_state[td->channel].hcsplt != 0) { 979 sc->sc_chan_state[td->channel].hcsplt &= 980 ~HCSPLT_COMPSPLT; 981 sc->sc_chan_state[td->channel].state = 982 DWC_CHAN_ST_WAIT_S_ANE; 983 goto receive_spkt; 984 } else { 985 sc->sc_chan_state[td->channel].state = 986 DWC_CHAN_ST_WAIT_ANE; 987 goto receive_pkt; 988 } 989 case DWC_CHAN_ST_WAIT_ANE: 990 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 991 break; 992 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 993 goto receive_pkt; 994 if (!(sc->sc_chan_state[td->channel].hcint & 995 HCINT_SOFTWARE_ONLY)) 996 break; 997 if (sc->sc_chan_state[td->channel].hcint & 998 (HCINT_ACK | HCINT_NYET)) { 999 /* check if we are complete */ 1000 if ((td->remainder == 0) || (td->got_short != 0)) { 1001 if (td->short_pkt) { 1002 /* we are complete */ 1003 sc->sc_chan_state[ 1004 td->channel].hcint = 0; 1005 sc->sc_chan_state[ 1006 td->channel].state = 0; 1007 return (0); 1008 } 1009 /* 1010 * Else need to receive a zero length 1011 * packet. 1012 */ 1013 } 1014 if (sc->sc_chan_state[td->channel].hcsplt != 0) { 1015 sc->sc_chan_state[td->channel].hcsplt &= 1016 ~HCSPLT_COMPSPLT; 1017 sc->sc_chan_state[td->channel].state = 1018 DWC_CHAN_ST_WAIT_S_ANE; 1019 goto receive_spkt; 1020 } else { 1021 sc->sc_chan_state[td->channel].state = 1022 DWC_CHAN_ST_WAIT_ANE; 1023 goto receive_pkt; 1024 } 1025 } 1026 break; 1027 case DWC_CHAN_ST_WAIT_S_ANE: 1028 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 1029 break; 1030 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 1031 goto receive_spkt; 1032 if (sc->sc_chan_state[td->channel].hcint & (HCINT_ACK | HCINT_NYET)) { 1033 sc->sc_chan_state[td->channel].hcsplt |= 1034 HCSPLT_COMPSPLT; 1035 sc->sc_chan_state[td->channel].state = 1036 DWC_CHAN_ST_WAIT_ANE; 1037 goto receive_pkt; 1038 } 1039 break; 1040 default: 1041 break; 1042 } 1043 return (1); /* busy */ 1044 1045 receive_pkt: 1046 if (ep_type == UE_ISOCHRONOUS) { 1047 td->toggle = 0; 1048 } else if (td->set_toggle) { 1049 td->set_toggle = 0; 1050 td->toggle = 1; 1051 } 1052 1053 /* receive one packet */ 1054 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1055 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1056 (1 << HCTSIZ_PKTCNT_SHIFT) | 1057 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1058 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1059 1060 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 1061 sc->sc_chan_state[td->channel].hcsplt); 1062 1063 temp = sc->sc_chan_state[td->channel].hcchar; 1064 temp |= HCCHAR_EPDIR_IN; 1065 1066 /* must enable channel before data can be received */ 1067 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 1068 1069 /* clear interrupts */ 1070 sc->sc_chan_state[td->channel].hcint = 0; 1071 1072 return (1); /* busy */ 1073 1074 receive_spkt: 1075 if (ep_type == UE_ISOCHRONOUS) { 1076 td->toggle = 0; 1077 } else if (td->set_toggle) { 1078 td->set_toggle = 0; 1079 td->toggle = 1; 1080 } 1081 1082 /* receive one packet */ 1083 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1084 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1085 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1086 1087 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 1088 sc->sc_chan_state[td->channel].hcsplt); 1089 1090 temp = sc->sc_chan_state[td->channel].hcchar; 1091 temp |= HCCHAR_EPDIR_IN; 1092 1093 /* must enable channel before data can be received */ 1094 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 1095 1096 /* clear interrupts */ 1097 sc->sc_chan_state[td->channel].hcint = 0; 1098 1099 return (1); /* busy */ 1100 } 1101 1102 static uint8_t 1103 dwc_otg_data_rx(struct dwc_otg_td *td) 1104 { 1105 struct dwc_otg_softc *sc; 1106 uint32_t temp; 1107 uint16_t count; 1108 uint8_t got_short; 1109 1110 got_short = 0; 1111 1112 /* get pointer to softc */ 1113 sc = DWC_OTG_PC2SC(td->pc); 1114 1115 /* check endpoint status */ 1116 if (sc->sc_last_rx_status == 0) 1117 goto not_complete; 1118 1119 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1120 goto not_complete; 1121 1122 /* check for SETUP packet */ 1123 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1124 GRXSTSRD_STP_DATA) { 1125 if (td->remainder == 0) { 1126 /* 1127 * We are actually complete and have 1128 * received the next SETUP 1129 */ 1130 DPRINTFN(5, "faking complete\n"); 1131 return (0); /* complete */ 1132 } 1133 /* 1134 * USB Host Aborted the transfer. 1135 */ 1136 td->error_any = 1; 1137 return (0); /* complete */ 1138 } 1139 1140 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1141 GRXSTSRD_OUT_DATA) { 1142 /* release FIFO */ 1143 dwc_otg_common_rx_ack(sc); 1144 goto not_complete; 1145 } 1146 1147 /* get the packet byte count */ 1148 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1149 1150 /* verify the packet byte count */ 1151 if (count != td->max_packet_size) { 1152 if (count < td->max_packet_size) { 1153 /* we have a short packet */ 1154 td->short_pkt = 1; 1155 got_short = 1; 1156 } else { 1157 /* invalid USB packet */ 1158 td->error_any = 1; 1159 1160 /* release FIFO */ 1161 dwc_otg_common_rx_ack(sc); 1162 return (0); /* we are complete */ 1163 } 1164 } 1165 /* verify the packet byte count */ 1166 if (count > td->remainder) { 1167 /* invalid USB packet */ 1168 td->error_any = 1; 1169 1170 /* release FIFO */ 1171 dwc_otg_common_rx_ack(sc); 1172 return (0); /* we are complete */ 1173 } 1174 1175 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1176 td->remainder -= count; 1177 td->offset += count; 1178 1179 /* release FIFO */ 1180 dwc_otg_common_rx_ack(sc); 1181 1182 /* check if we are complete */ 1183 if ((td->remainder == 0) || got_short) { 1184 if (td->short_pkt) { 1185 /* we are complete */ 1186 return (0); 1187 } 1188 /* else need to receive a zero length packet */ 1189 } 1190 1191 not_complete: 1192 1193 temp = sc->sc_out_ctl[td->ep_no]; 1194 1195 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1196 1197 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1198 1199 /* enable SETUP and transfer complete interrupt */ 1200 if (td->ep_no == 0) { 1201 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1202 DXEPTSIZ_SET_NPKT(1) | 1203 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1204 } else { 1205 /* allow reception of multiple packets */ 1206 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1207 DXEPTSIZ_SET_MULTI(1) | 1208 DXEPTSIZ_SET_NPKT(4) | 1209 DXEPTSIZ_SET_NBYTES(4 * 1210 ((td->max_packet_size + 3) & ~3))); 1211 } 1212 return (1); /* not complete */ 1213 } 1214 1215 static uint8_t 1216 dwc_otg_host_data_tx(struct dwc_otg_td *td) 1217 { 1218 struct dwc_otg_softc *sc; 1219 uint32_t count; 1220 uint32_t temp; 1221 uint8_t ep_type; 1222 1223 if (dwc_otg_host_channel_alloc(td)) 1224 return (1); /* busy */ 1225 1226 /* get pointer to softc */ 1227 sc = DWC_OTG_PC2SC(td->pc); 1228 1229 ep_type = ((sc->sc_chan_state[td->channel].hcchar & 1230 HCCHAR_EPTYPE_MASK) >> HCCHAR_EPTYPE_SHIFT); 1231 1232 temp = sc->sc_chan_state[td->channel].hcint; 1233 1234 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1235 td->channel, sc->sc_chan_state[td->channel].state, temp, 1236 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 1237 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 1238 1239 if (temp & HCINT_STALL) { 1240 td->error_stall = 1; 1241 td->error_any = 1; 1242 return (0); /* complete */ 1243 } 1244 1245 if (temp & (HCINT_BBLERR | HCINT_XACTERR)) { 1246 td->error_any = 1; 1247 return (0); /* complete */ 1248 } 1249 1250 /* channel must be disabled before we can complete the transfer */ 1251 1252 if (temp & (HCINT_NAK | HCINT_ACK | HCINT_NYET)) { 1253 uint32_t hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)); 1254 if (hcchar & HCCHAR_CHENA) { 1255 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), 1256 HCCHAR_CHENA | HCCHAR_CHDIS); 1257 } else { 1258 sc->sc_chan_state[td->channel].hcint |= HCINT_CHHLTD; 1259 } 1260 } 1261 1262 if (ep_type == UE_ISOCHRONOUS) { 1263 if ((sc->sc_sof_val & 0xFF) != td->sof_val) 1264 return (1); /* busy */ 1265 if (td->sof_val & 1) 1266 sc->sc_chan_state[td->channel].hcchar |= HCCHAR_ODDFRM; 1267 else 1268 sc->sc_chan_state[td->channel].hcchar &= ~HCCHAR_ODDFRM; 1269 td->sof_val += td->sof_res; 1270 } else if (ep_type == UE_INTERRUPT) { 1271 if ((sc->sc_sof_val & 0xFF) != td->sof_val) 1272 return (1); /* busy */ 1273 td->sof_val += td->sof_res; 1274 } else if (temp & HCINT_NAK) { 1275 if ((sc->sc_sof_val & 1) != (td->sof_val & 1)) 1276 return (1); /* busy */ 1277 td->sof_val += 1; 1278 } 1279 1280 switch (sc->sc_chan_state[td->channel].state) { 1281 case DWC_CHAN_ST_START: 1282 if (sc->sc_chan_state[td->channel].hcsplt != 0) { 1283 sc->sc_chan_state[td->channel].hcsplt &= ~HCSPLT_COMPSPLT; 1284 sc->sc_chan_state[td->channel].state = 1285 DWC_CHAN_ST_WAIT_S_ANE; 1286 } else { 1287 sc->sc_chan_state[td->channel].state = 1288 DWC_CHAN_ST_WAIT_ANE; 1289 } 1290 goto send_pkt; 1291 case DWC_CHAN_ST_WAIT_ANE: 1292 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 1293 break; 1294 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 1295 goto send_pkt; 1296 if (sc->sc_chan_state[td->channel].hcint & 1297 (HCINT_ACK | HCINT_NYET)) { 1298 td->offset += td->tx_bytes; 1299 td->remainder -= td->tx_bytes; 1300 td->toggle ^= 1; 1301 1302 /* check remainder */ 1303 if (td->remainder == 0) { 1304 if (td->short_pkt) { 1305 sc->sc_chan_state[td->channel].hcint = 0; 1306 sc->sc_chan_state[td->channel].state = 0; 1307 return (0); /* complete */ 1308 } 1309 1310 /* else we need to transmit a short packet */ 1311 } 1312 goto send_pkt; 1313 } 1314 break; 1315 case DWC_CHAN_ST_WAIT_S_ANE: 1316 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 1317 break; 1318 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 1319 goto send_pkt; 1320 if (sc->sc_chan_state[td->channel].hcint & 1321 (HCINT_ACK | HCINT_NYET)) { 1322 sc->sc_chan_state[td->channel].hcsplt |= HCSPLT_COMPSPLT; 1323 sc->sc_chan_state[td->channel].state = 1324 DWC_CHAN_ST_WAIT_C_ANE; 1325 goto send_cpkt; 1326 } 1327 break; 1328 case DWC_CHAN_ST_WAIT_C_ANE: 1329 if (!(sc->sc_chan_state[td->channel].hcint & HCINT_CHHLTD)) 1330 break; 1331 if (sc->sc_chan_state[td->channel].hcint & HCINT_NAK) 1332 goto send_cpkt; 1333 if (sc->sc_chan_state[td->channel].hcint & 1334 (HCINT_ACK | HCINT_NYET)) { 1335 td->offset += td->tx_bytes; 1336 td->remainder -= td->tx_bytes; 1337 td->toggle ^= 1; 1338 1339 /* check remainder */ 1340 if (td->remainder == 0) { 1341 if (td->short_pkt) { 1342 sc->sc_chan_state[ 1343 td->channel].hcint = 0; 1344 sc->sc_chan_state[ 1345 td->channel].state = 0; 1346 return (0); /* complete */ 1347 } 1348 1349 /* else we need to transmit a short packet */ 1350 } 1351 sc->sc_chan_state[td->channel].hcsplt &= 1352 ~HCSPLT_COMPSPLT; 1353 sc->sc_chan_state[td->channel].state = 1354 DWC_CHAN_ST_WAIT_S_ANE; 1355 goto send_pkt; 1356 } 1357 break; 1358 default: 1359 break; 1360 } 1361 return (1); /* busy */ 1362 1363 send_pkt: 1364 if (ep_type == UE_ISOCHRONOUS) { 1365 td->toggle = 0; 1366 } else if (td->set_toggle) { 1367 td->set_toggle = 0; 1368 td->toggle = 1; 1369 } 1370 1371 /* send one packet at a time */ 1372 count = td->max_packet_size; 1373 if (td->remainder < count) { 1374 /* we have a short packet */ 1375 td->short_pkt = 1; 1376 count = td->remainder; 1377 } 1378 1379 /* TODO: HCTSIZ_DOPNG */ 1380 1381 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1382 (count << HCTSIZ_XFERSIZE_SHIFT) | 1383 (1 << HCTSIZ_PKTCNT_SHIFT) | 1384 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1385 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1386 1387 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 1388 sc->sc_chan_state[td->channel].hcsplt); 1389 1390 temp = sc->sc_chan_state[td->channel].hcchar; 1391 temp &= ~HCCHAR_EPDIR_IN; 1392 1393 /* must enable before writing data to FIFO */ 1394 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 1395 1396 if (count != 0) { 1397 1398 /* clear topmost word before copy */ 1399 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1400 1401 /* copy out data */ 1402 usbd_copy_out(td->pc, td->offset, 1403 sc->sc_tx_bounce_buffer, count); 1404 1405 /* transfer data into FIFO */ 1406 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1407 DOTG_DFIFO(td->channel), 1408 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1409 } 1410 1411 /* store number of bytes transmitted */ 1412 td->tx_bytes = count; 1413 1414 /* clear interrupts */ 1415 sc->sc_chan_state[td->channel].hcint = 0; 1416 1417 return (1); /* busy */ 1418 1419 send_cpkt: 1420 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 1421 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1422 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1423 1424 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), 1425 sc->sc_chan_state[td->channel].hcsplt); 1426 1427 temp = sc->sc_chan_state[td->channel].hcchar; 1428 temp &= ~HCCHAR_EPDIR_IN; 1429 1430 /* must enable channel before writing data to FIFO */ 1431 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), temp); 1432 1433 /* clear interrupts */ 1434 sc->sc_chan_state[td->channel].hcint = 0; 1435 1436 return (1); /* busy */ 1437 } 1438 1439 static uint8_t 1440 dwc_otg_data_tx(struct dwc_otg_td *td) 1441 { 1442 struct dwc_otg_softc *sc; 1443 uint32_t max_buffer; 1444 uint32_t count; 1445 uint32_t fifo_left; 1446 uint32_t mpkt; 1447 uint32_t temp; 1448 uint8_t to; 1449 1450 to = 3; /* don't loop forever! */ 1451 1452 /* get pointer to softc */ 1453 sc = DWC_OTG_PC2SC(td->pc); 1454 1455 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1456 1457 repeat: 1458 /* check for for endpoint 0 data */ 1459 1460 temp = sc->sc_last_rx_status; 1461 1462 if ((td->ep_no == 0) && (temp != 0) && 1463 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1464 1465 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1466 GRXSTSRD_STP_DATA) { 1467 1468 /* dump data - wrong direction */ 1469 dwc_otg_common_rx_ack(sc); 1470 } else { 1471 /* 1472 * The current transfer was cancelled 1473 * by the USB Host: 1474 */ 1475 td->error_any = 1; 1476 return (0); /* complete */ 1477 } 1478 } 1479 1480 /* fill in more TX data, if possible */ 1481 if (td->tx_bytes != 0) { 1482 1483 uint16_t cpkt; 1484 1485 /* check if packets have been transferred */ 1486 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1487 1488 /* get current packet number */ 1489 cpkt = DXEPTSIZ_GET_NPKT(temp); 1490 1491 if (cpkt >= td->npkt) { 1492 fifo_left = 0; 1493 } else { 1494 if (max_buffer != 0) { 1495 fifo_left = (td->npkt - cpkt) * 1496 td->max_packet_size; 1497 1498 if (fifo_left > max_buffer) 1499 fifo_left = max_buffer; 1500 } else { 1501 fifo_left = td->max_packet_size; 1502 } 1503 } 1504 1505 count = td->tx_bytes; 1506 if (count > fifo_left) 1507 count = fifo_left; 1508 1509 if (count != 0) { 1510 1511 /* clear topmost word before copy */ 1512 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1513 1514 /* copy out data */ 1515 usbd_copy_out(td->pc, td->offset, 1516 sc->sc_tx_bounce_buffer, count); 1517 1518 /* transfer data into FIFO */ 1519 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1520 DOTG_DFIFO(td->ep_no), 1521 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1522 1523 td->tx_bytes -= count; 1524 td->remainder -= count; 1525 td->offset += count; 1526 td->npkt = cpkt; 1527 } 1528 if (td->tx_bytes != 0) 1529 goto not_complete; 1530 1531 /* check remainder */ 1532 if (td->remainder == 0) { 1533 if (td->short_pkt) 1534 return (0); /* complete */ 1535 1536 /* else we need to transmit a short packet */ 1537 } 1538 } 1539 1540 if (!to--) 1541 goto not_complete; 1542 1543 /* check if not all packets have been transferred */ 1544 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1545 1546 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1547 1548 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 1549 "DIEPCTL=0x%08x\n", td->ep_no, 1550 DXEPTSIZ_GET_NPKT(temp), 1551 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 1552 1553 goto not_complete; 1554 } 1555 1556 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 1557 1558 /* try to optimise by sending more data */ 1559 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 1560 1561 /* send multiple packets at the same time */ 1562 mpkt = max_buffer / td->max_packet_size; 1563 1564 if (mpkt > 0x3FE) 1565 mpkt = 0x3FE; 1566 1567 count = td->remainder; 1568 if (count > 0x7FFFFF) 1569 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 1570 1571 td->npkt = count / td->max_packet_size; 1572 1573 /* 1574 * NOTE: We could use 0x3FE instead of "mpkt" in the 1575 * check below to get more throughput, but then we 1576 * have a dependency towards non-generic chip features 1577 * to disable the TX-FIFO-EMPTY interrupts on a per 1578 * endpoint basis. Increase the maximum buffer size of 1579 * the IN endpoint to increase the performance. 1580 */ 1581 if (td->npkt > mpkt) { 1582 td->npkt = mpkt; 1583 count = td->max_packet_size * mpkt; 1584 } else if ((count == 0) || (count % td->max_packet_size)) { 1585 /* we are transmitting a short packet */ 1586 td->npkt++; 1587 td->short_pkt = 1; 1588 } 1589 } else { 1590 /* send one packet at a time */ 1591 mpkt = 1; 1592 count = td->max_packet_size; 1593 if (td->remainder < count) { 1594 /* we have a short packet */ 1595 td->short_pkt = 1; 1596 count = td->remainder; 1597 } 1598 td->npkt = 1; 1599 } 1600 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 1601 DXEPTSIZ_SET_MULTI(1) | 1602 DXEPTSIZ_SET_NPKT(td->npkt) | 1603 DXEPTSIZ_SET_NBYTES(count)); 1604 1605 /* make room for buffering */ 1606 td->npkt += mpkt; 1607 1608 temp = sc->sc_in_ctl[td->ep_no]; 1609 1610 /* must enable before writing data to FIFO */ 1611 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 1612 DIEPCTL_EPENA | 1613 DIEPCTL_CNAK); 1614 1615 td->tx_bytes = count; 1616 1617 /* check remainder */ 1618 if (td->tx_bytes == 0 && 1619 td->remainder == 0) { 1620 if (td->short_pkt) 1621 return (0); /* complete */ 1622 1623 /* else we need to transmit a short packet */ 1624 } 1625 goto repeat; 1626 1627 not_complete: 1628 return (1); /* not complete */ 1629 } 1630 1631 static uint8_t 1632 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 1633 { 1634 struct dwc_otg_softc *sc; 1635 uint32_t temp; 1636 1637 /* get pointer to softc */ 1638 sc = DWC_OTG_PC2SC(td->pc); 1639 1640 /* 1641 * If all packets are transferred we are complete: 1642 */ 1643 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 1644 1645 /* check that all packets have been transferred */ 1646 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 1647 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 1648 goto not_complete; 1649 } 1650 return (0); 1651 1652 not_complete: 1653 1654 /* we only want to know if there is a SETUP packet or free IN packet */ 1655 1656 temp = sc->sc_last_rx_status; 1657 1658 if ((td->ep_no == 0) && (temp != 0) && 1659 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1660 1661 if ((temp & GRXSTSRD_PKTSTS_MASK) == 1662 GRXSTSRD_STP_DATA) { 1663 DPRINTFN(5, "faking complete\n"); 1664 /* 1665 * Race condition: We are complete! 1666 */ 1667 return (0); 1668 } else { 1669 /* dump data - wrong direction */ 1670 dwc_otg_common_rx_ack(sc); 1671 } 1672 } 1673 return (1); /* not complete */ 1674 } 1675 1676 static uint8_t 1677 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 1678 { 1679 struct dwc_otg_td *td; 1680 uint8_t toggle; 1681 uint8_t channel; 1682 uint8_t sof_val; 1683 uint8_t sof_res; 1684 1685 DPRINTFN(9, "\n"); 1686 1687 td = xfer->td_transfer_cache; 1688 while (1) { 1689 if ((td->func) (td)) { 1690 /* operation in progress */ 1691 break; 1692 } 1693 if (((void *)td) == xfer->td_transfer_last) { 1694 goto done; 1695 } 1696 if (td->error_any) { 1697 goto done; 1698 } else if (td->remainder > 0) { 1699 /* 1700 * We had a short transfer. If there is no alternate 1701 * next, stop processing ! 1702 */ 1703 if (!td->alt_next) 1704 goto done; 1705 } 1706 1707 /* 1708 * Fetch the next transfer descriptor and transfer 1709 * some flags to the next transfer descriptor 1710 */ 1711 sof_res = td->sof_res; 1712 sof_val = td->sof_val; 1713 toggle = td->toggle; 1714 channel = td->channel; 1715 td = td->obj_next; 1716 xfer->td_transfer_cache = td; 1717 td->toggle = toggle; /* transfer toggle */ 1718 td->channel = channel; /* transfer channel */ 1719 td->sof_res = sof_res; 1720 td->sof_val = sof_val; 1721 } 1722 return (1); /* not complete */ 1723 1724 done: 1725 /* compute all actual lengths */ 1726 1727 dwc_otg_standard_done(xfer); 1728 return (0); /* complete */ 1729 } 1730 1731 static void 1732 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 1733 { 1734 struct usb_xfer *xfer; 1735 uint32_t temp; 1736 uint8_t got_rx_status; 1737 1738 repeat: 1739 if (sc->sc_last_rx_status == 0) { 1740 1741 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 1742 if (temp & GINTSTS_RXFLVL) { 1743 /* pop current status */ 1744 sc->sc_last_rx_status = 1745 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 1746 } 1747 1748 if (sc->sc_last_rx_status != 0) { 1749 1750 uint8_t ep_no; 1751 1752 temp = sc->sc_last_rx_status & 1753 GRXSTSRD_PKTSTS_MASK; 1754 1755 /* non-data messages we simply skip */ 1756 if (temp != GRXSTSRD_STP_DATA && 1757 temp != GRXSTSRD_OUT_DATA) { 1758 dwc_otg_common_rx_ack(sc); 1759 goto repeat; 1760 } 1761 1762 temp = GRXSTSRD_BCNT_GET( 1763 sc->sc_last_rx_status); 1764 ep_no = GRXSTSRD_CHNUM_GET( 1765 sc->sc_last_rx_status); 1766 1767 /* receive data, if any */ 1768 if (temp != 0) { 1769 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 1770 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1771 DOTG_DFIFO(ep_no), 1772 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 1773 } 1774 1775 /* check if we should dump the data */ 1776 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 1777 dwc_otg_common_rx_ack(sc); 1778 goto repeat; 1779 } 1780 1781 got_rx_status = 1; 1782 1783 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 1784 sc->sc_last_rx_status, ep_no, 1785 (sc->sc_last_rx_status >> 15) & 3, 1786 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 1787 (sc->sc_last_rx_status >> 17) & 15); 1788 } else { 1789 got_rx_status = 0; 1790 } 1791 } else { 1792 uint8_t ep_no; 1793 1794 ep_no = GRXSTSRD_CHNUM_GET( 1795 sc->sc_last_rx_status); 1796 1797 /* check if we should dump the data */ 1798 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 1799 dwc_otg_common_rx_ack(sc); 1800 goto repeat; 1801 } 1802 1803 got_rx_status = 1; 1804 } 1805 1806 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1807 if (!dwc_otg_xfer_do_fifo(xfer)) { 1808 /* queue has been modified */ 1809 goto repeat; 1810 } 1811 } 1812 1813 if (got_rx_status) { 1814 /* check if data was consumed */ 1815 if (sc->sc_last_rx_status == 0) 1816 goto repeat; 1817 1818 /* disable RX FIFO level interrupt */ 1819 sc->sc_irq_mask &= ~GINTSTS_RXFLVL; 1820 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1821 } 1822 } 1823 1824 static void 1825 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 1826 { 1827 DPRINTFN(5, "vbus = %u\n", is_on); 1828 1829 if (is_on) { 1830 if (!sc->sc_flags.status_vbus) { 1831 sc->sc_flags.status_vbus = 1; 1832 1833 /* complete root HUB interrupt endpoint */ 1834 1835 dwc_otg_root_intr(sc); 1836 } 1837 } else { 1838 if (sc->sc_flags.status_vbus) { 1839 sc->sc_flags.status_vbus = 0; 1840 sc->sc_flags.status_bus_reset = 0; 1841 sc->sc_flags.status_suspend = 0; 1842 sc->sc_flags.change_suspend = 0; 1843 sc->sc_flags.change_connect = 1; 1844 1845 /* complete root HUB interrupt endpoint */ 1846 1847 dwc_otg_root_intr(sc); 1848 } 1849 } 1850 } 1851 1852 void 1853 dwc_otg_interrupt(struct dwc_otg_softc *sc) 1854 { 1855 uint32_t status; 1856 uint8_t x; 1857 1858 USB_BUS_LOCK(&sc->sc_bus); 1859 1860 /* read and clear interrupt status */ 1861 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 1862 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status); 1863 1864 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 1865 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 1866 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 1867 1868 /* get all channel interrupts */ 1869 for (x = 0; x != sc->sc_host_ch_max; x++) { 1870 uint32_t temp; 1871 1872 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 1873 if (temp != 0) { 1874 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 1875 sc->sc_chan_state[x].hcint |= 1876 (temp & ~(HCINT_SOFTWARE_ONLY | 1877 HCINT_SUSPEND_ONLY | HCINT_CHHLTD)); 1878 } 1879 } 1880 1881 if (status & GINTSTS_USBRST) { 1882 1883 /* set correct state */ 1884 sc->sc_flags.status_device_mode = 1; 1885 sc->sc_flags.status_bus_reset = 0; 1886 sc->sc_flags.status_suspend = 0; 1887 sc->sc_flags.change_suspend = 0; 1888 sc->sc_flags.change_connect = 1; 1889 1890 /* complete root HUB interrupt endpoint */ 1891 dwc_otg_root_intr(sc); 1892 } 1893 1894 /* check for any bus state change interrupts */ 1895 if (status & GINTSTS_ENUMDONE) { 1896 1897 uint32_t temp; 1898 1899 DPRINTFN(5, "end of reset\n"); 1900 1901 /* set correct state */ 1902 sc->sc_flags.status_device_mode = 1; 1903 sc->sc_flags.status_bus_reset = 1; 1904 sc->sc_flags.status_suspend = 0; 1905 sc->sc_flags.change_suspend = 0; 1906 sc->sc_flags.change_connect = 1; 1907 sc->sc_flags.status_low_speed = 0; 1908 sc->sc_flags.port_enabled = 1; 1909 1910 /* reset FIFOs */ 1911 dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 1912 1913 /* reset function address */ 1914 dwc_otg_set_address(sc, 0); 1915 1916 /* figure out enumeration speed */ 1917 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 1918 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 1919 sc->sc_flags.status_high_speed = 1; 1920 else 1921 sc->sc_flags.status_high_speed = 0; 1922 1923 /* disable resume interrupt and enable suspend interrupt */ 1924 1925 sc->sc_irq_mask &= ~GINTSTS_WKUPINT; 1926 sc->sc_irq_mask |= GINTSTS_USBSUSP; 1927 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 1928 1929 /* complete root HUB interrupt endpoint */ 1930 dwc_otg_root_intr(sc); 1931 } 1932 1933 if (status & GINTSTS_PRTINT) { 1934 uint32_t hprt; 1935 1936 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 1937 1938 /* clear change bits */ 1939 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 1940 HPRT_PRTPWR | HPRT_PRTENCHNG | 1941 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 1942 sc->sc_hprt_val); 1943 1944 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 1945 1946 sc->sc_flags.status_device_mode = 0; 1947 1948 if (hprt & HPRT_PRTCONNSTS) 1949 sc->sc_flags.status_bus_reset = 1; 1950 else 1951 sc->sc_flags.status_bus_reset = 0; 1952 1953 if (hprt & HPRT_PRTENCHNG) 1954 sc->sc_flags.change_enabled = 1; 1955 1956 if (hprt & HPRT_PRTENA) 1957 sc->sc_flags.port_enabled = 1; 1958 else 1959 sc->sc_flags.port_enabled = 0; 1960 1961 if (hprt & HPRT_PRTOVRCURRCHNG) 1962 sc->sc_flags.change_over_current = 1; 1963 1964 if (hprt & HPRT_PRTOVRCURRACT) 1965 sc->sc_flags.port_over_current = 1; 1966 else 1967 sc->sc_flags.port_over_current = 0; 1968 1969 if (hprt & HPRT_PRTPWR) 1970 sc->sc_flags.port_powered = 1; 1971 else 1972 sc->sc_flags.port_powered = 0; 1973 1974 if (((hprt & HPRT_PRTSPD_MASK) 1975 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 1976 sc->sc_flags.status_low_speed = 1; 1977 else 1978 sc->sc_flags.status_low_speed = 0; 1979 1980 if (((hprt & HPRT_PRTSPD_MASK) 1981 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 1982 sc->sc_flags.status_high_speed = 1; 1983 else 1984 sc->sc_flags.status_high_speed = 0; 1985 1986 if (hprt & HPRT_PRTCONNDET) 1987 sc->sc_flags.change_connect = 1; 1988 1989 if (hprt & HPRT_PRTSUSP) 1990 dwc_otg_suspend_irq(sc); 1991 else 1992 dwc_otg_resume_irq(sc); 1993 1994 /* complete root HUB interrupt endpoint */ 1995 dwc_otg_root_intr(sc); 1996 } 1997 1998 /* 1999 * If resume and suspend is set at the same time we interpret 2000 * that like RESUME. Resume is set when there is at least 3 2001 * milliseconds of inactivity on the USB BUS. 2002 */ 2003 if (status & GINTSTS_WKUPINT) { 2004 2005 DPRINTFN(5, "resume interrupt\n"); 2006 2007 dwc_otg_resume_irq(sc); 2008 2009 } else if (status & GINTSTS_USBSUSP) { 2010 2011 DPRINTFN(5, "suspend interrupt\n"); 2012 2013 dwc_otg_suspend_irq(sc); 2014 } 2015 /* check VBUS */ 2016 if (status & (GINTSTS_USBSUSP | 2017 GINTSTS_USBRST | 2018 GINTMSK_OTGINTMSK | 2019 GINTSTS_SESSREQINT)) { 2020 uint32_t temp; 2021 2022 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2023 2024 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2025 2026 dwc_otg_vbus_interrupt(sc, 2027 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2028 } 2029 2030 /* clear all IN endpoint interrupts */ 2031 if (status & GINTSTS_IEPINT) { 2032 uint32_t temp; 2033 uint8_t x; 2034 2035 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2036 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2037 if (temp & DIEPMSK_XFERCOMPLMSK) { 2038 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2039 DIEPMSK_XFERCOMPLMSK); 2040 } 2041 } 2042 } 2043 2044 /* check for Start Of Frame IRQ */ 2045 if (status & GINTMSK_SOFMSK) 2046 sc->sc_sof_val++; 2047 2048 /* poll FIFO(s) */ 2049 dwc_otg_interrupt_poll(sc); 2050 2051 USB_BUS_UNLOCK(&sc->sc_bus); 2052 } 2053 2054 static void 2055 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2056 { 2057 struct dwc_otg_td *td; 2058 2059 /* get current Transfer Descriptor */ 2060 td = temp->td_next; 2061 temp->td = td; 2062 2063 /* prepare for next TD */ 2064 temp->td_next = td->obj_next; 2065 2066 /* fill out the Transfer Descriptor */ 2067 td->func = temp->func; 2068 td->pc = temp->pc; 2069 td->offset = temp->offset; 2070 td->remainder = temp->len; 2071 td->tx_bytes = 0; 2072 td->error_any = 0; 2073 td->npkt = 0; 2074 td->did_stall = temp->did_stall; 2075 td->short_pkt = temp->short_pkt; 2076 td->alt_next = temp->setup_alt_next; 2077 td->set_toggle = 0; 2078 td->got_short = 0; 2079 td->channel = DWC_OTG_MAX_CHANNELS; 2080 } 2081 2082 static void 2083 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 2084 { 2085 struct dwc_otg_std_temp temp; 2086 struct dwc_otg_td *td; 2087 uint32_t x; 2088 uint8_t need_sync; 2089 uint8_t is_host; 2090 2091 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 2092 xfer->address, UE_GET_ADDR(xfer->endpointno), 2093 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 2094 2095 temp.max_frame_size = xfer->max_frame_size; 2096 2097 td = xfer->td_start[0]; 2098 xfer->td_transfer_first = td; 2099 xfer->td_transfer_cache = td; 2100 2101 /* setup temp */ 2102 2103 temp.pc = NULL; 2104 temp.td = NULL; 2105 temp.td_next = xfer->td_start[0]; 2106 temp.offset = 0; 2107 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 2108 temp.did_stall = !xfer->flags_int.control_stall; 2109 2110 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 2111 2112 /* check if we should prepend a setup message */ 2113 2114 if (xfer->flags_int.control_xfr) { 2115 if (xfer->flags_int.control_hdr) { 2116 2117 if (is_host) 2118 temp.func = &dwc_otg_host_setup_tx; 2119 else 2120 temp.func = &dwc_otg_setup_rx; 2121 2122 temp.len = xfer->frlengths[0]; 2123 temp.pc = xfer->frbuffers + 0; 2124 temp.short_pkt = temp.len ? 1 : 0; 2125 2126 /* check for last frame */ 2127 if (xfer->nframes == 1) { 2128 /* no STATUS stage yet, SETUP is last */ 2129 if (xfer->flags_int.control_act) 2130 temp.setup_alt_next = 0; 2131 } 2132 2133 dwc_otg_setup_standard_chain_sub(&temp); 2134 } 2135 x = 1; 2136 } else { 2137 x = 0; 2138 } 2139 2140 if (x != xfer->nframes) { 2141 if (xfer->endpointno & UE_DIR_IN) { 2142 if (is_host) { 2143 temp.func = &dwc_otg_host_data_rx; 2144 need_sync = 0; 2145 } else { 2146 temp.func = &dwc_otg_data_tx; 2147 need_sync = 1; 2148 } 2149 } else { 2150 if (is_host) { 2151 temp.func = &dwc_otg_host_data_tx; 2152 need_sync = 0; 2153 } else { 2154 temp.func = &dwc_otg_data_rx; 2155 need_sync = 0; 2156 } 2157 } 2158 2159 /* setup "pc" pointer */ 2160 temp.pc = xfer->frbuffers + x; 2161 } else { 2162 need_sync = 0; 2163 } 2164 while (x != xfer->nframes) { 2165 2166 /* DATA0 / DATA1 message */ 2167 2168 temp.len = xfer->frlengths[x]; 2169 2170 x++; 2171 2172 if (x == xfer->nframes) { 2173 if (xfer->flags_int.control_xfr) { 2174 if (xfer->flags_int.control_act) { 2175 temp.setup_alt_next = 0; 2176 } 2177 } else { 2178 temp.setup_alt_next = 0; 2179 } 2180 } 2181 if (temp.len == 0) { 2182 2183 /* make sure that we send an USB packet */ 2184 2185 temp.short_pkt = 0; 2186 2187 } else { 2188 2189 /* regular data transfer */ 2190 2191 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 2192 } 2193 2194 dwc_otg_setup_standard_chain_sub(&temp); 2195 2196 if (xfer->flags_int.isochronous_xfr) { 2197 temp.offset += temp.len; 2198 } else { 2199 /* get next Page Cache pointer */ 2200 temp.pc = xfer->frbuffers + x; 2201 } 2202 } 2203 2204 if (xfer->flags_int.control_xfr) { 2205 2206 /* always setup a valid "pc" pointer for status and sync */ 2207 temp.pc = xfer->frbuffers + 0; 2208 temp.len = 0; 2209 temp.short_pkt = 0; 2210 temp.setup_alt_next = 0; 2211 2212 /* check if we need to sync */ 2213 if (need_sync) { 2214 /* we need a SYNC point after TX */ 2215 temp.func = &dwc_otg_data_tx_sync; 2216 dwc_otg_setup_standard_chain_sub(&temp); 2217 } 2218 2219 /* check if we should append a status stage */ 2220 if (!xfer->flags_int.control_act) { 2221 2222 /* 2223 * Send a DATA1 message and invert the current 2224 * endpoint direction. 2225 */ 2226 if (xfer->endpointno & UE_DIR_IN) { 2227 if (is_host) { 2228 temp.func = &dwc_otg_host_data_tx; 2229 need_sync = 0; 2230 } else { 2231 temp.func = &dwc_otg_data_rx; 2232 need_sync = 0; 2233 } 2234 } else { 2235 if (is_host) { 2236 temp.func = &dwc_otg_host_data_rx; 2237 need_sync = 0; 2238 } else { 2239 temp.func = &dwc_otg_data_tx; 2240 need_sync = 1; 2241 } 2242 } 2243 2244 dwc_otg_setup_standard_chain_sub(&temp); 2245 2246 /* data toggle should be DATA1 */ 2247 td = temp.td; 2248 td->set_toggle = 1; 2249 2250 if (need_sync) { 2251 /* we need a SYNC point after TX */ 2252 temp.func = &dwc_otg_data_tx_sync; 2253 dwc_otg_setup_standard_chain_sub(&temp); 2254 } 2255 } 2256 } else { 2257 /* check if we need to sync */ 2258 if (need_sync) { 2259 2260 temp.pc = xfer->frbuffers + 0; 2261 temp.len = 0; 2262 temp.short_pkt = 0; 2263 temp.setup_alt_next = 0; 2264 2265 /* we need a SYNC point after TX */ 2266 temp.func = &dwc_otg_data_tx_sync; 2267 dwc_otg_setup_standard_chain_sub(&temp); 2268 } 2269 } 2270 2271 /* must have at least one frame! */ 2272 td = temp.td; 2273 xfer->td_transfer_last = td; 2274 2275 if (is_host) { 2276 2277 struct dwc_otg_softc *sc; 2278 uint8_t xfer_type; 2279 2280 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2281 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE; 2282 2283 /* get first again */ 2284 td = xfer->td_transfer_first; 2285 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 2286 2287 td->hcchar = 2288 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 2289 (xfer_type << HCCHAR_EPTYPE_SHIFT) | 2290 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 2291 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 2292 HCCHAR_CHENA; 2293 2294 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 2295 td->hcchar |= HCCHAR_LSPDDEV; 2296 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2297 td->hcchar |= HCCHAR_EPDIR_IN; 2298 2299 switch (xfer->xroot->udev->speed) { 2300 case USB_SPEED_FULL: 2301 case USB_SPEED_LOW: 2302 /* check if root HUB port is running High Speed */ 2303 if (sc->sc_flags.status_high_speed != 0) { 2304 td->hcsplt = HCSPLT_SPLTENA | 2305 (xfer->xroot->udev->hs_port_no << 2306 HCSPLT_PRTADDR_SHIFT) | 2307 (xfer->xroot->udev->hs_hub_addr << 2308 HCSPLT_HUBADDR_SHIFT); 2309 if (xfer_type == UE_ISOCHRONOUS) /* XXX */ 2310 td->hcsplt |= (3 << HCSPLT_XACTPOS_SHIFT); 2311 } else { 2312 td->hcsplt = 0; 2313 } 2314 if (xfer_type == UE_INTERRUPT) { 2315 uint32_t ival; 2316 ival = xfer->interval; 2317 if (ival == 0) 2318 ival = 1; 2319 else if (ival > 255) 2320 ival = 255; 2321 td->sof_val = sc->sc_sof_val + ival; 2322 td->sof_res = ival; 2323 } 2324 break; 2325 case USB_SPEED_HIGH: 2326 td->hcsplt = 0; 2327 if (xfer_type == UE_ISOCHRONOUS || 2328 xfer_type == UE_INTERRUPT) { 2329 td->hcchar |= ((xfer->max_packet_count & 3) 2330 << HCCHAR_MC_SHIFT); 2331 } 2332 if (xfer_type == UE_INTERRUPT) { 2333 uint32_t ival; 2334 ival = xfer->interval * 8; 2335 if (ival == 0) 2336 ival = 1; 2337 else if (ival > 255) 2338 ival = 255; 2339 td->sof_val = sc->sc_sof_val + ival; 2340 td->sof_res = ival; 2341 } 2342 break; 2343 default: 2344 td->hcsplt = 0; 2345 break; 2346 } 2347 2348 if (xfer_type == UE_ISOCHRONOUS) { 2349 td->sof_val = xfer->endpoint->isoc_next & 0xFF; 2350 td->sof_res = 1 << usbd_xfer_get_fps_shift(xfer); 2351 } else if (xfer_type != UE_INTERRUPT) { 2352 td->sof_val = sc->sc_sof_val + 1; 2353 td->sof_res = 1; 2354 } 2355 } 2356 } 2357 2358 static void 2359 dwc_otg_timeout(void *arg) 2360 { 2361 struct usb_xfer *xfer = arg; 2362 2363 DPRINTF("xfer=%p\n", xfer); 2364 2365 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 2366 2367 /* transfer is transferred */ 2368 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 2369 } 2370 2371 static void 2372 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 2373 { 2374 DPRINTFN(9, "\n"); 2375 2376 /* poll one time - will turn on interrupts */ 2377 if (dwc_otg_xfer_do_fifo(xfer)) { 2378 2379 /* put transfer on interrupt queue */ 2380 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2381 2382 /* start timeout, if any */ 2383 if (xfer->timeout != 0) { 2384 usbd_transfer_timeout_ms(xfer, 2385 &dwc_otg_timeout, xfer->timeout); 2386 } 2387 } 2388 } 2389 2390 static void 2391 dwc_otg_root_intr(struct dwc_otg_softc *sc) 2392 { 2393 DPRINTFN(9, "\n"); 2394 2395 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2396 2397 /* set port bit */ 2398 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 2399 2400 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2401 sizeof(sc->sc_hub_idata)); 2402 } 2403 2404 static usb_error_t 2405 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 2406 { 2407 struct dwc_otg_td *td; 2408 uint32_t len; 2409 usb_error_t error; 2410 2411 DPRINTFN(9, "\n"); 2412 2413 td = xfer->td_transfer_cache; 2414 2415 do { 2416 len = td->remainder; 2417 2418 /* store last data toggle */ 2419 xfer->endpoint->toggle_next = td->toggle; 2420 2421 if (xfer->aframes != xfer->nframes) { 2422 /* 2423 * Verify the length and subtract 2424 * the remainder from "frlengths[]": 2425 */ 2426 if (len > xfer->frlengths[xfer->aframes]) { 2427 td->error_any = 1; 2428 } else { 2429 xfer->frlengths[xfer->aframes] -= len; 2430 } 2431 } 2432 /* Check for transfer error */ 2433 if (td->error_any) { 2434 /* the transfer is finished */ 2435 error = (td->error_stall ? 2436 USB_ERR_STALLED : USB_ERR_IOERROR); 2437 td = NULL; 2438 break; 2439 } 2440 /* Check for short transfer */ 2441 if (len > 0) { 2442 if (xfer->flags_int.short_frames_ok) { 2443 /* follow alt next */ 2444 if (td->alt_next) { 2445 td = td->obj_next; 2446 } else { 2447 td = NULL; 2448 } 2449 } else { 2450 /* the transfer is finished */ 2451 td = NULL; 2452 } 2453 error = 0; 2454 break; 2455 } 2456 td = td->obj_next; 2457 2458 /* this USB frame is complete */ 2459 error = 0; 2460 break; 2461 2462 } while (0); 2463 2464 /* update transfer cache */ 2465 2466 xfer->td_transfer_cache = td; 2467 2468 return (error); 2469 } 2470 2471 static void 2472 dwc_otg_standard_done(struct usb_xfer *xfer) 2473 { 2474 usb_error_t err = 0; 2475 2476 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2477 xfer, xfer->endpoint); 2478 2479 /* reset scanner */ 2480 2481 xfer->td_transfer_cache = xfer->td_transfer_first; 2482 2483 if (xfer->flags_int.control_xfr) { 2484 2485 if (xfer->flags_int.control_hdr) { 2486 2487 err = dwc_otg_standard_done_sub(xfer); 2488 } 2489 xfer->aframes = 1; 2490 2491 if (xfer->td_transfer_cache == NULL) { 2492 goto done; 2493 } 2494 } 2495 while (xfer->aframes != xfer->nframes) { 2496 2497 err = dwc_otg_standard_done_sub(xfer); 2498 xfer->aframes++; 2499 2500 if (xfer->td_transfer_cache == NULL) { 2501 goto done; 2502 } 2503 } 2504 2505 if (xfer->flags_int.control_xfr && 2506 !xfer->flags_int.control_act) { 2507 2508 err = dwc_otg_standard_done_sub(xfer); 2509 } 2510 done: 2511 dwc_otg_device_done(xfer, err); 2512 } 2513 2514 /*------------------------------------------------------------------------* 2515 * dwc_otg_device_done 2516 * 2517 * NOTE: this function can be called more than one time on the 2518 * same USB transfer! 2519 *------------------------------------------------------------------------*/ 2520 static void 2521 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 2522 { 2523 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 2524 xfer, xfer->endpoint, error); 2525 2526 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 2527 DPRINTFN(15, "disabled interrupts!\n"); 2528 } else { 2529 struct dwc_otg_td *td; 2530 2531 td = xfer->td_transfer_first; 2532 2533 if (td != NULL && td->channel < DWC_OTG_MAX_CHANNELS) { 2534 2535 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 2536 2537 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(td->channel), 0); 2538 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), 2539 HCCHAR_CHENA | HCCHAR_CHDIS); 2540 2541 sc->sc_chan_state[td->channel].hcchar = 0; 2542 sc->sc_active_rx_ep &= ~(1 << td->channel); 2543 2544 /* release SOF's */ 2545 if (sc->sc_chan_state[td->channel].sof_requested != 0) 2546 dwc_otg_release_sof(sc); 2547 2548 td->channel = DWC_OTG_MAX_CHANNELS; 2549 } 2550 } 2551 /* dequeue transfer and start next transfer */ 2552 usbd_transfer_done(xfer, error); 2553 } 2554 2555 static void 2556 dwc_otg_xfer_stall(struct usb_xfer *xfer) 2557 { 2558 dwc_otg_device_done(xfer, USB_ERR_STALLED); 2559 } 2560 2561 static void 2562 dwc_otg_set_stall(struct usb_device *udev, 2563 struct usb_endpoint *ep, uint8_t *did_stall) 2564 { 2565 struct dwc_otg_softc *sc; 2566 uint32_t temp; 2567 uint32_t reg; 2568 uint8_t ep_no; 2569 2570 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2571 2572 /* check mode */ 2573 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2574 /* not supported */ 2575 return; 2576 } 2577 2578 sc = DWC_OTG_BUS2SC(udev->bus); 2579 2580 /* get endpoint address */ 2581 ep_no = ep->edesc->bEndpointAddress; 2582 2583 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 2584 2585 if (ep_no & UE_DIR_IN) { 2586 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 2587 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 2588 } else { 2589 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 2590 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 2591 } 2592 2593 /* disable and stall endpoint */ 2594 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2595 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 2596 2597 /* clear active OUT ep */ 2598 if (!(ep_no & UE_DIR_IN)) { 2599 2600 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 2601 2602 if (sc->sc_last_rx_status != 0 && 2603 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 2604 sc->sc_last_rx_status)) { 2605 /* dump data */ 2606 dwc_otg_common_rx_ack(sc); 2607 /* poll interrupt */ 2608 dwc_otg_interrupt_poll(sc); 2609 } 2610 } 2611 } 2612 2613 static void 2614 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 2615 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 2616 { 2617 uint32_t reg; 2618 uint32_t temp; 2619 2620 if (ep_type == UE_CONTROL) { 2621 /* clearing stall is not needed */ 2622 return; 2623 } 2624 2625 if (ep_dir) { 2626 reg = DOTG_DIEPCTL(ep_no); 2627 } else { 2628 reg = DOTG_DOEPCTL(ep_no); 2629 sc->sc_active_rx_ep |= (1U << ep_no); 2630 } 2631 2632 /* round up and mask away the multiplier count */ 2633 mps = (mps + 3) & 0x7FC; 2634 2635 if (ep_type == UE_BULK) { 2636 temp = DIEPCTL_EPTYPE_SET( 2637 DIEPCTL_EPTYPE_BULK) | 2638 DIEPCTL_USBACTEP; 2639 } else if (ep_type == UE_INTERRUPT) { 2640 temp = DIEPCTL_EPTYPE_SET( 2641 DIEPCTL_EPTYPE_INTERRUPT) | 2642 DIEPCTL_USBACTEP; 2643 } else { 2644 temp = DIEPCTL_EPTYPE_SET( 2645 DIEPCTL_EPTYPE_ISOC) | 2646 DIEPCTL_USBACTEP; 2647 } 2648 2649 temp |= DIEPCTL_MPS_SET(mps); 2650 temp |= DIEPCTL_TXFNUM_SET(ep_no); 2651 2652 if (ep_dir) 2653 sc->sc_in_ctl[ep_no] = temp; 2654 else 2655 sc->sc_out_ctl[ep_no] = temp; 2656 2657 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 2658 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 2659 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 2660 2661 /* we only reset the transmit FIFO */ 2662 if (ep_dir) { 2663 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2664 GRSTCTL_TXFIFO(ep_no) | 2665 GRSTCTL_TXFFLSH); 2666 2667 DWC_OTG_WRITE_4(sc, 2668 DOTG_DIEPTSIZ(ep_no), 0); 2669 } 2670 2671 /* poll interrupt */ 2672 dwc_otg_interrupt_poll(sc); 2673 } 2674 2675 static void 2676 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 2677 { 2678 struct dwc_otg_softc *sc; 2679 struct usb_endpoint_descriptor *ed; 2680 2681 DPRINTFN(5, "endpoint=%p\n", ep); 2682 2683 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 2684 2685 /* check mode */ 2686 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2687 /* not supported */ 2688 return; 2689 } 2690 /* get softc */ 2691 sc = DWC_OTG_BUS2SC(udev->bus); 2692 2693 /* get endpoint descriptor */ 2694 ed = ep->edesc; 2695 2696 /* reset endpoint */ 2697 dwc_otg_clear_stall_sub(sc, 2698 UGETW(ed->wMaxPacketSize), 2699 (ed->bEndpointAddress & UE_ADDR), 2700 (ed->bmAttributes & UE_XFERTYPE), 2701 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 2702 } 2703 2704 static void 2705 dwc_otg_device_state_change(struct usb_device *udev) 2706 { 2707 struct dwc_otg_softc *sc; 2708 uint8_t x; 2709 2710 /* check mode */ 2711 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2712 /* not supported */ 2713 return; 2714 } 2715 2716 /* get softc */ 2717 sc = DWC_OTG_BUS2SC(udev->bus); 2718 2719 /* deactivate all other endpoint but the control endpoint */ 2720 if (udev->state == USB_STATE_CONFIGURED || 2721 udev->state == USB_STATE_ADDRESSED) { 2722 2723 USB_BUS_LOCK(&sc->sc_bus); 2724 2725 for (x = 1; x != sc->sc_dev_ep_max; x++) { 2726 2727 if (x < sc->sc_dev_in_ep_max) { 2728 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 2729 DIEPCTL_EPDIS); 2730 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 2731 } 2732 2733 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 2734 DOEPCTL_EPDIS); 2735 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 2736 } 2737 USB_BUS_UNLOCK(&sc->sc_bus); 2738 } 2739 } 2740 2741 int 2742 dwc_otg_init(struct dwc_otg_softc *sc) 2743 { 2744 uint32_t temp; 2745 2746 DPRINTF("start\n"); 2747 2748 /* set up the bus structure */ 2749 sc->sc_bus.usbrev = USB_REV_2_0; 2750 sc->sc_bus.methods = &dwc_otg_bus_methods; 2751 2752 USB_BUS_LOCK(&sc->sc_bus); 2753 2754 /* turn on clocks */ 2755 dwc_otg_clocks_on(sc); 2756 2757 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 2758 DPRINTF("Version = 0x%08x\n", temp); 2759 2760 /* disconnect */ 2761 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 2762 DCTL_SFTDISCON); 2763 2764 /* wait for host to detect disconnect */ 2765 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 2766 2767 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 2768 GRSTCTL_CSFTRST); 2769 2770 /* wait a little bit for block to reset */ 2771 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 2772 2773 switch (sc->sc_mode) { 2774 case DWC_MODE_DEVICE: 2775 temp = GUSBCFG_FORCEDEVMODE; 2776 break; 2777 case DWC_MODE_HOST: 2778 temp = GUSBCFG_FORCEHOSTMODE; 2779 break; 2780 default: 2781 temp = 0; 2782 break; 2783 } 2784 2785 /* select HSIC or non-HSIC mode */ 2786 if (DWC_OTG_USE_HSIC) { 2787 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 2788 GUSBCFG_PHYIF | 2789 GUSBCFG_TRD_TIM_SET(5) | temp); 2790 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 2791 0x000000EC); 2792 2793 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 2794 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 2795 temp & ~GLPMCFG_HSIC_CONN); 2796 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 2797 temp | GLPMCFG_HSIC_CONN); 2798 } else { 2799 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 2800 GUSBCFG_ULPI_UTMI_SEL | 2801 GUSBCFG_TRD_TIM_SET(5) | temp); 2802 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 2803 2804 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 2805 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 2806 temp & ~GLPMCFG_HSIC_CONN); 2807 } 2808 2809 /* clear global nak */ 2810 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 2811 DCTL_CGOUTNAK | 2812 DCTL_CGNPINNAK); 2813 2814 /* disable USB port */ 2815 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 2816 2817 /* wait 10ms */ 2818 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 2819 2820 /* enable USB port */ 2821 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 2822 2823 /* wait 10ms */ 2824 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 2825 2826 /* pull up D+ */ 2827 dwc_otg_pull_up(sc); 2828 2829 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 2830 2831 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 2832 2833 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 2834 2835 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 2836 2837 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 2838 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 2839 2840 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 2841 2842 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 2843 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 2844 2845 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 2846 2847 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 2848 2849 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 2850 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 2851 sc->sc_host_ch_max); 2852 2853 /* setup FIFO */ 2854 if (dwc_otg_init_fifo(sc, DWC_MODE_OTG)) 2855 return (EINVAL); 2856 2857 /* enable interrupts */ 2858 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 2859 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2860 2861 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 2862 2863 /* enable all endpoint interrupts */ 2864 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 2865 if (temp & GHWCFG2_MPI) { 2866 uint8_t x; 2867 2868 DPRINTF("Multi Process Interrupts\n"); 2869 2870 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2871 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 2872 DIEPMSK_XFERCOMPLMSK); 2873 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 2874 } 2875 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 2876 } else { 2877 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 2878 DIEPMSK_XFERCOMPLMSK); 2879 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 2880 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 2881 } 2882 } 2883 2884 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 2885 2886 uint8_t x; 2887 2888 for (x = 0; x != sc->sc_host_ch_max; x++) { 2889 /* enable interrupts */ 2890 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 2891 HCINT_STALL | HCINT_BBLERR | 2892 HCINT_XACTERR | HCINT_XFERCOMPL | 2893 HCINT_NAK | HCINT_ACK | HCINT_NYET | 2894 HCINT_CHHLTD); 2895 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2896 HCCHAR_CHENA | HCCHAR_CHDIS); 2897 } 2898 2899 /* enable host channel interrupts */ 2900 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 2901 (1 << sc->sc_host_ch_max) - 1); 2902 2903 /* setup clocks */ 2904 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 2905 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 2906 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 2907 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 2908 } 2909 2910 /* only enable global IRQ */ 2911 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 2912 GAHBCFG_GLBLINTRMSK); 2913 2914 /* turn off clocks */ 2915 dwc_otg_clocks_off(sc); 2916 2917 /* read initial VBUS state */ 2918 2919 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2920 2921 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 2922 2923 dwc_otg_vbus_interrupt(sc, 2924 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2925 2926 USB_BUS_UNLOCK(&sc->sc_bus); 2927 2928 /* catch any lost interrupts */ 2929 2930 dwc_otg_do_poll(&sc->sc_bus); 2931 2932 return (0); /* success */ 2933 } 2934 2935 void 2936 dwc_otg_uninit(struct dwc_otg_softc *sc) 2937 { 2938 USB_BUS_LOCK(&sc->sc_bus); 2939 2940 /* set disconnect */ 2941 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 2942 DCTL_SFTDISCON); 2943 2944 /* turn off global IRQ */ 2945 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 2946 2947 sc->sc_flags.port_enabled = 0; 2948 sc->sc_flags.port_powered = 0; 2949 sc->sc_flags.status_vbus = 0; 2950 sc->sc_flags.status_bus_reset = 0; 2951 sc->sc_flags.status_suspend = 0; 2952 sc->sc_flags.change_suspend = 0; 2953 sc->sc_flags.change_connect = 1; 2954 2955 dwc_otg_pull_down(sc); 2956 dwc_otg_clocks_off(sc); 2957 2958 USB_BUS_UNLOCK(&sc->sc_bus); 2959 } 2960 2961 static void 2962 dwc_otg_suspend(struct dwc_otg_softc *sc) 2963 { 2964 return; 2965 } 2966 2967 static void 2968 dwc_otg_resume(struct dwc_otg_softc *sc) 2969 { 2970 return; 2971 } 2972 2973 static void 2974 dwc_otg_do_poll(struct usb_bus *bus) 2975 { 2976 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 2977 2978 USB_BUS_LOCK(&sc->sc_bus); 2979 dwc_otg_interrupt_poll(sc); 2980 USB_BUS_UNLOCK(&sc->sc_bus); 2981 } 2982 2983 /*------------------------------------------------------------------------* 2984 * DWC OTG bulk support 2985 * DWC OTG control support 2986 * DWC OTG interrupt support 2987 *------------------------------------------------------------------------*/ 2988 static void 2989 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 2990 { 2991 } 2992 2993 static void 2994 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 2995 { 2996 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 2997 } 2998 2999 static void 3000 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3001 { 3002 } 3003 3004 static void 3005 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3006 { 3007 /* setup TDs */ 3008 dwc_otg_setup_standard_chain(xfer); 3009 dwc_otg_start_standard_chain(xfer); 3010 } 3011 3012 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 3013 { 3014 .open = dwc_otg_device_non_isoc_open, 3015 .close = dwc_otg_device_non_isoc_close, 3016 .enter = dwc_otg_device_non_isoc_enter, 3017 .start = dwc_otg_device_non_isoc_start, 3018 }; 3019 3020 /*------------------------------------------------------------------------* 3021 * DWC OTG full speed isochronous support 3022 *------------------------------------------------------------------------*/ 3023 static void 3024 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 3025 { 3026 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3027 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3028 3029 xfer->qh_pos = 1; 3030 dwc_otg_request_sof(sc); 3031 } 3032 } 3033 3034 static void 3035 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 3036 { 3037 if (xfer->qh_pos != 0) { 3038 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3039 3040 xfer->qh_pos = 0; 3041 dwc_otg_release_sof(sc); 3042 } 3043 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3044 } 3045 3046 static void 3047 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 3048 { 3049 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3050 uint32_t temp; 3051 uint32_t nframes; 3052 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 3053 3054 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 3055 xfer, xfer->endpoint->isoc_next, xfer->nframes); 3056 3057 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 3058 temp = sc->sc_sof_val; 3059 3060 /* get the current frame index */ 3061 nframes = (temp & HFNUM_FRNUM_MASK); 3062 } else { 3063 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 3064 3065 /* get the current frame index */ 3066 nframes = DSTS_SOFFN_GET(temp); 3067 } 3068 3069 if (sc->sc_flags.status_high_speed) 3070 nframes /= 8; 3071 3072 nframes &= DWC_OTG_FRAME_MASK; 3073 3074 /* 3075 * check if the frame index is within the window where the frames 3076 * will be inserted 3077 */ 3078 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 3079 3080 if ((xfer->endpoint->is_synced == 0) || 3081 (temp < (((xfer->nframes << shift) + 7) / 8))) { 3082 /* 3083 * If there is data underflow or the pipe queue is 3084 * empty we schedule the transfer a few frames ahead 3085 * of the current frame position. Else two isochronous 3086 * transfers might overlap. 3087 */ 3088 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 3089 xfer->endpoint->is_synced = 1; 3090 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 3091 } 3092 /* 3093 * compute how many milliseconds the insertion is ahead of the 3094 * current frame position: 3095 */ 3096 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 3097 3098 /* 3099 * pre-compute when the isochronous transfer will be finished: 3100 */ 3101 xfer->isoc_time_complete = 3102 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 3103 (((xfer->nframes << shift) + 7) / 8); 3104 3105 /* setup TDs */ 3106 dwc_otg_setup_standard_chain(xfer); 3107 3108 /* compute frame number for next insertion */ 3109 xfer->endpoint->isoc_next += (xfer->nframes << shift); 3110 } 3111 3112 static void 3113 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 3114 { 3115 /* start TD chain */ 3116 dwc_otg_start_standard_chain(xfer); 3117 } 3118 3119 struct usb_pipe_methods dwc_otg_device_isoc_methods = 3120 { 3121 .open = dwc_otg_device_isoc_open, 3122 .close = dwc_otg_device_isoc_close, 3123 .enter = dwc_otg_device_isoc_enter, 3124 .start = dwc_otg_device_isoc_start, 3125 }; 3126 3127 /*------------------------------------------------------------------------* 3128 * DWC OTG root control support 3129 *------------------------------------------------------------------------* 3130 * Simulate a hardware HUB by handling all the necessary requests. 3131 *------------------------------------------------------------------------*/ 3132 3133 static const struct usb_device_descriptor dwc_otg_devd = { 3134 .bLength = sizeof(struct usb_device_descriptor), 3135 .bDescriptorType = UDESC_DEVICE, 3136 .bcdUSB = {0x00, 0x02}, 3137 .bDeviceClass = UDCLASS_HUB, 3138 .bDeviceSubClass = UDSUBCLASS_HUB, 3139 .bDeviceProtocol = UDPROTO_HSHUBSTT, 3140 .bMaxPacketSize = 64, 3141 .bcdDevice = {0x00, 0x01}, 3142 .iManufacturer = 1, 3143 .iProduct = 2, 3144 .bNumConfigurations = 1, 3145 }; 3146 3147 static const struct dwc_otg_config_desc dwc_otg_confd = { 3148 .confd = { 3149 .bLength = sizeof(struct usb_config_descriptor), 3150 .bDescriptorType = UDESC_CONFIG, 3151 .wTotalLength[0] = sizeof(dwc_otg_confd), 3152 .bNumInterface = 1, 3153 .bConfigurationValue = 1, 3154 .iConfiguration = 0, 3155 .bmAttributes = UC_SELF_POWERED, 3156 .bMaxPower = 0, 3157 }, 3158 .ifcd = { 3159 .bLength = sizeof(struct usb_interface_descriptor), 3160 .bDescriptorType = UDESC_INTERFACE, 3161 .bNumEndpoints = 1, 3162 .bInterfaceClass = UICLASS_HUB, 3163 .bInterfaceSubClass = UISUBCLASS_HUB, 3164 .bInterfaceProtocol = 0, 3165 }, 3166 .endpd = { 3167 .bLength = sizeof(struct usb_endpoint_descriptor), 3168 .bDescriptorType = UDESC_ENDPOINT, 3169 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 3170 .bmAttributes = UE_INTERRUPT, 3171 .wMaxPacketSize[0] = 8, 3172 .bInterval = 255, 3173 }, 3174 }; 3175 3176 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3177 3178 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 3179 .bDescLength = sizeof(dwc_otg_hubd), 3180 .bDescriptorType = UDESC_HUB, 3181 .bNbrPorts = 1, 3182 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 3183 .bPwrOn2PwrGood = 50, 3184 .bHubContrCurrent = 0, 3185 .DeviceRemovable = {0}, /* port is removable */ 3186 }; 3187 3188 #define STRING_LANG \ 3189 0x09, 0x04, /* American English */ 3190 3191 #define STRING_VENDOR \ 3192 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 3193 3194 #define STRING_PRODUCT \ 3195 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \ 3196 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 3197 'U', 0, 'B', 0, 3198 3199 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 3200 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 3201 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 3202 3203 static usb_error_t 3204 dwc_otg_roothub_exec(struct usb_device *udev, 3205 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3206 { 3207 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3208 const void *ptr; 3209 uint16_t len; 3210 uint16_t value; 3211 uint16_t index; 3212 usb_error_t err; 3213 3214 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3215 3216 /* buffer reset */ 3217 ptr = (const void *)&sc->sc_hub_temp; 3218 len = 0; 3219 err = 0; 3220 3221 value = UGETW(req->wValue); 3222 index = UGETW(req->wIndex); 3223 3224 /* demultiplex the control request */ 3225 3226 switch (req->bmRequestType) { 3227 case UT_READ_DEVICE: 3228 switch (req->bRequest) { 3229 case UR_GET_DESCRIPTOR: 3230 goto tr_handle_get_descriptor; 3231 case UR_GET_CONFIG: 3232 goto tr_handle_get_config; 3233 case UR_GET_STATUS: 3234 goto tr_handle_get_status; 3235 default: 3236 goto tr_stalled; 3237 } 3238 break; 3239 3240 case UT_WRITE_DEVICE: 3241 switch (req->bRequest) { 3242 case UR_SET_ADDRESS: 3243 goto tr_handle_set_address; 3244 case UR_SET_CONFIG: 3245 goto tr_handle_set_config; 3246 case UR_CLEAR_FEATURE: 3247 goto tr_valid; /* nop */ 3248 case UR_SET_DESCRIPTOR: 3249 goto tr_valid; /* nop */ 3250 case UR_SET_FEATURE: 3251 default: 3252 goto tr_stalled; 3253 } 3254 break; 3255 3256 case UT_WRITE_ENDPOINT: 3257 switch (req->bRequest) { 3258 case UR_CLEAR_FEATURE: 3259 switch (UGETW(req->wValue)) { 3260 case UF_ENDPOINT_HALT: 3261 goto tr_handle_clear_halt; 3262 case UF_DEVICE_REMOTE_WAKEUP: 3263 goto tr_handle_clear_wakeup; 3264 default: 3265 goto tr_stalled; 3266 } 3267 break; 3268 case UR_SET_FEATURE: 3269 switch (UGETW(req->wValue)) { 3270 case UF_ENDPOINT_HALT: 3271 goto tr_handle_set_halt; 3272 case UF_DEVICE_REMOTE_WAKEUP: 3273 goto tr_handle_set_wakeup; 3274 default: 3275 goto tr_stalled; 3276 } 3277 break; 3278 case UR_SYNCH_FRAME: 3279 goto tr_valid; /* nop */ 3280 default: 3281 goto tr_stalled; 3282 } 3283 break; 3284 3285 case UT_READ_ENDPOINT: 3286 switch (req->bRequest) { 3287 case UR_GET_STATUS: 3288 goto tr_handle_get_ep_status; 3289 default: 3290 goto tr_stalled; 3291 } 3292 break; 3293 3294 case UT_WRITE_INTERFACE: 3295 switch (req->bRequest) { 3296 case UR_SET_INTERFACE: 3297 goto tr_handle_set_interface; 3298 case UR_CLEAR_FEATURE: 3299 goto tr_valid; /* nop */ 3300 case UR_SET_FEATURE: 3301 default: 3302 goto tr_stalled; 3303 } 3304 break; 3305 3306 case UT_READ_INTERFACE: 3307 switch (req->bRequest) { 3308 case UR_GET_INTERFACE: 3309 goto tr_handle_get_interface; 3310 case UR_GET_STATUS: 3311 goto tr_handle_get_iface_status; 3312 default: 3313 goto tr_stalled; 3314 } 3315 break; 3316 3317 case UT_WRITE_CLASS_INTERFACE: 3318 case UT_WRITE_VENDOR_INTERFACE: 3319 /* XXX forward */ 3320 break; 3321 3322 case UT_READ_CLASS_INTERFACE: 3323 case UT_READ_VENDOR_INTERFACE: 3324 /* XXX forward */ 3325 break; 3326 3327 case UT_WRITE_CLASS_DEVICE: 3328 switch (req->bRequest) { 3329 case UR_CLEAR_FEATURE: 3330 goto tr_valid; 3331 case UR_SET_DESCRIPTOR: 3332 case UR_SET_FEATURE: 3333 break; 3334 default: 3335 goto tr_stalled; 3336 } 3337 break; 3338 3339 case UT_WRITE_CLASS_OTHER: 3340 switch (req->bRequest) { 3341 case UR_CLEAR_FEATURE: 3342 goto tr_handle_clear_port_feature; 3343 case UR_SET_FEATURE: 3344 goto tr_handle_set_port_feature; 3345 case UR_CLEAR_TT_BUFFER: 3346 case UR_RESET_TT: 3347 case UR_STOP_TT: 3348 goto tr_valid; 3349 3350 default: 3351 goto tr_stalled; 3352 } 3353 break; 3354 3355 case UT_READ_CLASS_OTHER: 3356 switch (req->bRequest) { 3357 case UR_GET_TT_STATE: 3358 goto tr_handle_get_tt_state; 3359 case UR_GET_STATUS: 3360 goto tr_handle_get_port_status; 3361 default: 3362 goto tr_stalled; 3363 } 3364 break; 3365 3366 case UT_READ_CLASS_DEVICE: 3367 switch (req->bRequest) { 3368 case UR_GET_DESCRIPTOR: 3369 goto tr_handle_get_class_descriptor; 3370 case UR_GET_STATUS: 3371 goto tr_handle_get_class_status; 3372 3373 default: 3374 goto tr_stalled; 3375 } 3376 break; 3377 default: 3378 goto tr_stalled; 3379 } 3380 goto tr_valid; 3381 3382 tr_handle_get_descriptor: 3383 switch (value >> 8) { 3384 case UDESC_DEVICE: 3385 if (value & 0xff) { 3386 goto tr_stalled; 3387 } 3388 len = sizeof(dwc_otg_devd); 3389 ptr = (const void *)&dwc_otg_devd; 3390 goto tr_valid; 3391 case UDESC_CONFIG: 3392 if (value & 0xff) { 3393 goto tr_stalled; 3394 } 3395 len = sizeof(dwc_otg_confd); 3396 ptr = (const void *)&dwc_otg_confd; 3397 goto tr_valid; 3398 case UDESC_STRING: 3399 switch (value & 0xff) { 3400 case 0: /* Language table */ 3401 len = sizeof(dwc_otg_langtab); 3402 ptr = (const void *)&dwc_otg_langtab; 3403 goto tr_valid; 3404 3405 case 1: /* Vendor */ 3406 len = sizeof(dwc_otg_vendor); 3407 ptr = (const void *)&dwc_otg_vendor; 3408 goto tr_valid; 3409 3410 case 2: /* Product */ 3411 len = sizeof(dwc_otg_product); 3412 ptr = (const void *)&dwc_otg_product; 3413 goto tr_valid; 3414 default: 3415 break; 3416 } 3417 break; 3418 default: 3419 goto tr_stalled; 3420 } 3421 goto tr_stalled; 3422 3423 tr_handle_get_config: 3424 len = 1; 3425 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 3426 goto tr_valid; 3427 3428 tr_handle_get_status: 3429 len = 2; 3430 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 3431 goto tr_valid; 3432 3433 tr_handle_set_address: 3434 if (value & 0xFF00) { 3435 goto tr_stalled; 3436 } 3437 sc->sc_rt_addr = value; 3438 goto tr_valid; 3439 3440 tr_handle_set_config: 3441 if (value >= 2) { 3442 goto tr_stalled; 3443 } 3444 sc->sc_conf = value; 3445 goto tr_valid; 3446 3447 tr_handle_get_interface: 3448 len = 1; 3449 sc->sc_hub_temp.wValue[0] = 0; 3450 goto tr_valid; 3451 3452 tr_handle_get_tt_state: 3453 tr_handle_get_class_status: 3454 tr_handle_get_iface_status: 3455 tr_handle_get_ep_status: 3456 len = 2; 3457 USETW(sc->sc_hub_temp.wValue, 0); 3458 goto tr_valid; 3459 3460 tr_handle_set_halt: 3461 tr_handle_set_interface: 3462 tr_handle_set_wakeup: 3463 tr_handle_clear_wakeup: 3464 tr_handle_clear_halt: 3465 goto tr_valid; 3466 3467 tr_handle_clear_port_feature: 3468 if (index != 1) 3469 goto tr_stalled; 3470 3471 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 3472 3473 switch (value) { 3474 case UHF_PORT_SUSPEND: 3475 dwc_otg_wakeup_peer(sc); 3476 break; 3477 3478 case UHF_PORT_ENABLE: 3479 if (sc->sc_flags.status_device_mode == 0) { 3480 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 3481 sc->sc_hprt_val | HPRT_PRTENA); 3482 } 3483 sc->sc_flags.port_enabled = 0; 3484 break; 3485 3486 case UHF_C_PORT_RESET: 3487 sc->sc_flags.change_reset = 0; 3488 break; 3489 3490 case UHF_C_PORT_ENABLE: 3491 sc->sc_flags.change_enabled = 0; 3492 break; 3493 3494 case UHF_C_PORT_OVER_CURRENT: 3495 sc->sc_flags.change_over_current = 0; 3496 break; 3497 3498 case UHF_PORT_TEST: 3499 case UHF_PORT_INDICATOR: 3500 /* nops */ 3501 break; 3502 3503 case UHF_PORT_POWER: 3504 sc->sc_flags.port_powered = 0; 3505 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3506 sc->sc_hprt_val = 0; 3507 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 3508 } 3509 dwc_otg_pull_down(sc); 3510 dwc_otg_clocks_off(sc); 3511 break; 3512 3513 case UHF_C_PORT_CONNECTION: 3514 /* clear connect change flag */ 3515 sc->sc_flags.change_connect = 0; 3516 break; 3517 3518 case UHF_C_PORT_SUSPEND: 3519 sc->sc_flags.change_suspend = 0; 3520 break; 3521 3522 default: 3523 err = USB_ERR_IOERROR; 3524 goto done; 3525 } 3526 goto tr_valid; 3527 3528 tr_handle_set_port_feature: 3529 if (index != 1) { 3530 goto tr_stalled; 3531 } 3532 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 3533 3534 switch (value) { 3535 case UHF_PORT_ENABLE: 3536 break; 3537 3538 case UHF_PORT_SUSPEND: 3539 if (sc->sc_flags.status_device_mode == 0) { 3540 /* set suspend BIT */ 3541 sc->sc_hprt_val |= HPRT_PRTSUSP; 3542 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3543 3544 /* generate HUB suspend event */ 3545 dwc_otg_suspend_irq(sc); 3546 } 3547 break; 3548 3549 case UHF_PORT_RESET: 3550 if (sc->sc_flags.status_device_mode == 0) { 3551 3552 DPRINTF("PORT RESET\n"); 3553 3554 /* enable PORT reset */ 3555 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 3556 3557 /* Wait 62.5ms for reset to complete */ 3558 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3559 3560 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3561 3562 /* Wait 62.5ms for reset to complete */ 3563 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 3564 3565 /* reset FIFOs */ 3566 dwc_otg_init_fifo(sc, DWC_MODE_HOST); 3567 3568 sc->sc_flags.change_reset = 1; 3569 } else { 3570 err = USB_ERR_IOERROR; 3571 } 3572 break; 3573 3574 case UHF_PORT_TEST: 3575 case UHF_PORT_INDICATOR: 3576 /* nops */ 3577 break; 3578 case UHF_PORT_POWER: 3579 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 3580 sc->sc_hprt_val |= HPRT_PRTPWR; 3581 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 3582 } 3583 sc->sc_flags.port_powered = 1; 3584 break; 3585 default: 3586 err = USB_ERR_IOERROR; 3587 goto done; 3588 } 3589 goto tr_valid; 3590 3591 tr_handle_get_port_status: 3592 3593 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 3594 3595 if (index != 1) 3596 goto tr_stalled; 3597 3598 if (sc->sc_flags.status_vbus) 3599 dwc_otg_clocks_on(sc); 3600 else 3601 dwc_otg_clocks_off(sc); 3602 3603 /* Select Device Side Mode */ 3604 3605 if (sc->sc_flags.status_device_mode) 3606 value = UPS_PORT_MODE_DEVICE; 3607 else 3608 value = 0; 3609 3610 if (sc->sc_flags.status_high_speed) 3611 value |= UPS_HIGH_SPEED; 3612 else if (sc->sc_flags.status_low_speed) 3613 value |= UPS_LOW_SPEED; 3614 3615 if (sc->sc_flags.port_powered) 3616 value |= UPS_PORT_POWER; 3617 3618 if (sc->sc_flags.port_enabled) 3619 value |= UPS_PORT_ENABLED; 3620 3621 if (sc->sc_flags.port_over_current) 3622 value |= UPS_OVERCURRENT_INDICATOR; 3623 3624 if (sc->sc_flags.status_vbus && 3625 sc->sc_flags.status_bus_reset) 3626 value |= UPS_CURRENT_CONNECT_STATUS; 3627 3628 if (sc->sc_flags.status_suspend) 3629 value |= UPS_SUSPEND; 3630 3631 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 3632 3633 value = 0; 3634 3635 if (sc->sc_flags.change_connect) 3636 value |= UPS_C_CONNECT_STATUS; 3637 if (sc->sc_flags.change_suspend) 3638 value |= UPS_C_SUSPEND; 3639 if (sc->sc_flags.change_reset) 3640 value |= UPS_C_PORT_RESET; 3641 if (sc->sc_flags.change_over_current) 3642 value |= UPS_C_OVERCURRENT_INDICATOR; 3643 3644 USETW(sc->sc_hub_temp.ps.wPortChange, value); 3645 len = sizeof(sc->sc_hub_temp.ps); 3646 goto tr_valid; 3647 3648 tr_handle_get_class_descriptor: 3649 if (value & 0xFF) { 3650 goto tr_stalled; 3651 } 3652 ptr = (const void *)&dwc_otg_hubd; 3653 len = sizeof(dwc_otg_hubd); 3654 goto tr_valid; 3655 3656 tr_stalled: 3657 err = USB_ERR_STALLED; 3658 tr_valid: 3659 done: 3660 *plength = len; 3661 *pptr = ptr; 3662 return (err); 3663 } 3664 3665 static void 3666 dwc_otg_xfer_setup(struct usb_setup_params *parm) 3667 { 3668 const struct usb_hw_ep_profile *pf; 3669 struct usb_xfer *xfer; 3670 void *last_obj; 3671 uint32_t ntd; 3672 uint32_t n; 3673 uint8_t ep_no; 3674 3675 xfer = parm->curr_xfer; 3676 3677 /* 3678 * NOTE: This driver does not use any of the parameters that 3679 * are computed from the following values. Just set some 3680 * reasonable dummies: 3681 */ 3682 parm->hc_max_packet_size = 0x500; 3683 parm->hc_max_packet_count = 1; 3684 parm->hc_max_frame_size = 0x500; 3685 3686 usbd_transfer_setup_sub(parm); 3687 3688 /* 3689 * compute maximum number of TDs 3690 */ 3691 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 3692 3693 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 3694 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 3695 } else { 3696 3697 ntd = xfer->nframes + 1 /* SYNC */ ; 3698 } 3699 3700 /* 3701 * check if "usbd_transfer_setup_sub" set an error 3702 */ 3703 if (parm->err) 3704 return; 3705 3706 /* 3707 * allocate transfer descriptors 3708 */ 3709 last_obj = NULL; 3710 3711 /* 3712 * get profile stuff 3713 */ 3714 ep_no = xfer->endpointno & UE_ADDR; 3715 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 3716 3717 if (pf == NULL) { 3718 /* should not happen */ 3719 parm->err = USB_ERR_INVAL; 3720 return; 3721 } 3722 3723 /* align data */ 3724 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 3725 3726 for (n = 0; n != ntd; n++) { 3727 3728 struct dwc_otg_td *td; 3729 3730 if (parm->buf) { 3731 3732 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 3733 3734 /* init TD */ 3735 td->max_packet_size = xfer->max_packet_size; 3736 td->ep_no = ep_no; 3737 td->obj_next = last_obj; 3738 3739 last_obj = td; 3740 } 3741 parm->size[0] += sizeof(*td); 3742 } 3743 3744 xfer->td_start[0] = last_obj; 3745 } 3746 3747 static void 3748 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 3749 { 3750 return; 3751 } 3752 3753 static void 3754 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3755 struct usb_endpoint *ep) 3756 { 3757 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3758 3759 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 3760 ep, udev->address, 3761 edesc->bEndpointAddress, udev->flags.usb_mode, 3762 sc->sc_rt_addr, udev->device_index); 3763 3764 if (udev->device_index != sc->sc_rt_addr) { 3765 3766 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 3767 if (udev->speed != USB_SPEED_FULL && 3768 udev->speed != USB_SPEED_HIGH) { 3769 /* not supported */ 3770 return; 3771 } 3772 } else { 3773 if (udev->speed != USB_SPEED_LOW && 3774 udev->speed != USB_SPEED_FULL && 3775 udev->speed != USB_SPEED_HIGH) { 3776 /* not supported */ 3777 return; 3778 } 3779 } 3780 3781 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 3782 ep->methods = &dwc_otg_device_isoc_methods; 3783 else 3784 ep->methods = &dwc_otg_device_non_isoc_methods; 3785 } 3786 } 3787 3788 static void 3789 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3790 { 3791 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3792 3793 switch (state) { 3794 case USB_HW_POWER_SUSPEND: 3795 dwc_otg_suspend(sc); 3796 break; 3797 case USB_HW_POWER_SHUTDOWN: 3798 dwc_otg_uninit(sc); 3799 break; 3800 case USB_HW_POWER_RESUME: 3801 dwc_otg_resume(sc); 3802 break; 3803 default: 3804 break; 3805 } 3806 } 3807 3808 static void 3809 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3810 { 3811 /* DMA delay - wait until any use of memory is finished */ 3812 *pus = (2125); /* microseconds */ 3813 } 3814 3815 static void 3816 dwc_otg_device_resume(struct usb_device *udev) 3817 { 3818 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3819 struct usb_xfer *xfer; 3820 struct dwc_otg_td *td; 3821 3822 DPRINTF("\n"); 3823 3824 /* Enable relevant Host channels before resuming */ 3825 3826 USB_BUS_LOCK(udev->bus); 3827 3828 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3829 3830 if (xfer->xroot->udev == udev) { 3831 3832 td = xfer->td_transfer_cache; 3833 if (td != NULL && 3834 td->channel < DWC_OTG_MAX_CHANNELS) { 3835 sc->sc_chan_state[td->channel].hcint &= 3836 ~HCINT_SUSPEND_ONLY; 3837 3838 if (sc->sc_chan_state[td->channel].sof_requested == 0) { 3839 sc->sc_chan_state[td->channel].sof_requested = 1; 3840 dwc_otg_request_sof(sc); 3841 } 3842 } 3843 } 3844 } 3845 3846 USB_BUS_UNLOCK(udev->bus); 3847 3848 /* poll all transfers again to restart resumed ones */ 3849 dwc_otg_do_poll(udev->bus); 3850 } 3851 3852 static void 3853 dwc_otg_device_suspend(struct usb_device *udev) 3854 { 3855 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 3856 struct usb_xfer *xfer; 3857 struct dwc_otg_td *td; 3858 3859 DPRINTF("\n"); 3860 3861 /* Disable relevant Host channels before going to suspend */ 3862 3863 USB_BUS_LOCK(udev->bus); 3864 3865 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3866 3867 if (xfer->xroot->udev == udev) { 3868 3869 td = xfer->td_transfer_cache; 3870 if (td != NULL && 3871 td->channel < DWC_OTG_MAX_CHANNELS) { 3872 3873 sc->sc_chan_state[td->channel].hcint |= 3874 HCINT_NAK | HCINT_CHHLTD | HCINT_SUSPEND_ONLY; 3875 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), 3876 HCCHAR_CHENA | HCCHAR_CHDIS); 3877 3878 if (sc->sc_chan_state[td->channel].sof_requested != 0) { 3879 sc->sc_chan_state[td->channel].sof_requested = 0; 3880 dwc_otg_release_sof(sc); 3881 } 3882 } 3883 } 3884 } 3885 3886 USB_BUS_UNLOCK(udev->bus); 3887 } 3888 3889 struct usb_bus_methods dwc_otg_bus_methods = 3890 { 3891 .endpoint_init = &dwc_otg_ep_init, 3892 .xfer_setup = &dwc_otg_xfer_setup, 3893 .xfer_unsetup = &dwc_otg_xfer_unsetup, 3894 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 3895 .xfer_stall = &dwc_otg_xfer_stall, 3896 .set_stall = &dwc_otg_set_stall, 3897 .clear_stall = &dwc_otg_clear_stall, 3898 .roothub_exec = &dwc_otg_roothub_exec, 3899 .xfer_poll = &dwc_otg_do_poll, 3900 .device_state_change = &dwc_otg_device_state_change, 3901 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 3902 .get_dma_delay = &dwc_otg_get_dma_delay, 3903 .device_resume = &dwc_otg_device_resume, 3904 .device_suspend = &dwc_otg_device_suspend, 3905 }; 3906