1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved. 4 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved. 5 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the DesignWare series USB 2.0 OTG 31 * Controller. 32 */ 33 34 /* 35 * LIMITATION: Drivers must be bound to all OUT endpoints in the 36 * active configuration for this driver to work properly. Blocking any 37 * OUT endpoint will block all OUT endpoints including the control 38 * endpoint. Usually this is not a problem. 39 */ 40 41 /* 42 * NOTE: Writing to non-existing registers appears to cause an 43 * internal reset. 44 */ 45 46 #ifdef USB_GLOBAL_INCLUDE_FILE 47 #include USB_GLOBAL_INCLUDE_FILE 48 #else 49 #include <sys/stdint.h> 50 #include <sys/stddef.h> 51 #include <sys/param.h> 52 #include <sys/queue.h> 53 #include <sys/types.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/bus.h> 57 #include <sys/module.h> 58 #include <sys/lock.h> 59 #include <sys/mutex.h> 60 #include <sys/condvar.h> 61 #include <sys/sysctl.h> 62 #include <sys/sx.h> 63 #include <sys/unistd.h> 64 #include <sys/callout.h> 65 #include <sys/malloc.h> 66 #include <sys/priv.h> 67 68 #include <dev/usb/usb.h> 69 #include <dev/usb/usbdi.h> 70 71 #define USB_DEBUG_VAR dwc_otg_debug 72 73 #include <dev/usb/usb_core.h> 74 #include <dev/usb/usb_debug.h> 75 #include <dev/usb/usb_busdma.h> 76 #include <dev/usb/usb_process.h> 77 #include <dev/usb/usb_transfer.h> 78 #include <dev/usb/usb_device.h> 79 #include <dev/usb/usb_hub.h> 80 #include <dev/usb/usb_util.h> 81 82 #include <dev/usb/usb_controller.h> 83 #include <dev/usb/usb_bus.h> 84 #endif /* USB_GLOBAL_INCLUDE_FILE */ 85 86 #include <dev/usb/controller/dwc_otg.h> 87 #include <dev/usb/controller/dwc_otgreg.h> 88 89 #define DWC_OTG_BUS2SC(bus) \ 90 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 91 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 92 93 #define DWC_OTG_PC2UDEV(pc) \ 94 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 95 96 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 97 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 98 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 99 GINTSTS_SESSREQINT) 100 101 #define DWC_OTG_PHY_ULPI 0 102 #define DWC_OTG_PHY_HSIC 1 103 #define DWC_OTG_PHY_INTERNAL 2 104 105 #ifndef DWC_OTG_PHY_DEFAULT 106 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 107 #endif 108 109 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 110 111 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 112 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 113 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 114 115 #ifdef USB_DEBUG 116 static int dwc_otg_debug; 117 118 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 119 &dwc_otg_debug, 0, "DWC OTG debug level"); 120 #endif 121 122 #define DWC_OTG_INTR_ENDPT 1 123 124 /* prototypes */ 125 126 static const struct usb_bus_methods dwc_otg_bus_methods; 127 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 128 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 129 130 static dwc_otg_cmd_t dwc_otg_setup_rx; 131 static dwc_otg_cmd_t dwc_otg_data_rx; 132 static dwc_otg_cmd_t dwc_otg_data_tx; 133 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 134 135 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 136 static dwc_otg_cmd_t dwc_otg_host_data_tx; 137 static dwc_otg_cmd_t dwc_otg_host_data_rx; 138 139 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 140 static void dwc_otg_do_poll(struct usb_bus *); 141 static void dwc_otg_standard_done(struct usb_xfer *); 142 static void dwc_otg_root_intr(struct dwc_otg_softc *); 143 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 144 145 /* 146 * Here is a configuration that the chip supports. 147 */ 148 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 149 150 [0] = { 151 .max_in_frame_size = 64,/* fixed */ 152 .max_out_frame_size = 64, /* fixed */ 153 .is_simplex = 1, 154 .support_control = 1, 155 } 156 }; 157 158 static void 159 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 160 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 161 { 162 struct dwc_otg_softc *sc; 163 164 sc = DWC_OTG_BUS2SC(udev->bus); 165 166 if (ep_addr < sc->sc_dev_ep_max) 167 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 168 else 169 *ppf = NULL; 170 } 171 172 static void 173 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 174 uint32_t offset, uint32_t fifo, uint32_t count) 175 { 176 uint32_t temp; 177 178 /* round down length to nearest 4-bytes */ 179 temp = count & ~3; 180 181 /* check if we can write the data directly */ 182 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 183 struct usb_page_search buf_res; 184 185 /* pre-subtract length */ 186 count -= temp; 187 188 /* iterate buffer list */ 189 do { 190 /* get current buffer pointer */ 191 usbd_get_page(pc, offset, &buf_res); 192 193 if (buf_res.length > temp) 194 buf_res.length = temp; 195 196 /* transfer data into FIFO */ 197 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 198 fifo, buf_res.buffer, buf_res.length / 4); 199 200 offset += buf_res.length; 201 fifo += buf_res.length; 202 temp -= buf_res.length; 203 } while (temp != 0); 204 } 205 206 /* check for remainder */ 207 if (count != 0) { 208 /* clear topmost word before copy */ 209 sc->sc_bounce_buffer[(count - 1) / 4] = 0; 210 211 /* copy out data */ 212 usbd_copy_out(pc, offset, 213 sc->sc_bounce_buffer, count); 214 215 /* transfer data into FIFO */ 216 bus_space_write_region_4(sc->sc_io_tag, 217 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer, 218 (count + 3) / 4); 219 } 220 } 221 222 static void 223 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc, 224 uint32_t offset, uint32_t count) 225 { 226 uint32_t temp; 227 228 /* round down length to nearest 4-bytes */ 229 temp = count & ~3; 230 231 /* check if we can read the data directly */ 232 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) { 233 struct usb_page_search buf_res; 234 235 /* pre-subtract length */ 236 count -= temp; 237 238 /* iterate buffer list */ 239 do { 240 /* get current buffer pointer */ 241 usbd_get_page(pc, offset, &buf_res); 242 243 if (buf_res.length > temp) 244 buf_res.length = temp; 245 246 /* transfer data from FIFO */ 247 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 248 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4); 249 250 offset += buf_res.length; 251 sc->sc_current_rx_fifo += buf_res.length; 252 sc->sc_current_rx_bytes -= buf_res.length; 253 temp -= buf_res.length; 254 } while (temp != 0); 255 } 256 257 /* check for remainder */ 258 if (count != 0) { 259 /* read data into bounce buffer */ 260 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 261 sc->sc_current_rx_fifo, 262 sc->sc_bounce_buffer, (count + 3) / 4); 263 264 /* store data into proper buffer */ 265 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count); 266 267 /* round length up to nearest 4 bytes */ 268 count = (count + 3) & ~3; 269 270 /* update counters */ 271 sc->sc_current_rx_bytes -= count; 272 sc->sc_current_rx_fifo += count; 273 } 274 } 275 276 static void 277 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value) 278 { 279 uint32_t temp; 280 281 /* reset FIFO */ 282 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value); 283 284 /* wait for reset to complete */ 285 for (temp = 0; temp != 16; temp++) { 286 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL); 287 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))) 288 break; 289 } 290 } 291 292 static int 293 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 294 { 295 struct dwc_otg_profile *pf; 296 uint32_t fifo_size; 297 uint32_t fifo_regs; 298 uint32_t tx_start; 299 uint8_t x; 300 301 fifo_size = sc->sc_fifo_size; 302 303 /* 304 * NOTE: Reserved fixed size area at end of RAM, which must 305 * not be allocated to the FIFOs: 306 */ 307 fifo_regs = 4 * 16; 308 309 if (fifo_size < fifo_regs) { 310 DPRINTF("Too little FIFO\n"); 311 return (EINVAL); 312 } 313 314 /* subtract FIFO regs from total once */ 315 fifo_size -= fifo_regs; 316 317 /* split equally for IN and OUT */ 318 fifo_size /= 2; 319 320 /* Align to 4 bytes boundary (refer to PGM) */ 321 fifo_size &= ~3; 322 323 /* set global receive FIFO size */ 324 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 325 326 tx_start = fifo_size; 327 328 if (fifo_size < 64) { 329 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 330 return (EINVAL); 331 } 332 333 if (mode == DWC_MODE_HOST) { 334 335 /* reset active endpoints */ 336 sc->sc_active_rx_ep = 0; 337 338 /* split equally for periodic and non-periodic */ 339 fifo_size /= 2; 340 341 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size); 342 343 /* align to 4 bytes boundary */ 344 fifo_size &= ~3; 345 346 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 347 ((fifo_size / 4) << 16) | 348 (tx_start / 4)); 349 350 tx_start += fifo_size; 351 352 for (x = 0; x != sc->sc_host_ch_max; x++) { 353 /* enable all host interrupts */ 354 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 355 HCINT_DEFAULT_MASK); 356 } 357 358 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 359 ((fifo_size / 4) << 16) | 360 (tx_start / 4)); 361 362 /* reset host channel state */ 363 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 364 365 /* enable all host channel interrupts */ 366 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 367 (1U << sc->sc_host_ch_max) - 1U); 368 369 /* enable proper host channel interrupts */ 370 sc->sc_irq_mask |= GINTMSK_HCHINTMSK; 371 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK; 372 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 373 } 374 375 if (mode == DWC_MODE_DEVICE) { 376 377 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 378 (0x10 << 16) | (tx_start / 4)); 379 fifo_size -= 0x40; 380 tx_start += 0x40; 381 382 /* setup control endpoint profile */ 383 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 384 385 /* reset active endpoints */ 386 sc->sc_active_rx_ep = 1; 387 388 for (x = 1; x != sc->sc_dev_ep_max; x++) { 389 390 pf = sc->sc_hw_ep_profile + x; 391 392 pf->usb.max_out_frame_size = 1024 * 3; 393 pf->usb.is_simplex = 0; /* assume duplex */ 394 pf->usb.support_bulk = 1; 395 pf->usb.support_interrupt = 1; 396 pf->usb.support_isochronous = 1; 397 pf->usb.support_out = 1; 398 399 if (x < sc->sc_dev_in_ep_max) { 400 uint32_t limit; 401 402 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 403 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 404 DWC_OTG_TX_MAX_FIFO_SIZE); 405 406 /* see if there is enough FIFO space */ 407 if (limit <= fifo_size) { 408 pf->max_buffer = limit; 409 pf->usb.support_in = 1; 410 } else { 411 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 412 if (limit <= fifo_size) { 413 pf->usb.support_in = 1; 414 } else { 415 pf->usb.is_simplex = 1; 416 limit = 0; 417 } 418 } 419 /* set FIFO size */ 420 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 421 ((limit / 4) << 16) | (tx_start / 4)); 422 tx_start += limit; 423 fifo_size -= limit; 424 pf->usb.max_in_frame_size = limit; 425 } else { 426 pf->usb.is_simplex = 1; 427 } 428 429 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 430 pf->usb.max_in_frame_size, 431 pf->usb.max_out_frame_size); 432 } 433 434 /* enable proper device channel interrupts */ 435 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK; 436 sc->sc_irq_mask |= GINTMSK_IEPINTMSK; 437 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 438 } 439 440 /* reset RX FIFO */ 441 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH); 442 443 if (mode != DWC_MODE_OTG) { 444 /* reset all TX FIFOs */ 445 dwc_otg_tx_fifo_reset(sc, 446 GRSTCTL_TXFIFO(0x10) | 447 GRSTCTL_TXFFLSH); 448 } else { 449 /* reset active endpoints */ 450 sc->sc_active_rx_ep = 0; 451 452 /* reset host channel state */ 453 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 454 } 455 return (0); 456 } 457 458 static uint8_t 459 dwc_otg_uses_split(struct usb_device *udev) 460 { 461 /* 462 * When a LOW or FULL speed device is connected directly to 463 * the USB port we don't use split transactions: 464 */ 465 return (udev->speed != USB_SPEED_HIGH && 466 udev->parent_hs_hub != NULL && 467 udev->parent_hs_hub->parent_hub != NULL); 468 } 469 470 static void 471 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 472 { 473 474 /* 475 * Disabled until further. Assuming that the register is already 476 * programmed correctly by the boot loader. 477 */ 478 #if 0 479 uint32_t temp; 480 481 /* setup HOST frame interval register, based on existing value */ 482 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 483 if (temp >= 10000) 484 temp /= 1000; 485 else 486 temp /= 125; 487 488 /* figure out nearest X-tal value */ 489 if (temp >= 54) 490 temp = 60; /* MHz */ 491 else if (temp >= 39) 492 temp = 48; /* MHz */ 493 else 494 temp = 30; /* MHz */ 495 496 if (sc->sc_flags.status_high_speed) 497 temp *= 125; 498 else 499 temp *= 1000; 500 501 DPRINTF("HFIR=0x%08x\n", temp); 502 503 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 504 #endif 505 } 506 507 static void 508 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 509 { 510 if (sc->sc_flags.clocks_off && 511 sc->sc_flags.port_powered) { 512 513 DPRINTFN(5, "\n"); 514 515 /* TODO - platform specific */ 516 517 sc->sc_flags.clocks_off = 0; 518 } 519 } 520 521 static void 522 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 523 { 524 if (!sc->sc_flags.clocks_off) { 525 526 DPRINTFN(5, "\n"); 527 528 /* TODO - platform specific */ 529 530 sc->sc_flags.clocks_off = 1; 531 } 532 } 533 534 static void 535 dwc_otg_pull_up(struct dwc_otg_softc *sc) 536 { 537 uint32_t temp; 538 539 /* pullup D+, if possible */ 540 541 if (!sc->sc_flags.d_pulled_up && 542 sc->sc_flags.port_powered) { 543 sc->sc_flags.d_pulled_up = 1; 544 545 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 546 temp &= ~DCTL_SFTDISCON; 547 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 548 } 549 } 550 551 static void 552 dwc_otg_pull_down(struct dwc_otg_softc *sc) 553 { 554 uint32_t temp; 555 556 /* pulldown D+, if possible */ 557 558 if (sc->sc_flags.d_pulled_up) { 559 sc->sc_flags.d_pulled_up = 0; 560 561 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 562 temp |= DCTL_SFTDISCON; 563 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 564 } 565 } 566 567 static void 568 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 569 { 570 /* In device mode we don't use the SOF interrupt */ 571 if (sc->sc_flags.status_device_mode != 0) 572 return; 573 /* Ensure the SOF interrupt is not disabled */ 574 sc->sc_needsof = 1; 575 /* Check if the SOF interrupt is already enabled */ 576 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 577 return; 578 sc->sc_irq_mask |= GINTMSK_SOFMSK; 579 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 580 } 581 582 static void 583 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 584 { 585 if (sc->sc_flags.status_suspend) { 586 /* update status bits */ 587 sc->sc_flags.status_suspend = 0; 588 sc->sc_flags.change_suspend = 1; 589 590 if (sc->sc_flags.status_device_mode) { 591 /* 592 * Disable resume interrupt and enable suspend 593 * interrupt: 594 */ 595 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 596 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 597 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 598 } 599 600 /* complete root HUB interrupt endpoint */ 601 dwc_otg_root_intr(sc); 602 } 603 } 604 605 static void 606 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 607 { 608 if (!sc->sc_flags.status_suspend) { 609 /* update status bits */ 610 sc->sc_flags.status_suspend = 1; 611 sc->sc_flags.change_suspend = 1; 612 613 if (sc->sc_flags.status_device_mode) { 614 /* 615 * Disable suspend interrupt and enable resume 616 * interrupt: 617 */ 618 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 619 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 620 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 621 } 622 623 /* complete root HUB interrupt endpoint */ 624 dwc_otg_root_intr(sc); 625 } 626 } 627 628 static void 629 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 630 { 631 if (!sc->sc_flags.status_suspend) 632 return; 633 634 DPRINTFN(5, "Remote wakeup\n"); 635 636 if (sc->sc_flags.status_device_mode) { 637 uint32_t temp; 638 639 /* enable remote wakeup signalling */ 640 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 641 temp |= DCTL_RMTWKUPSIG; 642 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 643 644 /* Wait 8ms for remote wakeup to complete. */ 645 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 646 647 temp &= ~DCTL_RMTWKUPSIG; 648 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 649 } else { 650 /* enable USB port */ 651 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 652 653 /* wait 10ms */ 654 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 655 656 /* resume port */ 657 sc->sc_hprt_val |= HPRT_PRTRES; 658 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 659 660 /* Wait 100ms for resume signalling to complete. */ 661 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 662 663 /* clear suspend and resume */ 664 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 665 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 666 667 /* Wait 4ms */ 668 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 669 } 670 671 /* need to fake resume IRQ */ 672 dwc_otg_resume_irq(sc); 673 } 674 675 static void 676 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 677 { 678 uint32_t temp; 679 680 DPRINTFN(5, "addr=%d\n", addr); 681 682 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 683 temp &= ~DCFG_DEVADDR_SET(0x7F); 684 temp |= DCFG_DEVADDR_SET(addr); 685 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 686 } 687 688 static void 689 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 690 { 691 DPRINTFN(5, "RX status clear\n"); 692 693 /* enable RX FIFO level interrupt */ 694 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 695 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 696 697 if (sc->sc_current_rx_bytes != 0) { 698 /* need to dump remaining data */ 699 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 700 sc->sc_current_rx_fifo, sc->sc_bounce_buffer, 701 sc->sc_current_rx_bytes / 4); 702 /* clear number of active bytes to receive */ 703 sc->sc_current_rx_bytes = 0; 704 } 705 /* clear cached status */ 706 sc->sc_last_rx_status = 0; 707 } 708 709 static void 710 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 711 { 712 uint32_t hcint; 713 714 /* clear all pending interrupts */ 715 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 716 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 717 718 /* clear buffered interrupts */ 719 sc->sc_chan_state[x].hcint = 0; 720 } 721 722 static uint8_t 723 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 724 { 725 uint32_t temp; 726 727 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 728 729 if (td->ep_type == UE_ISOCHRONOUS) { 730 /* 731 * NOTE: USB INTERRUPT transactions are executed like 732 * USB CONTROL transactions! See the setup standard 733 * chain function for more information. 734 */ 735 if (!(temp & GINTSTS_PTXFEMP)) { 736 DPRINTF("Periodic TX FIFO is not empty\n"); 737 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) { 738 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK; 739 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 740 } 741 return (1); /* busy */ 742 } 743 } else { 744 if (!(temp & GINTSTS_NPTXFEMP)) { 745 DPRINTF("Non-periodic TX FIFO is not empty\n"); 746 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) { 747 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK; 748 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 749 } 750 return (1); /* busy */ 751 } 752 } 753 return (0); /* ready for transmit */ 754 } 755 756 static uint8_t 757 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, 758 struct dwc_otg_td *td, uint8_t is_out) 759 { 760 uint8_t x; 761 uint8_t y; 762 uint8_t z; 763 764 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) 765 return (0); /* already allocated */ 766 767 /* check if device is suspended */ 768 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 769 return (1); /* busy - cannot transfer data */ 770 771 /* compute needed TX FIFO size */ 772 if (is_out != 0) { 773 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0) 774 return (1); /* busy - cannot transfer data */ 775 } 776 z = td->max_packet_count; 777 for (x = y = 0; x != sc->sc_host_ch_max; x++) { 778 /* check if channel is allocated */ 779 if (sc->sc_chan_state[x].allocated != 0) 780 continue; 781 /* check if channel is still enabled */ 782 if (sc->sc_chan_state[x].wait_halted != 0) 783 continue; 784 /* store channel number */ 785 td->channel[y++] = x; 786 /* check if we got all channels */ 787 if (y == z) 788 break; 789 } 790 if (y != z) { 791 /* reset channel variable */ 792 td->channel[0] = DWC_OTG_MAX_CHANNELS; 793 td->channel[1] = DWC_OTG_MAX_CHANNELS; 794 td->channel[2] = DWC_OTG_MAX_CHANNELS; 795 /* wait a bit */ 796 dwc_otg_enable_sof_irq(sc); 797 return (1); /* busy - not enough channels */ 798 } 799 800 for (y = 0; y != z; y++) { 801 x = td->channel[y]; 802 803 /* set allocated */ 804 sc->sc_chan_state[x].allocated = 1; 805 806 /* set wait halted */ 807 sc->sc_chan_state[x].wait_halted = 1; 808 809 /* clear interrupts */ 810 dwc_otg_clear_hcint(sc, x); 811 812 DPRINTF("CH=%d HCCHAR=0x%08x " 813 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 814 815 /* set active channel */ 816 sc->sc_active_rx_ep |= (1 << x); 817 } 818 return (0); /* allocated */ 819 } 820 821 static void 822 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index) 823 { 824 uint32_t hcchar; 825 uint8_t x; 826 827 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS) 828 return; /* already freed */ 829 830 /* free channel */ 831 x = td->channel[index]; 832 td->channel[index] = DWC_OTG_MAX_CHANNELS; 833 834 DPRINTF("CH=%d\n", x); 835 836 /* 837 * We need to let programmed host channels run till complete 838 * else the host channel will stop functioning. 839 */ 840 sc->sc_chan_state[x].allocated = 0; 841 842 /* ack any pending messages */ 843 if (sc->sc_last_rx_status != 0 && 844 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 845 dwc_otg_common_rx_ack(sc); 846 } 847 848 /* clear active channel */ 849 sc->sc_active_rx_ep &= ~(1 << x); 850 851 /* check if already halted */ 852 if (sc->sc_chan_state[x].wait_halted == 0) 853 return; 854 855 /* disable host channel */ 856 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 857 if (hcchar & HCCHAR_CHENA) { 858 DPRINTF("Halting channel %d\n", x); 859 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 860 hcchar | HCCHAR_CHDIS); 861 /* don't write HCCHAR until the channel is halted */ 862 } else { 863 sc->sc_chan_state[x].wait_halted = 0; 864 } 865 } 866 867 static void 868 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 869 { 870 uint8_t x; 871 for (x = 0; x != td->max_packet_count; x++) 872 dwc_otg_host_channel_free_sub(sc, td, x); 873 } 874 875 static void 876 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 877 { 878 uint8_t x; 879 /* dump any pending messages */ 880 if (sc->sc_last_rx_status == 0) 881 return; 882 for (x = 0; x != td->max_packet_count; x++) { 883 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS || 884 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) 885 continue; 886 dwc_otg_common_rx_ack(sc); 887 break; 888 } 889 } 890 891 static uint8_t 892 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 893 { 894 struct usb_device_request req __aligned(4); 895 uint32_t hcint; 896 uint32_t hcchar; 897 uint8_t delta; 898 899 dwc_otg_host_dump_rx(sc, td); 900 901 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) { 902 hcint = sc->sc_chan_state[td->channel[0]].hcint; 903 904 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 905 td->channel[0], td->state, hcint, 906 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])), 907 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0]))); 908 } else { 909 hcint = 0; 910 goto check_state; 911 } 912 913 if (hcint & (HCINT_RETRY | 914 HCINT_ACK | HCINT_NYET)) { 915 /* give success bits priority over failure bits */ 916 } else if (hcint & HCINT_STALL) { 917 DPRINTF("CH=%d STALL\n", td->channel[0]); 918 td->error_stall = 1; 919 td->error_any = 1; 920 goto complete; 921 } else if (hcint & HCINT_ERRORS) { 922 DPRINTF("CH=%d ERROR\n", td->channel[0]); 923 td->errcnt++; 924 if (td->hcsplt != 0 || td->errcnt >= 3) { 925 td->error_any = 1; 926 goto complete; 927 } 928 } 929 930 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 931 HCINT_ACK | HCINT_NYET)) { 932 if (!(hcint & HCINT_ERRORS)) 933 td->errcnt = 0; 934 } 935 936 check_state: 937 switch (td->state) { 938 case DWC_CHAN_ST_START: 939 goto send_pkt; 940 941 case DWC_CHAN_ST_WAIT_ANE: 942 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 943 td->did_nak = 1; 944 td->tt_scheduled = 0; 945 goto send_pkt; 946 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 947 td->offset += td->tx_bytes; 948 td->remainder -= td->tx_bytes; 949 td->toggle = 1; 950 td->tt_scheduled = 0; 951 goto complete; 952 } 953 break; 954 955 case DWC_CHAN_ST_WAIT_S_ANE: 956 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 957 td->did_nak = 1; 958 td->tt_scheduled = 0; 959 goto send_pkt; 960 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 961 goto send_cpkt; 962 } 963 break; 964 965 case DWC_CHAN_ST_WAIT_C_ANE: 966 if (hcint & HCINT_NYET) { 967 goto send_cpkt; 968 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 969 td->did_nak = 1; 970 td->tt_scheduled = 0; 971 goto send_pkt; 972 } else if (hcint & HCINT_ACK) { 973 td->offset += td->tx_bytes; 974 td->remainder -= td->tx_bytes; 975 td->toggle = 1; 976 goto complete; 977 } 978 break; 979 980 case DWC_CHAN_ST_WAIT_C_PKT: 981 goto send_cpkt; 982 983 default: 984 break; 985 } 986 goto busy; 987 988 send_pkt: 989 /* free existing channel, if any */ 990 dwc_otg_host_channel_free(sc, td); 991 992 if (sizeof(req) != td->remainder) { 993 td->error_any = 1; 994 goto complete; 995 } 996 997 if (td->hcsplt != 0) { 998 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 999 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1000 td->state = DWC_CHAN_ST_START; 1001 goto busy; 1002 } 1003 delta = sc->sc_last_frame_num - td->tt_start_slot; 1004 if (delta > 5) { 1005 /* missed it */ 1006 td->tt_scheduled = 0; 1007 td->state = DWC_CHAN_ST_START; 1008 goto busy; 1009 } 1010 } 1011 1012 /* allocate a new channel */ 1013 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1014 td->state = DWC_CHAN_ST_START; 1015 goto busy; 1016 } 1017 1018 if (td->hcsplt != 0) { 1019 td->hcsplt &= ~HCSPLT_COMPSPLT; 1020 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1021 } else { 1022 td->state = DWC_CHAN_ST_WAIT_ANE; 1023 } 1024 1025 /* copy out control request */ 1026 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1027 1028 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1029 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 1030 (1 << HCTSIZ_PKTCNT_SHIFT) | 1031 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1032 1033 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1034 1035 hcchar = td->hcchar; 1036 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1037 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1038 1039 /* must enable channel before writing data to FIFO */ 1040 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1041 1042 /* transfer data into FIFO */ 1043 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1044 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4); 1045 1046 /* wait until next slot before trying complete split */ 1047 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1048 1049 /* store number of bytes transmitted */ 1050 td->tx_bytes = sizeof(req); 1051 goto busy; 1052 1053 send_cpkt: 1054 /* free existing channel, if any */ 1055 dwc_otg_host_channel_free(sc, td); 1056 1057 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1058 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1059 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1060 goto busy; 1061 } 1062 delta = sc->sc_last_frame_num - td->tt_start_slot; 1063 if (delta > DWC_OTG_TT_SLOT_MAX) { 1064 /* we missed the service interval */ 1065 if (td->ep_type != UE_ISOCHRONOUS) 1066 td->error_any = 1; 1067 goto complete; 1068 } 1069 /* allocate a new channel */ 1070 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1071 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1072 goto busy; 1073 } 1074 1075 /* wait until next slot before trying complete split */ 1076 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1077 1078 td->hcsplt |= HCSPLT_COMPSPLT; 1079 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1080 1081 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]), 1082 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 1083 1084 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt); 1085 1086 hcchar = td->hcchar; 1087 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 1088 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 1089 1090 /* must enable channel before writing data to FIFO */ 1091 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar); 1092 1093 busy: 1094 return (1); /* busy */ 1095 1096 complete: 1097 dwc_otg_host_channel_free(sc, td); 1098 return (0); /* complete */ 1099 } 1100 1101 static uint8_t 1102 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1103 { 1104 struct usb_device_request req __aligned(4); 1105 uint32_t temp; 1106 uint16_t count; 1107 1108 /* check endpoint status */ 1109 1110 if (sc->sc_last_rx_status == 0) 1111 goto not_complete; 1112 1113 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 1114 goto not_complete; 1115 1116 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1117 GRXSTSRD_STP_DATA) { 1118 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1119 GRXSTSRD_STP_COMPLETE || td->remainder != 0) { 1120 /* release FIFO */ 1121 dwc_otg_common_rx_ack(sc); 1122 goto not_complete; 1123 } 1124 /* release FIFO */ 1125 dwc_otg_common_rx_ack(sc); 1126 return (0); /* complete */ 1127 } 1128 1129 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1130 GRXSTSRD_DPID_DATA0) { 1131 /* release FIFO */ 1132 dwc_otg_common_rx_ack(sc); 1133 goto not_complete; 1134 } 1135 1136 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 1137 1138 /* clear did stall */ 1139 td->did_stall = 0; 1140 1141 /* get the packet byte count */ 1142 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1143 1144 if (count != sizeof(req)) { 1145 DPRINTFN(0, "Unsupported SETUP packet " 1146 "length, %d bytes\n", count); 1147 /* release FIFO */ 1148 dwc_otg_common_rx_ack(sc); 1149 goto not_complete; 1150 } 1151 1152 /* read FIFO */ 1153 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req)); 1154 1155 /* copy out control request */ 1156 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 1157 1158 td->offset = sizeof(req); 1159 td->remainder = 0; 1160 1161 /* sneak peek the set address */ 1162 if ((req.bmRequestType == UT_WRITE_DEVICE) && 1163 (req.bRequest == UR_SET_ADDRESS)) { 1164 /* must write address before ZLP */ 1165 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1166 } 1167 1168 /* don't send any data by default */ 1169 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS); 1170 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS); 1171 1172 /* reset IN endpoint buffer */ 1173 dwc_otg_tx_fifo_reset(sc, 1174 GRSTCTL_TXFIFO(0) | 1175 GRSTCTL_TXFFLSH); 1176 1177 /* acknowledge RX status */ 1178 dwc_otg_common_rx_ack(sc); 1179 td->did_stall = 1; 1180 1181 not_complete: 1182 /* abort any ongoing transfer, before enabling again */ 1183 if (!td->did_stall) { 1184 td->did_stall = 1; 1185 1186 DPRINTFN(5, "stalling IN and OUT direction\n"); 1187 1188 temp = sc->sc_out_ctl[0]; 1189 1190 /* set stall after enabling endpoint */ 1191 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1192 temp | DOEPCTL_STALL); 1193 1194 temp = sc->sc_in_ctl[0]; 1195 1196 /* set stall assuming endpoint is enabled */ 1197 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1198 temp | DIEPCTL_STALL); 1199 } 1200 return (1); /* not complete */ 1201 } 1202 1203 static uint8_t 1204 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1205 { 1206 uint8_t delta; 1207 1208 delta = sc->sc_tmr_val - td->tmr_val; 1209 if (delta >= 128) 1210 return (1); /* busy */ 1211 1212 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1213 1214 /* set toggle, if any */ 1215 if (td->set_toggle) { 1216 td->set_toggle = 0; 1217 td->toggle = 1; 1218 } 1219 return (0); 1220 } 1221 1222 static uint8_t 1223 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1224 { 1225 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num; 1226 1227 if (td->ep_type == UE_ISOCHRONOUS) { 1228 /* non TT isochronous traffic */ 1229 if (frame_num & (td->tmr_res - 1)) 1230 goto busy; 1231 if ((frame_num ^ td->tmr_val) & td->tmr_res) 1232 goto busy; 1233 td->tmr_val = td->tmr_res + sc->sc_last_frame_num; 1234 td->toggle = 0; 1235 return (0); 1236 } else if (td->ep_type == UE_INTERRUPT) { 1237 if (!td->tt_scheduled) 1238 goto busy; 1239 td->tt_scheduled = 0; 1240 return (0); 1241 } else if (td->did_nak != 0) { 1242 /* check if we should pause sending queries for 125us */ 1243 if (td->tmr_res == frame_num) { 1244 /* wait a bit */ 1245 dwc_otg_enable_sof_irq(sc); 1246 goto busy; 1247 } 1248 } else if (td->set_toggle) { 1249 td->set_toggle = 0; 1250 td->toggle = 1; 1251 } 1252 /* query for data one more time */ 1253 td->tmr_res = frame_num; 1254 td->did_nak = 0; 1255 return (0); 1256 busy: 1257 return (1); 1258 } 1259 1260 static uint8_t 1261 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, 1262 uint8_t channel) 1263 { 1264 uint32_t count; 1265 1266 /* check endpoint status */ 1267 if (sc->sc_last_rx_status == 0) 1268 goto busy; 1269 1270 if (channel >= DWC_OTG_MAX_CHANNELS) 1271 goto busy; 1272 1273 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1274 goto busy; 1275 1276 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1277 case GRXSTSRH_IN_DATA: 1278 1279 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1280 (int)td->state, (int)sc->sc_last_rx_status); 1281 1282 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1283 /* 1284 * When using SPLIT transactions on interrupt 1285 * endpoints, sometimes data occurs twice. 1286 */ 1287 DPRINTF("Data already received\n"); 1288 break; 1289 } 1290 1291 /* get the packet byte count */ 1292 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1293 1294 /* check for ISOCHRONOUS endpoint */ 1295 if (td->ep_type == UE_ISOCHRONOUS) { 1296 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 1297 GRXSTSRD_DPID_DATA0) { 1298 /* more data to be received */ 1299 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1300 } else { 1301 /* all data received */ 1302 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1303 /* verify the packet byte count */ 1304 if (count != td->remainder) { 1305 /* we have a short packet */ 1306 td->short_pkt = 1; 1307 td->got_short = 1; 1308 } 1309 } 1310 } else { 1311 /* verify the packet byte count */ 1312 if (count != td->max_packet_size) { 1313 if (count < td->max_packet_size) { 1314 /* we have a short packet */ 1315 td->short_pkt = 1; 1316 td->got_short = 1; 1317 } else { 1318 /* invalid USB packet */ 1319 td->error_any = 1; 1320 1321 /* release FIFO */ 1322 dwc_otg_common_rx_ack(sc); 1323 goto complete; 1324 } 1325 } 1326 td->toggle ^= 1; 1327 td->tt_scheduled = 0; 1328 } 1329 1330 /* verify the packet byte count */ 1331 if (count > td->remainder) { 1332 /* invalid USB packet */ 1333 td->error_any = 1; 1334 1335 /* release FIFO */ 1336 dwc_otg_common_rx_ack(sc); 1337 goto complete; 1338 } 1339 1340 /* read data from FIFO */ 1341 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1342 1343 td->remainder -= count; 1344 td->offset += count; 1345 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1346 break; 1347 default: 1348 break; 1349 } 1350 /* release FIFO */ 1351 dwc_otg_common_rx_ack(sc); 1352 busy: 1353 return (0); 1354 complete: 1355 return (1); 1356 } 1357 1358 static uint8_t 1359 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1360 { 1361 uint32_t hcint = 0; 1362 uint32_t hcchar; 1363 uint8_t delta; 1364 uint8_t channel; 1365 uint8_t x; 1366 1367 for (x = 0; x != td->max_packet_count; x++) { 1368 channel = td->channel[x]; 1369 if (channel >= DWC_OTG_MAX_CHANNELS) 1370 continue; 1371 hcint |= sc->sc_chan_state[channel].hcint; 1372 1373 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1374 channel, td->state, hcint, 1375 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1376 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1377 1378 /* check interrupt bits */ 1379 if (hcint & (HCINT_RETRY | 1380 HCINT_ACK | HCINT_NYET)) { 1381 /* give success bits priority over failure bits */ 1382 } else if (hcint & HCINT_STALL) { 1383 DPRINTF("CH=%d STALL\n", channel); 1384 td->error_stall = 1; 1385 td->error_any = 1; 1386 goto complete; 1387 } else if (hcint & HCINT_ERRORS) { 1388 DPRINTF("CH=%d ERROR\n", channel); 1389 td->errcnt++; 1390 if (td->hcsplt != 0 || td->errcnt >= 3) { 1391 if (td->ep_type != UE_ISOCHRONOUS) { 1392 td->error_any = 1; 1393 goto complete; 1394 } 1395 } 1396 } 1397 1398 /* check channels for data, if any */ 1399 if (dwc_otg_host_data_rx_sub(sc, td, channel)) 1400 goto complete; 1401 1402 /* refresh interrupt status */ 1403 hcint |= sc->sc_chan_state[channel].hcint; 1404 1405 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1406 HCINT_ACK | HCINT_NYET)) { 1407 if (!(hcint & HCINT_ERRORS)) 1408 td->errcnt = 0; 1409 } 1410 } 1411 1412 switch (td->state) { 1413 case DWC_CHAN_ST_START: 1414 if (td->hcsplt != 0) 1415 goto receive_spkt; 1416 else 1417 goto receive_pkt; 1418 1419 case DWC_CHAN_ST_WAIT_ANE: 1420 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1421 if (td->ep_type == UE_INTERRUPT) { 1422 /* 1423 * The USB specification does not 1424 * mandate a particular data toggle 1425 * value for USB INTERRUPT 1426 * transfers. Switch the data toggle 1427 * value to receive the packet 1428 * correctly: 1429 */ 1430 if (hcint & HCINT_DATATGLERR) { 1431 DPRINTF("Retrying packet due to " 1432 "data toggle error\n"); 1433 td->toggle ^= 1; 1434 goto receive_pkt; 1435 } 1436 } else if (td->ep_type == UE_ISOCHRONOUS) { 1437 goto complete; 1438 } 1439 td->did_nak = 1; 1440 td->tt_scheduled = 0; 1441 if (td->hcsplt != 0) 1442 goto receive_spkt; 1443 else 1444 goto receive_pkt; 1445 } else if (hcint & HCINT_NYET) { 1446 if (td->hcsplt != 0) { 1447 /* try again */ 1448 goto receive_pkt; 1449 } else { 1450 /* not a valid token for IN endpoints */ 1451 td->error_any = 1; 1452 goto complete; 1453 } 1454 } else if (hcint & HCINT_ACK) { 1455 /* wait for data - ACK arrived first */ 1456 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1457 goto busy; 1458 1459 if (td->ep_type == UE_ISOCHRONOUS) { 1460 /* check if we are complete */ 1461 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) { 1462 goto complete; 1463 } else { 1464 /* get more packets */ 1465 goto busy; 1466 } 1467 } else { 1468 /* check if we are complete */ 1469 if ((td->remainder == 0) || (td->got_short != 0)) { 1470 if (td->short_pkt) 1471 goto complete; 1472 1473 /* 1474 * Else need to receive a zero length 1475 * packet. 1476 */ 1477 } 1478 td->tt_scheduled = 0; 1479 td->did_nak = 0; 1480 if (td->hcsplt != 0) 1481 goto receive_spkt; 1482 else 1483 goto receive_pkt; 1484 } 1485 } 1486 break; 1487 1488 case DWC_CHAN_ST_WAIT_S_ANE: 1489 /* 1490 * NOTE: The DWC OTG hardware provides a fake ACK in 1491 * case of interrupt and isochronous transfers: 1492 */ 1493 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1494 td->did_nak = 1; 1495 td->tt_scheduled = 0; 1496 goto receive_spkt; 1497 } else if (hcint & HCINT_NYET) { 1498 td->tt_scheduled = 0; 1499 goto receive_spkt; 1500 } else if (hcint & HCINT_ACK) { 1501 td->did_nak = 0; 1502 goto receive_pkt; 1503 } 1504 break; 1505 1506 case DWC_CHAN_ST_WAIT_C_PKT: 1507 goto receive_pkt; 1508 1509 default: 1510 break; 1511 } 1512 goto busy; 1513 1514 receive_pkt: 1515 /* free existing channel, if any */ 1516 dwc_otg_host_channel_free(sc, td); 1517 1518 if (td->hcsplt != 0) { 1519 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1520 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1521 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1522 goto busy; 1523 } 1524 delta = sc->sc_last_frame_num - td->tt_start_slot; 1525 if (delta > DWC_OTG_TT_SLOT_MAX) { 1526 if (td->ep_type != UE_ISOCHRONOUS) { 1527 /* we missed the service interval */ 1528 td->error_any = 1; 1529 } 1530 goto complete; 1531 } 1532 /* complete split */ 1533 td->hcsplt |= HCSPLT_COMPSPLT; 1534 } else if (dwc_otg_host_rate_check(sc, td)) { 1535 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1536 goto busy; 1537 } 1538 1539 /* allocate a new channel */ 1540 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1541 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1542 goto busy; 1543 } 1544 1545 /* set toggle, if any */ 1546 if (td->set_toggle) { 1547 td->set_toggle = 0; 1548 td->toggle = 1; 1549 } 1550 1551 td->state = DWC_CHAN_ST_WAIT_ANE; 1552 1553 for (x = 0; x != td->max_packet_count; x++) { 1554 channel = td->channel[x]; 1555 1556 /* receive one packet */ 1557 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1558 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1559 (1 << HCTSIZ_PKTCNT_SHIFT) | 1560 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1561 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1562 1563 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1564 1565 hcchar = td->hcchar; 1566 hcchar |= HCCHAR_EPDIR_IN; 1567 1568 /* receive complete split ASAP */ 1569 if ((sc->sc_last_frame_num & 1) != 0 && 1570 td->ep_type == UE_ISOCHRONOUS) 1571 hcchar |= HCCHAR_ODDFRM; 1572 else 1573 hcchar &= ~HCCHAR_ODDFRM; 1574 1575 /* must enable channel before data can be received */ 1576 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1577 } 1578 /* wait until next slot before trying complete split */ 1579 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1580 1581 goto busy; 1582 1583 receive_spkt: 1584 /* free existing channel(s), if any */ 1585 dwc_otg_host_channel_free(sc, td); 1586 1587 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1588 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1589 td->state = DWC_CHAN_ST_START; 1590 goto busy; 1591 } 1592 delta = sc->sc_last_frame_num - td->tt_start_slot; 1593 if (delta > 5) { 1594 /* missed it */ 1595 td->tt_scheduled = 0; 1596 td->state = DWC_CHAN_ST_START; 1597 goto busy; 1598 } 1599 1600 /* allocate a new channel */ 1601 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1602 td->state = DWC_CHAN_ST_START; 1603 goto busy; 1604 } 1605 1606 channel = td->channel[0]; 1607 1608 td->hcsplt &= ~HCSPLT_COMPSPLT; 1609 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1610 1611 /* receive one packet */ 1612 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1613 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1614 1615 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1616 1617 /* send after next SOF event */ 1618 if ((sc->sc_last_frame_num & 1) == 0 && 1619 td->ep_type == UE_ISOCHRONOUS) 1620 td->hcchar |= HCCHAR_ODDFRM; 1621 else 1622 td->hcchar &= ~HCCHAR_ODDFRM; 1623 1624 hcchar = td->hcchar; 1625 hcchar |= HCCHAR_EPDIR_IN; 1626 1627 /* wait until next slot before trying complete split */ 1628 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1629 1630 /* must enable channel before data can be received */ 1631 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1632 busy: 1633 return (1); /* busy */ 1634 1635 complete: 1636 dwc_otg_host_channel_free(sc, td); 1637 return (0); /* complete */ 1638 } 1639 1640 static uint8_t 1641 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1642 { 1643 uint32_t temp; 1644 uint16_t count; 1645 uint8_t got_short; 1646 1647 got_short = 0; 1648 1649 /* check endpoint status */ 1650 if (sc->sc_last_rx_status == 0) 1651 goto not_complete; 1652 1653 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1654 goto not_complete; 1655 1656 /* check for SETUP packet */ 1657 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1658 GRXSTSRD_STP_DATA || 1659 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1660 GRXSTSRD_STP_COMPLETE) { 1661 if (td->remainder == 0) { 1662 /* 1663 * We are actually complete and have 1664 * received the next SETUP 1665 */ 1666 DPRINTFN(5, "faking complete\n"); 1667 return (0); /* complete */ 1668 } 1669 /* 1670 * USB Host Aborted the transfer. 1671 */ 1672 td->error_any = 1; 1673 return (0); /* complete */ 1674 } 1675 1676 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1677 GRXSTSRD_OUT_DATA) { 1678 /* release FIFO */ 1679 dwc_otg_common_rx_ack(sc); 1680 goto not_complete; 1681 } 1682 1683 /* get the packet byte count */ 1684 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1685 1686 /* verify the packet byte count */ 1687 if (count != td->max_packet_size) { 1688 if (count < td->max_packet_size) { 1689 /* we have a short packet */ 1690 td->short_pkt = 1; 1691 got_short = 1; 1692 } else { 1693 /* invalid USB packet */ 1694 td->error_any = 1; 1695 1696 /* release FIFO */ 1697 dwc_otg_common_rx_ack(sc); 1698 return (0); /* we are complete */ 1699 } 1700 } 1701 /* verify the packet byte count */ 1702 if (count > td->remainder) { 1703 /* invalid USB packet */ 1704 td->error_any = 1; 1705 1706 /* release FIFO */ 1707 dwc_otg_common_rx_ack(sc); 1708 return (0); /* we are complete */ 1709 } 1710 1711 /* read data from FIFO */ 1712 dwc_otg_read_fifo(sc, td->pc, td->offset, count); 1713 1714 td->remainder -= count; 1715 td->offset += count; 1716 1717 /* release FIFO */ 1718 dwc_otg_common_rx_ack(sc); 1719 1720 temp = sc->sc_out_ctl[td->ep_no]; 1721 1722 /* check for isochronous mode */ 1723 if ((temp & DIEPCTL_EPTYPE_MASK) == 1724 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1725 /* toggle odd or even frame bit */ 1726 if (temp & DIEPCTL_SETD1PID) { 1727 temp &= ~DIEPCTL_SETD1PID; 1728 temp |= DIEPCTL_SETD0PID; 1729 } else { 1730 temp &= ~DIEPCTL_SETD0PID; 1731 temp |= DIEPCTL_SETD1PID; 1732 } 1733 sc->sc_out_ctl[td->ep_no] = temp; 1734 } 1735 1736 /* check if we are complete */ 1737 if ((td->remainder == 0) || got_short) { 1738 if (td->short_pkt) { 1739 /* we are complete */ 1740 return (0); 1741 } 1742 /* else need to receive a zero length packet */ 1743 } 1744 1745 not_complete: 1746 1747 /* enable SETUP and transfer complete interrupt */ 1748 if (td->ep_no == 0) { 1749 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1750 DXEPTSIZ_SET_MULTI(3) | 1751 DXEPTSIZ_SET_NPKT(1) | 1752 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1753 } else { 1754 /* allow reception of multiple packets */ 1755 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1756 DXEPTSIZ_SET_MULTI(1) | 1757 DXEPTSIZ_SET_NPKT(4) | 1758 DXEPTSIZ_SET_NBYTES(4 * 1759 ((td->max_packet_size + 3) & ~3))); 1760 } 1761 temp = sc->sc_out_ctl[td->ep_no]; 1762 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp | 1763 DOEPCTL_EPENA | DOEPCTL_CNAK); 1764 1765 return (1); /* not complete */ 1766 } 1767 1768 static uint8_t 1769 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1770 { 1771 uint32_t count; 1772 uint32_t hcint; 1773 uint32_t hcchar; 1774 uint8_t delta; 1775 uint8_t channel; 1776 uint8_t x; 1777 1778 dwc_otg_host_dump_rx(sc, td); 1779 1780 /* check that last channel is complete */ 1781 channel = td->channel[td->npkt]; 1782 1783 if (channel < DWC_OTG_MAX_CHANNELS) { 1784 hcint = sc->sc_chan_state[channel].hcint; 1785 1786 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1787 channel, td->state, hcint, 1788 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1789 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1790 1791 if (hcint & (HCINT_RETRY | 1792 HCINT_ACK | HCINT_NYET)) { 1793 /* give success bits priority over failure bits */ 1794 } else if (hcint & HCINT_STALL) { 1795 DPRINTF("CH=%d STALL\n", channel); 1796 td->error_stall = 1; 1797 td->error_any = 1; 1798 goto complete; 1799 } else if (hcint & HCINT_ERRORS) { 1800 DPRINTF("CH=%d ERROR\n", channel); 1801 td->errcnt++; 1802 if (td->hcsplt != 0 || td->errcnt >= 3) { 1803 td->error_any = 1; 1804 goto complete; 1805 } 1806 } 1807 1808 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1809 HCINT_ACK | HCINT_NYET)) { 1810 1811 if (!(hcint & HCINT_ERRORS)) 1812 td->errcnt = 0; 1813 } 1814 } else { 1815 hcint = 0; 1816 } 1817 1818 switch (td->state) { 1819 case DWC_CHAN_ST_START: 1820 goto send_pkt; 1821 1822 case DWC_CHAN_ST_WAIT_ANE: 1823 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1824 td->did_nak = 1; 1825 td->tt_scheduled = 0; 1826 goto send_pkt; 1827 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1828 td->offset += td->tx_bytes; 1829 td->remainder -= td->tx_bytes; 1830 td->toggle ^= 1; 1831 /* check if next response will be a NAK */ 1832 if (hcint & HCINT_NYET) 1833 td->did_nak = 1; 1834 else 1835 td->did_nak = 0; 1836 td->tt_scheduled = 0; 1837 1838 /* check remainder */ 1839 if (td->remainder == 0) { 1840 if (td->short_pkt) 1841 goto complete; 1842 1843 /* 1844 * Else we need to transmit a short 1845 * packet: 1846 */ 1847 } 1848 goto send_pkt; 1849 } 1850 break; 1851 1852 case DWC_CHAN_ST_WAIT_S_ANE: 1853 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1854 td->did_nak = 1; 1855 td->tt_scheduled = 0; 1856 goto send_pkt; 1857 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1858 td->did_nak = 0; 1859 goto send_cpkt; 1860 } 1861 break; 1862 1863 case DWC_CHAN_ST_WAIT_C_ANE: 1864 if (hcint & HCINT_NYET) { 1865 goto send_cpkt; 1866 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1867 td->did_nak = 1; 1868 td->tt_scheduled = 0; 1869 goto send_pkt; 1870 } else if (hcint & HCINT_ACK) { 1871 td->offset += td->tx_bytes; 1872 td->remainder -= td->tx_bytes; 1873 td->toggle ^= 1; 1874 td->did_nak = 0; 1875 td->tt_scheduled = 0; 1876 1877 /* check remainder */ 1878 if (td->remainder == 0) { 1879 if (td->short_pkt) 1880 goto complete; 1881 1882 /* else we need to transmit a short packet */ 1883 } 1884 goto send_pkt; 1885 } 1886 break; 1887 1888 case DWC_CHAN_ST_WAIT_C_PKT: 1889 goto send_cpkt; 1890 1891 case DWC_CHAN_ST_TX_WAIT_ISOC: 1892 /* Check if ISOCHRONOUS OUT traffic is complete */ 1893 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1894 break; 1895 1896 td->offset += td->tx_bytes; 1897 td->remainder -= td->tx_bytes; 1898 goto complete; 1899 default: 1900 break; 1901 } 1902 goto busy; 1903 1904 send_pkt: 1905 /* free existing channel(s), if any */ 1906 dwc_otg_host_channel_free(sc, td); 1907 1908 if (td->hcsplt != 0) { 1909 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1910 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1911 td->state = DWC_CHAN_ST_START; 1912 goto busy; 1913 } 1914 delta = sc->sc_last_frame_num - td->tt_start_slot; 1915 if (delta > 5) { 1916 /* missed it */ 1917 td->tt_scheduled = 0; 1918 td->state = DWC_CHAN_ST_START; 1919 goto busy; 1920 } 1921 } else if (dwc_otg_host_rate_check(sc, td)) { 1922 td->state = DWC_CHAN_ST_START; 1923 goto busy; 1924 } 1925 1926 /* allocate a new channel */ 1927 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1928 td->state = DWC_CHAN_ST_START; 1929 goto busy; 1930 } 1931 1932 /* set toggle, if any */ 1933 if (td->set_toggle) { 1934 td->set_toggle = 0; 1935 td->toggle = 1; 1936 } 1937 1938 if (td->ep_type == UE_ISOCHRONOUS) { 1939 /* ISOCHRONOUS OUT transfers don't have any ACKs */ 1940 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1941 td->hcsplt &= ~HCSPLT_COMPSPLT; 1942 if (td->hcsplt != 0) { 1943 /* get maximum transfer length */ 1944 count = td->remainder; 1945 if (count > HCSPLT_XACTLEN_BURST) { 1946 DPRINTF("TT overflow\n"); 1947 td->error_any = 1; 1948 goto complete; 1949 } 1950 /* Update transaction position */ 1951 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1952 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1953 } 1954 } else if (td->hcsplt != 0) { 1955 td->hcsplt &= ~HCSPLT_COMPSPLT; 1956 /* Wait for ACK/NAK/ERR from TT */ 1957 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1958 } else { 1959 /* Wait for ACK/NAK/STALL from device */ 1960 td->state = DWC_CHAN_ST_WAIT_ANE; 1961 } 1962 1963 td->tx_bytes = 0; 1964 1965 for (x = 0; x != td->max_packet_count; x++) { 1966 uint32_t rem_bytes; 1967 1968 channel = td->channel[x]; 1969 1970 /* send one packet at a time */ 1971 count = td->max_packet_size; 1972 rem_bytes = td->remainder - td->tx_bytes; 1973 if (rem_bytes < count) { 1974 /* we have a short packet */ 1975 td->short_pkt = 1; 1976 count = rem_bytes; 1977 } 1978 if (count == rem_bytes) { 1979 /* last packet */ 1980 switch (x) { 1981 case 0: 1982 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1983 (count << HCTSIZ_XFERSIZE_SHIFT) | 1984 (1 << HCTSIZ_PKTCNT_SHIFT) | 1985 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1986 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1987 break; 1988 case 1: 1989 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1990 (count << HCTSIZ_XFERSIZE_SHIFT) | 1991 (1 << HCTSIZ_PKTCNT_SHIFT) | 1992 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1993 break; 1994 default: 1995 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1996 (count << HCTSIZ_XFERSIZE_SHIFT) | 1997 (1 << HCTSIZ_PKTCNT_SHIFT) | 1998 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1999 break; 2000 } 2001 } else if (td->ep_type == UE_ISOCHRONOUS && 2002 td->max_packet_count > 1) { 2003 /* ISOCHRONOUS multi packet */ 2004 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2005 (count << HCTSIZ_XFERSIZE_SHIFT) | 2006 (1 << HCTSIZ_PKTCNT_SHIFT) | 2007 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 2008 } else { 2009 /* TODO: HCTSIZ_DOPNG */ 2010 /* standard BULK/INTERRUPT/CONTROL packet */ 2011 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2012 (count << HCTSIZ_XFERSIZE_SHIFT) | 2013 (1 << HCTSIZ_PKTCNT_SHIFT) | 2014 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 2015 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 2016 } 2017 2018 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2019 2020 hcchar = td->hcchar; 2021 hcchar &= ~HCCHAR_EPDIR_IN; 2022 2023 /* send after next SOF event */ 2024 if ((sc->sc_last_frame_num & 1) == 0 && 2025 td->ep_type == UE_ISOCHRONOUS) 2026 hcchar |= HCCHAR_ODDFRM; 2027 else 2028 hcchar &= ~HCCHAR_ODDFRM; 2029 2030 /* must enable before writing data to FIFO */ 2031 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2032 2033 if (count != 0) { 2034 /* write data into FIFO */ 2035 dwc_otg_write_fifo(sc, td->pc, td->offset + 2036 td->tx_bytes, DOTG_DFIFO(channel), count); 2037 } 2038 2039 /* store number of bytes transmitted */ 2040 td->tx_bytes += count; 2041 2042 /* store last packet index */ 2043 td->npkt = x; 2044 2045 /* check for last packet */ 2046 if (count == rem_bytes) 2047 break; 2048 } 2049 goto busy; 2050 2051 send_cpkt: 2052 /* free existing channel, if any */ 2053 dwc_otg_host_channel_free(sc, td); 2054 2055 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 2056 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 2057 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2058 goto busy; 2059 } 2060 delta = sc->sc_last_frame_num - td->tt_start_slot; 2061 if (delta > DWC_OTG_TT_SLOT_MAX) { 2062 /* we missed the service interval */ 2063 if (td->ep_type != UE_ISOCHRONOUS) 2064 td->error_any = 1; 2065 goto complete; 2066 } 2067 2068 /* allocate a new channel */ 2069 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 2070 td->state = DWC_CHAN_ST_WAIT_C_PKT; 2071 goto busy; 2072 } 2073 2074 channel = td->channel[0]; 2075 2076 td->hcsplt |= HCSPLT_COMPSPLT; 2077 td->state = DWC_CHAN_ST_WAIT_C_ANE; 2078 2079 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 2080 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 2081 2082 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 2083 2084 hcchar = td->hcchar; 2085 hcchar &= ~HCCHAR_EPDIR_IN; 2086 2087 /* receive complete split ASAP */ 2088 if ((sc->sc_last_frame_num & 1) != 0 && 2089 td->ep_type == UE_ISOCHRONOUS) 2090 hcchar |= HCCHAR_ODDFRM; 2091 else 2092 hcchar &= ~HCCHAR_ODDFRM; 2093 2094 /* must enable channel before data can be received */ 2095 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 2096 2097 /* wait until next slot before trying complete split */ 2098 td->tt_complete_slot = sc->sc_last_frame_num + 1; 2099 busy: 2100 return (1); /* busy */ 2101 2102 complete: 2103 dwc_otg_host_channel_free(sc, td); 2104 return (0); /* complete */ 2105 } 2106 2107 static uint8_t 2108 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2109 { 2110 uint32_t max_buffer; 2111 uint32_t count; 2112 uint32_t fifo_left; 2113 uint32_t mpkt; 2114 uint32_t temp; 2115 uint8_t to; 2116 2117 to = 3; /* don't loop forever! */ 2118 2119 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 2120 2121 repeat: 2122 /* check for for endpoint 0 data */ 2123 2124 temp = sc->sc_last_rx_status; 2125 2126 if ((td->ep_no == 0) && (temp != 0) && 2127 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2128 2129 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2130 GRXSTSRD_STP_DATA && 2131 (temp & GRXSTSRD_PKTSTS_MASK) != 2132 GRXSTSRD_STP_COMPLETE) { 2133 2134 /* dump data - wrong direction */ 2135 dwc_otg_common_rx_ack(sc); 2136 } else { 2137 /* 2138 * The current transfer was cancelled 2139 * by the USB Host: 2140 */ 2141 td->error_any = 1; 2142 return (0); /* complete */ 2143 } 2144 } 2145 2146 /* fill in more TX data, if possible */ 2147 if (td->tx_bytes != 0) { 2148 2149 uint16_t cpkt; 2150 2151 /* check if packets have been transferred */ 2152 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2153 2154 /* get current packet number */ 2155 cpkt = DXEPTSIZ_GET_NPKT(temp); 2156 2157 if (cpkt >= td->npkt) { 2158 fifo_left = 0; 2159 } else { 2160 if (max_buffer != 0) { 2161 fifo_left = (td->npkt - cpkt) * 2162 td->max_packet_size; 2163 2164 if (fifo_left > max_buffer) 2165 fifo_left = max_buffer; 2166 } else { 2167 fifo_left = td->max_packet_size; 2168 } 2169 } 2170 2171 count = td->tx_bytes; 2172 if (count > fifo_left) 2173 count = fifo_left; 2174 2175 if (count != 0) { 2176 /* write data into FIFO */ 2177 dwc_otg_write_fifo(sc, td->pc, td->offset, 2178 DOTG_DFIFO(td->ep_no), count); 2179 2180 td->tx_bytes -= count; 2181 td->remainder -= count; 2182 td->offset += count; 2183 td->npkt = cpkt; 2184 } 2185 if (td->tx_bytes != 0) 2186 goto not_complete; 2187 2188 /* check remainder */ 2189 if (td->remainder == 0) { 2190 if (td->short_pkt) 2191 return (0); /* complete */ 2192 2193 /* else we need to transmit a short packet */ 2194 } 2195 } 2196 2197 if (!to--) 2198 goto not_complete; 2199 2200 /* check if not all packets have been transferred */ 2201 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2202 2203 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2204 2205 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2206 "DIEPCTL=0x%08x\n", td->ep_no, 2207 DXEPTSIZ_GET_NPKT(temp), 2208 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2209 2210 goto not_complete; 2211 } 2212 2213 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2214 2215 /* try to optimise by sending more data */ 2216 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2217 2218 /* send multiple packets at the same time */ 2219 mpkt = max_buffer / td->max_packet_size; 2220 2221 if (mpkt > 0x3FE) 2222 mpkt = 0x3FE; 2223 2224 count = td->remainder; 2225 if (count > 0x7FFFFF) 2226 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2227 2228 td->npkt = count / td->max_packet_size; 2229 2230 /* 2231 * NOTE: We could use 0x3FE instead of "mpkt" in the 2232 * check below to get more throughput, but then we 2233 * have a dependency towards non-generic chip features 2234 * to disable the TX-FIFO-EMPTY interrupts on a per 2235 * endpoint basis. Increase the maximum buffer size of 2236 * the IN endpoint to increase the performance. 2237 */ 2238 if (td->npkt > mpkt) { 2239 td->npkt = mpkt; 2240 count = td->max_packet_size * mpkt; 2241 } else if ((count == 0) || (count % td->max_packet_size)) { 2242 /* we are transmitting a short packet */ 2243 td->npkt++; 2244 td->short_pkt = 1; 2245 } 2246 } else { 2247 /* send one packet at a time */ 2248 mpkt = 1; 2249 count = td->max_packet_size; 2250 if (td->remainder < count) { 2251 /* we have a short packet */ 2252 td->short_pkt = 1; 2253 count = td->remainder; 2254 } 2255 td->npkt = 1; 2256 } 2257 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2258 DXEPTSIZ_SET_MULTI(1) | 2259 DXEPTSIZ_SET_NPKT(td->npkt) | 2260 DXEPTSIZ_SET_NBYTES(count)); 2261 2262 /* make room for buffering */ 2263 td->npkt += mpkt; 2264 2265 temp = sc->sc_in_ctl[td->ep_no]; 2266 2267 /* check for isochronous mode */ 2268 if ((temp & DIEPCTL_EPTYPE_MASK) == 2269 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2270 /* toggle odd or even frame bit */ 2271 if (temp & DIEPCTL_SETD1PID) { 2272 temp &= ~DIEPCTL_SETD1PID; 2273 temp |= DIEPCTL_SETD0PID; 2274 } else { 2275 temp &= ~DIEPCTL_SETD0PID; 2276 temp |= DIEPCTL_SETD1PID; 2277 } 2278 sc->sc_in_ctl[td->ep_no] = temp; 2279 } 2280 2281 /* must enable before writing data to FIFO */ 2282 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2283 DIEPCTL_EPENA | DIEPCTL_CNAK); 2284 2285 td->tx_bytes = count; 2286 2287 /* check remainder */ 2288 if (td->tx_bytes == 0 && 2289 td->remainder == 0) { 2290 if (td->short_pkt) 2291 return (0); /* complete */ 2292 2293 /* else we need to transmit a short packet */ 2294 } 2295 goto repeat; 2296 2297 not_complete: 2298 return (1); /* not complete */ 2299 } 2300 2301 static uint8_t 2302 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2303 { 2304 uint32_t temp; 2305 2306 /* 2307 * If all packets are transferred we are complete: 2308 */ 2309 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2310 2311 /* check that all packets have been transferred */ 2312 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2313 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2314 goto not_complete; 2315 } 2316 return (0); 2317 2318 not_complete: 2319 2320 /* we only want to know if there is a SETUP packet or free IN packet */ 2321 2322 temp = sc->sc_last_rx_status; 2323 2324 if ((td->ep_no == 0) && (temp != 0) && 2325 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2326 2327 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2328 GRXSTSRD_STP_DATA || 2329 (temp & GRXSTSRD_PKTSTS_MASK) == 2330 GRXSTSRD_STP_COMPLETE) { 2331 DPRINTFN(5, "faking complete\n"); 2332 /* 2333 * Race condition: We are complete! 2334 */ 2335 return (0); 2336 } else { 2337 /* dump data - wrong direction */ 2338 dwc_otg_common_rx_ack(sc); 2339 } 2340 } 2341 return (1); /* not complete */ 2342 } 2343 2344 static void 2345 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2346 { 2347 struct dwc_otg_td *td; 2348 uint8_t toggle; 2349 uint8_t tmr_val; 2350 uint8_t tmr_res; 2351 2352 DPRINTFN(9, "\n"); 2353 2354 td = xfer->td_transfer_cache; 2355 if (td == NULL) 2356 return; 2357 2358 while (1) { 2359 if ((td->func) (sc, td)) { 2360 /* operation in progress */ 2361 break; 2362 } 2363 if (((void *)td) == xfer->td_transfer_last) { 2364 goto done; 2365 } 2366 if (td->error_any) { 2367 goto done; 2368 } else if (td->remainder > 0) { 2369 /* 2370 * We had a short transfer. If there is no alternate 2371 * next, stop processing ! 2372 */ 2373 if (!td->alt_next) 2374 goto done; 2375 } 2376 2377 /* 2378 * Fetch the next transfer descriptor and transfer 2379 * some flags to the next transfer descriptor 2380 */ 2381 tmr_res = td->tmr_res; 2382 tmr_val = td->tmr_val; 2383 toggle = td->toggle; 2384 td = td->obj_next; 2385 xfer->td_transfer_cache = td; 2386 td->toggle = toggle; /* transfer toggle */ 2387 td->tmr_res = tmr_res; 2388 td->tmr_val = tmr_val; 2389 } 2390 return; 2391 2392 done: 2393 xfer->td_transfer_cache = NULL; 2394 sc->sc_xfer_complete = 1; 2395 } 2396 2397 static uint8_t 2398 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2399 { 2400 struct dwc_otg_td *td; 2401 2402 DPRINTFN(9, "\n"); 2403 2404 td = xfer->td_transfer_cache; 2405 if (td == NULL) { 2406 /* compute all actual lengths */ 2407 dwc_otg_standard_done(xfer); 2408 return (1); 2409 } 2410 return (0); 2411 } 2412 2413 static void 2414 dwc_otg_timer(void *_sc) 2415 { 2416 struct dwc_otg_softc *sc = _sc; 2417 2418 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2419 2420 DPRINTF("\n"); 2421 2422 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2423 2424 /* increment timer value */ 2425 sc->sc_tmr_val++; 2426 2427 /* enable SOF interrupt, which will poll jobs */ 2428 dwc_otg_enable_sof_irq(sc); 2429 2430 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2431 2432 if (sc->sc_timer_active) { 2433 /* restart timer */ 2434 usb_callout_reset(&sc->sc_timer, 2435 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2436 &dwc_otg_timer, sc); 2437 } 2438 } 2439 2440 static void 2441 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2442 { 2443 if (sc->sc_timer_active != 0) 2444 return; 2445 2446 sc->sc_timer_active = 1; 2447 2448 /* restart timer */ 2449 usb_callout_reset(&sc->sc_timer, 2450 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2451 &dwc_otg_timer, sc); 2452 } 2453 2454 static void 2455 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2456 { 2457 if (sc->sc_timer_active == 0) 2458 return; 2459 2460 sc->sc_timer_active = 0; 2461 2462 /* stop timer */ 2463 usb_callout_stop(&sc->sc_timer); 2464 } 2465 2466 static uint16_t 2467 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2468 { 2469 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2470 pinfo->slot_index++; 2471 return (pinfo->slot_index); 2472 } 2473 2474 static uint8_t 2475 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2476 { 2477 TAILQ_HEAD(, usb_xfer) head; 2478 struct usb_xfer *xfer; 2479 struct usb_xfer *xfer_next; 2480 struct dwc_otg_td *td; 2481 uint16_t temp; 2482 uint16_t slot; 2483 2484 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2485 2486 if (sc->sc_last_frame_num == temp) 2487 return (0); 2488 2489 sc->sc_last_frame_num = temp; 2490 2491 TAILQ_INIT(&head); 2492 2493 if ((temp & 7) == 0) { 2494 2495 /* reset the schedule */ 2496 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2497 2498 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2499 td = xfer->td_transfer_cache; 2500 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2501 continue; 2502 2503 /* check for IN direction */ 2504 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2505 continue; 2506 2507 sc->sc_needsof = 1; 2508 2509 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2510 continue; 2511 2512 /* compute slot */ 2513 slot = dwc_otg_compute_isoc_rx_tt_slot( 2514 sc->sc_tt_info + td->tt_index); 2515 if (slot > 3) { 2516 /* 2517 * Not enough time to get complete 2518 * split executed. 2519 */ 2520 continue; 2521 } 2522 /* Delayed start */ 2523 td->tt_start_slot = temp + slot; 2524 td->tt_scheduled = 1; 2525 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2526 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2527 } 2528 2529 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2530 td = xfer->td_transfer_cache; 2531 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2532 continue; 2533 2534 /* check for OUT direction */ 2535 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2536 continue; 2537 2538 sc->sc_needsof = 1; 2539 2540 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2541 continue; 2542 2543 /* Start ASAP */ 2544 td->tt_start_slot = temp; 2545 td->tt_scheduled = 1; 2546 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2547 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2548 } 2549 2550 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2551 td = xfer->td_transfer_cache; 2552 if (td == NULL || td->ep_type != UE_INTERRUPT) 2553 continue; 2554 2555 if (td->tt_scheduled != 0) { 2556 sc->sc_needsof = 1; 2557 continue; 2558 } 2559 2560 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2561 continue; 2562 2563 if (td->hcsplt == 0) { 2564 sc->sc_needsof = 1; 2565 td->tt_scheduled = 1; 2566 continue; 2567 } 2568 2569 /* start ASAP */ 2570 td->tt_start_slot = temp; 2571 sc->sc_needsof = 1; 2572 td->tt_scheduled = 1; 2573 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2574 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2575 } 2576 2577 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2578 td = xfer->td_transfer_cache; 2579 if (td == NULL || 2580 td->ep_type != UE_CONTROL) { 2581 continue; 2582 } 2583 2584 sc->sc_needsof = 1; 2585 2586 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2587 continue; 2588 2589 /* start ASAP */ 2590 td->tt_start_slot = temp; 2591 td->tt_scheduled = 1; 2592 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2593 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2594 } 2595 } 2596 if ((temp & 7) < 6) { 2597 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2598 td = xfer->td_transfer_cache; 2599 if (td == NULL || 2600 td->ep_type != UE_BULK) { 2601 continue; 2602 } 2603 2604 sc->sc_needsof = 1; 2605 2606 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2607 continue; 2608 2609 /* start ASAP */ 2610 td->tt_start_slot = temp; 2611 td->tt_scheduled = 1; 2612 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2613 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2614 } 2615 } 2616 2617 /* Put TT transfers in execution order at the end */ 2618 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2619 2620 /* move all TT transfers in front, keeping the current order */ 2621 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2622 td = xfer->td_transfer_cache; 2623 if (td == NULL || td->hcsplt == 0) 2624 continue; 2625 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2626 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2627 } 2628 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2629 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2630 2631 /* put non-TT non-ISOCHRONOUS transfers last */ 2632 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2633 td = xfer->td_transfer_cache; 2634 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS) 2635 continue; 2636 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2637 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2638 } 2639 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2640 2641 if ((temp & 7) == 0) { 2642 2643 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2644 (int)temp, (int)sc->sc_needsof); 2645 2646 /* update SOF IRQ mask */ 2647 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2648 if (sc->sc_needsof == 0) { 2649 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2650 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2651 } 2652 } else { 2653 if (sc->sc_needsof != 0) { 2654 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2655 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2656 } 2657 } 2658 2659 /* clear need SOF flag */ 2660 sc->sc_needsof = 0; 2661 } 2662 return (1); 2663 } 2664 2665 static void 2666 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2667 { 2668 struct usb_xfer *xfer; 2669 uint32_t count; 2670 uint32_t temp; 2671 uint32_t haint; 2672 uint8_t got_rx_status; 2673 uint8_t x; 2674 2675 if (sc->sc_flags.status_device_mode == 0) { 2676 /* 2677 * Update host transfer schedule, so that new 2678 * transfers can be issued: 2679 */ 2680 dwc_otg_update_host_transfer_schedule_locked(sc); 2681 } 2682 count = 0; 2683 repeat: 2684 if (++count == 16) { 2685 /* give other interrupts a chance */ 2686 DPRINTF("Yield\n"); 2687 return; 2688 } 2689 2690 /* get all host channel interrupts */ 2691 haint = DWC_OTG_READ_4(sc, DOTG_HAINT); 2692 while (1) { 2693 x = ffs(haint) - 1; 2694 if (x >= sc->sc_host_ch_max) 2695 break; 2696 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2697 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2698 temp &= ~HCINT_SOFTWARE_ONLY; 2699 sc->sc_chan_state[x].hcint |= temp; 2700 haint &= ~(1U << x); 2701 } 2702 2703 if (sc->sc_last_rx_status == 0) { 2704 2705 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2706 if (temp & GINTSTS_RXFLVL) { 2707 /* pop current status */ 2708 sc->sc_last_rx_status = 2709 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2710 } 2711 2712 if (sc->sc_last_rx_status != 0) { 2713 2714 uint8_t ep_no; 2715 2716 temp = sc->sc_last_rx_status & 2717 GRXSTSRD_PKTSTS_MASK; 2718 2719 /* non-data messages we simply skip */ 2720 if (temp != GRXSTSRD_STP_DATA && 2721 temp != GRXSTSRD_STP_COMPLETE && 2722 temp != GRXSTSRD_OUT_DATA) { 2723 /* check for halted channel */ 2724 if (temp == GRXSTSRH_HALTED) { 2725 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status); 2726 sc->sc_chan_state[ep_no].wait_halted = 0; 2727 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no); 2728 } 2729 /* store bytes and FIFO offset */ 2730 sc->sc_current_rx_bytes = 0; 2731 sc->sc_current_rx_fifo = 0; 2732 2733 /* acknowledge status */ 2734 dwc_otg_common_rx_ack(sc); 2735 goto repeat; 2736 } 2737 2738 temp = GRXSTSRD_BCNT_GET( 2739 sc->sc_last_rx_status); 2740 ep_no = GRXSTSRD_CHNUM_GET( 2741 sc->sc_last_rx_status); 2742 2743 /* store bytes and FIFO offset */ 2744 sc->sc_current_rx_bytes = (temp + 3) & ~3; 2745 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no); 2746 2747 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2748 2749 /* check if we should dump the data */ 2750 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2751 dwc_otg_common_rx_ack(sc); 2752 goto repeat; 2753 } 2754 2755 got_rx_status = 1; 2756 2757 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2758 sc->sc_last_rx_status, ep_no, 2759 (sc->sc_last_rx_status >> 15) & 3, 2760 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2761 (sc->sc_last_rx_status >> 17) & 15); 2762 } else { 2763 got_rx_status = 0; 2764 } 2765 } else { 2766 uint8_t ep_no; 2767 2768 ep_no = GRXSTSRD_CHNUM_GET( 2769 sc->sc_last_rx_status); 2770 2771 /* check if we should dump the data */ 2772 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2773 dwc_otg_common_rx_ack(sc); 2774 goto repeat; 2775 } 2776 2777 got_rx_status = 1; 2778 } 2779 2780 /* execute FIFOs */ 2781 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2782 dwc_otg_xfer_do_fifo(sc, xfer); 2783 2784 if (got_rx_status) { 2785 /* check if data was consumed */ 2786 if (sc->sc_last_rx_status == 0) 2787 goto repeat; 2788 2789 /* disable RX FIFO level interrupt */ 2790 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2791 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2792 } 2793 } 2794 2795 static void 2796 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2797 { 2798 struct usb_xfer *xfer; 2799 repeat: 2800 /* scan for completion events */ 2801 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2802 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2803 goto repeat; 2804 } 2805 } 2806 2807 static void 2808 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2809 { 2810 DPRINTFN(5, "vbus = %u\n", is_on); 2811 2812 /* 2813 * If the USB host mode is forced, then assume VBUS is always 2814 * present else rely on the input to this function: 2815 */ 2816 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2817 2818 if (!sc->sc_flags.status_vbus) { 2819 sc->sc_flags.status_vbus = 1; 2820 2821 /* complete root HUB interrupt endpoint */ 2822 2823 dwc_otg_root_intr(sc); 2824 } 2825 } else { 2826 if (sc->sc_flags.status_vbus) { 2827 sc->sc_flags.status_vbus = 0; 2828 sc->sc_flags.status_bus_reset = 0; 2829 sc->sc_flags.status_suspend = 0; 2830 sc->sc_flags.change_suspend = 0; 2831 sc->sc_flags.change_connect = 1; 2832 2833 /* complete root HUB interrupt endpoint */ 2834 2835 dwc_otg_root_intr(sc); 2836 } 2837 } 2838 } 2839 2840 int 2841 dwc_otg_filter_interrupt(void *arg) 2842 { 2843 struct dwc_otg_softc *sc = arg; 2844 int retval = FILTER_HANDLED; 2845 uint32_t status; 2846 2847 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2848 2849 /* read and clear interrupt status */ 2850 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2851 2852 /* clear interrupts we are handling here */ 2853 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2854 2855 /* check for USB state change interrupts */ 2856 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2857 retval = FILTER_SCHEDULE_THREAD; 2858 2859 /* clear FIFO empty interrupts */ 2860 if (status & sc->sc_irq_mask & 2861 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) { 2862 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); 2863 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2864 } 2865 /* clear all IN endpoint interrupts */ 2866 if (status & GINTSTS_IEPINT) { 2867 uint32_t temp; 2868 uint8_t x; 2869 2870 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2871 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2872 /* 2873 * NOTE: Need to clear all interrupt bits, 2874 * because some appears to be unmaskable and 2875 * can cause an interrupt loop: 2876 */ 2877 if (temp != 0) 2878 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp); 2879 } 2880 } 2881 2882 /* poll FIFOs, if any */ 2883 dwc_otg_interrupt_poll_locked(sc); 2884 2885 if (sc->sc_xfer_complete != 0) 2886 retval = FILTER_SCHEDULE_THREAD; 2887 2888 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2889 2890 return (retval); 2891 } 2892 2893 void 2894 dwc_otg_interrupt(void *arg) 2895 { 2896 struct dwc_otg_softc *sc = arg; 2897 uint32_t status; 2898 2899 USB_BUS_LOCK(&sc->sc_bus); 2900 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2901 2902 /* read and clear interrupt status */ 2903 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2904 2905 /* clear interrupts we are handling here */ 2906 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2907 2908 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2909 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2910 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2911 2912 if (status & GINTSTS_USBRST) { 2913 2914 /* set correct state */ 2915 sc->sc_flags.status_device_mode = 1; 2916 sc->sc_flags.status_bus_reset = 0; 2917 sc->sc_flags.status_suspend = 0; 2918 sc->sc_flags.change_suspend = 0; 2919 sc->sc_flags.change_connect = 1; 2920 2921 /* Disable SOF interrupt */ 2922 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2923 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2924 2925 /* complete root HUB interrupt endpoint */ 2926 dwc_otg_root_intr(sc); 2927 } 2928 2929 /* check for any bus state change interrupts */ 2930 if (status & GINTSTS_ENUMDONE) { 2931 2932 uint32_t temp; 2933 2934 DPRINTFN(5, "end of reset\n"); 2935 2936 /* set correct state */ 2937 sc->sc_flags.status_device_mode = 1; 2938 sc->sc_flags.status_bus_reset = 1; 2939 sc->sc_flags.status_suspend = 0; 2940 sc->sc_flags.change_suspend = 0; 2941 sc->sc_flags.change_connect = 1; 2942 sc->sc_flags.status_low_speed = 0; 2943 sc->sc_flags.port_enabled = 1; 2944 2945 /* reset FIFOs */ 2946 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2947 2948 /* reset function address */ 2949 dwc_otg_set_address(sc, 0); 2950 2951 /* figure out enumeration speed */ 2952 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2953 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2954 sc->sc_flags.status_high_speed = 1; 2955 else 2956 sc->sc_flags.status_high_speed = 0; 2957 2958 /* 2959 * Disable resume and SOF interrupt, and enable 2960 * suspend and RX frame interrupt: 2961 */ 2962 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2963 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2964 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2965 2966 /* complete root HUB interrupt endpoint */ 2967 dwc_otg_root_intr(sc); 2968 } 2969 2970 if (status & GINTSTS_PRTINT) { 2971 uint32_t hprt; 2972 2973 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2974 2975 /* clear change bits */ 2976 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2977 HPRT_PRTPWR | HPRT_PRTENCHNG | 2978 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2979 sc->sc_hprt_val); 2980 2981 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2982 2983 sc->sc_flags.status_device_mode = 0; 2984 2985 if (hprt & HPRT_PRTCONNSTS) 2986 sc->sc_flags.status_bus_reset = 1; 2987 else 2988 sc->sc_flags.status_bus_reset = 0; 2989 2990 if ((hprt & HPRT_PRTENCHNG) && 2991 (hprt & HPRT_PRTENA) == 0) 2992 sc->sc_flags.change_enabled = 1; 2993 2994 if (hprt & HPRT_PRTENA) 2995 sc->sc_flags.port_enabled = 1; 2996 else 2997 sc->sc_flags.port_enabled = 0; 2998 2999 if (hprt & HPRT_PRTOVRCURRCHNG) 3000 sc->sc_flags.change_over_current = 1; 3001 3002 if (hprt & HPRT_PRTOVRCURRACT) 3003 sc->sc_flags.port_over_current = 1; 3004 else 3005 sc->sc_flags.port_over_current = 0; 3006 3007 if (hprt & HPRT_PRTPWR) 3008 sc->sc_flags.port_powered = 1; 3009 else 3010 sc->sc_flags.port_powered = 0; 3011 3012 if (((hprt & HPRT_PRTSPD_MASK) 3013 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 3014 sc->sc_flags.status_low_speed = 1; 3015 else 3016 sc->sc_flags.status_low_speed = 0; 3017 3018 if (((hprt & HPRT_PRTSPD_MASK) 3019 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 3020 sc->sc_flags.status_high_speed = 1; 3021 else 3022 sc->sc_flags.status_high_speed = 0; 3023 3024 if (hprt & HPRT_PRTCONNDET) 3025 sc->sc_flags.change_connect = 1; 3026 3027 if (hprt & HPRT_PRTSUSP) 3028 dwc_otg_suspend_irq(sc); 3029 else 3030 dwc_otg_resume_irq(sc); 3031 3032 /* complete root HUB interrupt endpoint */ 3033 dwc_otg_root_intr(sc); 3034 3035 /* update host frame interval */ 3036 dwc_otg_update_host_frame_interval(sc); 3037 } 3038 3039 /* 3040 * If resume and suspend is set at the same time we interpret 3041 * that like RESUME. Resume is set when there is at least 3 3042 * milliseconds of inactivity on the USB BUS. 3043 */ 3044 if (status & GINTSTS_WKUPINT) { 3045 3046 DPRINTFN(5, "resume interrupt\n"); 3047 3048 dwc_otg_resume_irq(sc); 3049 3050 } else if (status & GINTSTS_USBSUSP) { 3051 3052 DPRINTFN(5, "suspend interrupt\n"); 3053 3054 dwc_otg_suspend_irq(sc); 3055 } 3056 /* check VBUS */ 3057 if (status & (GINTSTS_USBSUSP | 3058 GINTSTS_USBRST | 3059 GINTMSK_OTGINTMSK | 3060 GINTSTS_SESSREQINT)) { 3061 uint32_t temp; 3062 3063 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3064 3065 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 3066 3067 dwc_otg_vbus_interrupt(sc, 3068 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3069 } 3070 3071 if (sc->sc_xfer_complete != 0) { 3072 sc->sc_xfer_complete = 0; 3073 3074 /* complete FIFOs, if any */ 3075 dwc_otg_interrupt_complete_locked(sc); 3076 } 3077 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3078 USB_BUS_UNLOCK(&sc->sc_bus); 3079 } 3080 3081 static void 3082 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 3083 { 3084 struct dwc_otg_td *td; 3085 3086 /* get current Transfer Descriptor */ 3087 td = temp->td_next; 3088 temp->td = td; 3089 3090 /* prepare for next TD */ 3091 temp->td_next = td->obj_next; 3092 3093 /* fill out the Transfer Descriptor */ 3094 td->func = temp->func; 3095 td->pc = temp->pc; 3096 td->offset = temp->offset; 3097 td->remainder = temp->len; 3098 td->tx_bytes = 0; 3099 td->error_any = 0; 3100 td->error_stall = 0; 3101 td->npkt = 0; 3102 td->did_stall = temp->did_stall; 3103 td->short_pkt = temp->short_pkt; 3104 td->alt_next = temp->setup_alt_next; 3105 td->set_toggle = 0; 3106 td->got_short = 0; 3107 td->did_nak = 0; 3108 td->channel[0] = DWC_OTG_MAX_CHANNELS; 3109 td->channel[1] = DWC_OTG_MAX_CHANNELS; 3110 td->channel[2] = DWC_OTG_MAX_CHANNELS; 3111 td->state = 0; 3112 td->errcnt = 0; 3113 td->tt_scheduled = 0; 3114 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3115 } 3116 3117 static void 3118 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3119 { 3120 struct dwc_otg_std_temp temp; 3121 struct dwc_otg_td *td; 3122 uint32_t x; 3123 uint8_t need_sync; 3124 uint8_t is_host; 3125 3126 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3127 xfer->address, UE_GET_ADDR(xfer->endpointno), 3128 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3129 3130 temp.max_frame_size = xfer->max_frame_size; 3131 3132 td = xfer->td_start[0]; 3133 xfer->td_transfer_first = td; 3134 xfer->td_transfer_cache = td; 3135 3136 /* setup temp */ 3137 3138 temp.pc = NULL; 3139 temp.td = NULL; 3140 temp.td_next = xfer->td_start[0]; 3141 temp.offset = 0; 3142 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3143 xfer->flags_int.isochronous_xfr; 3144 temp.did_stall = !xfer->flags_int.control_stall; 3145 3146 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3147 3148 /* check if we should prepend a setup message */ 3149 3150 if (xfer->flags_int.control_xfr) { 3151 if (xfer->flags_int.control_hdr) { 3152 3153 if (is_host) 3154 temp.func = &dwc_otg_host_setup_tx; 3155 else 3156 temp.func = &dwc_otg_setup_rx; 3157 3158 temp.len = xfer->frlengths[0]; 3159 temp.pc = xfer->frbuffers + 0; 3160 temp.short_pkt = temp.len ? 1 : 0; 3161 3162 /* check for last frame */ 3163 if (xfer->nframes == 1) { 3164 /* no STATUS stage yet, SETUP is last */ 3165 if (xfer->flags_int.control_act) 3166 temp.setup_alt_next = 0; 3167 } 3168 3169 dwc_otg_setup_standard_chain_sub(&temp); 3170 } 3171 x = 1; 3172 } else { 3173 x = 0; 3174 } 3175 3176 if (x != xfer->nframes) { 3177 if (xfer->endpointno & UE_DIR_IN) { 3178 if (is_host) { 3179 temp.func = &dwc_otg_host_data_rx; 3180 need_sync = 0; 3181 } else { 3182 temp.func = &dwc_otg_data_tx; 3183 need_sync = 1; 3184 } 3185 } else { 3186 if (is_host) { 3187 temp.func = &dwc_otg_host_data_tx; 3188 need_sync = 0; 3189 } else { 3190 temp.func = &dwc_otg_data_rx; 3191 need_sync = 0; 3192 } 3193 } 3194 3195 /* setup "pc" pointer */ 3196 temp.pc = xfer->frbuffers + x; 3197 } else { 3198 need_sync = 0; 3199 } 3200 while (x != xfer->nframes) { 3201 3202 /* DATA0 / DATA1 message */ 3203 3204 temp.len = xfer->frlengths[x]; 3205 3206 x++; 3207 3208 if (x == xfer->nframes) { 3209 if (xfer->flags_int.control_xfr) { 3210 if (xfer->flags_int.control_act) { 3211 temp.setup_alt_next = 0; 3212 } 3213 } else { 3214 temp.setup_alt_next = 0; 3215 } 3216 } 3217 if (temp.len == 0) { 3218 3219 /* make sure that we send an USB packet */ 3220 3221 temp.short_pkt = 0; 3222 3223 } else { 3224 3225 /* regular data transfer */ 3226 3227 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3228 } 3229 3230 dwc_otg_setup_standard_chain_sub(&temp); 3231 3232 if (xfer->flags_int.isochronous_xfr) { 3233 temp.offset += temp.len; 3234 } else { 3235 /* get next Page Cache pointer */ 3236 temp.pc = xfer->frbuffers + x; 3237 } 3238 } 3239 3240 if (xfer->flags_int.control_xfr) { 3241 3242 /* always setup a valid "pc" pointer for status and sync */ 3243 temp.pc = xfer->frbuffers + 0; 3244 temp.len = 0; 3245 temp.short_pkt = 0; 3246 temp.setup_alt_next = 0; 3247 3248 /* check if we need to sync */ 3249 if (need_sync) { 3250 /* we need a SYNC point after TX */ 3251 temp.func = &dwc_otg_data_tx_sync; 3252 dwc_otg_setup_standard_chain_sub(&temp); 3253 } 3254 3255 /* check if we should append a status stage */ 3256 if (!xfer->flags_int.control_act) { 3257 3258 /* 3259 * Send a DATA1 message and invert the current 3260 * endpoint direction. 3261 */ 3262 if (xfer->endpointno & UE_DIR_IN) { 3263 if (is_host) { 3264 temp.func = &dwc_otg_host_data_tx; 3265 need_sync = 0; 3266 } else { 3267 temp.func = &dwc_otg_data_rx; 3268 need_sync = 0; 3269 } 3270 } else { 3271 if (is_host) { 3272 temp.func = &dwc_otg_host_data_rx; 3273 need_sync = 0; 3274 } else { 3275 temp.func = &dwc_otg_data_tx; 3276 need_sync = 1; 3277 } 3278 } 3279 3280 dwc_otg_setup_standard_chain_sub(&temp); 3281 3282 /* data toggle should be DATA1 */ 3283 td = temp.td; 3284 td->set_toggle = 1; 3285 3286 if (need_sync) { 3287 /* we need a SYNC point after TX */ 3288 temp.func = &dwc_otg_data_tx_sync; 3289 dwc_otg_setup_standard_chain_sub(&temp); 3290 } 3291 } 3292 } else { 3293 /* check if we need to sync */ 3294 if (need_sync) { 3295 3296 temp.pc = xfer->frbuffers + 0; 3297 temp.len = 0; 3298 temp.short_pkt = 0; 3299 temp.setup_alt_next = 0; 3300 3301 /* we need a SYNC point after TX */ 3302 temp.func = &dwc_otg_data_tx_sync; 3303 dwc_otg_setup_standard_chain_sub(&temp); 3304 } 3305 } 3306 3307 /* must have at least one frame! */ 3308 td = temp.td; 3309 xfer->td_transfer_last = td; 3310 3311 if (is_host) { 3312 3313 struct dwc_otg_softc *sc; 3314 uint32_t hcchar; 3315 uint32_t hcsplt; 3316 3317 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3318 3319 /* get first again */ 3320 td = xfer->td_transfer_first; 3321 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3322 3323 hcchar = 3324 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3325 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3326 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3327 HCCHAR_CHENA; 3328 3329 /* 3330 * We are not always able to meet the timing 3331 * requirements of the USB interrupt endpoint's 3332 * complete split token, when doing transfers going 3333 * via a transaction translator. Use the CONTROL 3334 * transfer type instead of the INTERRUPT transfer 3335 * type in general, as a means to workaround 3336 * that. This trick should work for both FULL and LOW 3337 * speed USB traffic going through a TT. For non-TT 3338 * traffic it works as well. The reason for using 3339 * CONTROL type instead of BULK is that some TTs might 3340 * reject LOW speed BULK traffic. 3341 */ 3342 if (td->ep_type == UE_INTERRUPT) 3343 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3344 else 3345 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3346 3347 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3348 hcchar |= HCCHAR_EPDIR_IN; 3349 3350 switch (xfer->xroot->udev->speed) { 3351 case USB_SPEED_LOW: 3352 hcchar |= HCCHAR_LSPDDEV; 3353 /* FALLTHROUGH */ 3354 case USB_SPEED_FULL: 3355 /* check if root HUB port is running High Speed */ 3356 if (dwc_otg_uses_split(xfer->xroot->udev)) { 3357 hcsplt = HCSPLT_SPLTENA | 3358 (xfer->xroot->udev->hs_port_no << 3359 HCSPLT_PRTADDR_SHIFT) | 3360 (xfer->xroot->udev->hs_hub_addr << 3361 HCSPLT_HUBADDR_SHIFT); 3362 } else { 3363 hcsplt = 0; 3364 } 3365 if (td->ep_type == UE_INTERRUPT) { 3366 uint32_t ival; 3367 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3368 if (ival == 0) 3369 ival = 1; 3370 else if (ival > 127) 3371 ival = 127; 3372 td->tmr_val = sc->sc_tmr_val + ival; 3373 td->tmr_res = ival; 3374 } else if (td->ep_type == UE_ISOCHRONOUS) { 3375 td->tmr_res = 1; 3376 td->tmr_val = sc->sc_last_frame_num; 3377 if (td->hcchar & HCCHAR_EPDIR_IN) 3378 td->tmr_val++; 3379 } else { 3380 td->tmr_val = 0; 3381 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3382 } 3383 break; 3384 case USB_SPEED_HIGH: 3385 hcsplt = 0; 3386 if (td->ep_type == UE_INTERRUPT) { 3387 uint32_t ival; 3388 hcchar |= ((xfer->max_packet_count & 3) 3389 << HCCHAR_MC_SHIFT); 3390 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3391 if (ival == 0) 3392 ival = 1; 3393 else if (ival > 127) 3394 ival = 127; 3395 td->tmr_val = sc->sc_tmr_val + ival; 3396 td->tmr_res = ival; 3397 } else if (td->ep_type == UE_ISOCHRONOUS) { 3398 hcchar |= ((xfer->max_packet_count & 3) 3399 << HCCHAR_MC_SHIFT); 3400 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3401 td->tmr_val = sc->sc_last_frame_num; 3402 if (td->hcchar & HCCHAR_EPDIR_IN) 3403 td->tmr_val += td->tmr_res; 3404 3405 } else { 3406 td->tmr_val = 0; 3407 td->tmr_res = (uint8_t)sc->sc_last_frame_num; 3408 } 3409 break; 3410 default: 3411 hcsplt = 0; 3412 td->tmr_val = 0; 3413 td->tmr_res = 0; 3414 break; 3415 } 3416 3417 /* store configuration in all TD's */ 3418 while (1) { 3419 td->hcchar = hcchar; 3420 td->hcsplt = hcsplt; 3421 3422 if (((void *)td) == xfer->td_transfer_last) 3423 break; 3424 3425 td = td->obj_next; 3426 } 3427 } 3428 } 3429 3430 static void 3431 dwc_otg_timeout(void *arg) 3432 { 3433 struct usb_xfer *xfer = arg; 3434 3435 DPRINTF("xfer=%p\n", xfer); 3436 3437 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3438 3439 /* transfer is transferred */ 3440 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3441 } 3442 3443 static void 3444 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3445 { 3446 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3447 3448 DPRINTFN(9, "\n"); 3449 3450 /* 3451 * Poll one time in device mode, which will turn on the 3452 * endpoint interrupts. Else wait for SOF interrupt in host 3453 * mode. 3454 */ 3455 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3456 3457 if (sc->sc_flags.status_device_mode != 0) { 3458 dwc_otg_xfer_do_fifo(sc, xfer); 3459 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3460 goto done; 3461 } else { 3462 struct dwc_otg_td *td = xfer->td_transfer_cache; 3463 if (td->ep_type == UE_ISOCHRONOUS && 3464 (td->hcchar & HCCHAR_EPDIR_IN) == 0) { 3465 /* 3466 * Need to start ISOCHRONOUS OUT transfer ASAP 3467 * because execution is delayed by one 125us 3468 * microframe: 3469 */ 3470 dwc_otg_xfer_do_fifo(sc, xfer); 3471 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3472 goto done; 3473 } 3474 } 3475 3476 /* put transfer on interrupt queue */ 3477 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3478 3479 /* start timeout, if any */ 3480 if (xfer->timeout != 0) { 3481 usbd_transfer_timeout_ms(xfer, 3482 &dwc_otg_timeout, xfer->timeout); 3483 } 3484 3485 if (sc->sc_flags.status_device_mode != 0) 3486 goto done; 3487 3488 /* enable SOF interrupt, if any */ 3489 dwc_otg_enable_sof_irq(sc); 3490 done: 3491 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3492 } 3493 3494 static void 3495 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3496 { 3497 DPRINTFN(9, "\n"); 3498 3499 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3500 3501 /* set port bit */ 3502 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3503 3504 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3505 sizeof(sc->sc_hub_idata)); 3506 } 3507 3508 static usb_error_t 3509 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3510 { 3511 struct dwc_otg_td *td; 3512 uint32_t len; 3513 usb_error_t error; 3514 3515 DPRINTFN(9, "\n"); 3516 3517 td = xfer->td_transfer_cache; 3518 3519 do { 3520 len = td->remainder; 3521 3522 /* store last data toggle */ 3523 xfer->endpoint->toggle_next = td->toggle; 3524 3525 if (xfer->aframes != xfer->nframes) { 3526 /* 3527 * Verify the length and subtract 3528 * the remainder from "frlengths[]": 3529 */ 3530 if (len > xfer->frlengths[xfer->aframes]) { 3531 td->error_any = 1; 3532 } else { 3533 xfer->frlengths[xfer->aframes] -= len; 3534 } 3535 } 3536 /* Check for transfer error */ 3537 if (td->error_any) { 3538 /* the transfer is finished */ 3539 error = (td->error_stall ? 3540 USB_ERR_STALLED : USB_ERR_IOERROR); 3541 td = NULL; 3542 break; 3543 } 3544 /* Check for short transfer */ 3545 if (len > 0) { 3546 if (xfer->flags_int.short_frames_ok || 3547 xfer->flags_int.isochronous_xfr) { 3548 /* follow alt next */ 3549 if (td->alt_next) { 3550 td = td->obj_next; 3551 } else { 3552 td = NULL; 3553 } 3554 } else { 3555 /* the transfer is finished */ 3556 td = NULL; 3557 } 3558 error = 0; 3559 break; 3560 } 3561 td = td->obj_next; 3562 3563 /* this USB frame is complete */ 3564 error = 0; 3565 break; 3566 3567 } while (0); 3568 3569 /* update transfer cache */ 3570 3571 xfer->td_transfer_cache = td; 3572 3573 return (error); 3574 } 3575 3576 static void 3577 dwc_otg_standard_done(struct usb_xfer *xfer) 3578 { 3579 usb_error_t err = 0; 3580 3581 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3582 xfer, xfer->endpoint); 3583 3584 /* reset scanner */ 3585 3586 xfer->td_transfer_cache = xfer->td_transfer_first; 3587 3588 if (xfer->flags_int.control_xfr) { 3589 3590 if (xfer->flags_int.control_hdr) { 3591 3592 err = dwc_otg_standard_done_sub(xfer); 3593 } 3594 xfer->aframes = 1; 3595 3596 if (xfer->td_transfer_cache == NULL) { 3597 goto done; 3598 } 3599 } 3600 while (xfer->aframes != xfer->nframes) { 3601 3602 err = dwc_otg_standard_done_sub(xfer); 3603 xfer->aframes++; 3604 3605 if (xfer->td_transfer_cache == NULL) { 3606 goto done; 3607 } 3608 } 3609 3610 if (xfer->flags_int.control_xfr && 3611 !xfer->flags_int.control_act) { 3612 3613 err = dwc_otg_standard_done_sub(xfer); 3614 } 3615 done: 3616 dwc_otg_device_done(xfer, err); 3617 } 3618 3619 /*------------------------------------------------------------------------* 3620 * dwc_otg_device_done 3621 * 3622 * NOTE: this function can be called more than one time on the 3623 * same USB transfer! 3624 *------------------------------------------------------------------------*/ 3625 static void 3626 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3627 { 3628 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3629 3630 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3631 xfer, xfer->endpoint, error); 3632 3633 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3634 3635 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3636 /* Interrupts are cleared by the interrupt handler */ 3637 } else { 3638 struct dwc_otg_td *td; 3639 3640 td = xfer->td_transfer_cache; 3641 if (td != NULL) 3642 dwc_otg_host_channel_free(sc, td); 3643 } 3644 /* dequeue transfer and start next transfer */ 3645 usbd_transfer_done(xfer, error); 3646 3647 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3648 } 3649 3650 static void 3651 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3652 { 3653 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3654 } 3655 3656 static void 3657 dwc_otg_set_stall(struct usb_device *udev, 3658 struct usb_endpoint *ep, uint8_t *did_stall) 3659 { 3660 struct dwc_otg_softc *sc; 3661 uint32_t temp; 3662 uint32_t reg; 3663 uint8_t ep_no; 3664 3665 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3666 3667 /* check mode */ 3668 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3669 /* not supported */ 3670 return; 3671 } 3672 3673 sc = DWC_OTG_BUS2SC(udev->bus); 3674 3675 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3676 3677 /* get endpoint address */ 3678 ep_no = ep->edesc->bEndpointAddress; 3679 3680 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3681 3682 if (ep_no & UE_DIR_IN) { 3683 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3684 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3685 } else { 3686 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3687 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3688 } 3689 3690 /* disable and stall endpoint */ 3691 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3692 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3693 3694 /* clear active OUT ep */ 3695 if (!(ep_no & UE_DIR_IN)) { 3696 3697 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3698 3699 if (sc->sc_last_rx_status != 0 && 3700 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3701 sc->sc_last_rx_status)) { 3702 /* dump data */ 3703 dwc_otg_common_rx_ack(sc); 3704 /* poll interrupt */ 3705 dwc_otg_interrupt_poll_locked(sc); 3706 dwc_otg_interrupt_complete_locked(sc); 3707 } 3708 } 3709 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3710 } 3711 3712 static void 3713 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3714 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3715 { 3716 uint32_t reg; 3717 uint32_t temp; 3718 3719 if (ep_type == UE_CONTROL) { 3720 /* clearing stall is not needed */ 3721 return; 3722 } 3723 3724 if (ep_dir) { 3725 reg = DOTG_DIEPCTL(ep_no); 3726 } else { 3727 reg = DOTG_DOEPCTL(ep_no); 3728 sc->sc_active_rx_ep |= (1U << ep_no); 3729 } 3730 3731 /* round up and mask away the multiplier count */ 3732 mps = (mps + 3) & 0x7FC; 3733 3734 if (ep_type == UE_BULK) { 3735 temp = DIEPCTL_EPTYPE_SET( 3736 DIEPCTL_EPTYPE_BULK) | 3737 DIEPCTL_USBACTEP; 3738 } else if (ep_type == UE_INTERRUPT) { 3739 temp = DIEPCTL_EPTYPE_SET( 3740 DIEPCTL_EPTYPE_INTERRUPT) | 3741 DIEPCTL_USBACTEP; 3742 } else { 3743 temp = DIEPCTL_EPTYPE_SET( 3744 DIEPCTL_EPTYPE_ISOC) | 3745 DIEPCTL_USBACTEP; 3746 } 3747 3748 temp |= DIEPCTL_MPS_SET(mps); 3749 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3750 3751 if (ep_dir) 3752 sc->sc_in_ctl[ep_no] = temp; 3753 else 3754 sc->sc_out_ctl[ep_no] = temp; 3755 3756 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3757 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3758 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3759 3760 /* we only reset the transmit FIFO */ 3761 if (ep_dir) { 3762 dwc_otg_tx_fifo_reset(sc, 3763 GRSTCTL_TXFIFO(ep_no) | 3764 GRSTCTL_TXFFLSH); 3765 3766 DWC_OTG_WRITE_4(sc, 3767 DOTG_DIEPTSIZ(ep_no), 0); 3768 } 3769 3770 /* poll interrupt */ 3771 dwc_otg_interrupt_poll_locked(sc); 3772 dwc_otg_interrupt_complete_locked(sc); 3773 } 3774 3775 static void 3776 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3777 { 3778 struct dwc_otg_softc *sc; 3779 struct usb_endpoint_descriptor *ed; 3780 3781 DPRINTFN(5, "endpoint=%p\n", ep); 3782 3783 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3784 3785 /* check mode */ 3786 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3787 /* not supported */ 3788 return; 3789 } 3790 /* get softc */ 3791 sc = DWC_OTG_BUS2SC(udev->bus); 3792 3793 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3794 3795 /* get endpoint descriptor */ 3796 ed = ep->edesc; 3797 3798 /* reset endpoint */ 3799 dwc_otg_clear_stall_sub_locked(sc, 3800 UGETW(ed->wMaxPacketSize), 3801 (ed->bEndpointAddress & UE_ADDR), 3802 (ed->bmAttributes & UE_XFERTYPE), 3803 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3804 3805 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3806 } 3807 3808 static void 3809 dwc_otg_device_state_change(struct usb_device *udev) 3810 { 3811 struct dwc_otg_softc *sc; 3812 uint8_t x; 3813 3814 /* check mode */ 3815 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3816 /* not supported */ 3817 return; 3818 } 3819 3820 /* get softc */ 3821 sc = DWC_OTG_BUS2SC(udev->bus); 3822 3823 /* deactivate all other endpoint but the control endpoint */ 3824 if (udev->state == USB_STATE_CONFIGURED || 3825 udev->state == USB_STATE_ADDRESSED) { 3826 3827 USB_BUS_LOCK(&sc->sc_bus); 3828 3829 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3830 3831 if (x < sc->sc_dev_in_ep_max) { 3832 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3833 DIEPCTL_EPDIS); 3834 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3835 } 3836 3837 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3838 DOEPCTL_EPDIS); 3839 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3840 } 3841 USB_BUS_UNLOCK(&sc->sc_bus); 3842 } 3843 } 3844 3845 int 3846 dwc_otg_init(struct dwc_otg_softc *sc) 3847 { 3848 uint32_t temp; 3849 3850 DPRINTF("start\n"); 3851 3852 /* set up the bus structure */ 3853 sc->sc_bus.usbrev = USB_REV_2_0; 3854 sc->sc_bus.methods = &dwc_otg_bus_methods; 3855 3856 usb_callout_init_mtx(&sc->sc_timer, 3857 &sc->sc_bus.bus_mtx, 0); 3858 3859 USB_BUS_LOCK(&sc->sc_bus); 3860 3861 /* turn on clocks */ 3862 dwc_otg_clocks_on(sc); 3863 3864 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3865 DPRINTF("Version = 0x%08x\n", temp); 3866 3867 /* disconnect */ 3868 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3869 DCTL_SFTDISCON); 3870 3871 /* wait for host to detect disconnect */ 3872 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3873 3874 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3875 GRSTCTL_CSFTRST); 3876 3877 /* wait a little bit for block to reset */ 3878 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3879 3880 switch (sc->sc_mode) { 3881 case DWC_MODE_DEVICE: 3882 temp = GUSBCFG_FORCEDEVMODE; 3883 break; 3884 case DWC_MODE_HOST: 3885 temp = GUSBCFG_FORCEHOSTMODE; 3886 break; 3887 default: 3888 temp = 0; 3889 break; 3890 } 3891 3892 /* select HSIC, ULPI or internal PHY mode */ 3893 switch (dwc_otg_phy_type) { 3894 case DWC_OTG_PHY_HSIC: 3895 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3896 GUSBCFG_PHYIF | 3897 GUSBCFG_TRD_TIM_SET(5) | temp); 3898 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3899 0x000000EC); 3900 3901 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3902 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3903 temp & ~GLPMCFG_HSIC_CONN); 3904 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3905 temp | GLPMCFG_HSIC_CONN); 3906 break; 3907 case DWC_OTG_PHY_ULPI: 3908 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3909 GUSBCFG_ULPI_UTMI_SEL | 3910 GUSBCFG_TRD_TIM_SET(5) | temp); 3911 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3912 3913 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3914 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3915 temp & ~GLPMCFG_HSIC_CONN); 3916 break; 3917 case DWC_OTG_PHY_INTERNAL: 3918 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3919 GUSBCFG_PHYSEL | 3920 GUSBCFG_TRD_TIM_SET(5) | temp); 3921 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3922 3923 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3924 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3925 temp & ~GLPMCFG_HSIC_CONN); 3926 3927 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3928 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3929 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3930 DOTG_GGPIO_PWRDWN); 3931 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3932 break; 3933 default: 3934 break; 3935 } 3936 3937 /* clear global nak */ 3938 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3939 DCTL_CGOUTNAK | 3940 DCTL_CGNPINNAK); 3941 3942 /* disable USB port */ 3943 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3944 3945 /* wait 10ms */ 3946 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3947 3948 /* enable USB port */ 3949 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3950 3951 /* wait 10ms */ 3952 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3953 3954 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3955 3956 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3957 3958 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3959 3960 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3961 3962 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3963 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3964 3965 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3966 3967 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3968 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3969 3970 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3971 3972 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3973 3974 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3975 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3976 sc->sc_host_ch_max); 3977 3978 /* setup FIFO */ 3979 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3980 USB_BUS_UNLOCK(&sc->sc_bus); 3981 return (EINVAL); 3982 } 3983 3984 /* enable interrupts */ 3985 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ; 3986 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3987 3988 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3989 3990 /* enable all endpoint interrupts */ 3991 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3992 if (temp & GHWCFG2_MPI) { 3993 uint8_t x; 3994 3995 DPRINTF("Disable Multi Process Interrupts\n"); 3996 3997 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3998 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3999 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 4000 } 4001 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 4002 } 4003 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 4004 DIEPMSK_XFERCOMPLMSK); 4005 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 4006 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 4007 } 4008 4009 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 4010 /* setup clocks */ 4011 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 4012 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 4013 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 4014 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 4015 } 4016 4017 /* only enable global IRQ */ 4018 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 4019 GAHBCFG_GLBLINTRMSK); 4020 4021 /* turn off clocks */ 4022 dwc_otg_clocks_off(sc); 4023 4024 /* read initial VBUS state */ 4025 4026 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 4027 4028 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 4029 4030 dwc_otg_vbus_interrupt(sc, 4031 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 4032 4033 USB_BUS_UNLOCK(&sc->sc_bus); 4034 4035 /* catch any lost interrupts */ 4036 4037 dwc_otg_do_poll(&sc->sc_bus); 4038 4039 return (0); /* success */ 4040 } 4041 4042 void 4043 dwc_otg_uninit(struct dwc_otg_softc *sc) 4044 { 4045 USB_BUS_LOCK(&sc->sc_bus); 4046 4047 /* stop host timer */ 4048 dwc_otg_timer_stop(sc); 4049 4050 /* set disconnect */ 4051 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 4052 DCTL_SFTDISCON); 4053 4054 /* turn off global IRQ */ 4055 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 4056 4057 sc->sc_flags.port_enabled = 0; 4058 sc->sc_flags.port_powered = 0; 4059 sc->sc_flags.status_vbus = 0; 4060 sc->sc_flags.status_bus_reset = 0; 4061 sc->sc_flags.status_suspend = 0; 4062 sc->sc_flags.change_suspend = 0; 4063 sc->sc_flags.change_connect = 1; 4064 4065 dwc_otg_pull_down(sc); 4066 dwc_otg_clocks_off(sc); 4067 4068 USB_BUS_UNLOCK(&sc->sc_bus); 4069 4070 usb_callout_drain(&sc->sc_timer); 4071 } 4072 4073 static void 4074 dwc_otg_suspend(struct dwc_otg_softc *sc) 4075 { 4076 return; 4077 } 4078 4079 static void 4080 dwc_otg_resume(struct dwc_otg_softc *sc) 4081 { 4082 return; 4083 } 4084 4085 static void 4086 dwc_otg_do_poll(struct usb_bus *bus) 4087 { 4088 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4089 4090 USB_BUS_LOCK(&sc->sc_bus); 4091 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4092 dwc_otg_interrupt_poll_locked(sc); 4093 dwc_otg_interrupt_complete_locked(sc); 4094 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4095 USB_BUS_UNLOCK(&sc->sc_bus); 4096 } 4097 4098 /*------------------------------------------------------------------------* 4099 * DWC OTG bulk support 4100 * DWC OTG control support 4101 * DWC OTG interrupt support 4102 *------------------------------------------------------------------------*/ 4103 static void 4104 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4105 { 4106 } 4107 4108 static void 4109 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4110 { 4111 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4112 } 4113 4114 static void 4115 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4116 { 4117 } 4118 4119 static void 4120 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4121 { 4122 /* setup TDs */ 4123 dwc_otg_setup_standard_chain(xfer); 4124 dwc_otg_start_standard_chain(xfer); 4125 } 4126 4127 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4128 { 4129 .open = dwc_otg_device_non_isoc_open, 4130 .close = dwc_otg_device_non_isoc_close, 4131 .enter = dwc_otg_device_non_isoc_enter, 4132 .start = dwc_otg_device_non_isoc_start, 4133 }; 4134 4135 /*------------------------------------------------------------------------* 4136 * DWC OTG full speed isochronous support 4137 *------------------------------------------------------------------------*/ 4138 static void 4139 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4140 { 4141 } 4142 4143 static void 4144 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4145 { 4146 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4147 } 4148 4149 static void 4150 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4151 { 4152 } 4153 4154 static void 4155 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4156 { 4157 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4158 uint32_t temp; 4159 uint32_t msframes; 4160 uint32_t framenum; 4161 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4162 4163 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4164 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4165 4166 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4167 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4168 4169 /* get the current frame index */ 4170 framenum = (temp & HFNUM_FRNUM_MASK); 4171 } else { 4172 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4173 4174 /* get the current frame index */ 4175 framenum = DSTS_SOFFN_GET(temp); 4176 } 4177 4178 /* 4179 * Check if port is doing 8000 or 1000 frames per second: 4180 */ 4181 if (sc->sc_flags.status_high_speed) 4182 framenum /= 8; 4183 4184 framenum &= DWC_OTG_FRAME_MASK; 4185 4186 /* 4187 * Compute number of milliseconds worth of data traffic for 4188 * this USB transfer: 4189 */ 4190 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4191 msframes = ((xfer->nframes << shift) + 7) / 8; 4192 else 4193 msframes = xfer->nframes; 4194 4195 /* 4196 * check if the frame index is within the window where the frames 4197 * will be inserted 4198 */ 4199 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4200 4201 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4202 /* 4203 * If there is data underflow or the pipe queue is 4204 * empty we schedule the transfer a few frames ahead 4205 * of the current frame position. Else two isochronous 4206 * transfers might overlap. 4207 */ 4208 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4209 xfer->endpoint->is_synced = 1; 4210 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4211 } 4212 /* 4213 * compute how many milliseconds the insertion is ahead of the 4214 * current frame position: 4215 */ 4216 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4217 4218 /* 4219 * pre-compute when the isochronous transfer will be finished: 4220 */ 4221 xfer->isoc_time_complete = 4222 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4223 4224 /* setup TDs */ 4225 dwc_otg_setup_standard_chain(xfer); 4226 4227 /* compute frame number for next insertion */ 4228 xfer->endpoint->isoc_next += msframes; 4229 4230 /* start TD chain */ 4231 dwc_otg_start_standard_chain(xfer); 4232 } 4233 4234 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4235 { 4236 .open = dwc_otg_device_isoc_open, 4237 .close = dwc_otg_device_isoc_close, 4238 .enter = dwc_otg_device_isoc_enter, 4239 .start = dwc_otg_device_isoc_start, 4240 }; 4241 4242 /*------------------------------------------------------------------------* 4243 * DWC OTG root control support 4244 *------------------------------------------------------------------------* 4245 * Simulate a hardware HUB by handling all the necessary requests. 4246 *------------------------------------------------------------------------*/ 4247 4248 static const struct usb_device_descriptor dwc_otg_devd = { 4249 .bLength = sizeof(struct usb_device_descriptor), 4250 .bDescriptorType = UDESC_DEVICE, 4251 .bcdUSB = {0x00, 0x02}, 4252 .bDeviceClass = UDCLASS_HUB, 4253 .bDeviceSubClass = UDSUBCLASS_HUB, 4254 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4255 .bMaxPacketSize = 64, 4256 .bcdDevice = {0x00, 0x01}, 4257 .iManufacturer = 1, 4258 .iProduct = 2, 4259 .bNumConfigurations = 1, 4260 }; 4261 4262 static const struct dwc_otg_config_desc dwc_otg_confd = { 4263 .confd = { 4264 .bLength = sizeof(struct usb_config_descriptor), 4265 .bDescriptorType = UDESC_CONFIG, 4266 .wTotalLength[0] = sizeof(dwc_otg_confd), 4267 .bNumInterface = 1, 4268 .bConfigurationValue = 1, 4269 .iConfiguration = 0, 4270 .bmAttributes = UC_SELF_POWERED, 4271 .bMaxPower = 0, 4272 }, 4273 .ifcd = { 4274 .bLength = sizeof(struct usb_interface_descriptor), 4275 .bDescriptorType = UDESC_INTERFACE, 4276 .bNumEndpoints = 1, 4277 .bInterfaceClass = UICLASS_HUB, 4278 .bInterfaceSubClass = UISUBCLASS_HUB, 4279 .bInterfaceProtocol = 0, 4280 }, 4281 .endpd = { 4282 .bLength = sizeof(struct usb_endpoint_descriptor), 4283 .bDescriptorType = UDESC_ENDPOINT, 4284 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4285 .bmAttributes = UE_INTERRUPT, 4286 .wMaxPacketSize[0] = 8, 4287 .bInterval = 255, 4288 }, 4289 }; 4290 4291 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4292 4293 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4294 .bDescLength = sizeof(dwc_otg_hubd), 4295 .bDescriptorType = UDESC_HUB, 4296 .bNbrPorts = 1, 4297 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4298 .bPwrOn2PwrGood = 50, 4299 .bHubContrCurrent = 0, 4300 .DeviceRemovable = {0}, /* port is removable */ 4301 }; 4302 4303 #define STRING_VENDOR \ 4304 "D\0W\0C\0O\0T\0G" 4305 4306 #define STRING_PRODUCT \ 4307 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4308 4309 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4310 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4311 4312 static usb_error_t 4313 dwc_otg_roothub_exec(struct usb_device *udev, 4314 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4315 { 4316 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4317 const void *ptr; 4318 uint16_t len; 4319 uint16_t value; 4320 uint16_t index; 4321 usb_error_t err; 4322 4323 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4324 4325 /* buffer reset */ 4326 ptr = (const void *)&sc->sc_hub_temp; 4327 len = 0; 4328 err = 0; 4329 4330 value = UGETW(req->wValue); 4331 index = UGETW(req->wIndex); 4332 4333 /* demultiplex the control request */ 4334 4335 switch (req->bmRequestType) { 4336 case UT_READ_DEVICE: 4337 switch (req->bRequest) { 4338 case UR_GET_DESCRIPTOR: 4339 goto tr_handle_get_descriptor; 4340 case UR_GET_CONFIG: 4341 goto tr_handle_get_config; 4342 case UR_GET_STATUS: 4343 goto tr_handle_get_status; 4344 default: 4345 goto tr_stalled; 4346 } 4347 break; 4348 4349 case UT_WRITE_DEVICE: 4350 switch (req->bRequest) { 4351 case UR_SET_ADDRESS: 4352 goto tr_handle_set_address; 4353 case UR_SET_CONFIG: 4354 goto tr_handle_set_config; 4355 case UR_CLEAR_FEATURE: 4356 goto tr_valid; /* nop */ 4357 case UR_SET_DESCRIPTOR: 4358 goto tr_valid; /* nop */ 4359 case UR_SET_FEATURE: 4360 default: 4361 goto tr_stalled; 4362 } 4363 break; 4364 4365 case UT_WRITE_ENDPOINT: 4366 switch (req->bRequest) { 4367 case UR_CLEAR_FEATURE: 4368 switch (UGETW(req->wValue)) { 4369 case UF_ENDPOINT_HALT: 4370 goto tr_handle_clear_halt; 4371 case UF_DEVICE_REMOTE_WAKEUP: 4372 goto tr_handle_clear_wakeup; 4373 default: 4374 goto tr_stalled; 4375 } 4376 break; 4377 case UR_SET_FEATURE: 4378 switch (UGETW(req->wValue)) { 4379 case UF_ENDPOINT_HALT: 4380 goto tr_handle_set_halt; 4381 case UF_DEVICE_REMOTE_WAKEUP: 4382 goto tr_handle_set_wakeup; 4383 default: 4384 goto tr_stalled; 4385 } 4386 break; 4387 case UR_SYNCH_FRAME: 4388 goto tr_valid; /* nop */ 4389 default: 4390 goto tr_stalled; 4391 } 4392 break; 4393 4394 case UT_READ_ENDPOINT: 4395 switch (req->bRequest) { 4396 case UR_GET_STATUS: 4397 goto tr_handle_get_ep_status; 4398 default: 4399 goto tr_stalled; 4400 } 4401 break; 4402 4403 case UT_WRITE_INTERFACE: 4404 switch (req->bRequest) { 4405 case UR_SET_INTERFACE: 4406 goto tr_handle_set_interface; 4407 case UR_CLEAR_FEATURE: 4408 goto tr_valid; /* nop */ 4409 case UR_SET_FEATURE: 4410 default: 4411 goto tr_stalled; 4412 } 4413 break; 4414 4415 case UT_READ_INTERFACE: 4416 switch (req->bRequest) { 4417 case UR_GET_INTERFACE: 4418 goto tr_handle_get_interface; 4419 case UR_GET_STATUS: 4420 goto tr_handle_get_iface_status; 4421 default: 4422 goto tr_stalled; 4423 } 4424 break; 4425 4426 case UT_WRITE_CLASS_INTERFACE: 4427 case UT_WRITE_VENDOR_INTERFACE: 4428 /* XXX forward */ 4429 break; 4430 4431 case UT_READ_CLASS_INTERFACE: 4432 case UT_READ_VENDOR_INTERFACE: 4433 /* XXX forward */ 4434 break; 4435 4436 case UT_WRITE_CLASS_DEVICE: 4437 switch (req->bRequest) { 4438 case UR_CLEAR_FEATURE: 4439 goto tr_valid; 4440 case UR_SET_DESCRIPTOR: 4441 case UR_SET_FEATURE: 4442 break; 4443 default: 4444 goto tr_stalled; 4445 } 4446 break; 4447 4448 case UT_WRITE_CLASS_OTHER: 4449 switch (req->bRequest) { 4450 case UR_CLEAR_FEATURE: 4451 goto tr_handle_clear_port_feature; 4452 case UR_SET_FEATURE: 4453 goto tr_handle_set_port_feature; 4454 case UR_CLEAR_TT_BUFFER: 4455 case UR_RESET_TT: 4456 case UR_STOP_TT: 4457 goto tr_valid; 4458 4459 default: 4460 goto tr_stalled; 4461 } 4462 break; 4463 4464 case UT_READ_CLASS_OTHER: 4465 switch (req->bRequest) { 4466 case UR_GET_TT_STATE: 4467 goto tr_handle_get_tt_state; 4468 case UR_GET_STATUS: 4469 goto tr_handle_get_port_status; 4470 default: 4471 goto tr_stalled; 4472 } 4473 break; 4474 4475 case UT_READ_CLASS_DEVICE: 4476 switch (req->bRequest) { 4477 case UR_GET_DESCRIPTOR: 4478 goto tr_handle_get_class_descriptor; 4479 case UR_GET_STATUS: 4480 goto tr_handle_get_class_status; 4481 4482 default: 4483 goto tr_stalled; 4484 } 4485 break; 4486 default: 4487 goto tr_stalled; 4488 } 4489 goto tr_valid; 4490 4491 tr_handle_get_descriptor: 4492 switch (value >> 8) { 4493 case UDESC_DEVICE: 4494 if (value & 0xff) { 4495 goto tr_stalled; 4496 } 4497 len = sizeof(dwc_otg_devd); 4498 ptr = (const void *)&dwc_otg_devd; 4499 goto tr_valid; 4500 case UDESC_CONFIG: 4501 if (value & 0xff) { 4502 goto tr_stalled; 4503 } 4504 len = sizeof(dwc_otg_confd); 4505 ptr = (const void *)&dwc_otg_confd; 4506 goto tr_valid; 4507 case UDESC_STRING: 4508 switch (value & 0xff) { 4509 case 0: /* Language table */ 4510 len = sizeof(usb_string_lang_en); 4511 ptr = (const void *)&usb_string_lang_en; 4512 goto tr_valid; 4513 4514 case 1: /* Vendor */ 4515 len = sizeof(dwc_otg_vendor); 4516 ptr = (const void *)&dwc_otg_vendor; 4517 goto tr_valid; 4518 4519 case 2: /* Product */ 4520 len = sizeof(dwc_otg_product); 4521 ptr = (const void *)&dwc_otg_product; 4522 goto tr_valid; 4523 default: 4524 break; 4525 } 4526 break; 4527 default: 4528 goto tr_stalled; 4529 } 4530 goto tr_stalled; 4531 4532 tr_handle_get_config: 4533 len = 1; 4534 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4535 goto tr_valid; 4536 4537 tr_handle_get_status: 4538 len = 2; 4539 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4540 goto tr_valid; 4541 4542 tr_handle_set_address: 4543 if (value & 0xFF00) { 4544 goto tr_stalled; 4545 } 4546 sc->sc_rt_addr = value; 4547 goto tr_valid; 4548 4549 tr_handle_set_config: 4550 if (value >= 2) { 4551 goto tr_stalled; 4552 } 4553 sc->sc_conf = value; 4554 goto tr_valid; 4555 4556 tr_handle_get_interface: 4557 len = 1; 4558 sc->sc_hub_temp.wValue[0] = 0; 4559 goto tr_valid; 4560 4561 tr_handle_get_tt_state: 4562 tr_handle_get_class_status: 4563 tr_handle_get_iface_status: 4564 tr_handle_get_ep_status: 4565 len = 2; 4566 USETW(sc->sc_hub_temp.wValue, 0); 4567 goto tr_valid; 4568 4569 tr_handle_set_halt: 4570 tr_handle_set_interface: 4571 tr_handle_set_wakeup: 4572 tr_handle_clear_wakeup: 4573 tr_handle_clear_halt: 4574 goto tr_valid; 4575 4576 tr_handle_clear_port_feature: 4577 if (index != 1) 4578 goto tr_stalled; 4579 4580 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4581 4582 switch (value) { 4583 case UHF_PORT_SUSPEND: 4584 dwc_otg_wakeup_peer(sc); 4585 break; 4586 4587 case UHF_PORT_ENABLE: 4588 if (sc->sc_flags.status_device_mode == 0) { 4589 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4590 sc->sc_hprt_val | HPRT_PRTENA); 4591 } 4592 sc->sc_flags.port_enabled = 0; 4593 break; 4594 4595 case UHF_C_PORT_RESET: 4596 sc->sc_flags.change_reset = 0; 4597 break; 4598 4599 case UHF_C_PORT_ENABLE: 4600 sc->sc_flags.change_enabled = 0; 4601 break; 4602 4603 case UHF_C_PORT_OVER_CURRENT: 4604 sc->sc_flags.change_over_current = 0; 4605 break; 4606 4607 case UHF_PORT_TEST: 4608 case UHF_PORT_INDICATOR: 4609 /* nops */ 4610 break; 4611 4612 case UHF_PORT_POWER: 4613 sc->sc_flags.port_powered = 0; 4614 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4615 sc->sc_hprt_val = 0; 4616 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4617 } 4618 dwc_otg_pull_down(sc); 4619 dwc_otg_clocks_off(sc); 4620 break; 4621 4622 case UHF_C_PORT_CONNECTION: 4623 /* clear connect change flag */ 4624 sc->sc_flags.change_connect = 0; 4625 break; 4626 4627 case UHF_C_PORT_SUSPEND: 4628 sc->sc_flags.change_suspend = 0; 4629 break; 4630 4631 default: 4632 err = USB_ERR_IOERROR; 4633 goto done; 4634 } 4635 goto tr_valid; 4636 4637 tr_handle_set_port_feature: 4638 if (index != 1) { 4639 goto tr_stalled; 4640 } 4641 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4642 4643 switch (value) { 4644 case UHF_PORT_ENABLE: 4645 break; 4646 4647 case UHF_PORT_SUSPEND: 4648 if (sc->sc_flags.status_device_mode == 0) { 4649 /* set suspend BIT */ 4650 sc->sc_hprt_val |= HPRT_PRTSUSP; 4651 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4652 4653 /* generate HUB suspend event */ 4654 dwc_otg_suspend_irq(sc); 4655 } 4656 break; 4657 4658 case UHF_PORT_RESET: 4659 if (sc->sc_flags.status_device_mode == 0) { 4660 4661 DPRINTF("PORT RESET\n"); 4662 4663 /* enable PORT reset */ 4664 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4665 4666 /* Wait 62.5ms for reset to complete */ 4667 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4668 4669 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4670 4671 /* Wait 62.5ms for reset to complete */ 4672 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4673 4674 /* reset FIFOs */ 4675 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4676 4677 sc->sc_flags.change_reset = 1; 4678 } else { 4679 err = USB_ERR_IOERROR; 4680 } 4681 break; 4682 4683 case UHF_PORT_TEST: 4684 case UHF_PORT_INDICATOR: 4685 /* nops */ 4686 break; 4687 case UHF_PORT_POWER: 4688 sc->sc_flags.port_powered = 1; 4689 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4690 sc->sc_hprt_val |= HPRT_PRTPWR; 4691 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4692 } 4693 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4694 /* pull up D+, if any */ 4695 dwc_otg_pull_up(sc); 4696 } 4697 break; 4698 default: 4699 err = USB_ERR_IOERROR; 4700 goto done; 4701 } 4702 goto tr_valid; 4703 4704 tr_handle_get_port_status: 4705 4706 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4707 4708 if (index != 1) 4709 goto tr_stalled; 4710 4711 if (sc->sc_flags.status_vbus) 4712 dwc_otg_clocks_on(sc); 4713 else 4714 dwc_otg_clocks_off(sc); 4715 4716 /* Select Device Side Mode */ 4717 4718 if (sc->sc_flags.status_device_mode) { 4719 value = UPS_PORT_MODE_DEVICE; 4720 dwc_otg_timer_stop(sc); 4721 } else { 4722 value = 0; 4723 dwc_otg_timer_start(sc); 4724 } 4725 4726 if (sc->sc_flags.status_high_speed) 4727 value |= UPS_HIGH_SPEED; 4728 else if (sc->sc_flags.status_low_speed) 4729 value |= UPS_LOW_SPEED; 4730 4731 if (sc->sc_flags.port_powered) 4732 value |= UPS_PORT_POWER; 4733 4734 if (sc->sc_flags.port_enabled) 4735 value |= UPS_PORT_ENABLED; 4736 4737 if (sc->sc_flags.port_over_current) 4738 value |= UPS_OVERCURRENT_INDICATOR; 4739 4740 if (sc->sc_flags.status_vbus && 4741 sc->sc_flags.status_bus_reset) 4742 value |= UPS_CURRENT_CONNECT_STATUS; 4743 4744 if (sc->sc_flags.status_suspend) 4745 value |= UPS_SUSPEND; 4746 4747 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4748 4749 value = 0; 4750 4751 if (sc->sc_flags.change_enabled) 4752 value |= UPS_C_PORT_ENABLED; 4753 if (sc->sc_flags.change_connect) 4754 value |= UPS_C_CONNECT_STATUS; 4755 if (sc->sc_flags.change_suspend) 4756 value |= UPS_C_SUSPEND; 4757 if (sc->sc_flags.change_reset) 4758 value |= UPS_C_PORT_RESET; 4759 if (sc->sc_flags.change_over_current) 4760 value |= UPS_C_OVERCURRENT_INDICATOR; 4761 4762 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4763 len = sizeof(sc->sc_hub_temp.ps); 4764 goto tr_valid; 4765 4766 tr_handle_get_class_descriptor: 4767 if (value & 0xFF) { 4768 goto tr_stalled; 4769 } 4770 ptr = (const void *)&dwc_otg_hubd; 4771 len = sizeof(dwc_otg_hubd); 4772 goto tr_valid; 4773 4774 tr_stalled: 4775 err = USB_ERR_STALLED; 4776 tr_valid: 4777 done: 4778 *plength = len; 4779 *pptr = ptr; 4780 return (err); 4781 } 4782 4783 static void 4784 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4785 { 4786 struct usb_xfer *xfer; 4787 void *last_obj; 4788 uint32_t ntd; 4789 uint32_t n; 4790 uint8_t ep_no; 4791 uint8_t ep_type; 4792 4793 xfer = parm->curr_xfer; 4794 4795 /* 4796 * NOTE: This driver does not use any of the parameters that 4797 * are computed from the following values. Just set some 4798 * reasonable dummies: 4799 */ 4800 parm->hc_max_packet_size = 0x500; 4801 parm->hc_max_packet_count = 3; 4802 parm->hc_max_frame_size = 3 * 0x500; 4803 4804 usbd_transfer_setup_sub(parm); 4805 4806 /* 4807 * compute maximum number of TDs 4808 */ 4809 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4810 4811 if (ep_type == UE_CONTROL) { 4812 4813 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4814 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4815 } else { 4816 4817 ntd = xfer->nframes + 1 /* SYNC */ ; 4818 } 4819 4820 /* 4821 * check if "usbd_transfer_setup_sub" set an error 4822 */ 4823 if (parm->err) 4824 return; 4825 4826 /* 4827 * allocate transfer descriptors 4828 */ 4829 last_obj = NULL; 4830 4831 ep_no = xfer->endpointno & UE_ADDR; 4832 4833 /* 4834 * Check for a valid endpoint profile in USB device mode: 4835 */ 4836 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4837 const struct usb_hw_ep_profile *pf; 4838 4839 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4840 4841 if (pf == NULL) { 4842 /* should not happen */ 4843 parm->err = USB_ERR_INVAL; 4844 return; 4845 } 4846 } 4847 4848 /* align data */ 4849 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4850 4851 for (n = 0; n != ntd; n++) { 4852 4853 struct dwc_otg_td *td; 4854 4855 if (parm->buf) { 4856 4857 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4858 4859 /* compute shared bandwidth resource index for TT */ 4860 if (dwc_otg_uses_split(parm->udev)) { 4861 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4862 td->tt_index = parm->udev->device_index; 4863 else 4864 td->tt_index = parm->udev->parent_hs_hub->device_index; 4865 } else { 4866 td->tt_index = parm->udev->device_index; 4867 } 4868 4869 /* init TD */ 4870 td->max_packet_size = xfer->max_packet_size; 4871 td->max_packet_count = xfer->max_packet_count; 4872 /* range check */ 4873 if (td->max_packet_count == 0 || td->max_packet_count > 3) 4874 td->max_packet_count = 1; 4875 td->ep_no = ep_no; 4876 td->ep_type = ep_type; 4877 td->obj_next = last_obj; 4878 4879 last_obj = td; 4880 } 4881 parm->size[0] += sizeof(*td); 4882 } 4883 4884 xfer->td_start[0] = last_obj; 4885 } 4886 4887 static void 4888 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4889 { 4890 return; 4891 } 4892 4893 static void 4894 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4895 struct usb_endpoint *ep) 4896 { 4897 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4898 4899 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4900 ep, udev->address, 4901 edesc->bEndpointAddress, udev->flags.usb_mode, 4902 sc->sc_rt_addr, udev->device_index); 4903 4904 if (udev->device_index != sc->sc_rt_addr) { 4905 4906 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4907 if (udev->speed != USB_SPEED_FULL && 4908 udev->speed != USB_SPEED_HIGH) { 4909 /* not supported */ 4910 return; 4911 } 4912 } else { 4913 if (udev->speed == USB_SPEED_HIGH && 4914 (edesc->wMaxPacketSize[1] & 0x18) != 0 && 4915 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) { 4916 /* not supported */ 4917 DPRINTFN(-1, "Non-isochronous high bandwidth " 4918 "endpoint not supported\n"); 4919 return; 4920 } 4921 } 4922 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4923 ep->methods = &dwc_otg_device_isoc_methods; 4924 else 4925 ep->methods = &dwc_otg_device_non_isoc_methods; 4926 } 4927 } 4928 4929 static void 4930 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4931 { 4932 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4933 4934 switch (state) { 4935 case USB_HW_POWER_SUSPEND: 4936 dwc_otg_suspend(sc); 4937 break; 4938 case USB_HW_POWER_SHUTDOWN: 4939 dwc_otg_uninit(sc); 4940 break; 4941 case USB_HW_POWER_RESUME: 4942 dwc_otg_resume(sc); 4943 break; 4944 default: 4945 break; 4946 } 4947 } 4948 4949 static void 4950 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4951 { 4952 /* DMA delay - wait until any use of memory is finished */ 4953 *pus = (2125); /* microseconds */ 4954 } 4955 4956 static void 4957 dwc_otg_device_resume(struct usb_device *udev) 4958 { 4959 DPRINTF("\n"); 4960 4961 /* poll all transfers again to restart resumed ones */ 4962 dwc_otg_do_poll(udev->bus); 4963 } 4964 4965 static void 4966 dwc_otg_device_suspend(struct usb_device *udev) 4967 { 4968 DPRINTF("\n"); 4969 } 4970 4971 static const struct usb_bus_methods dwc_otg_bus_methods = 4972 { 4973 .endpoint_init = &dwc_otg_ep_init, 4974 .xfer_setup = &dwc_otg_xfer_setup, 4975 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4976 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4977 .xfer_stall = &dwc_otg_xfer_stall, 4978 .set_stall = &dwc_otg_set_stall, 4979 .clear_stall = &dwc_otg_clear_stall, 4980 .roothub_exec = &dwc_otg_roothub_exec, 4981 .xfer_poll = &dwc_otg_do_poll, 4982 .device_state_change = &dwc_otg_device_state_change, 4983 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4984 .get_dma_delay = &dwc_otg_get_dma_delay, 4985 .device_resume = &dwc_otg_device_resume, 4986 .device_suspend = &dwc_otg_device_suspend, 4987 }; 4988