1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2UDEV(pc) \ 93 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_OTGINTMSK | \ 102 GINTMSK_PRTINTMSK) 103 104 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 105 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 106 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 107 GINTSTS_SESSREQINT) 108 109 static int dwc_otg_use_hsic; 110 111 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 112 113 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, use_hsic, CTLFLAG_RD | CTLFLAG_TUN, 114 &dwc_otg_use_hsic, 0, "DWC OTG uses HSIC interface"); 115 TUNABLE_INT("hw.usb.dwc_otg.use_hsic", &dwc_otg_use_hsic); 116 117 #ifdef USB_DEBUG 118 static int dwc_otg_debug; 119 120 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 121 &dwc_otg_debug, 0, "DWC OTG debug level"); 122 #endif 123 124 #define DWC_OTG_INTR_ENDPT 1 125 126 /* prototypes */ 127 128 static const struct usb_bus_methods dwc_otg_bus_methods; 129 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 130 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 131 132 static dwc_otg_cmd_t dwc_otg_setup_rx; 133 static dwc_otg_cmd_t dwc_otg_data_rx; 134 static dwc_otg_cmd_t dwc_otg_data_tx; 135 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 136 137 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 138 static dwc_otg_cmd_t dwc_otg_host_data_tx; 139 static dwc_otg_cmd_t dwc_otg_host_data_rx; 140 141 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 142 static void dwc_otg_do_poll(struct usb_bus *); 143 static void dwc_otg_standard_done(struct usb_xfer *); 144 static void dwc_otg_root_intr(struct dwc_otg_softc *); 145 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 146 static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); 147 148 /* 149 * Here is a configuration that the chip supports. 150 */ 151 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 152 153 [0] = { 154 .max_in_frame_size = 64,/* fixed */ 155 .max_out_frame_size = 64, /* fixed */ 156 .is_simplex = 1, 157 .support_control = 1, 158 } 159 }; 160 161 static void 162 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 163 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 164 { 165 struct dwc_otg_softc *sc; 166 167 sc = DWC_OTG_BUS2SC(udev->bus); 168 169 if (ep_addr < sc->sc_dev_ep_max) 170 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 171 else 172 *ppf = NULL; 173 } 174 175 static int 176 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 177 { 178 struct dwc_otg_profile *pf; 179 uint32_t fifo_size; 180 uint32_t fifo_regs; 181 uint32_t tx_start; 182 uint8_t x; 183 184 fifo_size = sc->sc_fifo_size; 185 186 /* 187 * NOTE: Reserved fixed size area at end of RAM, which must 188 * not be allocated to the FIFOs: 189 */ 190 fifo_regs = 4 * 16; 191 192 if (fifo_size < fifo_regs) { 193 DPRINTF("Too little FIFO\n"); 194 return (EINVAL); 195 } 196 197 /* subtract FIFO regs from total once */ 198 fifo_size -= fifo_regs; 199 200 /* split equally for IN and OUT */ 201 fifo_size /= 2; 202 203 /* align to 4 bytes boundary */ 204 fifo_size &= ~3; 205 206 /* set global receive FIFO size */ 207 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 208 209 tx_start = fifo_size; 210 211 if (fifo_size < 64) { 212 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 213 return (EINVAL); 214 } 215 216 /* disable any leftover host channels */ 217 for (x = 0; x != sc->sc_host_ch_max; x++) { 218 if (sc->sc_chan_state[x].wait_sof == 0) 219 continue; 220 dwc_otg_host_channel_disable(sc, x); 221 } 222 223 if (mode == DWC_MODE_HOST) { 224 225 /* reset active endpoints */ 226 sc->sc_active_rx_ep = 0; 227 228 /* split equally for periodic and non-periodic */ 229 fifo_size /= 2; 230 231 /* align to 4 bytes boundary */ 232 fifo_size &= ~3; 233 234 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 235 ((fifo_size / 4) << 16) | 236 (tx_start / 4)); 237 238 tx_start += fifo_size; 239 240 for (x = 0; x != sc->sc_host_ch_max; x++) { 241 /* disable all host interrupts */ 242 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 0); 243 } 244 245 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 246 ((fifo_size / 4) << 16) | 247 (tx_start / 4)); 248 249 /* reset host channel state */ 250 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 251 252 /* reset FIFO TX levels */ 253 sc->sc_tx_cur_p_level = 0; 254 sc->sc_tx_cur_np_level = 0; 255 256 /* store maximum periodic and non-periodic FIFO TX size */ 257 sc->sc_tx_max_size = fifo_size; 258 259 /* disable all host channel interrupts */ 260 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 0); 261 } 262 263 if (mode == DWC_MODE_DEVICE) { 264 265 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 266 (0x10 << 16) | (tx_start / 4)); 267 fifo_size -= 0x40; 268 tx_start += 0x40; 269 270 /* setup control endpoint profile */ 271 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 272 273 /* reset active endpoints */ 274 sc->sc_active_rx_ep = 1; 275 276 for (x = 1; x != sc->sc_dev_ep_max; x++) { 277 278 pf = sc->sc_hw_ep_profile + x; 279 280 pf->usb.max_out_frame_size = 1024 * 3; 281 pf->usb.is_simplex = 0; /* assume duplex */ 282 pf->usb.support_bulk = 1; 283 pf->usb.support_interrupt = 1; 284 pf->usb.support_isochronous = 1; 285 pf->usb.support_out = 1; 286 287 if (x < sc->sc_dev_in_ep_max) { 288 uint32_t limit; 289 290 limit = (x == 1) ? DWC_OTG_MAX_TXN : 291 (DWC_OTG_MAX_TXN / 2); 292 293 if (fifo_size >= limit) { 294 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 295 ((limit / 4) << 16) | 296 (tx_start / 4)); 297 tx_start += limit; 298 fifo_size -= limit; 299 pf->usb.max_in_frame_size = 0x200; 300 pf->usb.support_in = 1; 301 pf->max_buffer = limit; 302 303 } else if (fifo_size >= 0x80) { 304 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 305 ((0x80 / 4) << 16) | (tx_start / 4)); 306 tx_start += 0x80; 307 fifo_size -= 0x80; 308 pf->usb.max_in_frame_size = 0x40; 309 pf->usb.support_in = 1; 310 311 } else { 312 pf->usb.is_simplex = 1; 313 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 314 (0x0 << 16) | (tx_start / 4)); 315 } 316 } else { 317 pf->usb.is_simplex = 1; 318 } 319 320 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 321 pf->usb.max_in_frame_size, 322 pf->usb.max_out_frame_size); 323 } 324 } 325 326 /* reset RX FIFO */ 327 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 328 GRSTCTL_RXFFLSH); 329 330 if (mode != DWC_MODE_OTG) { 331 /* reset all TX FIFOs */ 332 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 333 GRSTCTL_TXFIFO(0x10) | 334 GRSTCTL_TXFFLSH); 335 } else { 336 /* reset active endpoints */ 337 sc->sc_active_rx_ep = 0; 338 339 /* reset periodic and non-periodic FIFO TX size */ 340 sc->sc_tx_max_size = fifo_size; 341 342 /* reset host channel state */ 343 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 344 345 /* reset FIFO TX levels */ 346 sc->sc_tx_cur_p_level = 0; 347 sc->sc_tx_cur_np_level = 0; 348 } 349 return (0); 350 } 351 352 static void 353 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 354 { 355 356 /* 357 * Disabled until further. Assuming that the register is already 358 * programmed correctly by the boot loader. 359 */ 360 #if 0 361 uint32_t temp; 362 363 /* setup HOST frame interval register, based on existing value */ 364 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 365 if (temp >= 10000) 366 temp /= 1000; 367 else 368 temp /= 125; 369 370 /* figure out nearest X-tal value */ 371 if (temp >= 54) 372 temp = 60; /* MHz */ 373 else if (temp >= 39) 374 temp = 48; /* MHz */ 375 else 376 temp = 30; /* MHz */ 377 378 if (sc->sc_flags.status_high_speed) 379 temp *= 125; 380 else 381 temp *= 1000; 382 383 DPRINTF("HFIR=0x%08x\n", temp); 384 385 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 386 #endif 387 } 388 389 static void 390 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 391 { 392 if (sc->sc_flags.clocks_off && 393 sc->sc_flags.port_powered) { 394 395 DPRINTFN(5, "\n"); 396 397 /* TODO - platform specific */ 398 399 sc->sc_flags.clocks_off = 0; 400 } 401 } 402 403 static void 404 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 405 { 406 if (!sc->sc_flags.clocks_off) { 407 408 DPRINTFN(5, "\n"); 409 410 /* TODO - platform specific */ 411 412 sc->sc_flags.clocks_off = 1; 413 } 414 } 415 416 static void 417 dwc_otg_pull_up(struct dwc_otg_softc *sc) 418 { 419 uint32_t temp; 420 421 /* pullup D+, if possible */ 422 423 if (!sc->sc_flags.d_pulled_up && 424 sc->sc_flags.port_powered) { 425 sc->sc_flags.d_pulled_up = 1; 426 427 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 428 temp &= ~DCTL_SFTDISCON; 429 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 430 } 431 } 432 433 static void 434 dwc_otg_pull_down(struct dwc_otg_softc *sc) 435 { 436 uint32_t temp; 437 438 /* pulldown D+, if possible */ 439 440 if (sc->sc_flags.d_pulled_up) { 441 sc->sc_flags.d_pulled_up = 0; 442 443 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 444 temp |= DCTL_SFTDISCON; 445 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 446 } 447 } 448 449 static void 450 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 451 { 452 /* In device mode we don't use the SOF interrupt */ 453 if (sc->sc_flags.status_device_mode != 0 || 454 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 455 return; 456 sc->sc_irq_mask |= GINTMSK_SOFMSK; 457 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 458 } 459 460 static void 461 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 462 { 463 if (sc->sc_flags.status_suspend) { 464 /* update status bits */ 465 sc->sc_flags.status_suspend = 0; 466 sc->sc_flags.change_suspend = 1; 467 468 if (sc->sc_flags.status_device_mode) { 469 /* 470 * Disable resume interrupt and enable suspend 471 * interrupt: 472 */ 473 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 474 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 475 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 476 } 477 478 /* complete root HUB interrupt endpoint */ 479 dwc_otg_root_intr(sc); 480 } 481 } 482 483 static void 484 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 485 { 486 if (!sc->sc_flags.status_suspend) { 487 /* update status bits */ 488 sc->sc_flags.status_suspend = 1; 489 sc->sc_flags.change_suspend = 1; 490 491 if (sc->sc_flags.status_device_mode) { 492 /* 493 * Disable suspend interrupt and enable resume 494 * interrupt: 495 */ 496 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 497 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 498 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 499 } 500 501 /* complete root HUB interrupt endpoint */ 502 dwc_otg_root_intr(sc); 503 } 504 } 505 506 static void 507 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 508 { 509 if (!sc->sc_flags.status_suspend) 510 return; 511 512 DPRINTFN(5, "Remote wakeup\n"); 513 514 if (sc->sc_flags.status_device_mode) { 515 uint32_t temp; 516 517 /* enable remote wakeup signalling */ 518 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 519 temp |= DCTL_RMTWKUPSIG; 520 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 521 522 /* Wait 8ms for remote wakeup to complete. */ 523 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 524 525 temp &= ~DCTL_RMTWKUPSIG; 526 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 527 } else { 528 /* enable USB port */ 529 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 530 531 /* wait 10ms */ 532 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 533 534 /* resume port */ 535 sc->sc_hprt_val |= HPRT_PRTRES; 536 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 537 538 /* Wait 100ms for resume signalling to complete. */ 539 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 540 541 /* clear suspend and resume */ 542 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 544 545 /* Wait 4ms */ 546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 547 } 548 549 /* need to fake resume IRQ */ 550 dwc_otg_resume_irq(sc); 551 } 552 553 static void 554 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 555 { 556 uint32_t temp; 557 558 DPRINTFN(5, "addr=%d\n", addr); 559 560 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 561 temp &= ~DCFG_DEVADDR_SET(0x7F); 562 temp |= DCFG_DEVADDR_SET(addr); 563 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 564 } 565 566 static void 567 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 568 { 569 DPRINTFN(5, "RX status clear\n"); 570 571 if (sc->sc_flags.status_device_mode != 0) { 572 /* enable RX FIFO level interrupt */ 573 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 574 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 575 } 576 577 /* clear cached status */ 578 sc->sc_last_rx_status = 0; 579 } 580 581 static void 582 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 583 { 584 uint32_t hcint; 585 586 /* clear all pending interrupts */ 587 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 588 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 589 590 /* clear buffered interrupts */ 591 sc->sc_chan_state[x].hcint = 0; 592 } 593 594 static uint8_t 595 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) 596 { 597 uint32_t tx_p_size; 598 uint32_t tx_np_size; 599 uint8_t x; 600 601 if (td->channel < DWC_OTG_MAX_CHANNELS) 602 return (0); /* already allocated */ 603 604 /* check if device is suspended */ 605 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 606 return (1); /* busy - cannot transfer data */ 607 608 /* compute needed TX FIFO size */ 609 if (is_out != 0) { 610 if (td->ep_type == UE_INTERRUPT || 611 td->ep_type == UE_ISOCHRONOUS) { 612 tx_p_size = td->max_packet_size; 613 tx_np_size = 0; 614 if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) 615 tx_p_size = HCSPLT_XACTLEN_BURST; 616 if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { 617 DPRINTF("Too little FIFO space\n"); 618 return (1); /* too little FIFO */ 619 } 620 } else { 621 tx_p_size = 0; 622 tx_np_size = td->max_packet_size; 623 if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) 624 tx_np_size = HCSPLT_XACTLEN_BURST; 625 if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { 626 DPRINTF("Too little FIFO space\n"); 627 return (1); /* too little FIFO */ 628 } 629 } 630 } else { 631 /* not a TX transaction */ 632 tx_p_size = 0; 633 tx_np_size = 0; 634 } 635 636 for (x = 0; x != sc->sc_host_ch_max; x++) { 637 if (sc->sc_chan_state[x].allocated != 0) 638 continue; 639 /* check if channel is still enabled */ 640 if (sc->sc_chan_state[x].wait_sof != 0) 641 continue; 642 643 sc->sc_chan_state[x].allocated = 1; 644 sc->sc_chan_state[x].tx_p_size = tx_p_size; 645 sc->sc_chan_state[x].tx_np_size = tx_np_size; 646 647 /* keep track of used TX FIFO, if any */ 648 sc->sc_tx_cur_p_level += tx_p_size; 649 sc->sc_tx_cur_np_level += tx_np_size; 650 651 /* clear interrupts */ 652 dwc_otg_clear_hcint(sc, x); 653 654 DPRINTF("CH=%d HCCHAR=0x%08x " 655 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 656 657 /* set active channel */ 658 sc->sc_active_rx_ep |= (1 << x); 659 660 /* set channel */ 661 td->channel = x; 662 663 return (0); /* allocated */ 664 } 665 /* wait a bit */ 666 dwc_otg_enable_sof_irq(sc); 667 return (1); /* busy */ 668 } 669 670 static void 671 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 672 { 673 uint8_t x; 674 675 if (td->channel >= DWC_OTG_MAX_CHANNELS) 676 return; /* already freed */ 677 678 /* free channel */ 679 x = td->channel; 680 td->channel = DWC_OTG_MAX_CHANNELS; 681 682 DPRINTF("CH=%d\n", x); 683 684 /* 685 * We need to let programmed host channels run till complete 686 * else the host channel will stop functioning. Assume that 687 * after a fixed given amount of time the host channel is no 688 * longer doing any USB traffic: 689 */ 690 if (td->ep_type == UE_ISOCHRONOUS || td->ep_type == UE_INTERRUPT) { 691 /* double buffered */ 692 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; 693 } else { 694 /* single buffered */ 695 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; 696 } 697 698 sc->sc_chan_state[x].allocated = 0; 699 700 /* ack any pending messages */ 701 if (sc->sc_last_rx_status != 0 && 702 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 703 dwc_otg_common_rx_ack(sc); 704 } 705 706 /* clear active channel */ 707 sc->sc_active_rx_ep &= ~(1 << x); 708 } 709 710 static void 711 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 712 { 713 /* dump any pending messages */ 714 if (sc->sc_last_rx_status != 0) { 715 if (td->channel < DWC_OTG_MAX_CHANNELS && 716 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 717 dwc_otg_common_rx_ack(sc); 718 } 719 } 720 } 721 722 static uint8_t 723 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 724 { 725 struct usb_device_request req __aligned(4); 726 uint32_t hcint; 727 uint32_t hcchar; 728 uint8_t delta; 729 730 dwc_otg_host_dump_rx(sc, td); 731 732 if (td->channel < DWC_OTG_MAX_CHANNELS) { 733 hcint = sc->sc_chan_state[td->channel].hcint; 734 735 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 736 td->channel, td->state, hcint, 737 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 738 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 739 } else { 740 hcint = 0; 741 goto check_state; 742 } 743 744 if (hcint & (HCINT_RETRY | 745 HCINT_ACK | HCINT_NYET)) { 746 /* give success bits priority over failure bits */ 747 } else if (hcint & HCINT_STALL) { 748 DPRINTF("CH=%d STALL\n", td->channel); 749 td->error_stall = 1; 750 td->error_any = 1; 751 goto complete; 752 } else if (hcint & HCINT_ERRORS) { 753 DPRINTF("CH=%d ERROR\n", td->channel); 754 td->errcnt++; 755 if (td->hcsplt != 0 || td->errcnt >= 3) { 756 td->error_any = 1; 757 goto complete; 758 } 759 } 760 761 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 762 HCINT_ACK | HCINT_NYET)) { 763 if (!(hcint & HCINT_ERRORS)) 764 td->errcnt = 0; 765 } 766 767 check_state: 768 switch (td->state) { 769 case DWC_CHAN_ST_START: 770 goto send_pkt; 771 772 case DWC_CHAN_ST_WAIT_ANE: 773 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 774 td->did_nak++; 775 td->tt_scheduled = 0; 776 goto send_pkt; 777 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 778 td->offset += td->tx_bytes; 779 td->remainder -= td->tx_bytes; 780 td->toggle = 1; 781 td->tt_scheduled = 0; 782 goto complete; 783 } 784 break; 785 786 case DWC_CHAN_ST_WAIT_S_ANE: 787 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 788 td->did_nak++; 789 td->tt_scheduled = 0; 790 goto send_pkt; 791 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 792 goto send_cpkt; 793 } 794 break; 795 796 case DWC_CHAN_ST_WAIT_C_ANE: 797 if (hcint & HCINT_NYET) { 798 goto send_cpkt; 799 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 800 td->did_nak++; 801 td->tt_scheduled = 0; 802 goto send_pkt; 803 } else if (hcint & HCINT_ACK) { 804 td->offset += td->tx_bytes; 805 td->remainder -= td->tx_bytes; 806 td->toggle = 1; 807 goto complete; 808 } 809 break; 810 811 case DWC_CHAN_ST_WAIT_C_PKT: 812 goto send_cpkt; 813 814 default: 815 break; 816 } 817 goto busy; 818 819 send_pkt: 820 /* free existing channel, if any */ 821 dwc_otg_host_channel_free(sc, td); 822 823 if (sizeof(req) != td->remainder) { 824 td->error_any = 1; 825 goto complete; 826 } 827 828 if (td->hcsplt != 0) { 829 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 830 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 831 td->state = DWC_CHAN_ST_START; 832 goto busy; 833 } 834 delta = sc->sc_last_frame_num - td->tt_start_slot; 835 if (delta > 5) { 836 /* missed it */ 837 td->tt_scheduled = 0; 838 td->state = DWC_CHAN_ST_START; 839 goto busy; 840 } 841 } 842 843 /* allocate a new channel */ 844 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 845 td->state = DWC_CHAN_ST_START; 846 goto busy; 847 } 848 849 if (td->hcsplt != 0) { 850 td->hcsplt &= ~HCSPLT_COMPSPLT; 851 td->state = DWC_CHAN_ST_WAIT_S_ANE; 852 } else { 853 td->state = DWC_CHAN_ST_WAIT_ANE; 854 } 855 856 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 857 858 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 859 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 860 (1 << HCTSIZ_PKTCNT_SHIFT) | 861 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 862 863 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 864 865 hcchar = td->hcchar; 866 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 867 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 868 869 /* must enable channel before writing data to FIFO */ 870 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 871 872 /* transfer data into FIFO */ 873 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 874 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 875 876 /* wait until next slot before trying complete split */ 877 if (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS) 878 td->tt_complete_slot = sc->sc_last_frame_num + 2; 879 else 880 td->tt_complete_slot = sc->sc_last_frame_num + 1; 881 882 /* store number of bytes transmitted */ 883 td->tx_bytes = sizeof(req); 884 goto busy; 885 886 send_cpkt: 887 /* free existing channel, if any */ 888 dwc_otg_host_channel_free(sc, td); 889 890 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 891 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 892 td->state = DWC_CHAN_ST_WAIT_C_PKT; 893 goto busy; 894 } 895 delta = sc->sc_last_frame_num - td->tt_start_slot; 896 if (delta > DWC_OTG_TT_SLOT_MAX) { 897 /* we missed the service interval */ 898 if (td->ep_type != UE_ISOCHRONOUS) 899 td->error_any = 1; 900 goto complete; 901 } 902 /* allocate a new channel */ 903 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 904 td->state = DWC_CHAN_ST_WAIT_C_PKT; 905 goto busy; 906 } 907 908 /* wait until next slot before trying complete split */ 909 td->tt_complete_slot = sc->sc_last_frame_num + 1; 910 911 td->hcsplt |= HCSPLT_COMPSPLT; 912 td->state = DWC_CHAN_ST_WAIT_C_ANE; 913 914 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 915 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 916 917 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 918 919 hcchar = td->hcchar; 920 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 921 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 922 923 /* must enable channel before writing data to FIFO */ 924 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 925 926 busy: 927 return (1); /* busy */ 928 929 complete: 930 dwc_otg_host_channel_free(sc, td); 931 return (0); /* complete */ 932 } 933 934 static uint8_t 935 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 936 { 937 struct usb_device_request req __aligned(4); 938 uint32_t temp; 939 uint16_t count; 940 941 /* check endpoint status */ 942 943 if (sc->sc_last_rx_status == 0) 944 goto not_complete; 945 946 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 947 goto not_complete; 948 949 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 950 GRXSTSRD_DPID_DATA0) { 951 /* release FIFO */ 952 dwc_otg_common_rx_ack(sc); 953 goto not_complete; 954 } 955 956 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 957 GRXSTSRD_STP_DATA) { 958 /* release FIFO */ 959 dwc_otg_common_rx_ack(sc); 960 goto not_complete; 961 } 962 963 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 964 965 /* clear did stall */ 966 td->did_stall = 0; 967 968 /* get the packet byte count */ 969 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 970 971 /* verify data length */ 972 if (count != td->remainder) { 973 DPRINTFN(0, "Invalid SETUP packet " 974 "length, %d bytes\n", count); 975 /* release FIFO */ 976 dwc_otg_common_rx_ack(sc); 977 goto not_complete; 978 } 979 if (count != sizeof(req)) { 980 DPRINTFN(0, "Unsupported SETUP packet " 981 "length, %d bytes\n", count); 982 /* release FIFO */ 983 dwc_otg_common_rx_ack(sc); 984 goto not_complete; 985 } 986 987 /* copy in control request */ 988 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 989 990 /* copy data into real buffer */ 991 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 992 993 td->offset = sizeof(req); 994 td->remainder = 0; 995 996 /* sneak peek the set address */ 997 if ((req.bmRequestType == UT_WRITE_DEVICE) && 998 (req.bRequest == UR_SET_ADDRESS)) { 999 /* must write address before ZLP */ 1000 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1001 } 1002 1003 /* don't send any data by default */ 1004 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 1005 DXEPTSIZ_SET_NPKT(0) | 1006 DXEPTSIZ_SET_NBYTES(0)); 1007 1008 temp = sc->sc_in_ctl[0]; 1009 1010 /* enable IN endpoint */ 1011 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1012 temp | DIEPCTL_EPENA); 1013 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1014 temp | DIEPCTL_SNAK); 1015 1016 /* reset IN endpoint buffer */ 1017 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1018 GRSTCTL_TXFIFO(0) | 1019 GRSTCTL_TXFFLSH); 1020 1021 /* acknowledge RX status */ 1022 dwc_otg_common_rx_ack(sc); 1023 return (0); /* complete */ 1024 1025 not_complete: 1026 /* abort any ongoing transfer, before enabling again */ 1027 1028 temp = sc->sc_out_ctl[0]; 1029 1030 temp |= DOEPCTL_EPENA | 1031 DOEPCTL_SNAK; 1032 1033 /* enable OUT endpoint */ 1034 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1035 1036 if (!td->did_stall) { 1037 td->did_stall = 1; 1038 1039 DPRINTFN(5, "stalling IN and OUT direction\n"); 1040 1041 /* set stall after enabling endpoint */ 1042 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1043 temp | DOEPCTL_STALL); 1044 1045 temp = sc->sc_in_ctl[0]; 1046 1047 /* set stall assuming endpoint is enabled */ 1048 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1049 temp | DIEPCTL_STALL); 1050 } 1051 1052 /* setup number of buffers to receive */ 1053 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1054 DXEPTSIZ_SET_MULTI(3) | 1055 DXEPTSIZ_SET_NPKT(1) | 1056 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1057 1058 return (1); /* not complete */ 1059 } 1060 1061 static uint8_t 1062 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1063 { 1064 uint8_t delta; 1065 1066 delta = sc->sc_tmr_val - td->tmr_val; 1067 if (delta >= 128) 1068 return (1); /* busy */ 1069 1070 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1071 1072 /* set toggle, if any */ 1073 if (td->set_toggle) { 1074 td->set_toggle = 0; 1075 td->toggle = 1; 1076 } 1077 return (0); 1078 } 1079 1080 static uint8_t 1081 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1082 { 1083 if (td->ep_type == UE_ISOCHRONOUS) { 1084 /* non TT isochronous traffic */ 1085 if ((td->tmr_val != 0) || 1086 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1087 goto busy; 1088 } 1089 td->tmr_val = 1; /* executed */ 1090 td->toggle = 0; 1091 1092 } else if (td->ep_type == UE_INTERRUPT) { 1093 if (!td->tt_scheduled) 1094 goto busy; 1095 td->tt_scheduled = 0; 1096 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1097 goto busy; 1098 } else if (td->set_toggle) { 1099 td->set_toggle = 0; 1100 td->toggle = 1; 1101 } 1102 return (0); 1103 busy: 1104 return (1); 1105 } 1106 1107 static uint8_t 1108 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1109 { 1110 uint32_t count; 1111 uint8_t channel; 1112 1113 /* check endpoint status */ 1114 if (sc->sc_last_rx_status == 0) 1115 goto busy; 1116 1117 channel = td->channel; 1118 if (channel >= DWC_OTG_MAX_CHANNELS) 1119 goto busy; 1120 1121 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1122 goto busy; 1123 1124 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1125 case GRXSTSRH_IN_DATA: 1126 1127 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1128 (int)td->state, (int)sc->sc_last_rx_status); 1129 1130 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1131 /* 1132 * When using SPLIT transactions on interrupt 1133 * endpoints, sometimes data occurs twice. 1134 */ 1135 DPRINTF("Data already received\n"); 1136 break; 1137 } 1138 1139 /* get the packet byte count */ 1140 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1141 1142 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1143 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1144 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1145 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1146 } else { 1147 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1148 1149 /* verify the packet byte count */ 1150 if (count < td->max_packet_size) { 1151 /* we have a short packet */ 1152 td->short_pkt = 1; 1153 td->got_short = 1; 1154 } 1155 } 1156 td->toggle = 0; 1157 } else { 1158 /* verify the packet byte count */ 1159 if (count != td->max_packet_size) { 1160 if (count < td->max_packet_size) { 1161 /* we have a short packet */ 1162 td->short_pkt = 1; 1163 td->got_short = 1; 1164 } else { 1165 /* invalid USB packet */ 1166 td->error_any = 1; 1167 1168 /* release FIFO */ 1169 dwc_otg_common_rx_ack(sc); 1170 goto complete; 1171 } 1172 } 1173 td->toggle ^= 1; 1174 td->tt_scheduled = 0; 1175 } 1176 1177 /* verify the packet byte count */ 1178 if (count > td->remainder) { 1179 /* invalid USB packet */ 1180 td->error_any = 1; 1181 1182 /* release FIFO */ 1183 dwc_otg_common_rx_ack(sc); 1184 goto complete; 1185 } 1186 1187 usbd_copy_in(td->pc, td->offset, 1188 sc->sc_rx_bounce_buffer, count); 1189 1190 td->remainder -= count; 1191 td->offset += count; 1192 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1193 break; 1194 default: 1195 break; 1196 } 1197 /* release FIFO */ 1198 dwc_otg_common_rx_ack(sc); 1199 busy: 1200 return (0); 1201 complete: 1202 return (1); 1203 } 1204 1205 static uint8_t 1206 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1207 { 1208 uint32_t hcint; 1209 uint32_t hcchar; 1210 uint8_t delta; 1211 uint8_t channel; 1212 1213 channel = td->channel; 1214 1215 if (channel < DWC_OTG_MAX_CHANNELS) { 1216 hcint = sc->sc_chan_state[channel].hcint; 1217 1218 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1219 channel, td->state, hcint, 1220 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1221 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1222 1223 /* check interrupt bits */ 1224 if (hcint & (HCINT_RETRY | 1225 HCINT_ACK | HCINT_NYET)) { 1226 /* give success bits priority over failure bits */ 1227 } else if (hcint & HCINT_STALL) { 1228 DPRINTF("CH=%d STALL\n", channel); 1229 td->error_stall = 1; 1230 td->error_any = 1; 1231 goto complete; 1232 } else if (hcint & HCINT_ERRORS) { 1233 DPRINTF("CH=%d ERROR\n", channel); 1234 td->errcnt++; 1235 if (td->hcsplt != 0 || td->errcnt >= 3) { 1236 if (td->ep_type != UE_ISOCHRONOUS) { 1237 td->error_any = 1; 1238 goto complete; 1239 } 1240 } 1241 } 1242 1243 /* check channels for data, if any */ 1244 if (dwc_otg_host_data_rx_sub(sc, td)) 1245 goto complete; 1246 1247 /* refresh interrupt status */ 1248 hcint = sc->sc_chan_state[channel].hcint; 1249 1250 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1251 HCINT_ACK | HCINT_NYET)) { 1252 if (!(hcint & HCINT_ERRORS)) 1253 td->errcnt = 0; 1254 } 1255 } else { 1256 hcint = 0; 1257 } 1258 1259 switch (td->state) { 1260 case DWC_CHAN_ST_START: 1261 if (td->hcsplt != 0) 1262 goto receive_spkt; 1263 else 1264 goto receive_pkt; 1265 1266 case DWC_CHAN_ST_WAIT_ANE: 1267 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1268 td->did_nak++; 1269 td->tt_scheduled = 0; 1270 if (td->hcsplt != 0) 1271 goto receive_spkt; 1272 else 1273 goto receive_pkt; 1274 } else if (hcint & HCINT_NYET) { 1275 if (td->hcsplt != 0) { 1276 /* try again */ 1277 goto receive_pkt; 1278 } else { 1279 /* not a valid token for IN endpoints */ 1280 td->error_any = 1; 1281 goto complete; 1282 } 1283 } else if (hcint & HCINT_ACK) { 1284 /* wait for data - ACK arrived first */ 1285 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1286 goto busy; 1287 1288 if (td->ep_type == UE_ISOCHRONOUS) { 1289 /* check if we are complete */ 1290 if ((td->remainder == 0) || 1291 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1292 goto complete; 1293 } 1294 /* get another packet */ 1295 goto receive_pkt; 1296 } else { 1297 /* check if we are complete */ 1298 if ((td->remainder == 0) || (td->got_short != 0)) { 1299 if (td->short_pkt) 1300 goto complete; 1301 1302 /* 1303 * Else need to receive a zero length 1304 * packet. 1305 */ 1306 } 1307 td->tt_scheduled = 0; 1308 td->did_nak = 0; 1309 if (td->hcsplt != 0) 1310 goto receive_spkt; 1311 else 1312 goto receive_pkt; 1313 } 1314 } 1315 break; 1316 1317 case DWC_CHAN_ST_WAIT_S_ANE: 1318 /* 1319 * NOTE: The DWC OTG hardware provides a fake ACK in 1320 * case of interrupt and isochronous transfers: 1321 */ 1322 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1323 td->did_nak++; 1324 td->tt_scheduled = 0; 1325 goto receive_spkt; 1326 } else if (hcint & HCINT_NYET) { 1327 td->tt_scheduled = 0; 1328 goto receive_spkt; 1329 } else if (hcint & HCINT_ACK) { 1330 td->did_nak = 0; 1331 goto receive_pkt; 1332 } 1333 break; 1334 1335 case DWC_CHAN_ST_WAIT_C_PKT: 1336 goto receive_pkt; 1337 1338 default: 1339 break; 1340 } 1341 goto busy; 1342 1343 receive_pkt: 1344 /* free existing channel, if any */ 1345 dwc_otg_host_channel_free(sc, td); 1346 1347 if (td->hcsplt != 0) { 1348 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1349 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1350 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1351 goto busy; 1352 } 1353 delta = sc->sc_last_frame_num - td->tt_start_slot; 1354 if (delta > DWC_OTG_TT_SLOT_MAX) { 1355 if (td->ep_type == UE_INTERRUPT) { 1356 /* 1357 * Happens from time to time avoid 1358 * posting an error, instead retry 1359 * the start split packet: 1360 */ 1361 td->tt_scheduled = 0; 1362 goto receive_spkt; 1363 } else if (td->ep_type != UE_ISOCHRONOUS) { 1364 /* we missed the service interval */ 1365 td->error_any = 1; 1366 } 1367 goto complete; 1368 } 1369 /* complete split */ 1370 td->hcsplt |= HCSPLT_COMPSPLT; 1371 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1372 dwc_otg_host_rate_check(sc, td)) { 1373 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1374 goto busy; 1375 } 1376 1377 /* allocate a new channel */ 1378 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1379 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1380 goto busy; 1381 } 1382 1383 channel = td->channel; 1384 1385 /* set toggle, if any */ 1386 if (td->set_toggle) { 1387 td->set_toggle = 0; 1388 td->toggle = 1; 1389 } 1390 1391 td->state = DWC_CHAN_ST_WAIT_ANE; 1392 1393 /* receive one packet */ 1394 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1395 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1396 (1 << HCTSIZ_PKTCNT_SHIFT) | 1397 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1398 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1399 1400 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1401 1402 hcchar = td->hcchar; 1403 hcchar |= HCCHAR_EPDIR_IN; 1404 1405 /* receive complete split ASAP */ 1406 if ((sc->sc_last_frame_num & 1) != 0) 1407 hcchar |= HCCHAR_ODDFRM; 1408 else 1409 hcchar &= ~HCCHAR_ODDFRM; 1410 1411 /* must enable channel before data can be received */ 1412 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1413 1414 /* wait until next slot before trying complete split */ 1415 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1416 1417 goto busy; 1418 1419 receive_spkt: 1420 /* free existing channel(s), if any */ 1421 dwc_otg_host_channel_free(sc, td); 1422 1423 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1424 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1425 td->state = DWC_CHAN_ST_START; 1426 goto busy; 1427 } 1428 delta = sc->sc_last_frame_num - td->tt_start_slot; 1429 if (delta > 5) { 1430 /* missed it */ 1431 td->tt_scheduled = 0; 1432 td->state = DWC_CHAN_ST_START; 1433 goto busy; 1434 } 1435 1436 /* allocate a new channel */ 1437 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1438 td->state = DWC_CHAN_ST_START; 1439 goto busy; 1440 } 1441 1442 channel = td->channel; 1443 1444 td->hcsplt &= ~HCSPLT_COMPSPLT; 1445 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1446 1447 /* receive one packet */ 1448 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1449 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1450 1451 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1452 1453 /* send after next SOF event */ 1454 if ((sc->sc_last_frame_num & 1) == 0) 1455 td->hcchar |= HCCHAR_ODDFRM; 1456 else 1457 td->hcchar &= ~HCCHAR_ODDFRM; 1458 1459 hcchar = td->hcchar; 1460 hcchar |= HCCHAR_EPDIR_IN; 1461 1462 /* wait until next slot before trying complete split */ 1463 if (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS) 1464 td->tt_complete_slot = sc->sc_last_frame_num + 2; 1465 else 1466 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1467 1468 /* must enable channel before data can be received */ 1469 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1470 busy: 1471 return (1); /* busy */ 1472 1473 complete: 1474 dwc_otg_host_channel_free(sc, td); 1475 return (0); /* complete */ 1476 } 1477 1478 static uint8_t 1479 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1480 { 1481 uint32_t temp; 1482 uint16_t count; 1483 uint8_t got_short; 1484 1485 got_short = 0; 1486 1487 /* check endpoint status */ 1488 if (sc->sc_last_rx_status == 0) 1489 goto not_complete; 1490 1491 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1492 goto not_complete; 1493 1494 /* check for SETUP packet */ 1495 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1496 GRXSTSRD_STP_DATA) { 1497 if (td->remainder == 0) { 1498 /* 1499 * We are actually complete and have 1500 * received the next SETUP 1501 */ 1502 DPRINTFN(5, "faking complete\n"); 1503 return (0); /* complete */ 1504 } 1505 /* 1506 * USB Host Aborted the transfer. 1507 */ 1508 td->error_any = 1; 1509 return (0); /* complete */ 1510 } 1511 1512 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1513 GRXSTSRD_OUT_DATA) { 1514 /* release FIFO */ 1515 dwc_otg_common_rx_ack(sc); 1516 goto not_complete; 1517 } 1518 1519 /* get the packet byte count */ 1520 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1521 1522 /* verify the packet byte count */ 1523 if (count != td->max_packet_size) { 1524 if (count < td->max_packet_size) { 1525 /* we have a short packet */ 1526 td->short_pkt = 1; 1527 got_short = 1; 1528 } else { 1529 /* invalid USB packet */ 1530 td->error_any = 1; 1531 1532 /* release FIFO */ 1533 dwc_otg_common_rx_ack(sc); 1534 return (0); /* we are complete */ 1535 } 1536 } 1537 /* verify the packet byte count */ 1538 if (count > td->remainder) { 1539 /* invalid USB packet */ 1540 td->error_any = 1; 1541 1542 /* release FIFO */ 1543 dwc_otg_common_rx_ack(sc); 1544 return (0); /* we are complete */ 1545 } 1546 1547 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1548 td->remainder -= count; 1549 td->offset += count; 1550 1551 /* release FIFO */ 1552 dwc_otg_common_rx_ack(sc); 1553 1554 /* check if we are complete */ 1555 if ((td->remainder == 0) || got_short) { 1556 if (td->short_pkt) { 1557 /* we are complete */ 1558 return (0); 1559 } 1560 /* else need to receive a zero length packet */ 1561 } 1562 1563 not_complete: 1564 1565 temp = sc->sc_out_ctl[td->ep_no]; 1566 1567 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1568 1569 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1570 1571 /* enable SETUP and transfer complete interrupt */ 1572 if (td->ep_no == 0) { 1573 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1574 DXEPTSIZ_SET_NPKT(1) | 1575 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1576 } else { 1577 /* allow reception of multiple packets */ 1578 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1579 DXEPTSIZ_SET_MULTI(1) | 1580 DXEPTSIZ_SET_NPKT(4) | 1581 DXEPTSIZ_SET_NBYTES(4 * 1582 ((td->max_packet_size + 3) & ~3))); 1583 } 1584 return (1); /* not complete */ 1585 } 1586 1587 static uint8_t 1588 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1589 { 1590 uint32_t count; 1591 uint32_t hcint; 1592 uint32_t hcchar; 1593 uint8_t delta; 1594 uint8_t channel; 1595 1596 dwc_otg_host_dump_rx(sc, td); 1597 1598 channel = td->channel; 1599 1600 if (channel < DWC_OTG_MAX_CHANNELS) { 1601 hcint = sc->sc_chan_state[channel].hcint; 1602 1603 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1604 channel, td->state, hcint, 1605 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1606 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1607 1608 if (hcint & (HCINT_RETRY | 1609 HCINT_ACK | HCINT_NYET)) { 1610 /* give success bits priority over failure bits */ 1611 } else if (hcint & HCINT_STALL) { 1612 DPRINTF("CH=%d STALL\n", channel); 1613 td->error_stall = 1; 1614 td->error_any = 1; 1615 goto complete; 1616 } else if (hcint & HCINT_ERRORS) { 1617 DPRINTF("CH=%d ERROR\n", channel); 1618 td->errcnt++; 1619 if (td->hcsplt != 0 || td->errcnt >= 3) { 1620 td->error_any = 1; 1621 goto complete; 1622 } 1623 } 1624 1625 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1626 HCINT_ACK | HCINT_NYET)) { 1627 1628 if (!(hcint & HCINT_ERRORS)) 1629 td->errcnt = 0; 1630 } 1631 } else { 1632 hcint = 0; 1633 } 1634 1635 switch (td->state) { 1636 case DWC_CHAN_ST_START: 1637 goto send_pkt; 1638 1639 case DWC_CHAN_ST_WAIT_ANE: 1640 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1641 td->did_nak++; 1642 td->tt_scheduled = 0; 1643 goto send_pkt; 1644 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1645 td->offset += td->tx_bytes; 1646 td->remainder -= td->tx_bytes; 1647 td->toggle ^= 1; 1648 td->did_nak = 0; 1649 td->tt_scheduled = 0; 1650 1651 /* check remainder */ 1652 if (td->remainder == 0) { 1653 if (td->short_pkt) 1654 goto complete; 1655 1656 /* 1657 * Else we need to transmit a short 1658 * packet: 1659 */ 1660 } 1661 goto send_pkt; 1662 } 1663 break; 1664 1665 case DWC_CHAN_ST_WAIT_S_ANE: 1666 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1667 td->did_nak++; 1668 td->tt_scheduled = 0; 1669 goto send_pkt; 1670 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1671 td->did_nak = 0; 1672 goto send_cpkt; 1673 } 1674 break; 1675 1676 case DWC_CHAN_ST_WAIT_C_ANE: 1677 if (hcint & HCINT_NYET) { 1678 goto send_cpkt; 1679 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1680 td->did_nak++; 1681 td->tt_scheduled = 0; 1682 goto send_pkt; 1683 } else if (hcint & HCINT_ACK) { 1684 td->offset += td->tx_bytes; 1685 td->remainder -= td->tx_bytes; 1686 td->toggle ^= 1; 1687 td->did_nak = 0; 1688 td->tt_scheduled = 0; 1689 1690 /* check remainder */ 1691 if (td->remainder == 0) { 1692 if (td->short_pkt) 1693 goto complete; 1694 1695 /* else we need to transmit a short packet */ 1696 } 1697 goto send_pkt; 1698 } 1699 break; 1700 1701 case DWC_CHAN_ST_WAIT_C_PKT: 1702 goto send_cpkt; 1703 1704 case DWC_CHAN_ST_TX_WAIT_ISOC: 1705 1706 /* Check if isochronous OUT traffic is complete */ 1707 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1708 break; 1709 1710 td->offset += td->tx_bytes; 1711 td->remainder -= td->tx_bytes; 1712 1713 if (td->hcsplt != 0 || td->remainder == 0) 1714 goto complete; 1715 1716 /* check for next packet */ 1717 if (td->max_packet_count > 1) 1718 td->tt_xactpos++; 1719 1720 /* free existing channel, if any */ 1721 dwc_otg_host_channel_free(sc, td); 1722 1723 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1724 1725 /* FALLTHROUGH */ 1726 1727 case DWC_CHAN_ST_TX_PKT_ISOC: 1728 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1729 break; 1730 channel = td->channel; 1731 goto send_isoc_pkt; 1732 default: 1733 break; 1734 } 1735 goto busy; 1736 1737 send_pkt: 1738 /* free existing channel(s), if any */ 1739 dwc_otg_host_channel_free(sc, td); 1740 1741 if (td->hcsplt != 0) { 1742 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1743 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1744 td->state = DWC_CHAN_ST_START; 1745 goto busy; 1746 } 1747 delta = sc->sc_last_frame_num - td->tt_start_slot; 1748 if (delta > 5) { 1749 /* missed it */ 1750 td->tt_scheduled = 0; 1751 td->state = DWC_CHAN_ST_START; 1752 goto busy; 1753 } 1754 } else if (dwc_otg_host_rate_check(sc, td)) { 1755 td->state = DWC_CHAN_ST_START; 1756 goto busy; 1757 } 1758 1759 /* allocate a new channel */ 1760 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1761 td->state = DWC_CHAN_ST_START; 1762 goto busy; 1763 } 1764 1765 channel = td->channel; 1766 1767 /* set toggle, if any */ 1768 if (td->set_toggle) { 1769 td->set_toggle = 0; 1770 td->toggle = 1; 1771 } 1772 1773 if (td->ep_type == UE_ISOCHRONOUS) { 1774 send_isoc_pkt: 1775 /* Isochronous OUT transfers don't have any ACKs */ 1776 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1777 td->hcsplt &= ~HCSPLT_COMPSPLT; 1778 if (td->hcsplt != 0) { 1779 /* get maximum transfer length */ 1780 count = td->remainder; 1781 if (count > HCSPLT_XACTLEN_BURST) { 1782 DPRINTF("TT overflow\n"); 1783 td->error_any = 1; 1784 goto complete; 1785 } 1786 /* Update transaction position */ 1787 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1788 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1789 } else { 1790 /* send one packet at a time */ 1791 count = td->max_packet_size; 1792 if (td->remainder < count) { 1793 /* we have a short packet */ 1794 td->short_pkt = 1; 1795 count = td->remainder; 1796 } 1797 } 1798 } else if (td->hcsplt != 0) { 1799 1800 td->hcsplt &= ~HCSPLT_COMPSPLT; 1801 1802 /* Wait for ACK/NAK/ERR from TT */ 1803 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1804 1805 /* send one packet at a time */ 1806 count = td->max_packet_size; 1807 if (td->remainder < count) { 1808 /* we have a short packet */ 1809 td->short_pkt = 1; 1810 count = td->remainder; 1811 } 1812 } else { 1813 /* Wait for ACK/NAK/STALL from device */ 1814 td->state = DWC_CHAN_ST_WAIT_ANE; 1815 1816 /* send one packet at a time */ 1817 count = td->max_packet_size; 1818 if (td->remainder < count) { 1819 /* we have a short packet */ 1820 td->short_pkt = 1; 1821 count = td->remainder; 1822 } 1823 } 1824 1825 /* check for High-Speed multi-packets */ 1826 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1827 if (td->npkt == 0) { 1828 if (td->remainder >= (3 * td->max_packet_size)) 1829 td->npkt = 3; 1830 else if (td->remainder >= (2 * td->max_packet_size)) 1831 td->npkt = 2; 1832 else 1833 td->npkt = 1; 1834 1835 if (td->npkt > td->max_packet_count) 1836 td->npkt = td->max_packet_count; 1837 1838 td->tt_xactpos = 1; /* overload */ 1839 } 1840 if (td->tt_xactpos == td->npkt) { 1841 if (td->npkt == 1) { 1842 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1843 (count << HCTSIZ_XFERSIZE_SHIFT) | 1844 (1 << HCTSIZ_PKTCNT_SHIFT) | 1845 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1846 } else if (td->npkt == 2) { 1847 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1848 (count << HCTSIZ_XFERSIZE_SHIFT) | 1849 (1 << HCTSIZ_PKTCNT_SHIFT) | 1850 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1851 } else { 1852 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1853 (count << HCTSIZ_XFERSIZE_SHIFT) | 1854 (1 << HCTSIZ_PKTCNT_SHIFT) | 1855 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1856 } 1857 td->npkt = 0; 1858 } else { 1859 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1860 (count << HCTSIZ_XFERSIZE_SHIFT) | 1861 (1 << HCTSIZ_PKTCNT_SHIFT) | 1862 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1863 } 1864 } else { 1865 /* TODO: HCTSIZ_DOPNG */ 1866 1867 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1868 (count << HCTSIZ_XFERSIZE_SHIFT) | 1869 (1 << HCTSIZ_PKTCNT_SHIFT) | 1870 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1871 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1872 } 1873 1874 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1875 1876 hcchar = td->hcchar; 1877 hcchar &= ~HCCHAR_EPDIR_IN; 1878 1879 /* send after next SOF event */ 1880 if ((sc->sc_last_frame_num & 1) == 0) 1881 hcchar |= HCCHAR_ODDFRM; 1882 else 1883 hcchar &= ~HCCHAR_ODDFRM; 1884 1885 /* must enable before writing data to FIFO */ 1886 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1887 1888 if (count != 0) { 1889 1890 /* clear topmost word before copy */ 1891 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1892 1893 /* copy out data */ 1894 usbd_copy_out(td->pc, td->offset, 1895 sc->sc_tx_bounce_buffer, count); 1896 1897 /* transfer data into FIFO */ 1898 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1899 DOTG_DFIFO(channel), 1900 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1901 } 1902 1903 /* store number of bytes transmitted */ 1904 td->tx_bytes = count; 1905 goto busy; 1906 1907 send_cpkt: 1908 /* free existing channel, if any */ 1909 dwc_otg_host_channel_free(sc, td); 1910 1911 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1912 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1913 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1914 goto busy; 1915 } 1916 delta = sc->sc_last_frame_num - td->tt_start_slot; 1917 if (delta > DWC_OTG_TT_SLOT_MAX) { 1918 /* we missed the service interval */ 1919 if (td->ep_type != UE_ISOCHRONOUS) 1920 td->error_any = 1; 1921 goto complete; 1922 } 1923 1924 /* allocate a new channel */ 1925 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1926 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1927 goto busy; 1928 } 1929 1930 channel = td->channel; 1931 1932 td->hcsplt |= HCSPLT_COMPSPLT; 1933 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1934 1935 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1936 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1937 1938 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1939 1940 hcchar = td->hcchar; 1941 hcchar &= ~HCCHAR_EPDIR_IN; 1942 1943 /* receive complete split ASAP */ 1944 if ((sc->sc_last_frame_num & 1) != 0) 1945 hcchar |= HCCHAR_ODDFRM; 1946 else 1947 hcchar &= ~HCCHAR_ODDFRM; 1948 1949 /* must enable channel before data can be received */ 1950 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1951 1952 /* wait until next slot before trying complete split */ 1953 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1954 busy: 1955 return (1); /* busy */ 1956 1957 complete: 1958 dwc_otg_host_channel_free(sc, td); 1959 return (0); /* complete */ 1960 } 1961 1962 static uint8_t 1963 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1964 { 1965 uint32_t max_buffer; 1966 uint32_t count; 1967 uint32_t fifo_left; 1968 uint32_t mpkt; 1969 uint32_t temp; 1970 uint8_t to; 1971 1972 to = 3; /* don't loop forever! */ 1973 1974 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1975 1976 repeat: 1977 /* check for for endpoint 0 data */ 1978 1979 temp = sc->sc_last_rx_status; 1980 1981 if ((td->ep_no == 0) && (temp != 0) && 1982 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 1983 1984 if ((temp & GRXSTSRD_PKTSTS_MASK) != 1985 GRXSTSRD_STP_DATA) { 1986 1987 /* dump data - wrong direction */ 1988 dwc_otg_common_rx_ack(sc); 1989 } else { 1990 /* 1991 * The current transfer was cancelled 1992 * by the USB Host: 1993 */ 1994 td->error_any = 1; 1995 return (0); /* complete */ 1996 } 1997 } 1998 1999 /* fill in more TX data, if possible */ 2000 if (td->tx_bytes != 0) { 2001 2002 uint16_t cpkt; 2003 2004 /* check if packets have been transferred */ 2005 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2006 2007 /* get current packet number */ 2008 cpkt = DXEPTSIZ_GET_NPKT(temp); 2009 2010 if (cpkt >= td->npkt) { 2011 fifo_left = 0; 2012 } else { 2013 if (max_buffer != 0) { 2014 fifo_left = (td->npkt - cpkt) * 2015 td->max_packet_size; 2016 2017 if (fifo_left > max_buffer) 2018 fifo_left = max_buffer; 2019 } else { 2020 fifo_left = td->max_packet_size; 2021 } 2022 } 2023 2024 count = td->tx_bytes; 2025 if (count > fifo_left) 2026 count = fifo_left; 2027 2028 if (count != 0) { 2029 2030 /* clear topmost word before copy */ 2031 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2032 2033 /* copy out data */ 2034 usbd_copy_out(td->pc, td->offset, 2035 sc->sc_tx_bounce_buffer, count); 2036 2037 /* transfer data into FIFO */ 2038 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2039 DOTG_DFIFO(td->ep_no), 2040 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2041 2042 td->tx_bytes -= count; 2043 td->remainder -= count; 2044 td->offset += count; 2045 td->npkt = cpkt; 2046 } 2047 if (td->tx_bytes != 0) 2048 goto not_complete; 2049 2050 /* check remainder */ 2051 if (td->remainder == 0) { 2052 if (td->short_pkt) 2053 return (0); /* complete */ 2054 2055 /* else we need to transmit a short packet */ 2056 } 2057 } 2058 2059 if (!to--) 2060 goto not_complete; 2061 2062 /* check if not all packets have been transferred */ 2063 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2064 2065 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2066 2067 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2068 "DIEPCTL=0x%08x\n", td->ep_no, 2069 DXEPTSIZ_GET_NPKT(temp), 2070 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2071 2072 goto not_complete; 2073 } 2074 2075 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2076 2077 /* try to optimise by sending more data */ 2078 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2079 2080 /* send multiple packets at the same time */ 2081 mpkt = max_buffer / td->max_packet_size; 2082 2083 if (mpkt > 0x3FE) 2084 mpkt = 0x3FE; 2085 2086 count = td->remainder; 2087 if (count > 0x7FFFFF) 2088 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2089 2090 td->npkt = count / td->max_packet_size; 2091 2092 /* 2093 * NOTE: We could use 0x3FE instead of "mpkt" in the 2094 * check below to get more throughput, but then we 2095 * have a dependency towards non-generic chip features 2096 * to disable the TX-FIFO-EMPTY interrupts on a per 2097 * endpoint basis. Increase the maximum buffer size of 2098 * the IN endpoint to increase the performance. 2099 */ 2100 if (td->npkt > mpkt) { 2101 td->npkt = mpkt; 2102 count = td->max_packet_size * mpkt; 2103 } else if ((count == 0) || (count % td->max_packet_size)) { 2104 /* we are transmitting a short packet */ 2105 td->npkt++; 2106 td->short_pkt = 1; 2107 } 2108 } else { 2109 /* send one packet at a time */ 2110 mpkt = 1; 2111 count = td->max_packet_size; 2112 if (td->remainder < count) { 2113 /* we have a short packet */ 2114 td->short_pkt = 1; 2115 count = td->remainder; 2116 } 2117 td->npkt = 1; 2118 } 2119 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2120 DXEPTSIZ_SET_MULTI(1) | 2121 DXEPTSIZ_SET_NPKT(td->npkt) | 2122 DXEPTSIZ_SET_NBYTES(count)); 2123 2124 /* make room for buffering */ 2125 td->npkt += mpkt; 2126 2127 temp = sc->sc_in_ctl[td->ep_no]; 2128 2129 /* must enable before writing data to FIFO */ 2130 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2131 DIEPCTL_EPENA | 2132 DIEPCTL_CNAK); 2133 2134 td->tx_bytes = count; 2135 2136 /* check remainder */ 2137 if (td->tx_bytes == 0 && 2138 td->remainder == 0) { 2139 if (td->short_pkt) 2140 return (0); /* complete */ 2141 2142 /* else we need to transmit a short packet */ 2143 } 2144 goto repeat; 2145 2146 not_complete: 2147 return (1); /* not complete */ 2148 } 2149 2150 static uint8_t 2151 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2152 { 2153 uint32_t temp; 2154 2155 /* 2156 * If all packets are transferred we are complete: 2157 */ 2158 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2159 2160 /* check that all packets have been transferred */ 2161 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2162 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2163 goto not_complete; 2164 } 2165 return (0); 2166 2167 not_complete: 2168 2169 /* we only want to know if there is a SETUP packet or free IN packet */ 2170 2171 temp = sc->sc_last_rx_status; 2172 2173 if ((td->ep_no == 0) && (temp != 0) && 2174 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2175 2176 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2177 GRXSTSRD_STP_DATA) { 2178 DPRINTFN(5, "faking complete\n"); 2179 /* 2180 * Race condition: We are complete! 2181 */ 2182 return (0); 2183 } else { 2184 /* dump data - wrong direction */ 2185 dwc_otg_common_rx_ack(sc); 2186 } 2187 } 2188 return (1); /* not complete */ 2189 } 2190 2191 static void 2192 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2193 { 2194 struct dwc_otg_td *td; 2195 uint8_t toggle; 2196 uint8_t tmr_val; 2197 uint8_t tmr_res; 2198 2199 DPRINTFN(9, "\n"); 2200 2201 td = xfer->td_transfer_cache; 2202 if (td == NULL) 2203 return; 2204 2205 while (1) { 2206 if ((td->func) (sc, td)) { 2207 /* operation in progress */ 2208 break; 2209 } 2210 if (((void *)td) == xfer->td_transfer_last) { 2211 goto done; 2212 } 2213 if (td->error_any) { 2214 goto done; 2215 } else if (td->remainder > 0) { 2216 /* 2217 * We had a short transfer. If there is no alternate 2218 * next, stop processing ! 2219 */ 2220 if (!td->alt_next) 2221 goto done; 2222 } 2223 2224 /* 2225 * Fetch the next transfer descriptor and transfer 2226 * some flags to the next transfer descriptor 2227 */ 2228 tmr_res = td->tmr_res; 2229 tmr_val = td->tmr_val; 2230 toggle = td->toggle; 2231 td = td->obj_next; 2232 xfer->td_transfer_cache = td; 2233 td->toggle = toggle; /* transfer toggle */ 2234 td->tmr_res = tmr_res; 2235 td->tmr_val = tmr_val; 2236 } 2237 return; 2238 2239 done: 2240 xfer->td_transfer_cache = NULL; 2241 sc->sc_xfer_complete = 1; 2242 } 2243 2244 static uint8_t 2245 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2246 { 2247 struct dwc_otg_td *td; 2248 2249 DPRINTFN(9, "\n"); 2250 2251 td = xfer->td_transfer_cache; 2252 if (td == NULL) { 2253 /* compute all actual lengths */ 2254 dwc_otg_standard_done(xfer); 2255 return (1); 2256 } 2257 return (0); 2258 } 2259 2260 static void 2261 dwc_otg_timer(void *_sc) 2262 { 2263 struct dwc_otg_softc *sc = _sc; 2264 struct usb_xfer *xfer; 2265 struct dwc_otg_td *td; 2266 2267 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2268 2269 DPRINTF("\n"); 2270 2271 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2272 2273 /* increment timer value */ 2274 sc->sc_tmr_val++; 2275 2276 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2277 td = xfer->td_transfer_cache; 2278 if (td != NULL) { 2279 /* reset NAK counter */ 2280 td->did_nak = 0; 2281 } 2282 } 2283 2284 /* enable SOF interrupt, which will poll jobs */ 2285 dwc_otg_enable_sof_irq(sc); 2286 2287 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2288 2289 if (sc->sc_timer_active) { 2290 /* restart timer */ 2291 usb_callout_reset(&sc->sc_timer, 2292 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2293 &dwc_otg_timer, sc); 2294 } 2295 } 2296 2297 static void 2298 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2299 { 2300 if (sc->sc_timer_active != 0) 2301 return; 2302 2303 sc->sc_timer_active = 1; 2304 2305 /* restart timer */ 2306 usb_callout_reset(&sc->sc_timer, 2307 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2308 &dwc_otg_timer, sc); 2309 } 2310 2311 static void 2312 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2313 { 2314 if (sc->sc_timer_active == 0) 2315 return; 2316 2317 sc->sc_timer_active = 0; 2318 2319 /* stop timer */ 2320 usb_callout_stop(&sc->sc_timer); 2321 } 2322 2323 static void 2324 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 2325 { 2326 uint32_t hcchar; 2327 2328 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 2329 2330 /* disable host channel, if any */ 2331 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 2332 /* disable channel */ 2333 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2334 HCCHAR_CHENA | HCCHAR_CHDIS); 2335 /* wait for chip to get its brains in order */ 2336 sc->sc_chan_state[x].wait_sof = 2; 2337 } 2338 2339 /* release TX FIFO usage, if any */ 2340 sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; 2341 sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; 2342 2343 /* don't release TX FIFO usage twice */ 2344 sc->sc_chan_state[x].tx_p_size = 0; 2345 sc->sc_chan_state[x].tx_np_size = 0; 2346 } 2347 2348 static uint16_t 2349 dwc_otg_compute_tt_slot(struct dwc_otg_tt_info *pinfo, uint16_t io_bytes) 2350 { 2351 const uint16_t limit = (188 * 5) / 6; /* includes bit-stuffing */ 2352 uint16_t retval = pinfo->slot_index; 2353 2354 pinfo->bytes_used += io_bytes; 2355 while (pinfo->slot_index < 6 && 2356 pinfo->bytes_used >= limit) { 2357 pinfo->bytes_used -= limit; 2358 pinfo->slot_index++; 2359 } 2360 return (retval); 2361 } 2362 2363 static uint8_t 2364 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2365 { 2366 TAILQ_HEAD(, usb_xfer) head; 2367 struct usb_xfer *xfer; 2368 struct usb_xfer *xfer_next; 2369 struct dwc_otg_td *td; 2370 uint16_t temp; 2371 uint16_t slot; 2372 uint8_t x; 2373 2374 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2375 2376 if (sc->sc_last_frame_num == temp) 2377 return (0); 2378 2379 sc->sc_last_frame_num = temp; 2380 2381 TAILQ_INIT(&head); 2382 2383 for (x = 0; x != sc->sc_host_ch_max; x++) { 2384 if (sc->sc_chan_state[x].wait_sof == 0) 2385 continue; 2386 2387 sc->sc_needsof = 1; 2388 if (--(sc->sc_chan_state[x].wait_sof) == 0) 2389 dwc_otg_host_channel_disable(sc, x); 2390 } 2391 2392 if ((temp & 7) == 0) { 2393 2394 /* reset the schedule */ 2395 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2396 2397 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2398 td = xfer->td_transfer_cache; 2399 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2400 continue; 2401 2402 /* check for IN direction */ 2403 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2404 continue; 2405 2406 /* execute more frames */ 2407 td->tmr_val = 0; 2408 2409 sc->sc_needsof = 1; 2410 2411 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2412 continue; 2413 2414 /* compute slot */ 2415 slot = temp + dwc_otg_compute_tt_slot( 2416 sc->sc_tt_info + td->tt_index, td->remainder); 2417 2418 /* Start ASAP */ 2419 td->tt_start_slot = slot + 0; 2420 td->tt_scheduled = 1; 2421 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2422 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2423 } 2424 2425 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2426 td = xfer->td_transfer_cache; 2427 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2428 continue; 2429 2430 /* check for OUT direction */ 2431 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2432 continue; 2433 2434 /* execute more frames */ 2435 td->tmr_val = 0; 2436 2437 sc->sc_needsof = 1; 2438 2439 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2440 continue; 2441 2442 /* compute slot */ 2443 slot = temp + dwc_otg_compute_tt_slot( 2444 sc->sc_tt_info + td->tt_index, td->remainder); 2445 2446 /* Start ASAP */ 2447 td->tt_start_slot = slot + 0; 2448 td->tt_scheduled = 1; 2449 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2450 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2451 } 2452 2453 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2454 td = xfer->td_transfer_cache; 2455 if (td == NULL || td->ep_type != UE_INTERRUPT) 2456 continue; 2457 2458 if (td->tt_scheduled != 0) { 2459 sc->sc_needsof = 1; 2460 continue; 2461 } 2462 2463 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2464 continue; 2465 2466 if (td->hcsplt == 0) { 2467 sc->sc_needsof = 1; 2468 td->tt_scheduled = 1; 2469 continue; 2470 } 2471 2472 /* compute slot */ 2473 slot = temp + dwc_otg_compute_tt_slot(sc->sc_tt_info + td->tt_index, 2474 td->max_packet_size); 2475 2476 /* start ASAP */ 2477 td->tt_start_slot = slot + 0; 2478 sc->sc_needsof = 1; 2479 td->tt_scheduled = 1; 2480 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2481 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2482 } 2483 2484 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2485 td = xfer->td_transfer_cache; 2486 if (td == NULL || 2487 td->ep_type != UE_CONTROL || 2488 td->did_nak >= DWC_OTG_NAK_MAX) { 2489 continue; 2490 } 2491 2492 sc->sc_needsof = 1; 2493 2494 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2495 continue; 2496 2497 /* compute slot */ 2498 slot = temp + dwc_otg_compute_tt_slot(sc->sc_tt_info + td->tt_index, 0); 2499 2500 /* start ASAP */ 2501 td->tt_start_slot = slot + 0; 2502 td->tt_scheduled = 1; 2503 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2504 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2505 } 2506 } 2507 if ((temp & 7) < 6) { 2508 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2509 td = xfer->td_transfer_cache; 2510 if (td == NULL || 2511 td->ep_type != UE_BULK || 2512 td->did_nak >= DWC_OTG_NAK_MAX) { 2513 continue; 2514 } 2515 2516 sc->sc_needsof = 1; 2517 2518 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2519 continue; 2520 2521 /* compute slot */ 2522 slot = dwc_otg_compute_tt_slot(sc->sc_tt_info + td->tt_index, 0); 2523 2524 /* figure out highest slot number */ 2525 if (slot < (temp & 7)) 2526 slot = temp; 2527 else 2528 slot += (temp & ~7); 2529 2530 /* start ASAP */ 2531 td->tt_start_slot = slot + 0; 2532 td->tt_scheduled = 1; 2533 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2534 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2535 } 2536 } 2537 2538 /* Put TT transfers in execution order at the end */ 2539 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2540 2541 /* move all TT transfers in front, keeping the current order */ 2542 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2543 td = xfer->td_transfer_cache; 2544 if (td == NULL || td->hcsplt == 0) 2545 continue; 2546 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2547 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2548 } 2549 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2550 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2551 2552 /* put non-TT BULK transfers last */ 2553 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2554 td = xfer->td_transfer_cache; 2555 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2556 continue; 2557 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2558 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2559 } 2560 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2561 2562 if ((temp & 7) == 0) { 2563 2564 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2565 (int)temp, (int)sc->sc_needsof); 2566 2567 /* update SOF IRQ mask */ 2568 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2569 if (sc->sc_needsof == 0) { 2570 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2571 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2572 } 2573 } else { 2574 if (sc->sc_needsof != 0) { 2575 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2576 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2577 } 2578 } 2579 2580 /* clear need SOF flag */ 2581 sc->sc_needsof = 0; 2582 } 2583 return (1); 2584 } 2585 2586 static void 2587 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2588 { 2589 struct usb_xfer *xfer; 2590 uint32_t temp; 2591 uint8_t got_rx_status; 2592 uint8_t x; 2593 2594 repeat: 2595 /* get all channel interrupts */ 2596 for (x = 0; x != sc->sc_host_ch_max; x++) { 2597 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2598 if (temp != 0) { 2599 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2600 temp &= ~HCINT_SOFTWARE_ONLY; 2601 sc->sc_chan_state[x].hcint |= temp; 2602 } 2603 } 2604 2605 if (sc->sc_last_rx_status == 0) { 2606 2607 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2608 if (temp & GINTSTS_RXFLVL) { 2609 /* pop current status */ 2610 sc->sc_last_rx_status = 2611 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2612 } 2613 2614 if (sc->sc_last_rx_status != 0) { 2615 2616 uint8_t ep_no; 2617 2618 temp = sc->sc_last_rx_status & 2619 GRXSTSRD_PKTSTS_MASK; 2620 2621 /* non-data messages we simply skip */ 2622 if (temp != GRXSTSRD_STP_DATA && 2623 temp != GRXSTSRD_OUT_DATA) { 2624 dwc_otg_common_rx_ack(sc); 2625 goto repeat; 2626 } 2627 2628 temp = GRXSTSRD_BCNT_GET( 2629 sc->sc_last_rx_status); 2630 ep_no = GRXSTSRD_CHNUM_GET( 2631 sc->sc_last_rx_status); 2632 2633 /* receive data, if any */ 2634 if (temp != 0) { 2635 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2636 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2637 DOTG_DFIFO(ep_no), 2638 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2639 } 2640 2641 /* check if we should dump the data */ 2642 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2643 dwc_otg_common_rx_ack(sc); 2644 goto repeat; 2645 } 2646 2647 got_rx_status = 1; 2648 2649 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2650 sc->sc_last_rx_status, ep_no, 2651 (sc->sc_last_rx_status >> 15) & 3, 2652 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2653 (sc->sc_last_rx_status >> 17) & 15); 2654 } else { 2655 got_rx_status = 0; 2656 } 2657 } else { 2658 uint8_t ep_no; 2659 2660 ep_no = GRXSTSRD_CHNUM_GET( 2661 sc->sc_last_rx_status); 2662 2663 /* check if we should dump the data */ 2664 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2665 dwc_otg_common_rx_ack(sc); 2666 goto repeat; 2667 } 2668 2669 got_rx_status = 1; 2670 } 2671 2672 /* execute FIFOs */ 2673 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2674 dwc_otg_xfer_do_fifo(sc, xfer); 2675 2676 if (got_rx_status) { 2677 /* check if data was consumed */ 2678 if (sc->sc_last_rx_status == 0) 2679 goto repeat; 2680 2681 /* disable RX FIFO level interrupt */ 2682 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2683 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2684 } 2685 2686 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2687 /* update host transfer schedule, so that new transfers can be issued */ 2688 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2689 goto repeat; 2690 } 2691 } 2692 2693 static void 2694 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2695 { 2696 struct usb_xfer *xfer; 2697 repeat: 2698 /* scan for completion events */ 2699 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2700 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2701 goto repeat; 2702 } 2703 } 2704 2705 static void 2706 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2707 { 2708 DPRINTFN(5, "vbus = %u\n", is_on); 2709 2710 /* 2711 * If the USB host mode is forced, then assume VBUS is always 2712 * present else rely on the input to this function: 2713 */ 2714 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2715 2716 if (!sc->sc_flags.status_vbus) { 2717 sc->sc_flags.status_vbus = 1; 2718 2719 /* complete root HUB interrupt endpoint */ 2720 2721 dwc_otg_root_intr(sc); 2722 } 2723 } else { 2724 if (sc->sc_flags.status_vbus) { 2725 sc->sc_flags.status_vbus = 0; 2726 sc->sc_flags.status_bus_reset = 0; 2727 sc->sc_flags.status_suspend = 0; 2728 sc->sc_flags.change_suspend = 0; 2729 sc->sc_flags.change_connect = 1; 2730 2731 /* complete root HUB interrupt endpoint */ 2732 2733 dwc_otg_root_intr(sc); 2734 } 2735 } 2736 } 2737 2738 int 2739 dwc_otg_filter_interrupt(void *arg) 2740 { 2741 struct dwc_otg_softc *sc = arg; 2742 int retval = FILTER_HANDLED; 2743 uint32_t status; 2744 2745 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2746 2747 /* read and clear interrupt status */ 2748 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2749 2750 /* clear interrupts we are handling here */ 2751 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2752 2753 /* check for USB state change interrupts */ 2754 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2755 retval = FILTER_SCHEDULE_THREAD; 2756 2757 /* clear all IN endpoint interrupts */ 2758 if (status & GINTSTS_IEPINT) { 2759 uint32_t temp; 2760 uint8_t x; 2761 2762 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2763 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2764 if (temp & DIEPMSK_XFERCOMPLMSK) { 2765 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2766 DIEPMSK_XFERCOMPLMSK); 2767 } 2768 } 2769 } 2770 2771 /* poll FIFOs, if any */ 2772 dwc_otg_interrupt_poll_locked(sc); 2773 2774 if (sc->sc_xfer_complete != 0) 2775 retval = FILTER_SCHEDULE_THREAD; 2776 2777 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2778 2779 return (retval); 2780 } 2781 2782 void 2783 dwc_otg_interrupt(void *arg) 2784 { 2785 struct dwc_otg_softc *sc = arg; 2786 uint32_t status; 2787 2788 USB_BUS_LOCK(&sc->sc_bus); 2789 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2790 2791 /* read and clear interrupt status */ 2792 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2793 2794 /* clear interrupts we are handling here */ 2795 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2796 2797 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2798 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2799 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2800 2801 if (status & GINTSTS_USBRST) { 2802 2803 /* set correct state */ 2804 sc->sc_flags.status_device_mode = 1; 2805 sc->sc_flags.status_bus_reset = 0; 2806 sc->sc_flags.status_suspend = 0; 2807 sc->sc_flags.change_suspend = 0; 2808 sc->sc_flags.change_connect = 1; 2809 2810 /* Disable SOF interrupt */ 2811 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2812 /* Enable RX frame interrupt */ 2813 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 2814 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2815 2816 /* complete root HUB interrupt endpoint */ 2817 dwc_otg_root_intr(sc); 2818 } 2819 2820 /* check for any bus state change interrupts */ 2821 if (status & GINTSTS_ENUMDONE) { 2822 2823 uint32_t temp; 2824 2825 DPRINTFN(5, "end of reset\n"); 2826 2827 /* set correct state */ 2828 sc->sc_flags.status_device_mode = 1; 2829 sc->sc_flags.status_bus_reset = 1; 2830 sc->sc_flags.status_suspend = 0; 2831 sc->sc_flags.change_suspend = 0; 2832 sc->sc_flags.change_connect = 1; 2833 sc->sc_flags.status_low_speed = 0; 2834 sc->sc_flags.port_enabled = 1; 2835 2836 /* reset FIFOs */ 2837 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2838 2839 /* reset function address */ 2840 dwc_otg_set_address(sc, 0); 2841 2842 /* figure out enumeration speed */ 2843 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2844 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2845 sc->sc_flags.status_high_speed = 1; 2846 else 2847 sc->sc_flags.status_high_speed = 0; 2848 2849 /* 2850 * Disable resume and SOF interrupt, and enable 2851 * suspend and RX frame interrupt: 2852 */ 2853 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2854 sc->sc_irq_mask |= (GINTMSK_USBSUSPMSK | GINTMSK_RXFLVLMSK); 2855 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2856 2857 /* complete root HUB interrupt endpoint */ 2858 dwc_otg_root_intr(sc); 2859 } 2860 2861 if (status & GINTSTS_PRTINT) { 2862 uint32_t hprt; 2863 2864 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2865 2866 /* clear change bits */ 2867 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2868 HPRT_PRTPWR | HPRT_PRTENCHNG | 2869 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2870 sc->sc_hprt_val); 2871 2872 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2873 2874 sc->sc_flags.status_device_mode = 0; 2875 2876 if (hprt & HPRT_PRTCONNSTS) 2877 sc->sc_flags.status_bus_reset = 1; 2878 else 2879 sc->sc_flags.status_bus_reset = 0; 2880 2881 if (hprt & HPRT_PRTENCHNG) 2882 sc->sc_flags.change_enabled = 1; 2883 2884 if (hprt & HPRT_PRTENA) 2885 sc->sc_flags.port_enabled = 1; 2886 else 2887 sc->sc_flags.port_enabled = 0; 2888 2889 if (hprt & HPRT_PRTOVRCURRCHNG) 2890 sc->sc_flags.change_over_current = 1; 2891 2892 if (hprt & HPRT_PRTOVRCURRACT) 2893 sc->sc_flags.port_over_current = 1; 2894 else 2895 sc->sc_flags.port_over_current = 0; 2896 2897 if (hprt & HPRT_PRTPWR) 2898 sc->sc_flags.port_powered = 1; 2899 else 2900 sc->sc_flags.port_powered = 0; 2901 2902 if (((hprt & HPRT_PRTSPD_MASK) 2903 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2904 sc->sc_flags.status_low_speed = 1; 2905 else 2906 sc->sc_flags.status_low_speed = 0; 2907 2908 if (((hprt & HPRT_PRTSPD_MASK) 2909 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2910 sc->sc_flags.status_high_speed = 1; 2911 else 2912 sc->sc_flags.status_high_speed = 0; 2913 2914 if (hprt & HPRT_PRTCONNDET) 2915 sc->sc_flags.change_connect = 1; 2916 2917 if (hprt & HPRT_PRTSUSP) 2918 dwc_otg_suspend_irq(sc); 2919 else 2920 dwc_otg_resume_irq(sc); 2921 2922 /* complete root HUB interrupt endpoint */ 2923 dwc_otg_root_intr(sc); 2924 2925 /* disable RX FIFO level interrupt */ 2926 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2927 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2928 2929 /* update host frame interval */ 2930 dwc_otg_update_host_frame_interval(sc); 2931 } 2932 2933 /* 2934 * If resume and suspend is set at the same time we interpret 2935 * that like RESUME. Resume is set when there is at least 3 2936 * milliseconds of inactivity on the USB BUS. 2937 */ 2938 if (status & GINTSTS_WKUPINT) { 2939 2940 DPRINTFN(5, "resume interrupt\n"); 2941 2942 dwc_otg_resume_irq(sc); 2943 2944 } else if (status & GINTSTS_USBSUSP) { 2945 2946 DPRINTFN(5, "suspend interrupt\n"); 2947 2948 dwc_otg_suspend_irq(sc); 2949 } 2950 /* check VBUS */ 2951 if (status & (GINTSTS_USBSUSP | 2952 GINTSTS_USBRST | 2953 GINTMSK_OTGINTMSK | 2954 GINTSTS_SESSREQINT)) { 2955 uint32_t temp; 2956 2957 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2958 2959 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2960 2961 dwc_otg_vbus_interrupt(sc, 2962 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2963 } 2964 2965 if (sc->sc_xfer_complete != 0) { 2966 sc->sc_xfer_complete = 0; 2967 2968 /* complete FIFOs, if any */ 2969 dwc_otg_interrupt_complete_locked(sc); 2970 2971 if (sc->sc_flags.status_device_mode == 0) { 2972 /* update host transfer schedule, so that new transfers can be issued */ 2973 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2974 dwc_otg_interrupt_poll_locked(sc); 2975 } 2976 } 2977 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2978 USB_BUS_UNLOCK(&sc->sc_bus); 2979 } 2980 2981 static void 2982 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2983 { 2984 struct dwc_otg_td *td; 2985 2986 /* get current Transfer Descriptor */ 2987 td = temp->td_next; 2988 temp->td = td; 2989 2990 /* prepare for next TD */ 2991 temp->td_next = td->obj_next; 2992 2993 /* fill out the Transfer Descriptor */ 2994 td->func = temp->func; 2995 td->pc = temp->pc; 2996 td->offset = temp->offset; 2997 td->remainder = temp->len; 2998 td->tx_bytes = 0; 2999 td->error_any = 0; 3000 td->error_stall = 0; 3001 td->npkt = 0; 3002 td->did_stall = temp->did_stall; 3003 td->short_pkt = temp->short_pkt; 3004 td->alt_next = temp->setup_alt_next; 3005 td->set_toggle = 0; 3006 td->got_short = 0; 3007 td->did_nak = 0; 3008 td->channel = DWC_OTG_MAX_CHANNELS; 3009 td->state = 0; 3010 td->errcnt = 0; 3011 td->tt_scheduled = 0; 3012 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3013 } 3014 3015 static void 3016 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3017 { 3018 struct dwc_otg_std_temp temp; 3019 struct dwc_otg_td *td; 3020 uint32_t x; 3021 uint8_t need_sync; 3022 uint8_t is_host; 3023 3024 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3025 xfer->address, UE_GET_ADDR(xfer->endpointno), 3026 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3027 3028 temp.max_frame_size = xfer->max_frame_size; 3029 3030 td = xfer->td_start[0]; 3031 xfer->td_transfer_first = td; 3032 xfer->td_transfer_cache = td; 3033 3034 /* setup temp */ 3035 3036 temp.pc = NULL; 3037 temp.td = NULL; 3038 temp.td_next = xfer->td_start[0]; 3039 temp.offset = 0; 3040 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3041 xfer->flags_int.isochronous_xfr; 3042 temp.did_stall = !xfer->flags_int.control_stall; 3043 3044 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3045 3046 /* check if we should prepend a setup message */ 3047 3048 if (xfer->flags_int.control_xfr) { 3049 if (xfer->flags_int.control_hdr) { 3050 3051 if (is_host) 3052 temp.func = &dwc_otg_host_setup_tx; 3053 else 3054 temp.func = &dwc_otg_setup_rx; 3055 3056 temp.len = xfer->frlengths[0]; 3057 temp.pc = xfer->frbuffers + 0; 3058 temp.short_pkt = temp.len ? 1 : 0; 3059 3060 /* check for last frame */ 3061 if (xfer->nframes == 1) { 3062 /* no STATUS stage yet, SETUP is last */ 3063 if (xfer->flags_int.control_act) 3064 temp.setup_alt_next = 0; 3065 } 3066 3067 dwc_otg_setup_standard_chain_sub(&temp); 3068 } 3069 x = 1; 3070 } else { 3071 x = 0; 3072 } 3073 3074 if (x != xfer->nframes) { 3075 if (xfer->endpointno & UE_DIR_IN) { 3076 if (is_host) { 3077 temp.func = &dwc_otg_host_data_rx; 3078 need_sync = 0; 3079 } else { 3080 temp.func = &dwc_otg_data_tx; 3081 need_sync = 1; 3082 } 3083 } else { 3084 if (is_host) { 3085 temp.func = &dwc_otg_host_data_tx; 3086 need_sync = 0; 3087 } else { 3088 temp.func = &dwc_otg_data_rx; 3089 need_sync = 0; 3090 } 3091 } 3092 3093 /* setup "pc" pointer */ 3094 temp.pc = xfer->frbuffers + x; 3095 } else { 3096 need_sync = 0; 3097 } 3098 while (x != xfer->nframes) { 3099 3100 /* DATA0 / DATA1 message */ 3101 3102 temp.len = xfer->frlengths[x]; 3103 3104 x++; 3105 3106 if (x == xfer->nframes) { 3107 if (xfer->flags_int.control_xfr) { 3108 if (xfer->flags_int.control_act) { 3109 temp.setup_alt_next = 0; 3110 } 3111 } else { 3112 temp.setup_alt_next = 0; 3113 } 3114 } 3115 if (temp.len == 0) { 3116 3117 /* make sure that we send an USB packet */ 3118 3119 temp.short_pkt = 0; 3120 3121 } else { 3122 3123 /* regular data transfer */ 3124 3125 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3126 } 3127 3128 dwc_otg_setup_standard_chain_sub(&temp); 3129 3130 if (xfer->flags_int.isochronous_xfr) { 3131 temp.offset += temp.len; 3132 } else { 3133 /* get next Page Cache pointer */ 3134 temp.pc = xfer->frbuffers + x; 3135 } 3136 } 3137 3138 if (xfer->flags_int.control_xfr) { 3139 3140 /* always setup a valid "pc" pointer for status and sync */ 3141 temp.pc = xfer->frbuffers + 0; 3142 temp.len = 0; 3143 temp.short_pkt = 0; 3144 temp.setup_alt_next = 0; 3145 3146 /* check if we need to sync */ 3147 if (need_sync) { 3148 /* we need a SYNC point after TX */ 3149 temp.func = &dwc_otg_data_tx_sync; 3150 dwc_otg_setup_standard_chain_sub(&temp); 3151 } 3152 3153 /* check if we should append a status stage */ 3154 if (!xfer->flags_int.control_act) { 3155 3156 /* 3157 * Send a DATA1 message and invert the current 3158 * endpoint direction. 3159 */ 3160 if (xfer->endpointno & UE_DIR_IN) { 3161 if (is_host) { 3162 temp.func = &dwc_otg_host_data_tx; 3163 need_sync = 0; 3164 } else { 3165 temp.func = &dwc_otg_data_rx; 3166 need_sync = 0; 3167 } 3168 } else { 3169 if (is_host) { 3170 temp.func = &dwc_otg_host_data_rx; 3171 need_sync = 0; 3172 } else { 3173 temp.func = &dwc_otg_data_tx; 3174 need_sync = 1; 3175 } 3176 } 3177 3178 dwc_otg_setup_standard_chain_sub(&temp); 3179 3180 /* data toggle should be DATA1 */ 3181 td = temp.td; 3182 td->set_toggle = 1; 3183 3184 if (need_sync) { 3185 /* we need a SYNC point after TX */ 3186 temp.func = &dwc_otg_data_tx_sync; 3187 dwc_otg_setup_standard_chain_sub(&temp); 3188 } 3189 } 3190 } else { 3191 /* check if we need to sync */ 3192 if (need_sync) { 3193 3194 temp.pc = xfer->frbuffers + 0; 3195 temp.len = 0; 3196 temp.short_pkt = 0; 3197 temp.setup_alt_next = 0; 3198 3199 /* we need a SYNC point after TX */ 3200 temp.func = &dwc_otg_data_tx_sync; 3201 dwc_otg_setup_standard_chain_sub(&temp); 3202 } 3203 } 3204 3205 /* must have at least one frame! */ 3206 td = temp.td; 3207 xfer->td_transfer_last = td; 3208 3209 if (is_host) { 3210 3211 struct dwc_otg_softc *sc; 3212 uint32_t hcchar; 3213 uint32_t hcsplt; 3214 3215 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3216 3217 /* get first again */ 3218 td = xfer->td_transfer_first; 3219 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3220 3221 hcchar = 3222 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3223 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3224 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3225 (td->ep_type << HCCHAR_EPTYPE_SHIFT) | 3226 HCCHAR_CHENA; 3227 3228 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3229 hcchar |= HCCHAR_LSPDDEV; 3230 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3231 hcchar |= HCCHAR_EPDIR_IN; 3232 3233 switch (xfer->xroot->udev->speed) { 3234 case USB_SPEED_FULL: 3235 case USB_SPEED_LOW: 3236 /* check if root HUB port is running High Speed */ 3237 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3238 hcsplt = HCSPLT_SPLTENA | 3239 (xfer->xroot->udev->hs_port_no << 3240 HCSPLT_PRTADDR_SHIFT) | 3241 (xfer->xroot->udev->hs_hub_addr << 3242 HCSPLT_HUBADDR_SHIFT); 3243 } else { 3244 hcsplt = 0; 3245 } 3246 if (td->ep_type == UE_INTERRUPT) { 3247 uint32_t ival; 3248 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3249 if (ival == 0) 3250 ival = 1; 3251 else if (ival > 127) 3252 ival = 127; 3253 td->tmr_val = sc->sc_tmr_val + ival; 3254 td->tmr_res = ival; 3255 } else if (td->ep_type == UE_ISOCHRONOUS) { 3256 td->tmr_val = 0; 3257 td->tmr_res = 1; 3258 } else { 3259 td->tmr_val = 0; 3260 td->tmr_res = 0; 3261 } 3262 break; 3263 case USB_SPEED_HIGH: 3264 hcsplt = 0; 3265 if (td->ep_type == UE_ISOCHRONOUS || 3266 td->ep_type == UE_INTERRUPT) { 3267 hcchar |= ((xfer->max_packet_count & 3) 3268 << HCCHAR_MC_SHIFT); 3269 } 3270 if (td->ep_type == UE_INTERRUPT) { 3271 uint32_t ival; 3272 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3273 if (ival == 0) 3274 ival = 1; 3275 else if (ival > 127) 3276 ival = 127; 3277 td->tmr_val = sc->sc_tmr_val + ival; 3278 td->tmr_res = ival; 3279 } else if (td->ep_type == UE_ISOCHRONOUS) { 3280 td->tmr_val = 0; 3281 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3282 } else { 3283 td->tmr_val = 0; 3284 td->tmr_res = 0; 3285 } 3286 break; 3287 default: 3288 hcsplt = 0; 3289 td->tmr_val = 0; 3290 td->tmr_res = 0; 3291 break; 3292 } 3293 3294 /* store configuration in all TD's */ 3295 while (1) { 3296 td->hcchar = hcchar; 3297 td->hcsplt = hcsplt; 3298 3299 if (((void *)td) == xfer->td_transfer_last) 3300 break; 3301 3302 td = td->obj_next; 3303 } 3304 } 3305 } 3306 3307 static void 3308 dwc_otg_timeout(void *arg) 3309 { 3310 struct usb_xfer *xfer = arg; 3311 3312 DPRINTF("xfer=%p\n", xfer); 3313 3314 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3315 3316 /* transfer is transferred */ 3317 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3318 } 3319 3320 static void 3321 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3322 { 3323 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3324 struct usb_xfer_root *xroot; 3325 struct dwc_otg_td *td; 3326 3327 DPRINTFN(9, "\n"); 3328 3329 /* 3330 * Poll one time in device mode, which will turn on the 3331 * endpoint interrupts. Else wait for SOF interrupt in host 3332 * mode. 3333 */ 3334 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3335 3336 if (sc->sc_flags.status_device_mode != 0) { 3337 dwc_otg_xfer_do_fifo(sc, xfer); 3338 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3339 goto done; 3340 } 3341 3342 /* put transfer on interrupt queue */ 3343 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3344 3345 /* start timeout, if any */ 3346 if (xfer->timeout != 0) { 3347 usbd_transfer_timeout_ms(xfer, 3348 &dwc_otg_timeout, xfer->timeout); 3349 } 3350 3351 if (sc->sc_flags.status_device_mode != 0) 3352 goto done; 3353 3354 /* enable SOF interrupt, if any */ 3355 dwc_otg_enable_sof_irq(sc); 3356 3357 td = xfer->td_transfer_cache; 3358 if (td->ep_type != UE_BULK) 3359 goto done; 3360 3361 xroot = xfer->xroot; 3362 3363 /* 3364 * Optimise the ping-pong effect by waking up other BULK 3365 * transfers belonging to the same device group: 3366 */ 3367 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3368 td = xfer->td_transfer_cache; 3369 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3370 continue; 3371 /* reset NAK counter */ 3372 td->did_nak = 0; 3373 } 3374 done: 3375 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3376 } 3377 3378 static void 3379 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3380 { 3381 DPRINTFN(9, "\n"); 3382 3383 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3384 3385 /* set port bit */ 3386 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3387 3388 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3389 sizeof(sc->sc_hub_idata)); 3390 } 3391 3392 static usb_error_t 3393 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3394 { 3395 struct dwc_otg_td *td; 3396 uint32_t len; 3397 usb_error_t error; 3398 3399 DPRINTFN(9, "\n"); 3400 3401 td = xfer->td_transfer_cache; 3402 3403 do { 3404 len = td->remainder; 3405 3406 /* store last data toggle */ 3407 xfer->endpoint->toggle_next = td->toggle; 3408 3409 if (xfer->aframes != xfer->nframes) { 3410 /* 3411 * Verify the length and subtract 3412 * the remainder from "frlengths[]": 3413 */ 3414 if (len > xfer->frlengths[xfer->aframes]) { 3415 td->error_any = 1; 3416 } else { 3417 xfer->frlengths[xfer->aframes] -= len; 3418 } 3419 } 3420 /* Check for transfer error */ 3421 if (td->error_any) { 3422 /* the transfer is finished */ 3423 error = (td->error_stall ? 3424 USB_ERR_STALLED : USB_ERR_IOERROR); 3425 td = NULL; 3426 break; 3427 } 3428 /* Check for short transfer */ 3429 if (len > 0) { 3430 if (xfer->flags_int.short_frames_ok || 3431 xfer->flags_int.isochronous_xfr) { 3432 /* follow alt next */ 3433 if (td->alt_next) { 3434 td = td->obj_next; 3435 } else { 3436 td = NULL; 3437 } 3438 } else { 3439 /* the transfer is finished */ 3440 td = NULL; 3441 } 3442 error = 0; 3443 break; 3444 } 3445 td = td->obj_next; 3446 3447 /* this USB frame is complete */ 3448 error = 0; 3449 break; 3450 3451 } while (0); 3452 3453 /* update transfer cache */ 3454 3455 xfer->td_transfer_cache = td; 3456 3457 return (error); 3458 } 3459 3460 static void 3461 dwc_otg_standard_done(struct usb_xfer *xfer) 3462 { 3463 usb_error_t err = 0; 3464 3465 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3466 xfer, xfer->endpoint); 3467 3468 /* reset scanner */ 3469 3470 xfer->td_transfer_cache = xfer->td_transfer_first; 3471 3472 if (xfer->flags_int.control_xfr) { 3473 3474 if (xfer->flags_int.control_hdr) { 3475 3476 err = dwc_otg_standard_done_sub(xfer); 3477 } 3478 xfer->aframes = 1; 3479 3480 if (xfer->td_transfer_cache == NULL) { 3481 goto done; 3482 } 3483 } 3484 while (xfer->aframes != xfer->nframes) { 3485 3486 err = dwc_otg_standard_done_sub(xfer); 3487 xfer->aframes++; 3488 3489 if (xfer->td_transfer_cache == NULL) { 3490 goto done; 3491 } 3492 } 3493 3494 if (xfer->flags_int.control_xfr && 3495 !xfer->flags_int.control_act) { 3496 3497 err = dwc_otg_standard_done_sub(xfer); 3498 } 3499 done: 3500 dwc_otg_device_done(xfer, err); 3501 } 3502 3503 /*------------------------------------------------------------------------* 3504 * dwc_otg_device_done 3505 * 3506 * NOTE: this function can be called more than one time on the 3507 * same USB transfer! 3508 *------------------------------------------------------------------------*/ 3509 static void 3510 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3511 { 3512 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3513 3514 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3515 xfer, xfer->endpoint, error); 3516 3517 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3518 3519 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3520 /* Interrupts are cleared by the interrupt handler */ 3521 } else { 3522 struct dwc_otg_td *td; 3523 3524 td = xfer->td_transfer_cache; 3525 if (td != NULL) 3526 dwc_otg_host_channel_free(sc, td); 3527 } 3528 /* dequeue transfer and start next transfer */ 3529 usbd_transfer_done(xfer, error); 3530 3531 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3532 } 3533 3534 static void 3535 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3536 { 3537 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3538 } 3539 3540 static void 3541 dwc_otg_set_stall(struct usb_device *udev, 3542 struct usb_endpoint *ep, uint8_t *did_stall) 3543 { 3544 struct dwc_otg_softc *sc; 3545 uint32_t temp; 3546 uint32_t reg; 3547 uint8_t ep_no; 3548 3549 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3550 3551 /* check mode */ 3552 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3553 /* not supported */ 3554 return; 3555 } 3556 3557 sc = DWC_OTG_BUS2SC(udev->bus); 3558 3559 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3560 3561 /* get endpoint address */ 3562 ep_no = ep->edesc->bEndpointAddress; 3563 3564 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3565 3566 if (ep_no & UE_DIR_IN) { 3567 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3568 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3569 } else { 3570 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3571 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3572 } 3573 3574 /* disable and stall endpoint */ 3575 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3576 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3577 3578 /* clear active OUT ep */ 3579 if (!(ep_no & UE_DIR_IN)) { 3580 3581 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3582 3583 if (sc->sc_last_rx_status != 0 && 3584 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3585 sc->sc_last_rx_status)) { 3586 /* dump data */ 3587 dwc_otg_common_rx_ack(sc); 3588 /* poll interrupt */ 3589 dwc_otg_interrupt_poll_locked(sc); 3590 dwc_otg_interrupt_complete_locked(sc); 3591 } 3592 } 3593 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3594 } 3595 3596 static void 3597 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3598 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3599 { 3600 uint32_t reg; 3601 uint32_t temp; 3602 3603 if (ep_type == UE_CONTROL) { 3604 /* clearing stall is not needed */ 3605 return; 3606 } 3607 3608 if (ep_dir) { 3609 reg = DOTG_DIEPCTL(ep_no); 3610 } else { 3611 reg = DOTG_DOEPCTL(ep_no); 3612 sc->sc_active_rx_ep |= (1U << ep_no); 3613 } 3614 3615 /* round up and mask away the multiplier count */ 3616 mps = (mps + 3) & 0x7FC; 3617 3618 if (ep_type == UE_BULK) { 3619 temp = DIEPCTL_EPTYPE_SET( 3620 DIEPCTL_EPTYPE_BULK) | 3621 DIEPCTL_USBACTEP; 3622 } else if (ep_type == UE_INTERRUPT) { 3623 temp = DIEPCTL_EPTYPE_SET( 3624 DIEPCTL_EPTYPE_INTERRUPT) | 3625 DIEPCTL_USBACTEP; 3626 } else { 3627 temp = DIEPCTL_EPTYPE_SET( 3628 DIEPCTL_EPTYPE_ISOC) | 3629 DIEPCTL_USBACTEP; 3630 } 3631 3632 temp |= DIEPCTL_MPS_SET(mps); 3633 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3634 3635 if (ep_dir) 3636 sc->sc_in_ctl[ep_no] = temp; 3637 else 3638 sc->sc_out_ctl[ep_no] = temp; 3639 3640 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3641 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3642 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3643 3644 /* we only reset the transmit FIFO */ 3645 if (ep_dir) { 3646 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3647 GRSTCTL_TXFIFO(ep_no) | 3648 GRSTCTL_TXFFLSH); 3649 3650 DWC_OTG_WRITE_4(sc, 3651 DOTG_DIEPTSIZ(ep_no), 0); 3652 } 3653 3654 /* poll interrupt */ 3655 dwc_otg_interrupt_poll_locked(sc); 3656 dwc_otg_interrupt_complete_locked(sc); 3657 } 3658 3659 static void 3660 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3661 { 3662 struct dwc_otg_softc *sc; 3663 struct usb_endpoint_descriptor *ed; 3664 3665 DPRINTFN(5, "endpoint=%p\n", ep); 3666 3667 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3668 3669 /* check mode */ 3670 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3671 /* not supported */ 3672 return; 3673 } 3674 /* get softc */ 3675 sc = DWC_OTG_BUS2SC(udev->bus); 3676 3677 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3678 3679 /* get endpoint descriptor */ 3680 ed = ep->edesc; 3681 3682 /* reset endpoint */ 3683 dwc_otg_clear_stall_sub_locked(sc, 3684 UGETW(ed->wMaxPacketSize), 3685 (ed->bEndpointAddress & UE_ADDR), 3686 (ed->bmAttributes & UE_XFERTYPE), 3687 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3688 3689 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3690 } 3691 3692 static void 3693 dwc_otg_device_state_change(struct usb_device *udev) 3694 { 3695 struct dwc_otg_softc *sc; 3696 uint8_t x; 3697 3698 /* check mode */ 3699 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3700 /* not supported */ 3701 return; 3702 } 3703 3704 /* get softc */ 3705 sc = DWC_OTG_BUS2SC(udev->bus); 3706 3707 /* deactivate all other endpoint but the control endpoint */ 3708 if (udev->state == USB_STATE_CONFIGURED || 3709 udev->state == USB_STATE_ADDRESSED) { 3710 3711 USB_BUS_LOCK(&sc->sc_bus); 3712 3713 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3714 3715 if (x < sc->sc_dev_in_ep_max) { 3716 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3717 DIEPCTL_EPDIS); 3718 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3719 } 3720 3721 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3722 DOEPCTL_EPDIS); 3723 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3724 } 3725 USB_BUS_UNLOCK(&sc->sc_bus); 3726 } 3727 } 3728 3729 int 3730 dwc_otg_init(struct dwc_otg_softc *sc) 3731 { 3732 uint32_t temp; 3733 3734 DPRINTF("start\n"); 3735 3736 /* set up the bus structure */ 3737 sc->sc_bus.usbrev = USB_REV_2_0; 3738 sc->sc_bus.methods = &dwc_otg_bus_methods; 3739 3740 usb_callout_init_mtx(&sc->sc_timer, 3741 &sc->sc_bus.bus_mtx, 0); 3742 3743 USB_BUS_LOCK(&sc->sc_bus); 3744 3745 /* turn on clocks */ 3746 dwc_otg_clocks_on(sc); 3747 3748 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3749 DPRINTF("Version = 0x%08x\n", temp); 3750 3751 /* disconnect */ 3752 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3753 DCTL_SFTDISCON); 3754 3755 /* wait for host to detect disconnect */ 3756 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3757 3758 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3759 GRSTCTL_CSFTRST); 3760 3761 /* wait a little bit for block to reset */ 3762 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3763 3764 switch (sc->sc_mode) { 3765 case DWC_MODE_DEVICE: 3766 temp = GUSBCFG_FORCEDEVMODE; 3767 break; 3768 case DWC_MODE_HOST: 3769 temp = GUSBCFG_FORCEHOSTMODE; 3770 break; 3771 default: 3772 temp = 0; 3773 break; 3774 } 3775 3776 /* select HSIC or non-HSIC mode */ 3777 if (dwc_otg_use_hsic) { 3778 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3779 GUSBCFG_PHYIF | 3780 GUSBCFG_TRD_TIM_SET(5) | temp); 3781 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3782 0x000000EC); 3783 3784 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3785 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3786 temp & ~GLPMCFG_HSIC_CONN); 3787 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3788 temp | GLPMCFG_HSIC_CONN); 3789 } else { 3790 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3791 GUSBCFG_ULPI_UTMI_SEL | 3792 GUSBCFG_TRD_TIM_SET(5) | temp); 3793 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3794 3795 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3796 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3797 temp & ~GLPMCFG_HSIC_CONN); 3798 } 3799 3800 /* clear global nak */ 3801 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3802 DCTL_CGOUTNAK | 3803 DCTL_CGNPINNAK); 3804 3805 /* disable USB port */ 3806 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3807 3808 /* wait 10ms */ 3809 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3810 3811 /* enable USB port */ 3812 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3813 3814 /* wait 10ms */ 3815 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3816 3817 /* pull up D+ */ 3818 dwc_otg_pull_up(sc); 3819 3820 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3821 3822 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3823 3824 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3825 3826 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3827 3828 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3829 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3830 3831 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3832 3833 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3834 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3835 3836 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3837 3838 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3839 3840 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3841 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3842 sc->sc_host_ch_max); 3843 3844 /* setup FIFO */ 3845 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3846 USB_BUS_UNLOCK(&sc->sc_bus); 3847 return (EINVAL); 3848 } 3849 3850 /* enable interrupts */ 3851 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3852 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3853 3854 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3855 3856 /* enable all endpoint interrupts */ 3857 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3858 if (temp & GHWCFG2_MPI) { 3859 uint8_t x; 3860 3861 DPRINTF("Multi Process Interrupts\n"); 3862 3863 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3864 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 3865 DIEPMSK_XFERCOMPLMSK); 3866 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3867 } 3868 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0xFFFF); 3869 } else { 3870 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3871 DIEPMSK_XFERCOMPLMSK); 3872 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3873 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3874 } 3875 } 3876 3877 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3878 /* setup clocks */ 3879 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3880 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3881 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3882 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3883 } 3884 3885 /* only enable global IRQ */ 3886 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3887 GAHBCFG_GLBLINTRMSK); 3888 3889 /* turn off clocks */ 3890 dwc_otg_clocks_off(sc); 3891 3892 /* read initial VBUS state */ 3893 3894 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3895 3896 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3897 3898 dwc_otg_vbus_interrupt(sc, 3899 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3900 3901 USB_BUS_UNLOCK(&sc->sc_bus); 3902 3903 /* catch any lost interrupts */ 3904 3905 dwc_otg_do_poll(&sc->sc_bus); 3906 3907 return (0); /* success */ 3908 } 3909 3910 void 3911 dwc_otg_uninit(struct dwc_otg_softc *sc) 3912 { 3913 USB_BUS_LOCK(&sc->sc_bus); 3914 3915 /* stop host timer */ 3916 dwc_otg_timer_stop(sc); 3917 3918 /* set disconnect */ 3919 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3920 DCTL_SFTDISCON); 3921 3922 /* turn off global IRQ */ 3923 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3924 3925 sc->sc_flags.port_enabled = 0; 3926 sc->sc_flags.port_powered = 0; 3927 sc->sc_flags.status_vbus = 0; 3928 sc->sc_flags.status_bus_reset = 0; 3929 sc->sc_flags.status_suspend = 0; 3930 sc->sc_flags.change_suspend = 0; 3931 sc->sc_flags.change_connect = 1; 3932 3933 dwc_otg_pull_down(sc); 3934 dwc_otg_clocks_off(sc); 3935 3936 USB_BUS_UNLOCK(&sc->sc_bus); 3937 3938 usb_callout_drain(&sc->sc_timer); 3939 } 3940 3941 static void 3942 dwc_otg_suspend(struct dwc_otg_softc *sc) 3943 { 3944 return; 3945 } 3946 3947 static void 3948 dwc_otg_resume(struct dwc_otg_softc *sc) 3949 { 3950 return; 3951 } 3952 3953 static void 3954 dwc_otg_do_poll(struct usb_bus *bus) 3955 { 3956 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3957 3958 USB_BUS_LOCK(&sc->sc_bus); 3959 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3960 dwc_otg_interrupt_poll_locked(sc); 3961 dwc_otg_interrupt_complete_locked(sc); 3962 if (sc->sc_flags.status_device_mode == 0) { 3963 /* update host transfer schedule, so that new transfers can be issued */ 3964 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 3965 dwc_otg_interrupt_poll_locked(sc); 3966 } 3967 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3968 USB_BUS_UNLOCK(&sc->sc_bus); 3969 } 3970 3971 /*------------------------------------------------------------------------* 3972 * DWC OTG bulk support 3973 * DWC OTG control support 3974 * DWC OTG interrupt support 3975 *------------------------------------------------------------------------*/ 3976 static void 3977 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 3978 { 3979 } 3980 3981 static void 3982 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 3983 { 3984 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 3985 } 3986 3987 static void 3988 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 3989 { 3990 } 3991 3992 static void 3993 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 3994 { 3995 /* setup TDs */ 3996 dwc_otg_setup_standard_chain(xfer); 3997 dwc_otg_start_standard_chain(xfer); 3998 } 3999 4000 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4001 { 4002 .open = dwc_otg_device_non_isoc_open, 4003 .close = dwc_otg_device_non_isoc_close, 4004 .enter = dwc_otg_device_non_isoc_enter, 4005 .start = dwc_otg_device_non_isoc_start, 4006 }; 4007 4008 /*------------------------------------------------------------------------* 4009 * DWC OTG full speed isochronous support 4010 *------------------------------------------------------------------------*/ 4011 static void 4012 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4013 { 4014 } 4015 4016 static void 4017 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4018 { 4019 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4020 } 4021 4022 static void 4023 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4024 { 4025 } 4026 4027 static void 4028 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4029 { 4030 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4031 uint32_t temp; 4032 uint32_t msframes; 4033 uint32_t framenum; 4034 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4035 4036 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4037 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4038 4039 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4040 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4041 4042 /* get the current frame index */ 4043 framenum = (temp & HFNUM_FRNUM_MASK); 4044 } else { 4045 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4046 4047 /* get the current frame index */ 4048 framenum = DSTS_SOFFN_GET(temp); 4049 } 4050 4051 if (xfer->xroot->udev->parent_hs_hub != NULL) 4052 framenum /= 8; 4053 4054 framenum &= DWC_OTG_FRAME_MASK; 4055 4056 /* 4057 * Compute number of milliseconds worth of data traffic for 4058 * this USB transfer: 4059 */ 4060 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4061 msframes = ((xfer->nframes << shift) + 7) / 8; 4062 else 4063 msframes = xfer->nframes; 4064 4065 /* 4066 * check if the frame index is within the window where the frames 4067 * will be inserted 4068 */ 4069 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4070 4071 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4072 /* 4073 * If there is data underflow or the pipe queue is 4074 * empty we schedule the transfer a few frames ahead 4075 * of the current frame position. Else two isochronous 4076 * transfers might overlap. 4077 */ 4078 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4079 xfer->endpoint->is_synced = 1; 4080 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4081 } 4082 /* 4083 * compute how many milliseconds the insertion is ahead of the 4084 * current frame position: 4085 */ 4086 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4087 4088 /* 4089 * pre-compute when the isochronous transfer will be finished: 4090 */ 4091 xfer->isoc_time_complete = 4092 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4093 4094 /* setup TDs */ 4095 dwc_otg_setup_standard_chain(xfer); 4096 4097 /* compute frame number for next insertion */ 4098 xfer->endpoint->isoc_next += msframes; 4099 4100 /* start TD chain */ 4101 dwc_otg_start_standard_chain(xfer); 4102 } 4103 4104 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4105 { 4106 .open = dwc_otg_device_isoc_open, 4107 .close = dwc_otg_device_isoc_close, 4108 .enter = dwc_otg_device_isoc_enter, 4109 .start = dwc_otg_device_isoc_start, 4110 }; 4111 4112 /*------------------------------------------------------------------------* 4113 * DWC OTG root control support 4114 *------------------------------------------------------------------------* 4115 * Simulate a hardware HUB by handling all the necessary requests. 4116 *------------------------------------------------------------------------*/ 4117 4118 static const struct usb_device_descriptor dwc_otg_devd = { 4119 .bLength = sizeof(struct usb_device_descriptor), 4120 .bDescriptorType = UDESC_DEVICE, 4121 .bcdUSB = {0x00, 0x02}, 4122 .bDeviceClass = UDCLASS_HUB, 4123 .bDeviceSubClass = UDSUBCLASS_HUB, 4124 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4125 .bMaxPacketSize = 64, 4126 .bcdDevice = {0x00, 0x01}, 4127 .iManufacturer = 1, 4128 .iProduct = 2, 4129 .bNumConfigurations = 1, 4130 }; 4131 4132 static const struct dwc_otg_config_desc dwc_otg_confd = { 4133 .confd = { 4134 .bLength = sizeof(struct usb_config_descriptor), 4135 .bDescriptorType = UDESC_CONFIG, 4136 .wTotalLength[0] = sizeof(dwc_otg_confd), 4137 .bNumInterface = 1, 4138 .bConfigurationValue = 1, 4139 .iConfiguration = 0, 4140 .bmAttributes = UC_SELF_POWERED, 4141 .bMaxPower = 0, 4142 }, 4143 .ifcd = { 4144 .bLength = sizeof(struct usb_interface_descriptor), 4145 .bDescriptorType = UDESC_INTERFACE, 4146 .bNumEndpoints = 1, 4147 .bInterfaceClass = UICLASS_HUB, 4148 .bInterfaceSubClass = UISUBCLASS_HUB, 4149 .bInterfaceProtocol = 0, 4150 }, 4151 .endpd = { 4152 .bLength = sizeof(struct usb_endpoint_descriptor), 4153 .bDescriptorType = UDESC_ENDPOINT, 4154 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4155 .bmAttributes = UE_INTERRUPT, 4156 .wMaxPacketSize[0] = 8, 4157 .bInterval = 255, 4158 }, 4159 }; 4160 4161 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4162 4163 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4164 .bDescLength = sizeof(dwc_otg_hubd), 4165 .bDescriptorType = UDESC_HUB, 4166 .bNbrPorts = 1, 4167 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4168 .bPwrOn2PwrGood = 50, 4169 .bHubContrCurrent = 0, 4170 .DeviceRemovable = {0}, /* port is removable */ 4171 }; 4172 4173 #define STRING_VENDOR \ 4174 "D\0W\0C\0O\0T\0G" 4175 4176 #define STRING_PRODUCT \ 4177 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4178 4179 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4180 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4181 4182 static usb_error_t 4183 dwc_otg_roothub_exec(struct usb_device *udev, 4184 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4185 { 4186 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4187 const void *ptr; 4188 uint16_t len; 4189 uint16_t value; 4190 uint16_t index; 4191 usb_error_t err; 4192 4193 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4194 4195 /* buffer reset */ 4196 ptr = (const void *)&sc->sc_hub_temp; 4197 len = 0; 4198 err = 0; 4199 4200 value = UGETW(req->wValue); 4201 index = UGETW(req->wIndex); 4202 4203 /* demultiplex the control request */ 4204 4205 switch (req->bmRequestType) { 4206 case UT_READ_DEVICE: 4207 switch (req->bRequest) { 4208 case UR_GET_DESCRIPTOR: 4209 goto tr_handle_get_descriptor; 4210 case UR_GET_CONFIG: 4211 goto tr_handle_get_config; 4212 case UR_GET_STATUS: 4213 goto tr_handle_get_status; 4214 default: 4215 goto tr_stalled; 4216 } 4217 break; 4218 4219 case UT_WRITE_DEVICE: 4220 switch (req->bRequest) { 4221 case UR_SET_ADDRESS: 4222 goto tr_handle_set_address; 4223 case UR_SET_CONFIG: 4224 goto tr_handle_set_config; 4225 case UR_CLEAR_FEATURE: 4226 goto tr_valid; /* nop */ 4227 case UR_SET_DESCRIPTOR: 4228 goto tr_valid; /* nop */ 4229 case UR_SET_FEATURE: 4230 default: 4231 goto tr_stalled; 4232 } 4233 break; 4234 4235 case UT_WRITE_ENDPOINT: 4236 switch (req->bRequest) { 4237 case UR_CLEAR_FEATURE: 4238 switch (UGETW(req->wValue)) { 4239 case UF_ENDPOINT_HALT: 4240 goto tr_handle_clear_halt; 4241 case UF_DEVICE_REMOTE_WAKEUP: 4242 goto tr_handle_clear_wakeup; 4243 default: 4244 goto tr_stalled; 4245 } 4246 break; 4247 case UR_SET_FEATURE: 4248 switch (UGETW(req->wValue)) { 4249 case UF_ENDPOINT_HALT: 4250 goto tr_handle_set_halt; 4251 case UF_DEVICE_REMOTE_WAKEUP: 4252 goto tr_handle_set_wakeup; 4253 default: 4254 goto tr_stalled; 4255 } 4256 break; 4257 case UR_SYNCH_FRAME: 4258 goto tr_valid; /* nop */ 4259 default: 4260 goto tr_stalled; 4261 } 4262 break; 4263 4264 case UT_READ_ENDPOINT: 4265 switch (req->bRequest) { 4266 case UR_GET_STATUS: 4267 goto tr_handle_get_ep_status; 4268 default: 4269 goto tr_stalled; 4270 } 4271 break; 4272 4273 case UT_WRITE_INTERFACE: 4274 switch (req->bRequest) { 4275 case UR_SET_INTERFACE: 4276 goto tr_handle_set_interface; 4277 case UR_CLEAR_FEATURE: 4278 goto tr_valid; /* nop */ 4279 case UR_SET_FEATURE: 4280 default: 4281 goto tr_stalled; 4282 } 4283 break; 4284 4285 case UT_READ_INTERFACE: 4286 switch (req->bRequest) { 4287 case UR_GET_INTERFACE: 4288 goto tr_handle_get_interface; 4289 case UR_GET_STATUS: 4290 goto tr_handle_get_iface_status; 4291 default: 4292 goto tr_stalled; 4293 } 4294 break; 4295 4296 case UT_WRITE_CLASS_INTERFACE: 4297 case UT_WRITE_VENDOR_INTERFACE: 4298 /* XXX forward */ 4299 break; 4300 4301 case UT_READ_CLASS_INTERFACE: 4302 case UT_READ_VENDOR_INTERFACE: 4303 /* XXX forward */ 4304 break; 4305 4306 case UT_WRITE_CLASS_DEVICE: 4307 switch (req->bRequest) { 4308 case UR_CLEAR_FEATURE: 4309 goto tr_valid; 4310 case UR_SET_DESCRIPTOR: 4311 case UR_SET_FEATURE: 4312 break; 4313 default: 4314 goto tr_stalled; 4315 } 4316 break; 4317 4318 case UT_WRITE_CLASS_OTHER: 4319 switch (req->bRequest) { 4320 case UR_CLEAR_FEATURE: 4321 goto tr_handle_clear_port_feature; 4322 case UR_SET_FEATURE: 4323 goto tr_handle_set_port_feature; 4324 case UR_CLEAR_TT_BUFFER: 4325 case UR_RESET_TT: 4326 case UR_STOP_TT: 4327 goto tr_valid; 4328 4329 default: 4330 goto tr_stalled; 4331 } 4332 break; 4333 4334 case UT_READ_CLASS_OTHER: 4335 switch (req->bRequest) { 4336 case UR_GET_TT_STATE: 4337 goto tr_handle_get_tt_state; 4338 case UR_GET_STATUS: 4339 goto tr_handle_get_port_status; 4340 default: 4341 goto tr_stalled; 4342 } 4343 break; 4344 4345 case UT_READ_CLASS_DEVICE: 4346 switch (req->bRequest) { 4347 case UR_GET_DESCRIPTOR: 4348 goto tr_handle_get_class_descriptor; 4349 case UR_GET_STATUS: 4350 goto tr_handle_get_class_status; 4351 4352 default: 4353 goto tr_stalled; 4354 } 4355 break; 4356 default: 4357 goto tr_stalled; 4358 } 4359 goto tr_valid; 4360 4361 tr_handle_get_descriptor: 4362 switch (value >> 8) { 4363 case UDESC_DEVICE: 4364 if (value & 0xff) { 4365 goto tr_stalled; 4366 } 4367 len = sizeof(dwc_otg_devd); 4368 ptr = (const void *)&dwc_otg_devd; 4369 goto tr_valid; 4370 case UDESC_CONFIG: 4371 if (value & 0xff) { 4372 goto tr_stalled; 4373 } 4374 len = sizeof(dwc_otg_confd); 4375 ptr = (const void *)&dwc_otg_confd; 4376 goto tr_valid; 4377 case UDESC_STRING: 4378 switch (value & 0xff) { 4379 case 0: /* Language table */ 4380 len = sizeof(usb_string_lang_en); 4381 ptr = (const void *)&usb_string_lang_en; 4382 goto tr_valid; 4383 4384 case 1: /* Vendor */ 4385 len = sizeof(dwc_otg_vendor); 4386 ptr = (const void *)&dwc_otg_vendor; 4387 goto tr_valid; 4388 4389 case 2: /* Product */ 4390 len = sizeof(dwc_otg_product); 4391 ptr = (const void *)&dwc_otg_product; 4392 goto tr_valid; 4393 default: 4394 break; 4395 } 4396 break; 4397 default: 4398 goto tr_stalled; 4399 } 4400 goto tr_stalled; 4401 4402 tr_handle_get_config: 4403 len = 1; 4404 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4405 goto tr_valid; 4406 4407 tr_handle_get_status: 4408 len = 2; 4409 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4410 goto tr_valid; 4411 4412 tr_handle_set_address: 4413 if (value & 0xFF00) { 4414 goto tr_stalled; 4415 } 4416 sc->sc_rt_addr = value; 4417 goto tr_valid; 4418 4419 tr_handle_set_config: 4420 if (value >= 2) { 4421 goto tr_stalled; 4422 } 4423 sc->sc_conf = value; 4424 goto tr_valid; 4425 4426 tr_handle_get_interface: 4427 len = 1; 4428 sc->sc_hub_temp.wValue[0] = 0; 4429 goto tr_valid; 4430 4431 tr_handle_get_tt_state: 4432 tr_handle_get_class_status: 4433 tr_handle_get_iface_status: 4434 tr_handle_get_ep_status: 4435 len = 2; 4436 USETW(sc->sc_hub_temp.wValue, 0); 4437 goto tr_valid; 4438 4439 tr_handle_set_halt: 4440 tr_handle_set_interface: 4441 tr_handle_set_wakeup: 4442 tr_handle_clear_wakeup: 4443 tr_handle_clear_halt: 4444 goto tr_valid; 4445 4446 tr_handle_clear_port_feature: 4447 if (index != 1) 4448 goto tr_stalled; 4449 4450 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4451 4452 switch (value) { 4453 case UHF_PORT_SUSPEND: 4454 dwc_otg_wakeup_peer(sc); 4455 break; 4456 4457 case UHF_PORT_ENABLE: 4458 if (sc->sc_flags.status_device_mode == 0) { 4459 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4460 sc->sc_hprt_val | HPRT_PRTENA); 4461 } 4462 sc->sc_flags.port_enabled = 0; 4463 break; 4464 4465 case UHF_C_PORT_RESET: 4466 sc->sc_flags.change_reset = 0; 4467 break; 4468 4469 case UHF_C_PORT_ENABLE: 4470 sc->sc_flags.change_enabled = 0; 4471 break; 4472 4473 case UHF_C_PORT_OVER_CURRENT: 4474 sc->sc_flags.change_over_current = 0; 4475 break; 4476 4477 case UHF_PORT_TEST: 4478 case UHF_PORT_INDICATOR: 4479 /* nops */ 4480 break; 4481 4482 case UHF_PORT_POWER: 4483 sc->sc_flags.port_powered = 0; 4484 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4485 sc->sc_hprt_val = 0; 4486 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4487 } 4488 dwc_otg_pull_down(sc); 4489 dwc_otg_clocks_off(sc); 4490 break; 4491 4492 case UHF_C_PORT_CONNECTION: 4493 /* clear connect change flag */ 4494 sc->sc_flags.change_connect = 0; 4495 break; 4496 4497 case UHF_C_PORT_SUSPEND: 4498 sc->sc_flags.change_suspend = 0; 4499 break; 4500 4501 default: 4502 err = USB_ERR_IOERROR; 4503 goto done; 4504 } 4505 goto tr_valid; 4506 4507 tr_handle_set_port_feature: 4508 if (index != 1) { 4509 goto tr_stalled; 4510 } 4511 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4512 4513 switch (value) { 4514 case UHF_PORT_ENABLE: 4515 break; 4516 4517 case UHF_PORT_SUSPEND: 4518 if (sc->sc_flags.status_device_mode == 0) { 4519 /* set suspend BIT */ 4520 sc->sc_hprt_val |= HPRT_PRTSUSP; 4521 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4522 4523 /* generate HUB suspend event */ 4524 dwc_otg_suspend_irq(sc); 4525 } 4526 break; 4527 4528 case UHF_PORT_RESET: 4529 if (sc->sc_flags.status_device_mode == 0) { 4530 4531 DPRINTF("PORT RESET\n"); 4532 4533 /* enable PORT reset */ 4534 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4535 4536 /* Wait 62.5ms for reset to complete */ 4537 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4538 4539 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4540 4541 /* Wait 62.5ms for reset to complete */ 4542 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4543 4544 /* reset FIFOs */ 4545 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4546 4547 sc->sc_flags.change_reset = 1; 4548 } else { 4549 err = USB_ERR_IOERROR; 4550 } 4551 break; 4552 4553 case UHF_PORT_TEST: 4554 case UHF_PORT_INDICATOR: 4555 /* nops */ 4556 break; 4557 case UHF_PORT_POWER: 4558 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4559 sc->sc_hprt_val |= HPRT_PRTPWR; 4560 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4561 } 4562 sc->sc_flags.port_powered = 1; 4563 break; 4564 default: 4565 err = USB_ERR_IOERROR; 4566 goto done; 4567 } 4568 goto tr_valid; 4569 4570 tr_handle_get_port_status: 4571 4572 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4573 4574 if (index != 1) 4575 goto tr_stalled; 4576 4577 if (sc->sc_flags.status_vbus) 4578 dwc_otg_clocks_on(sc); 4579 else 4580 dwc_otg_clocks_off(sc); 4581 4582 /* Select Device Side Mode */ 4583 4584 if (sc->sc_flags.status_device_mode) { 4585 value = UPS_PORT_MODE_DEVICE; 4586 dwc_otg_timer_stop(sc); 4587 } else { 4588 value = 0; 4589 dwc_otg_timer_start(sc); 4590 } 4591 4592 if (sc->sc_flags.status_high_speed) 4593 value |= UPS_HIGH_SPEED; 4594 else if (sc->sc_flags.status_low_speed) 4595 value |= UPS_LOW_SPEED; 4596 4597 if (sc->sc_flags.port_powered) 4598 value |= UPS_PORT_POWER; 4599 4600 if (sc->sc_flags.port_enabled) 4601 value |= UPS_PORT_ENABLED; 4602 4603 if (sc->sc_flags.port_over_current) 4604 value |= UPS_OVERCURRENT_INDICATOR; 4605 4606 if (sc->sc_flags.status_vbus && 4607 sc->sc_flags.status_bus_reset) 4608 value |= UPS_CURRENT_CONNECT_STATUS; 4609 4610 if (sc->sc_flags.status_suspend) 4611 value |= UPS_SUSPEND; 4612 4613 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4614 4615 value = 0; 4616 4617 if (sc->sc_flags.change_connect) 4618 value |= UPS_C_CONNECT_STATUS; 4619 if (sc->sc_flags.change_suspend) 4620 value |= UPS_C_SUSPEND; 4621 if (sc->sc_flags.change_reset) 4622 value |= UPS_C_PORT_RESET; 4623 if (sc->sc_flags.change_over_current) 4624 value |= UPS_C_OVERCURRENT_INDICATOR; 4625 4626 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4627 len = sizeof(sc->sc_hub_temp.ps); 4628 goto tr_valid; 4629 4630 tr_handle_get_class_descriptor: 4631 if (value & 0xFF) { 4632 goto tr_stalled; 4633 } 4634 ptr = (const void *)&dwc_otg_hubd; 4635 len = sizeof(dwc_otg_hubd); 4636 goto tr_valid; 4637 4638 tr_stalled: 4639 err = USB_ERR_STALLED; 4640 tr_valid: 4641 done: 4642 *plength = len; 4643 *pptr = ptr; 4644 return (err); 4645 } 4646 4647 static void 4648 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4649 { 4650 struct usb_xfer *xfer; 4651 void *last_obj; 4652 uint32_t ntd; 4653 uint32_t n; 4654 uint8_t ep_no; 4655 uint8_t ep_type; 4656 4657 xfer = parm->curr_xfer; 4658 4659 /* 4660 * NOTE: This driver does not use any of the parameters that 4661 * are computed from the following values. Just set some 4662 * reasonable dummies: 4663 */ 4664 parm->hc_max_packet_size = 0x500; 4665 parm->hc_max_packet_count = 3; 4666 parm->hc_max_frame_size = 3 * 0x500; 4667 4668 usbd_transfer_setup_sub(parm); 4669 4670 /* 4671 * compute maximum number of TDs 4672 */ 4673 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4674 4675 if (ep_type == UE_CONTROL) { 4676 4677 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4678 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4679 } else { 4680 4681 ntd = xfer->nframes + 1 /* SYNC */ ; 4682 } 4683 4684 /* 4685 * check if "usbd_transfer_setup_sub" set an error 4686 */ 4687 if (parm->err) 4688 return; 4689 4690 /* 4691 * allocate transfer descriptors 4692 */ 4693 last_obj = NULL; 4694 4695 ep_no = xfer->endpointno & UE_ADDR; 4696 4697 /* 4698 * Check for a valid endpoint profile in USB device mode: 4699 */ 4700 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4701 const struct usb_hw_ep_profile *pf; 4702 4703 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4704 4705 if (pf == NULL) { 4706 /* should not happen */ 4707 parm->err = USB_ERR_INVAL; 4708 return; 4709 } 4710 } 4711 4712 /* align data */ 4713 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4714 4715 for (n = 0; n != ntd; n++) { 4716 4717 struct dwc_otg_td *td; 4718 4719 if (parm->buf) { 4720 4721 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4722 4723 /* compute shared bandwidth resource index for TT */ 4724 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4725 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4726 td->tt_index = parm->udev->device_index; 4727 else 4728 td->tt_index = parm->udev->parent_hs_hub->device_index; 4729 } else { 4730 td->tt_index = parm->udev->device_index; 4731 } 4732 4733 /* init TD */ 4734 td->max_packet_size = xfer->max_packet_size; 4735 td->max_packet_count = xfer->max_packet_count; 4736 td->ep_no = ep_no; 4737 td->ep_type = ep_type; 4738 td->obj_next = last_obj; 4739 4740 last_obj = td; 4741 } 4742 parm->size[0] += sizeof(*td); 4743 } 4744 4745 xfer->td_start[0] = last_obj; 4746 } 4747 4748 static void 4749 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4750 { 4751 return; 4752 } 4753 4754 static void 4755 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4756 struct usb_endpoint *ep) 4757 { 4758 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4759 4760 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4761 ep, udev->address, 4762 edesc->bEndpointAddress, udev->flags.usb_mode, 4763 sc->sc_rt_addr, udev->device_index); 4764 4765 if (udev->device_index != sc->sc_rt_addr) { 4766 4767 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4768 if (udev->speed != USB_SPEED_FULL && 4769 udev->speed != USB_SPEED_HIGH) { 4770 /* not supported */ 4771 return; 4772 } 4773 } else { 4774 if (udev->speed == USB_SPEED_HIGH) { 4775 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4776 /* high bandwidth endpoint - not tested */ 4777 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4778 return; 4779 } 4780 } 4781 } 4782 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4783 ep->methods = &dwc_otg_device_isoc_methods; 4784 else 4785 ep->methods = &dwc_otg_device_non_isoc_methods; 4786 } 4787 } 4788 4789 static void 4790 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4791 { 4792 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4793 4794 switch (state) { 4795 case USB_HW_POWER_SUSPEND: 4796 dwc_otg_suspend(sc); 4797 break; 4798 case USB_HW_POWER_SHUTDOWN: 4799 dwc_otg_uninit(sc); 4800 break; 4801 case USB_HW_POWER_RESUME: 4802 dwc_otg_resume(sc); 4803 break; 4804 default: 4805 break; 4806 } 4807 } 4808 4809 static void 4810 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4811 { 4812 /* DMA delay - wait until any use of memory is finished */ 4813 *pus = (2125); /* microseconds */ 4814 } 4815 4816 static void 4817 dwc_otg_device_resume(struct usb_device *udev) 4818 { 4819 DPRINTF("\n"); 4820 4821 /* poll all transfers again to restart resumed ones */ 4822 dwc_otg_do_poll(udev->bus); 4823 } 4824 4825 static void 4826 dwc_otg_device_suspend(struct usb_device *udev) 4827 { 4828 DPRINTF("\n"); 4829 } 4830 4831 static const struct usb_bus_methods dwc_otg_bus_methods = 4832 { 4833 .endpoint_init = &dwc_otg_ep_init, 4834 .xfer_setup = &dwc_otg_xfer_setup, 4835 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4836 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4837 .xfer_stall = &dwc_otg_xfer_stall, 4838 .set_stall = &dwc_otg_set_stall, 4839 .clear_stall = &dwc_otg_clear_stall, 4840 .roothub_exec = &dwc_otg_roothub_exec, 4841 .xfer_poll = &dwc_otg_do_poll, 4842 .device_state_change = &dwc_otg_device_state_change, 4843 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4844 .get_dma_delay = &dwc_otg_get_dma_delay, 4845 .device_resume = &dwc_otg_device_resume, 4846 .device_suspend = &dwc_otg_device_suspend, 4847 }; 4848