1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org> 5 * Copyright (c) 2021-2022 Bjoern A. Zeeb <bz@FreeBSD.ORG> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_platform.h" 31 #include "opt_acpi.h" 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/condvar.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #ifdef FDT 42 #include <sys/gpio.h> 43 #endif 44 45 #include <machine/bus.h> 46 47 #include <dev/usb/usb.h> 48 #include <dev/usb/usbdi.h> 49 50 #include <dev/usb/usb_core.h> 51 #include <dev/usb/usb_busdma.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/generic_xhci.h> 57 #include <dev/usb/controller/xhci.h> 58 #include <dev/usb/controller/dwc3/dwc3.h> 59 60 #ifdef FDT 61 #include <dev/fdt/simplebus.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 #include <dev/ofw/ofw_subr.h> 67 68 #include <dev/clk/clk.h> 69 #include <dev/phy/phy_usb.h> 70 #endif 71 72 #ifdef DEV_ACPI 73 #include <contrib/dev/acpica/include/acpi.h> 74 #include <contrib/dev/acpica/include/accommon.h> 75 #include <dev/acpica/acpivar.h> 76 #endif 77 78 struct snps_dwc3_softc { 79 struct xhci_softc sc; 80 device_t dev; 81 struct resource * mem_res; 82 bus_space_tag_t bst; 83 bus_space_handle_t bsh; 84 uint32_t snpsid; 85 uint32_t snpsversion; 86 uint32_t snpsrevision; 87 uint32_t snpsversion_type; 88 #ifdef FDT 89 clk_t clk_ref; 90 clk_t clk_suspend; 91 clk_t clk_bus; 92 #endif 93 }; 94 95 #define DWC3_WRITE(_sc, _off, _val) \ 96 bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) 97 #define DWC3_READ(_sc, _off) \ 98 bus_space_read_4(_sc->bst, _sc->bsh, _off) 99 100 #define IS_DMA_32B 1 101 102 static void 103 xhci_interrupt_poll(void *_sc) 104 { 105 struct xhci_softc *sc = _sc; 106 107 USB_BUS_UNLOCK(&sc->sc_bus); 108 xhci_interrupt(sc); 109 USB_BUS_LOCK(&sc->sc_bus); 110 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 111 } 112 113 static int 114 snps_dwc3_attach_xhci(device_t dev) 115 { 116 struct snps_dwc3_softc *snps_sc = device_get_softc(dev); 117 struct xhci_softc *sc = &snps_sc->sc; 118 int err = 0, rid = 0; 119 120 sc->sc_io_res = snps_sc->mem_res; 121 sc->sc_io_tag = snps_sc->bst; 122 sc->sc_io_hdl = snps_sc->bsh; 123 sc->sc_io_size = rman_get_size(snps_sc->mem_res); 124 125 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 126 RF_SHAREABLE | RF_ACTIVE); 127 if (sc->sc_irq_res == NULL) { 128 device_printf(dev, "Failed to allocate IRQ\n"); 129 return (ENXIO); 130 } 131 132 sc->sc_bus.bdev = device_add_child(dev, "usbus", DEVICE_UNIT_ANY); 133 if (sc->sc_bus.bdev == NULL) { 134 device_printf(dev, "Failed to add USB device\n"); 135 return (ENXIO); 136 } 137 138 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 139 140 sprintf(sc->sc_vendor, "Synopsys"); 141 device_set_desc(sc->sc_bus.bdev, "Synopsys"); 142 143 if (xhci_use_polling() == 0) { 144 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 145 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 146 if (err != 0) { 147 device_printf(dev, "Failed to setup IRQ, %d\n", err); 148 sc->sc_intr_hdl = NULL; 149 return (err); 150 } 151 } 152 153 err = xhci_init(sc, dev, IS_DMA_32B); 154 if (err != 0) { 155 device_printf(dev, "Failed to init XHCI, with error %d\n", err); 156 return (ENXIO); 157 } 158 159 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 160 161 if (xhci_use_polling() != 0) { 162 device_printf(dev, "Interrupt polling at %dHz\n", hz); 163 USB_BUS_LOCK(&sc->sc_bus); 164 xhci_interrupt_poll(sc); 165 USB_BUS_UNLOCK(&sc->sc_bus); 166 } 167 168 err = xhci_start_controller(sc); 169 if (err != 0) { 170 device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); 171 return (ENXIO); 172 } 173 174 device_printf(sc->sc_bus.bdev, "trying to attach\n"); 175 err = device_probe_and_attach(sc->sc_bus.bdev); 176 if (err != 0) { 177 device_printf(dev, "Failed to initialize USB, with error %d\n", err); 178 return (ENXIO); 179 } 180 181 return (0); 182 } 183 184 #ifdef DWC3_DEBUG 185 static void 186 snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc, const char *msg) 187 { 188 struct xhci_softc *xsc; 189 uint32_t reg; 190 191 if (!bootverbose) 192 return; 193 194 device_printf(sc->dev, "%s: %s:\n", __func__, msg ? msg : ""); 195 196 reg = DWC3_READ(sc, DWC3_GCTL); 197 device_printf(sc->dev, "GCTL: %#012x\n", reg); 198 reg = DWC3_READ(sc, DWC3_GUCTL); 199 device_printf(sc->dev, "GUCTL: %#012x\n", reg); 200 reg = DWC3_READ(sc, DWC3_GUCTL1); 201 device_printf(sc->dev, "GUCTL1: %#012x\n", reg); 202 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 203 device_printf(sc->dev, "GUSB2PHYCFG0: %#012x\n", reg); 204 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 205 device_printf(sc->dev, "GUSB3PIPECTL0: %#012x\n", reg); 206 reg = DWC3_READ(sc, DWC3_DCFG); 207 device_printf(sc->dev, "DCFG: %#012x\n", reg); 208 209 xsc = &sc->sc; 210 device_printf(sc->dev, "xhci quirks: %#012x\n", xsc->sc_quirks); 211 } 212 213 static void 214 snps_dwc3_dump_ctrlparams(struct snps_dwc3_softc *sc) 215 { 216 const bus_size_t offs[] = { 217 DWC3_GHWPARAMS0, DWC3_GHWPARAMS1, DWC3_GHWPARAMS2, DWC3_GHWPARAMS3, 218 DWC3_GHWPARAMS4, DWC3_GHWPARAMS5, DWC3_GHWPARAMS6, DWC3_GHWPARAMS7, 219 DWC3_GHWPARAMS8, 220 }; 221 uint32_t reg; 222 int i; 223 224 for (i = 0; i < nitems(offs); i++) { 225 reg = DWC3_READ(sc, offs[i]); 226 if (bootverbose) 227 device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg); 228 } 229 } 230 #endif 231 232 static void 233 snps_dwc3_reset(struct snps_dwc3_softc *sc) 234 { 235 uint32_t gctl, ghwp0, phy2, phy3; 236 237 ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); 238 239 gctl = DWC3_READ(sc, DWC3_GCTL); 240 gctl |= DWC3_GCTL_CORESOFTRESET; 241 DWC3_WRITE(sc, DWC3_GCTL, gctl); 242 243 phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 244 phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; 245 if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 246 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 247 phy2 &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 248 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 249 250 phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 251 phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; 252 if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 253 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 254 phy3 &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 255 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 256 257 DELAY(1000); 258 259 phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; 260 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); 261 262 phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; 263 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); 264 265 gctl &= ~DWC3_GCTL_CORESOFTRESET; 266 DWC3_WRITE(sc, DWC3_GCTL, gctl); 267 268 } 269 270 static void 271 snps_dwc3_configure_host(struct snps_dwc3_softc *sc) 272 { 273 uint32_t reg; 274 275 reg = DWC3_READ(sc, DWC3_GCTL); 276 reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; 277 reg |= DWC3_GCTL_PRTCAPDIR_HOST; 278 DWC3_WRITE(sc, DWC3_GCTL, reg); 279 280 /* 281 * Enable the Host IN Auto Retry feature, making the 282 * host respond with a non-terminating retry ACK. 283 * XXX If we ever support more than host mode this needs a dr_mode check. 284 */ 285 reg = DWC3_READ(sc, DWC3_GUCTL); 286 reg |= DWC3_GUCTL_HOST_AUTO_RETRY; 287 DWC3_WRITE(sc, DWC3_GUCTL, reg); 288 } 289 290 #ifdef FDT 291 static void 292 snps_dwc3_configure_phy(struct snps_dwc3_softc *sc, phandle_t node) 293 { 294 char *phy_type; 295 uint32_t reg; 296 int nphy_types; 297 298 phy_type = NULL; 299 nphy_types = OF_getprop_alloc(node, "phy_type", (void **)&phy_type); 300 if (nphy_types <= 0) 301 return; 302 303 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 304 if (strncmp(phy_type, "utmi_wide", 9) == 0) { 305 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 306 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 307 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); 308 } else { 309 reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); 310 reg |= DWC3_GUSB2PHYCFG0_PHYIF | 311 DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); 312 } 313 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 314 OF_prop_free(phy_type); 315 } 316 #endif 317 318 static void 319 snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) 320 { 321 struct xhci_softc *xsc; 322 uint32_t ghwp0, reg; 323 324 ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); 325 reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); 326 if (device_has_property(sc->dev, "snps,dis-u2-freeclk-exists-quirk")) 327 reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 328 else 329 reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; 330 if (device_has_property(sc->dev, "snps,dis_u2_susphy_quirk")) 331 reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 332 else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 333 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 334 reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; 335 if (device_has_property(sc->dev, "snps,dis_enblslpm_quirk")) 336 reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; 337 else 338 reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; 339 DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); 340 341 reg = DWC3_READ(sc, DWC3_GUCTL1); 342 if (device_has_property(sc->dev, "snps,dis-tx-ipgap-linecheck-quirk")) 343 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 344 DWC3_WRITE(sc, DWC3_GUCTL1, reg); 345 346 reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); 347 if (device_has_property(sc->dev, "snps,dis-del-phy-power-chg-quirk")) 348 reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS; 349 if (device_has_property(sc->dev, "snps,dis_rxdet_inp3_quirk")) 350 reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3; 351 if (device_has_property(sc->dev, "snps,dis_u3_susphy_quirk")) 352 reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 353 else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == 354 DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) 355 reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3; 356 DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); 357 358 /* Port Disable does not work on <= 3.00a. Disable PORT_PED. */ 359 if ((sc->snpsid & 0xffff) <= 0x300a) { 360 xsc = &sc->sc; 361 xsc->sc_quirks |= XHCI_QUIRK_DISABLE_PORT_PED; 362 } 363 } 364 365 static int 366 snps_dwc3_probe_common(device_t dev) 367 { 368 char dr_mode[16] = { 0 }; 369 ssize_t s; 370 371 s = device_get_property(dev, "dr_mode", dr_mode, sizeof(dr_mode), 372 DEVICE_PROP_BUFFER); 373 if (s == -1) { 374 device_printf(dev, "Cannot determine dr_mode\n"); 375 return (ENXIO); 376 } 377 if (strcmp(dr_mode, "host") != 0) { 378 device_printf(dev, 379 "Found dr_mode '%s' but only 'host' supported. s=%zd\n", 380 dr_mode, s); 381 return (ENXIO); 382 } 383 384 device_set_desc(dev, "Synopsys Designware DWC3"); 385 return (BUS_PROBE_DEFAULT); 386 } 387 388 static int 389 snps_dwc3_common_attach(device_t dev, bool is_fdt) 390 { 391 struct snps_dwc3_softc *sc; 392 #ifdef FDT 393 phandle_t node; 394 phy_t usb2_phy, usb3_phy; 395 uint32_t reg; 396 #endif 397 int error, rid; 398 399 sc = device_get_softc(dev); 400 sc->dev = dev; 401 402 rid = 0; 403 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 404 RF_ACTIVE); 405 if (sc->mem_res == NULL) { 406 device_printf(dev, "Failed to map memory\n"); 407 return (ENXIO); 408 } 409 sc->bst = rman_get_bustag(sc->mem_res); 410 sc->bsh = rman_get_bushandle(sc->mem_res); 411 412 sc->snpsid = DWC3_READ(sc, DWC3_GSNPSID); 413 sc->snpsversion = DWC3_VERSION(sc->snpsid); 414 sc->snpsrevision = DWC3_REVISION(sc->snpsid); 415 if (sc->snpsversion == DWC3_1_IP_ID || 416 sc->snpsversion == DWC3_2_IP_ID) { 417 sc->snpsrevision = DWC3_READ(sc, DWC3_1_VER_NUMBER); 418 sc->snpsversion_type = DWC3_READ(sc, DWC3_1_VER_TYPE); 419 } 420 if (bootverbose) { 421 switch (sc->snpsversion) { 422 case DWC3_IP_ID: 423 device_printf(sc->dev, "SNPS Version: DWC3 (%x %x)\n", 424 sc->snpsversion, sc->snpsrevision); 425 break; 426 case DWC3_1_IP_ID: 427 device_printf(sc->dev, "SNPS Version: DWC3.1 (%x %x %x)\n", 428 sc->snpsversion, sc->snpsrevision, 429 sc->snpsversion_type); 430 break; 431 case DWC3_2_IP_ID: 432 device_printf(sc->dev, "SNPS Version: DWC3.2 (%x %x %x)\n", 433 sc->snpsversion, sc->snpsrevision, 434 sc->snpsversion_type); 435 break; 436 } 437 } 438 #ifdef DWC3_DEBUG 439 snps_dwc3_dump_ctrlparams(sc); 440 #endif 441 442 #ifdef FDT 443 if (!is_fdt) 444 goto skip_phys; 445 446 node = ofw_bus_get_node(dev); 447 448 /* Get the clocks if any */ 449 if (ofw_bus_is_compatible(dev, "rockchip,rk3328-dwc3") == 1 || 450 ofw_bus_is_compatible(dev, "rockchip,rk3568-dwc3") == 1) { 451 if (clk_get_by_ofw_name(dev, node, "ref_clk", &sc->clk_ref) != 0) 452 device_printf(dev, "Cannot get ref_clk\n"); 453 if (clk_get_by_ofw_name(dev, node, "suspend_clk", &sc->clk_suspend) != 0) 454 device_printf(dev, "Cannot get suspend_clk\n"); 455 if (clk_get_by_ofw_name(dev, node, "bus_clk", &sc->clk_bus) != 0) 456 device_printf(dev, "Cannot get bus_clk\n"); 457 } 458 459 if (sc->clk_ref != NULL) { 460 if (clk_enable(sc->clk_ref) != 0) 461 device_printf(dev, "Cannot enable ref_clk\n"); 462 } 463 if (sc->clk_suspend != NULL) { 464 if (clk_enable(sc->clk_suspend) != 0) 465 device_printf(dev, "Cannot enable suspend_clk\n"); 466 } 467 if (sc->clk_bus != NULL) { 468 if (clk_enable(sc->clk_bus) != 0) 469 device_printf(dev, "Cannot enable bus_clk\n"); 470 } 471 472 /* Get the phys */ 473 usb2_phy = usb3_phy = NULL; 474 error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); 475 if (error == 0 && usb2_phy != NULL) 476 phy_enable(usb2_phy); 477 error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); 478 if (error == 0 && usb3_phy != NULL) 479 phy_enable(usb3_phy); 480 if (sc->snpsversion == DWC3_IP_ID) { 481 if (sc->snpsrevision >= 0x290A) { 482 uint32_t hwparams3; 483 484 hwparams3 = DWC3_READ(sc, DWC3_GHWPARAMS3); 485 if (DWC3_HWPARAMS3_SSPHY(hwparams3) == DWC3_HWPARAMS3_SSPHY_DISABLE) { 486 reg = DWC3_READ(sc, DWC3_GUCTL1); 487 if (bootverbose) 488 device_printf(dev, "Forcing USB2 clock only\n"); 489 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 490 DWC3_WRITE(sc, DWC3_GUCTL1, reg); 491 } 492 } 493 } 494 snps_dwc3_configure_phy(sc, node); 495 skip_phys: 496 #endif 497 498 snps_dwc3_reset(sc); 499 snps_dwc3_configure_host(sc); 500 snps_dwc3_do_quirks(sc); 501 502 #ifdef DWC3_DEBUG 503 snsp_dwc3_dump_regs(sc, "Pre XHCI init"); 504 #endif 505 error = snps_dwc3_attach_xhci(dev); 506 #ifdef DWC3_DEBUG 507 snsp_dwc3_dump_regs(sc, "Post XHCI init"); 508 #endif 509 510 #ifdef FDT 511 if (error) { 512 if (sc->clk_ref != NULL) 513 clk_disable(sc->clk_ref); 514 if (sc->clk_suspend != NULL) 515 clk_disable(sc->clk_suspend); 516 if (sc->clk_bus != NULL) 517 clk_disable(sc->clk_bus); 518 } 519 #endif 520 return (error); 521 } 522 523 #ifdef FDT 524 static struct ofw_compat_data compat_data[] = { 525 { "snps,dwc3", 1 }, 526 { NULL, 0 } 527 }; 528 529 static int 530 snps_dwc3_fdt_probe(device_t dev) 531 { 532 533 if (!ofw_bus_status_okay(dev)) 534 return (ENXIO); 535 536 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 537 return (ENXIO); 538 539 return (snps_dwc3_probe_common(dev)); 540 } 541 542 static int 543 snps_dwc3_fdt_attach(device_t dev) 544 { 545 546 return (snps_dwc3_common_attach(dev, true)); 547 } 548 549 static device_method_t snps_dwc3_fdt_methods[] = { 550 /* Device interface */ 551 DEVMETHOD(device_probe, snps_dwc3_fdt_probe), 552 DEVMETHOD(device_attach, snps_dwc3_fdt_attach), 553 554 DEVMETHOD_END 555 }; 556 557 DEFINE_CLASS_1(snps_dwc3_fdt, snps_dwc3_fdt_driver, snps_dwc3_fdt_methods, 558 sizeof(struct snps_dwc3_softc), generic_xhci_driver); 559 560 DRIVER_MODULE(snps_dwc3_fdt, simplebus, snps_dwc3_fdt_driver, 0, 0); 561 MODULE_DEPEND(snps_dwc3_fdt, xhci, 1, 1, 1); 562 #endif 563 564 #ifdef DEV_ACPI 565 static char *dwc3_acpi_ids[] = { 566 "808622B7", /* This was an Intel PCI Vendor/Device ID used. */ 567 "PNP0D10", /* The generic XHCI PNP ID needing extra probe checks. */ 568 NULL 569 }; 570 571 static int 572 snps_dwc3_acpi_probe(device_t dev) 573 { 574 char *match; 575 int error; 576 577 if (acpi_disabled("snps_dwc3")) 578 return (ENXIO); 579 580 error = ACPI_ID_PROBE(device_get_parent(dev), dev, dwc3_acpi_ids, &match); 581 if (error > 0) 582 return (ENXIO); 583 584 /* 585 * If we found the Generic XHCI PNP ID we can only attach if we have 586 * some other means to identify the device as dwc3. 587 */ 588 if (strcmp(match, "PNP0D10") == 0) { 589 /* This is needed in SolidRun's HoneyComb. */ 590 if (device_has_property(dev, "snps,dis_rxdet_inp3_quirk")) 591 goto is_dwc3; 592 593 return (ENXIO); 594 } 595 596 is_dwc3: 597 return (snps_dwc3_probe_common(dev)); 598 } 599 600 static int 601 snps_dwc3_acpi_attach(device_t dev) 602 { 603 604 return (snps_dwc3_common_attach(dev, false)); 605 } 606 607 static device_method_t snps_dwc3_acpi_methods[] = { 608 /* Device interface */ 609 DEVMETHOD(device_probe, snps_dwc3_acpi_probe), 610 DEVMETHOD(device_attach, snps_dwc3_acpi_attach), 611 612 DEVMETHOD_END 613 }; 614 615 DEFINE_CLASS_1(snps_dwc3_acpi, snps_dwc3_acpi_driver, snps_dwc3_acpi_methods, 616 sizeof(struct snps_dwc3_softc), generic_xhci_driver); 617 618 DRIVER_MODULE(snps_dwc3_acpi, acpi, snps_dwc3_acpi_driver, 0, 0); 619 MODULE_DEPEND(snps_dwc3_acpi, usb, 1, 1, 1); 620 #endif 621