1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the AVR32 series USB Device 29 * Controller 30 */ 31 32 /* 33 * NOTE: When the chip detects BUS-reset it will also reset the 34 * endpoints, Function-address and more. 35 */ 36 #ifdef USB_GLOBAL_INCLUDE_FILE 37 #include USB_GLOBAL_INCLUDE_FILE 38 #else 39 #include <sys/stdint.h> 40 #include <sys/stddef.h> 41 #include <sys/param.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sx.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 61 #define USB_DEBUG_VAR avr32dci_debug 62 63 #include <dev/usb/usb_core.h> 64 #include <dev/usb/usb_debug.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_transfer.h> 68 #include <dev/usb/usb_device.h> 69 #include <dev/usb/usb_hub.h> 70 #include <dev/usb/usb_util.h> 71 72 #include <dev/usb/usb_controller.h> 73 #include <dev/usb/usb_bus.h> 74 #endif /* USB_GLOBAL_INCLUDE_FILE */ 75 76 #include <dev/usb/controller/avr32dci.h> 77 78 #define AVR32_BUS2SC(bus) \ 79 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ 80 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) 81 82 #define AVR32_PC2SC(pc) \ 83 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 84 85 #ifdef USB_DEBUG 86 static int avr32dci_debug = 0; 87 88 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI"); 89 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW, 90 &avr32dci_debug, 0, "AVR32 DCI debug level"); 91 #endif 92 93 #define AVR32_INTR_ENDPT 1 94 95 /* prototypes */ 96 97 static const struct usb_bus_methods avr32dci_bus_methods; 98 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 99 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 100 101 static avr32dci_cmd_t avr32dci_setup_rx; 102 static avr32dci_cmd_t avr32dci_data_rx; 103 static avr32dci_cmd_t avr32dci_data_tx; 104 static avr32dci_cmd_t avr32dci_data_tx_sync; 105 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 106 static void avr32dci_do_poll(struct usb_bus *); 107 static void avr32dci_standard_done(struct usb_xfer *); 108 static void avr32dci_root_intr(struct avr32dci_softc *sc); 109 110 /* 111 * Here is a list of what the chip supports: 112 */ 113 static const struct usb_hw_ep_profile 114 avr32dci_ep_profile[4] = { 115 116 [0] = { 117 .max_in_frame_size = 64, 118 .max_out_frame_size = 64, 119 .is_simplex = 1, 120 .support_control = 1, 121 }, 122 123 [1] = { 124 .max_in_frame_size = 512, 125 .max_out_frame_size = 512, 126 .is_simplex = 1, 127 .support_bulk = 1, 128 .support_interrupt = 1, 129 .support_isochronous = 1, 130 .support_in = 1, 131 .support_out = 1, 132 }, 133 134 [2] = { 135 .max_in_frame_size = 64, 136 .max_out_frame_size = 64, 137 .is_simplex = 1, 138 .support_bulk = 1, 139 .support_interrupt = 1, 140 .support_in = 1, 141 .support_out = 1, 142 }, 143 144 [3] = { 145 .max_in_frame_size = 1024, 146 .max_out_frame_size = 1024, 147 .is_simplex = 1, 148 .support_bulk = 1, 149 .support_interrupt = 1, 150 .support_isochronous = 1, 151 .support_in = 1, 152 .support_out = 1, 153 }, 154 }; 155 156 static void 157 avr32dci_get_hw_ep_profile(struct usb_device *udev, 158 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 159 { 160 if (ep_addr == 0) 161 *ppf = avr32dci_ep_profile; 162 else if (ep_addr < 3) 163 *ppf = avr32dci_ep_profile + 1; 164 else if (ep_addr < 5) 165 *ppf = avr32dci_ep_profile + 2; 166 else if (ep_addr < 7) 167 *ppf = avr32dci_ep_profile + 3; 168 else 169 *ppf = NULL; 170 } 171 172 static void 173 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 174 { 175 uint32_t temp; 176 177 temp = AVR32_READ_4(sc, AVR32_CTRL); 178 temp |= set; 179 temp &= ~clear; 180 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 181 } 182 183 static void 184 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 185 { 186 uint32_t temp; 187 188 temp = AVR32_READ_4(sc, AVR32_IEN); 189 temp |= set; 190 temp &= ~clear; 191 AVR32_WRITE_4(sc, AVR32_IEN, temp); 192 } 193 194 static void 195 avr32dci_clocks_on(struct avr32dci_softc *sc) 196 { 197 if (sc->sc_flags.clocks_off && 198 sc->sc_flags.port_powered) { 199 200 DPRINTFN(5, "\n"); 201 202 /* turn on clocks */ 203 (sc->sc_clocks_on) (&sc->sc_bus); 204 205 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 206 207 sc->sc_flags.clocks_off = 0; 208 } 209 } 210 211 static void 212 avr32dci_clocks_off(struct avr32dci_softc *sc) 213 { 214 if (!sc->sc_flags.clocks_off) { 215 216 DPRINTFN(5, "\n"); 217 218 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 219 220 /* turn clocks off */ 221 (sc->sc_clocks_off) (&sc->sc_bus); 222 223 sc->sc_flags.clocks_off = 1; 224 } 225 } 226 227 static void 228 avr32dci_pull_up(struct avr32dci_softc *sc) 229 { 230 /* pullup D+, if possible */ 231 232 if (!sc->sc_flags.d_pulled_up && 233 sc->sc_flags.port_powered) { 234 sc->sc_flags.d_pulled_up = 1; 235 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 236 } 237 } 238 239 static void 240 avr32dci_pull_down(struct avr32dci_softc *sc) 241 { 242 /* pulldown D+, if possible */ 243 244 if (sc->sc_flags.d_pulled_up) { 245 sc->sc_flags.d_pulled_up = 0; 246 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 247 } 248 } 249 250 static void 251 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 252 { 253 if (!sc->sc_flags.status_suspend) { 254 return; 255 } 256 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 257 258 /* wait 8 milliseconds */ 259 /* Wait for reset to complete. */ 260 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 261 262 /* hardware should have cleared RMWKUP bit */ 263 } 264 265 static void 266 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 267 { 268 DPRINTFN(5, "addr=%d\n", addr); 269 270 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 271 } 272 273 static uint8_t 274 avr32dci_setup_rx(struct avr32dci_td *td) 275 { 276 struct avr32dci_softc *sc; 277 struct usb_device_request req; 278 uint16_t count; 279 uint32_t temp; 280 281 /* get pointer to softc */ 282 sc = AVR32_PC2SC(td->pc); 283 284 /* check endpoint status */ 285 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 286 287 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 288 289 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 290 goto not_complete; 291 } 292 /* clear did stall */ 293 td->did_stall = 0; 294 /* get the packet byte count */ 295 count = AVR32_EPTSTA_BYTE_COUNT(temp); 296 297 /* verify data length */ 298 if (count != td->remainder) { 299 DPRINTFN(0, "Invalid SETUP packet " 300 "length, %d bytes\n", count); 301 goto not_complete; 302 } 303 if (count != sizeof(req)) { 304 DPRINTFN(0, "Unsupported SETUP packet " 305 "length, %d bytes\n", count); 306 goto not_complete; 307 } 308 /* receive data */ 309 memcpy(&req, sc->physdata, sizeof(req)); 310 311 /* copy data into real buffer */ 312 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 313 314 td->offset = sizeof(req); 315 td->remainder = 0; 316 317 /* sneak peek the set address */ 318 if ((req.bmRequestType == UT_WRITE_DEVICE) && 319 (req.bRequest == UR_SET_ADDRESS)) { 320 sc->sc_dv_addr = req.wValue[0] & 0x7F; 321 /* must write address before ZLP */ 322 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 323 AVR32_CTRL_DEV_ADDR); 324 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 325 } else { 326 sc->sc_dv_addr = 0xFF; 327 } 328 329 /* clear SETUP packet interrupt */ 330 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 331 return (0); /* complete */ 332 333 not_complete: 334 if (temp & AVR32_EPTSTA_RX_SETUP) { 335 /* clear SETUP packet interrupt */ 336 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 337 } 338 /* abort any ongoing transfer */ 339 if (!td->did_stall) { 340 DPRINTFN(5, "stalling\n"); 341 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 342 AVR32_EPTSTA_FRCESTALL); 343 td->did_stall = 1; 344 } 345 return (1); /* not complete */ 346 } 347 348 static uint8_t 349 avr32dci_data_rx(struct avr32dci_td *td) 350 { 351 struct avr32dci_softc *sc; 352 struct usb_page_search buf_res; 353 uint16_t count; 354 uint32_t temp; 355 uint8_t to; 356 uint8_t got_short; 357 358 to = 4; /* don't loop forever! */ 359 got_short = 0; 360 361 /* get pointer to softc */ 362 sc = AVR32_PC2SC(td->pc); 363 364 repeat: 365 /* check if any of the FIFO banks have data */ 366 /* check endpoint status */ 367 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 368 369 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 370 371 if (temp & AVR32_EPTSTA_RX_SETUP) { 372 if (td->remainder == 0) { 373 /* 374 * We are actually complete and have 375 * received the next SETUP 376 */ 377 DPRINTFN(5, "faking complete\n"); 378 return (0); /* complete */ 379 } 380 /* 381 * USB Host Aborted the transfer. 382 */ 383 td->error = 1; 384 return (0); /* complete */ 385 } 386 /* check status */ 387 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 388 /* no data */ 389 goto not_complete; 390 } 391 /* get the packet byte count */ 392 count = AVR32_EPTSTA_BYTE_COUNT(temp); 393 394 /* verify the packet byte count */ 395 if (count != td->max_packet_size) { 396 if (count < td->max_packet_size) { 397 /* we have a short packet */ 398 td->short_pkt = 1; 399 got_short = 1; 400 } else { 401 /* invalid USB packet */ 402 td->error = 1; 403 return (0); /* we are complete */ 404 } 405 } 406 /* verify the packet byte count */ 407 if (count > td->remainder) { 408 /* invalid USB packet */ 409 td->error = 1; 410 return (0); /* we are complete */ 411 } 412 while (count > 0) { 413 usbd_get_page(td->pc, td->offset, &buf_res); 414 415 /* get correct length */ 416 if (buf_res.length > count) { 417 buf_res.length = count; 418 } 419 /* receive data */ 420 memcpy(buf_res.buffer, sc->physdata + 421 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 422 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 423 /* update counters */ 424 count -= buf_res.length; 425 td->offset += buf_res.length; 426 td->remainder -= buf_res.length; 427 } 428 429 /* clear OUT packet interrupt */ 430 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 431 432 /* check if we are complete */ 433 if ((td->remainder == 0) || got_short) { 434 if (td->short_pkt) { 435 /* we are complete */ 436 return (0); 437 } 438 /* else need to receive a zero length packet */ 439 } 440 if (--to) { 441 goto repeat; 442 } 443 not_complete: 444 return (1); /* not complete */ 445 } 446 447 static uint8_t 448 avr32dci_data_tx(struct avr32dci_td *td) 449 { 450 struct avr32dci_softc *sc; 451 struct usb_page_search buf_res; 452 uint16_t count; 453 uint8_t to; 454 uint32_t temp; 455 456 to = 4; /* don't loop forever! */ 457 458 /* get pointer to softc */ 459 sc = AVR32_PC2SC(td->pc); 460 461 repeat: 462 463 /* check endpoint status */ 464 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 465 466 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 467 468 if (temp & AVR32_EPTSTA_RX_SETUP) { 469 /* 470 * The current transfer was aborted 471 * by the USB Host 472 */ 473 td->error = 1; 474 return (0); /* complete */ 475 } 476 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 477 /* cannot write any data - all banks are busy */ 478 goto not_complete; 479 } 480 count = td->max_packet_size; 481 if (td->remainder < count) { 482 /* we have a short packet */ 483 td->short_pkt = 1; 484 count = td->remainder; 485 } 486 while (count > 0) { 487 488 usbd_get_page(td->pc, td->offset, &buf_res); 489 490 /* get correct length */ 491 if (buf_res.length > count) { 492 buf_res.length = count; 493 } 494 /* transmit data */ 495 memcpy(sc->physdata + 496 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 497 (td->ep_no << 16) + (td->offset % td->max_packet_size), 498 buf_res.buffer, buf_res.length); 499 /* update counters */ 500 count -= buf_res.length; 501 td->offset += buf_res.length; 502 td->remainder -= buf_res.length; 503 } 504 505 /* allocate FIFO bank */ 506 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 507 508 /* check remainder */ 509 if (td->remainder == 0) { 510 if (td->short_pkt) { 511 return (0); /* complete */ 512 } 513 /* else we need to transmit a short packet */ 514 } 515 if (--to) { 516 goto repeat; 517 } 518 not_complete: 519 return (1); /* not complete */ 520 } 521 522 static uint8_t 523 avr32dci_data_tx_sync(struct avr32dci_td *td) 524 { 525 struct avr32dci_softc *sc; 526 uint32_t temp; 527 528 /* get pointer to softc */ 529 sc = AVR32_PC2SC(td->pc); 530 531 /* check endpoint status */ 532 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 533 534 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 535 536 if (temp & AVR32_EPTSTA_RX_SETUP) { 537 DPRINTFN(5, "faking complete\n"); 538 /* Race condition */ 539 return (0); /* complete */ 540 } 541 /* 542 * The control endpoint has only got one bank, so if that bank 543 * is free the packet has been transferred! 544 */ 545 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 546 /* cannot write any data - a bank is busy */ 547 goto not_complete; 548 } 549 if (sc->sc_dv_addr != 0xFF) { 550 /* set new address */ 551 avr32dci_set_address(sc, sc->sc_dv_addr); 552 } 553 return (0); /* complete */ 554 555 not_complete: 556 return (1); /* not complete */ 557 } 558 559 static uint8_t 560 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 561 { 562 struct avr32dci_td *td; 563 564 DPRINTFN(9, "\n"); 565 566 td = xfer->td_transfer_cache; 567 while (1) { 568 if ((td->func) (td)) { 569 /* operation in progress */ 570 break; 571 } 572 if (((void *)td) == xfer->td_transfer_last) { 573 goto done; 574 } 575 if (td->error) { 576 goto done; 577 } else if (td->remainder > 0) { 578 /* 579 * We had a short transfer. If there is no alternate 580 * next, stop processing ! 581 */ 582 if (!td->alt_next) { 583 goto done; 584 } 585 } 586 /* 587 * Fetch the next transfer descriptor and transfer 588 * some flags to the next transfer descriptor 589 */ 590 td = td->obj_next; 591 xfer->td_transfer_cache = td; 592 } 593 return (1); /* not complete */ 594 595 done: 596 /* compute all actual lengths */ 597 598 avr32dci_standard_done(xfer); 599 return (0); /* complete */ 600 } 601 602 static void 603 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 604 { 605 struct usb_xfer *xfer; 606 607 repeat: 608 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 609 if (!avr32dci_xfer_do_fifo(xfer)) { 610 /* queue has been modified */ 611 goto repeat; 612 } 613 } 614 } 615 616 void 617 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 618 { 619 DPRINTFN(5, "vbus = %u\n", is_on); 620 621 if (is_on) { 622 if (!sc->sc_flags.status_vbus) { 623 sc->sc_flags.status_vbus = 1; 624 625 /* complete root HUB interrupt endpoint */ 626 627 avr32dci_root_intr(sc); 628 } 629 } else { 630 if (sc->sc_flags.status_vbus) { 631 sc->sc_flags.status_vbus = 0; 632 sc->sc_flags.status_bus_reset = 0; 633 sc->sc_flags.status_suspend = 0; 634 sc->sc_flags.change_suspend = 0; 635 sc->sc_flags.change_connect = 1; 636 637 /* complete root HUB interrupt endpoint */ 638 639 avr32dci_root_intr(sc); 640 } 641 } 642 } 643 644 void 645 avr32dci_interrupt(struct avr32dci_softc *sc) 646 { 647 uint32_t status; 648 649 USB_BUS_LOCK(&sc->sc_bus); 650 651 /* read interrupt status */ 652 status = AVR32_READ_4(sc, AVR32_INTSTA); 653 654 /* clear all set interrupts */ 655 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 656 657 DPRINTFN(14, "INTSTA=0x%08x\n", status); 658 659 /* check for any bus state change interrupts */ 660 if (status & AVR32_INT_ENDRESET) { 661 662 DPRINTFN(5, "end of reset\n"); 663 664 /* set correct state */ 665 sc->sc_flags.status_bus_reset = 1; 666 sc->sc_flags.status_suspend = 0; 667 sc->sc_flags.change_suspend = 0; 668 sc->sc_flags.change_connect = 1; 669 670 /* disable resume interrupt */ 671 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 672 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 673 674 /* complete root HUB interrupt endpoint */ 675 avr32dci_root_intr(sc); 676 } 677 /* 678 * If resume and suspend is set at the same time we interpret 679 * that like RESUME. Resume is set when there is at least 3 680 * milliseconds of inactivity on the USB BUS. 681 */ 682 if (status & AVR32_INT_WAKE_UP) { 683 684 DPRINTFN(5, "resume interrupt\n"); 685 686 if (sc->sc_flags.status_suspend) { 687 /* update status bits */ 688 sc->sc_flags.status_suspend = 0; 689 sc->sc_flags.change_suspend = 1; 690 691 /* disable resume interrupt */ 692 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 693 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 694 695 /* complete root HUB interrupt endpoint */ 696 avr32dci_root_intr(sc); 697 } 698 } else if (status & AVR32_INT_DET_SUSPD) { 699 700 DPRINTFN(5, "suspend interrupt\n"); 701 702 if (!sc->sc_flags.status_suspend) { 703 /* update status bits */ 704 sc->sc_flags.status_suspend = 1; 705 sc->sc_flags.change_suspend = 1; 706 707 /* disable suspend interrupt */ 708 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 709 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 710 711 /* complete root HUB interrupt endpoint */ 712 avr32dci_root_intr(sc); 713 } 714 } 715 /* check for any endpoint interrupts */ 716 if (status & -AVR32_INT_EPT_INT(0)) { 717 718 DPRINTFN(5, "real endpoint interrupt\n"); 719 720 avr32dci_interrupt_poll(sc); 721 } 722 USB_BUS_UNLOCK(&sc->sc_bus); 723 } 724 725 static void 726 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 727 { 728 struct avr32dci_td *td; 729 730 /* get current Transfer Descriptor */ 731 td = temp->td_next; 732 temp->td = td; 733 734 /* prepare for next TD */ 735 temp->td_next = td->obj_next; 736 737 /* fill out the Transfer Descriptor */ 738 td->func = temp->func; 739 td->pc = temp->pc; 740 td->offset = temp->offset; 741 td->remainder = temp->len; 742 td->error = 0; 743 td->did_stall = temp->did_stall; 744 td->short_pkt = temp->short_pkt; 745 td->alt_next = temp->setup_alt_next; 746 } 747 748 static void 749 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 750 { 751 struct avr32dci_std_temp temp; 752 struct avr32dci_softc *sc; 753 struct avr32dci_td *td; 754 uint32_t x; 755 uint8_t ep_no; 756 uint8_t need_sync; 757 758 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 759 xfer->address, UE_GET_ADDR(xfer->endpointno), 760 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 761 762 temp.max_frame_size = xfer->max_frame_size; 763 764 td = xfer->td_start[0]; 765 xfer->td_transfer_first = td; 766 xfer->td_transfer_cache = td; 767 768 /* setup temp */ 769 770 temp.pc = NULL; 771 temp.td = NULL; 772 temp.td_next = xfer->td_start[0]; 773 temp.offset = 0; 774 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 775 temp.did_stall = !xfer->flags_int.control_stall; 776 777 sc = AVR32_BUS2SC(xfer->xroot->bus); 778 ep_no = (xfer->endpointno & UE_ADDR); 779 780 /* check if we should prepend a setup message */ 781 782 if (xfer->flags_int.control_xfr) { 783 if (xfer->flags_int.control_hdr) { 784 785 temp.func = &avr32dci_setup_rx; 786 temp.len = xfer->frlengths[0]; 787 temp.pc = xfer->frbuffers + 0; 788 temp.short_pkt = temp.len ? 1 : 0; 789 /* check for last frame */ 790 if (xfer->nframes == 1) { 791 /* no STATUS stage yet, SETUP is last */ 792 if (xfer->flags_int.control_act) 793 temp.setup_alt_next = 0; 794 } 795 avr32dci_setup_standard_chain_sub(&temp); 796 } 797 x = 1; 798 } else { 799 x = 0; 800 } 801 802 if (x != xfer->nframes) { 803 if (xfer->endpointno & UE_DIR_IN) { 804 temp.func = &avr32dci_data_tx; 805 need_sync = 1; 806 } else { 807 temp.func = &avr32dci_data_rx; 808 need_sync = 0; 809 } 810 811 /* setup "pc" pointer */ 812 temp.pc = xfer->frbuffers + x; 813 } else { 814 need_sync = 0; 815 } 816 while (x != xfer->nframes) { 817 818 /* DATA0 / DATA1 message */ 819 820 temp.len = xfer->frlengths[x]; 821 822 x++; 823 824 if (x == xfer->nframes) { 825 if (xfer->flags_int.control_xfr) { 826 if (xfer->flags_int.control_act) { 827 temp.setup_alt_next = 0; 828 } 829 } else { 830 temp.setup_alt_next = 0; 831 } 832 } 833 if (temp.len == 0) { 834 835 /* make sure that we send an USB packet */ 836 837 temp.short_pkt = 0; 838 839 } else { 840 841 /* regular data transfer */ 842 843 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 844 } 845 846 avr32dci_setup_standard_chain_sub(&temp); 847 848 if (xfer->flags_int.isochronous_xfr) { 849 temp.offset += temp.len; 850 } else { 851 /* get next Page Cache pointer */ 852 temp.pc = xfer->frbuffers + x; 853 } 854 } 855 856 if (xfer->flags_int.control_xfr) { 857 858 /* always setup a valid "pc" pointer for status and sync */ 859 temp.pc = xfer->frbuffers + 0; 860 temp.len = 0; 861 temp.short_pkt = 0; 862 temp.setup_alt_next = 0; 863 864 /* check if we need to sync */ 865 if (need_sync) { 866 /* we need a SYNC point after TX */ 867 temp.func = &avr32dci_data_tx_sync; 868 avr32dci_setup_standard_chain_sub(&temp); 869 } 870 /* check if we should append a status stage */ 871 if (!xfer->flags_int.control_act) { 872 873 /* 874 * Send a DATA1 message and invert the current 875 * endpoint direction. 876 */ 877 if (xfer->endpointno & UE_DIR_IN) { 878 temp.func = &avr32dci_data_rx; 879 need_sync = 0; 880 } else { 881 temp.func = &avr32dci_data_tx; 882 need_sync = 1; 883 } 884 885 avr32dci_setup_standard_chain_sub(&temp); 886 if (need_sync) { 887 /* we need a SYNC point after TX */ 888 temp.func = &avr32dci_data_tx_sync; 889 avr32dci_setup_standard_chain_sub(&temp); 890 } 891 } 892 } 893 /* must have at least one frame! */ 894 td = temp.td; 895 xfer->td_transfer_last = td; 896 } 897 898 static void 899 avr32dci_timeout(void *arg) 900 { 901 struct usb_xfer *xfer = arg; 902 903 DPRINTF("xfer=%p\n", xfer); 904 905 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 906 907 /* transfer is transferred */ 908 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 909 } 910 911 static void 912 avr32dci_start_standard_chain(struct usb_xfer *xfer) 913 { 914 DPRINTFN(9, "\n"); 915 916 /* poll one time - will turn on interrupts */ 917 if (avr32dci_xfer_do_fifo(xfer)) { 918 uint8_t ep_no = xfer->endpointno & UE_ADDR; 919 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 920 921 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 922 923 /* put transfer on interrupt queue */ 924 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 925 926 /* start timeout, if any */ 927 if (xfer->timeout != 0) { 928 usbd_transfer_timeout_ms(xfer, 929 &avr32dci_timeout, xfer->timeout); 930 } 931 } 932 } 933 934 static void 935 avr32dci_root_intr(struct avr32dci_softc *sc) 936 { 937 DPRINTFN(9, "\n"); 938 939 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 940 941 /* set port bit */ 942 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 943 944 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 945 sizeof(sc->sc_hub_idata)); 946 } 947 948 static usb_error_t 949 avr32dci_standard_done_sub(struct usb_xfer *xfer) 950 { 951 struct avr32dci_td *td; 952 uint32_t len; 953 uint8_t error; 954 955 DPRINTFN(9, "\n"); 956 957 td = xfer->td_transfer_cache; 958 959 do { 960 len = td->remainder; 961 962 if (xfer->aframes != xfer->nframes) { 963 /* 964 * Verify the length and subtract 965 * the remainder from "frlengths[]": 966 */ 967 if (len > xfer->frlengths[xfer->aframes]) { 968 td->error = 1; 969 } else { 970 xfer->frlengths[xfer->aframes] -= len; 971 } 972 } 973 /* Check for transfer error */ 974 if (td->error) { 975 /* the transfer is finished */ 976 error = 1; 977 td = NULL; 978 break; 979 } 980 /* Check for short transfer */ 981 if (len > 0) { 982 if (xfer->flags_int.short_frames_ok) { 983 /* follow alt next */ 984 if (td->alt_next) { 985 td = td->obj_next; 986 } else { 987 td = NULL; 988 } 989 } else { 990 /* the transfer is finished */ 991 td = NULL; 992 } 993 error = 0; 994 break; 995 } 996 td = td->obj_next; 997 998 /* this USB frame is complete */ 999 error = 0; 1000 break; 1001 1002 } while (0); 1003 1004 /* update transfer cache */ 1005 1006 xfer->td_transfer_cache = td; 1007 1008 return (error ? 1009 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1010 } 1011 1012 static void 1013 avr32dci_standard_done(struct usb_xfer *xfer) 1014 { 1015 usb_error_t err = 0; 1016 1017 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1018 xfer, xfer->endpoint); 1019 1020 /* reset scanner */ 1021 1022 xfer->td_transfer_cache = xfer->td_transfer_first; 1023 1024 if (xfer->flags_int.control_xfr) { 1025 1026 if (xfer->flags_int.control_hdr) { 1027 1028 err = avr32dci_standard_done_sub(xfer); 1029 } 1030 xfer->aframes = 1; 1031 1032 if (xfer->td_transfer_cache == NULL) { 1033 goto done; 1034 } 1035 } 1036 while (xfer->aframes != xfer->nframes) { 1037 1038 err = avr32dci_standard_done_sub(xfer); 1039 xfer->aframes++; 1040 1041 if (xfer->td_transfer_cache == NULL) { 1042 goto done; 1043 } 1044 } 1045 1046 if (xfer->flags_int.control_xfr && 1047 !xfer->flags_int.control_act) { 1048 1049 err = avr32dci_standard_done_sub(xfer); 1050 } 1051 done: 1052 avr32dci_device_done(xfer, err); 1053 } 1054 1055 /*------------------------------------------------------------------------* 1056 * avr32dci_device_done 1057 * 1058 * NOTE: this function can be called more than one time on the 1059 * same USB transfer! 1060 *------------------------------------------------------------------------*/ 1061 static void 1062 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1063 { 1064 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1065 uint8_t ep_no; 1066 1067 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1068 1069 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1070 xfer, xfer->endpoint, error); 1071 1072 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1073 ep_no = (xfer->endpointno & UE_ADDR); 1074 1075 /* disable endpoint interrupt */ 1076 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1077 1078 DPRINTFN(15, "disabled interrupts!\n"); 1079 } 1080 /* dequeue transfer and start next transfer */ 1081 usbd_transfer_done(xfer, error); 1082 } 1083 1084 static void 1085 avr32dci_xfer_stall(struct usb_xfer *xfer) 1086 { 1087 avr32dci_device_done(xfer, USB_ERR_STALLED); 1088 } 1089 1090 static void 1091 avr32dci_set_stall(struct usb_device *udev, 1092 struct usb_endpoint *pipe, uint8_t *did_stall) 1093 { 1094 struct avr32dci_softc *sc; 1095 uint8_t ep_no; 1096 1097 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1098 1099 DPRINTFN(5, "pipe=%p\n", pipe); 1100 1101 sc = AVR32_BUS2SC(udev->bus); 1102 /* get endpoint number */ 1103 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1104 /* set stall */ 1105 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1106 } 1107 1108 static void 1109 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1110 uint8_t ep_type, uint8_t ep_dir) 1111 { 1112 const struct usb_hw_ep_profile *pf; 1113 uint32_t temp; 1114 uint32_t epsize; 1115 uint8_t n; 1116 1117 if (ep_type == UE_CONTROL) { 1118 /* clearing stall is not needed */ 1119 return; 1120 } 1121 /* set endpoint reset */ 1122 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1123 1124 /* set stall */ 1125 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1126 1127 /* reset data toggle */ 1128 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1129 1130 /* clear stall */ 1131 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1132 1133 if (ep_type == UE_BULK) { 1134 temp = AVR32_EPTCFG_TYPE_BULK; 1135 } else if (ep_type == UE_INTERRUPT) { 1136 temp = AVR32_EPTCFG_TYPE_INTR; 1137 } else { 1138 temp = AVR32_EPTCFG_TYPE_ISOC | 1139 AVR32_EPTCFG_NB_TRANS(1); 1140 } 1141 if (ep_dir & UE_DIR_IN) { 1142 temp |= AVR32_EPTCFG_EPDIR_IN; 1143 } 1144 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1145 1146 /* compute endpoint size (use maximum) */ 1147 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1148 n = 0; 1149 while ((epsize /= 2)) 1150 n++; 1151 temp |= AVR32_EPTCFG_EPSIZE(n); 1152 1153 /* use the maximum number of banks supported */ 1154 if (ep_no < 1) 1155 temp |= AVR32_EPTCFG_NBANK(1); 1156 else if (ep_no < 3) 1157 temp |= AVR32_EPTCFG_NBANK(2); 1158 else 1159 temp |= AVR32_EPTCFG_NBANK(3); 1160 1161 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1162 1163 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1164 1165 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1166 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1167 } else { 1168 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1169 AVR32_EPTCTL_EPT_ENABL); 1170 } 1171 } 1172 1173 static void 1174 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1175 { 1176 struct avr32dci_softc *sc; 1177 struct usb_endpoint_descriptor *ed; 1178 1179 DPRINTFN(5, "pipe=%p\n", pipe); 1180 1181 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1182 1183 /* check mode */ 1184 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1185 /* not supported */ 1186 return; 1187 } 1188 /* get softc */ 1189 sc = AVR32_BUS2SC(udev->bus); 1190 1191 /* get endpoint descriptor */ 1192 ed = pipe->edesc; 1193 1194 /* reset endpoint */ 1195 avr32dci_clear_stall_sub(sc, 1196 (ed->bEndpointAddress & UE_ADDR), 1197 (ed->bmAttributes & UE_XFERTYPE), 1198 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1199 } 1200 1201 usb_error_t 1202 avr32dci_init(struct avr32dci_softc *sc) 1203 { 1204 uint8_t n; 1205 1206 DPRINTF("start\n"); 1207 1208 /* set up the bus structure */ 1209 sc->sc_bus.usbrev = USB_REV_1_1; 1210 sc->sc_bus.methods = &avr32dci_bus_methods; 1211 1212 USB_BUS_LOCK(&sc->sc_bus); 1213 1214 /* make sure USB is enabled */ 1215 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1216 1217 /* turn on clocks */ 1218 (sc->sc_clocks_on) (&sc->sc_bus); 1219 1220 /* make sure device is re-enumerated */ 1221 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1222 1223 /* wait a little for things to stabilise */ 1224 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1225 1226 /* disable interrupts */ 1227 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1228 1229 /* enable interrupts */ 1230 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1231 AVR32_INT_ENDRESET, 0); 1232 1233 /* reset all endpoints */ 1234 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1235 1236 /* disable all endpoints */ 1237 for (n = 0; n != AVR32_EP_MAX; n++) { 1238 /* disable endpoint */ 1239 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1240 } 1241 1242 /* turn off clocks */ 1243 1244 avr32dci_clocks_off(sc); 1245 1246 USB_BUS_UNLOCK(&sc->sc_bus); 1247 1248 /* catch any lost interrupts */ 1249 1250 avr32dci_do_poll(&sc->sc_bus); 1251 1252 return (0); /* success */ 1253 } 1254 1255 void 1256 avr32dci_uninit(struct avr32dci_softc *sc) 1257 { 1258 uint8_t n; 1259 1260 USB_BUS_LOCK(&sc->sc_bus); 1261 1262 /* turn on clocks */ 1263 (sc->sc_clocks_on) (&sc->sc_bus); 1264 1265 /* disable interrupts */ 1266 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1267 1268 /* reset all endpoints */ 1269 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1270 1271 /* disable all endpoints */ 1272 for (n = 0; n != AVR32_EP_MAX; n++) { 1273 /* disable endpoint */ 1274 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1275 } 1276 1277 sc->sc_flags.port_powered = 0; 1278 sc->sc_flags.status_vbus = 0; 1279 sc->sc_flags.status_bus_reset = 0; 1280 sc->sc_flags.status_suspend = 0; 1281 sc->sc_flags.change_suspend = 0; 1282 sc->sc_flags.change_connect = 1; 1283 1284 avr32dci_pull_down(sc); 1285 avr32dci_clocks_off(sc); 1286 1287 USB_BUS_UNLOCK(&sc->sc_bus); 1288 } 1289 1290 static void 1291 avr32dci_suspend(struct avr32dci_softc *sc) 1292 { 1293 /* TODO */ 1294 } 1295 1296 static void 1297 avr32dci_resume(struct avr32dci_softc *sc) 1298 { 1299 /* TODO */ 1300 } 1301 1302 static void 1303 avr32dci_do_poll(struct usb_bus *bus) 1304 { 1305 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1306 1307 USB_BUS_LOCK(&sc->sc_bus); 1308 avr32dci_interrupt_poll(sc); 1309 USB_BUS_UNLOCK(&sc->sc_bus); 1310 } 1311 1312 /*------------------------------------------------------------------------* 1313 * at91dci bulk support 1314 * at91dci control support 1315 * at91dci interrupt support 1316 *------------------------------------------------------------------------*/ 1317 static void 1318 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1319 { 1320 return; 1321 } 1322 1323 static void 1324 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1325 { 1326 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1327 } 1328 1329 static void 1330 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1331 { 1332 return; 1333 } 1334 1335 static void 1336 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1337 { 1338 /* setup TDs */ 1339 avr32dci_setup_standard_chain(xfer); 1340 avr32dci_start_standard_chain(xfer); 1341 } 1342 1343 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1344 { 1345 .open = avr32dci_device_non_isoc_open, 1346 .close = avr32dci_device_non_isoc_close, 1347 .enter = avr32dci_device_non_isoc_enter, 1348 .start = avr32dci_device_non_isoc_start, 1349 }; 1350 1351 /*------------------------------------------------------------------------* 1352 * at91dci full speed isochronous support 1353 *------------------------------------------------------------------------*/ 1354 static void 1355 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1356 { 1357 return; 1358 } 1359 1360 static void 1361 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1362 { 1363 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1364 } 1365 1366 static void 1367 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1368 { 1369 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1370 uint32_t temp; 1371 uint32_t nframes; 1372 uint8_t ep_no; 1373 1374 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1375 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1376 1377 /* get the current frame index */ 1378 ep_no = xfer->endpointno & UE_ADDR; 1379 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1380 1381 nframes &= AVR32_FRAME_MASK; 1382 1383 /* 1384 * check if the frame index is within the window where the frames 1385 * will be inserted 1386 */ 1387 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK; 1388 1389 if ((xfer->endpoint->is_synced == 0) || 1390 (temp < xfer->nframes)) { 1391 /* 1392 * If there is data underflow or the pipe queue is 1393 * empty we schedule the transfer a few frames ahead 1394 * of the current frame position. Else two isochronous 1395 * transfers might overlap. 1396 */ 1397 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1398 xfer->endpoint->is_synced = 1; 1399 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1400 } 1401 /* 1402 * compute how many milliseconds the insertion is ahead of the 1403 * current frame position: 1404 */ 1405 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK; 1406 1407 /* 1408 * pre-compute when the isochronous transfer will be finished: 1409 */ 1410 xfer->isoc_time_complete = 1411 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1412 xfer->nframes; 1413 1414 /* compute frame number for next insertion */ 1415 xfer->endpoint->isoc_next += xfer->nframes; 1416 1417 /* setup TDs */ 1418 avr32dci_setup_standard_chain(xfer); 1419 } 1420 1421 static void 1422 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1423 { 1424 /* start TD chain */ 1425 avr32dci_start_standard_chain(xfer); 1426 } 1427 1428 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1429 { 1430 .open = avr32dci_device_isoc_fs_open, 1431 .close = avr32dci_device_isoc_fs_close, 1432 .enter = avr32dci_device_isoc_fs_enter, 1433 .start = avr32dci_device_isoc_fs_start, 1434 }; 1435 1436 /*------------------------------------------------------------------------* 1437 * at91dci root control support 1438 *------------------------------------------------------------------------* 1439 * Simulate a hardware HUB by handling all the necessary requests. 1440 *------------------------------------------------------------------------*/ 1441 1442 static const struct usb_device_descriptor avr32dci_devd = { 1443 .bLength = sizeof(struct usb_device_descriptor), 1444 .bDescriptorType = UDESC_DEVICE, 1445 .bcdUSB = {0x00, 0x02}, 1446 .bDeviceClass = UDCLASS_HUB, 1447 .bDeviceSubClass = UDSUBCLASS_HUB, 1448 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1449 .bMaxPacketSize = 64, 1450 .bcdDevice = {0x00, 0x01}, 1451 .iManufacturer = 1, 1452 .iProduct = 2, 1453 .bNumConfigurations = 1, 1454 }; 1455 1456 static const struct usb_device_qualifier avr32dci_odevd = { 1457 .bLength = sizeof(struct usb_device_qualifier), 1458 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1459 .bcdUSB = {0x00, 0x02}, 1460 .bDeviceClass = UDCLASS_HUB, 1461 .bDeviceSubClass = UDSUBCLASS_HUB, 1462 .bDeviceProtocol = UDPROTO_FSHUB, 1463 .bMaxPacketSize0 = 0, 1464 .bNumConfigurations = 0, 1465 }; 1466 1467 static const struct avr32dci_config_desc avr32dci_confd = { 1468 .confd = { 1469 .bLength = sizeof(struct usb_config_descriptor), 1470 .bDescriptorType = UDESC_CONFIG, 1471 .wTotalLength[0] = sizeof(avr32dci_confd), 1472 .bNumInterface = 1, 1473 .bConfigurationValue = 1, 1474 .iConfiguration = 0, 1475 .bmAttributes = UC_SELF_POWERED, 1476 .bMaxPower = 0, 1477 }, 1478 .ifcd = { 1479 .bLength = sizeof(struct usb_interface_descriptor), 1480 .bDescriptorType = UDESC_INTERFACE, 1481 .bNumEndpoints = 1, 1482 .bInterfaceClass = UICLASS_HUB, 1483 .bInterfaceSubClass = UISUBCLASS_HUB, 1484 .bInterfaceProtocol = 0, 1485 }, 1486 .endpd = { 1487 .bLength = sizeof(struct usb_endpoint_descriptor), 1488 .bDescriptorType = UDESC_ENDPOINT, 1489 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1490 .bmAttributes = UE_INTERRUPT, 1491 .wMaxPacketSize[0] = 8, 1492 .bInterval = 255, 1493 }, 1494 }; 1495 1496 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1497 1498 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1499 .bDescLength = sizeof(avr32dci_hubd), 1500 .bDescriptorType = UDESC_HUB, 1501 .bNbrPorts = 1, 1502 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1503 .bPwrOn2PwrGood = 50, 1504 .bHubContrCurrent = 0, 1505 .DeviceRemovable = {0}, /* port is removable */ 1506 }; 1507 1508 #define STRING_VENDOR \ 1509 "A\0V\0R\0003\0002" 1510 1511 #define STRING_PRODUCT \ 1512 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1513 1514 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1515 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1516 1517 static usb_error_t 1518 avr32dci_roothub_exec(struct usb_device *udev, 1519 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1520 { 1521 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1522 const void *ptr; 1523 uint16_t len; 1524 uint16_t value; 1525 uint16_t index; 1526 uint32_t temp; 1527 usb_error_t err; 1528 1529 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1530 1531 /* buffer reset */ 1532 ptr = (const void *)&sc->sc_hub_temp; 1533 len = 0; 1534 err = 0; 1535 1536 value = UGETW(req->wValue); 1537 index = UGETW(req->wIndex); 1538 1539 /* demultiplex the control request */ 1540 1541 switch (req->bmRequestType) { 1542 case UT_READ_DEVICE: 1543 switch (req->bRequest) { 1544 case UR_GET_DESCRIPTOR: 1545 goto tr_handle_get_descriptor; 1546 case UR_GET_CONFIG: 1547 goto tr_handle_get_config; 1548 case UR_GET_STATUS: 1549 goto tr_handle_get_status; 1550 default: 1551 goto tr_stalled; 1552 } 1553 break; 1554 1555 case UT_WRITE_DEVICE: 1556 switch (req->bRequest) { 1557 case UR_SET_ADDRESS: 1558 goto tr_handle_set_address; 1559 case UR_SET_CONFIG: 1560 goto tr_handle_set_config; 1561 case UR_CLEAR_FEATURE: 1562 goto tr_valid; /* nop */ 1563 case UR_SET_DESCRIPTOR: 1564 goto tr_valid; /* nop */ 1565 case UR_SET_FEATURE: 1566 default: 1567 goto tr_stalled; 1568 } 1569 break; 1570 1571 case UT_WRITE_ENDPOINT: 1572 switch (req->bRequest) { 1573 case UR_CLEAR_FEATURE: 1574 switch (UGETW(req->wValue)) { 1575 case UF_ENDPOINT_HALT: 1576 goto tr_handle_clear_halt; 1577 case UF_DEVICE_REMOTE_WAKEUP: 1578 goto tr_handle_clear_wakeup; 1579 default: 1580 goto tr_stalled; 1581 } 1582 break; 1583 case UR_SET_FEATURE: 1584 switch (UGETW(req->wValue)) { 1585 case UF_ENDPOINT_HALT: 1586 goto tr_handle_set_halt; 1587 case UF_DEVICE_REMOTE_WAKEUP: 1588 goto tr_handle_set_wakeup; 1589 default: 1590 goto tr_stalled; 1591 } 1592 break; 1593 case UR_SYNCH_FRAME: 1594 goto tr_valid; /* nop */ 1595 default: 1596 goto tr_stalled; 1597 } 1598 break; 1599 1600 case UT_READ_ENDPOINT: 1601 switch (req->bRequest) { 1602 case UR_GET_STATUS: 1603 goto tr_handle_get_ep_status; 1604 default: 1605 goto tr_stalled; 1606 } 1607 break; 1608 1609 case UT_WRITE_INTERFACE: 1610 switch (req->bRequest) { 1611 case UR_SET_INTERFACE: 1612 goto tr_handle_set_interface; 1613 case UR_CLEAR_FEATURE: 1614 goto tr_valid; /* nop */ 1615 case UR_SET_FEATURE: 1616 default: 1617 goto tr_stalled; 1618 } 1619 break; 1620 1621 case UT_READ_INTERFACE: 1622 switch (req->bRequest) { 1623 case UR_GET_INTERFACE: 1624 goto tr_handle_get_interface; 1625 case UR_GET_STATUS: 1626 goto tr_handle_get_iface_status; 1627 default: 1628 goto tr_stalled; 1629 } 1630 break; 1631 1632 case UT_WRITE_CLASS_INTERFACE: 1633 case UT_WRITE_VENDOR_INTERFACE: 1634 /* XXX forward */ 1635 break; 1636 1637 case UT_READ_CLASS_INTERFACE: 1638 case UT_READ_VENDOR_INTERFACE: 1639 /* XXX forward */ 1640 break; 1641 1642 case UT_WRITE_CLASS_DEVICE: 1643 switch (req->bRequest) { 1644 case UR_CLEAR_FEATURE: 1645 goto tr_valid; 1646 case UR_SET_DESCRIPTOR: 1647 case UR_SET_FEATURE: 1648 break; 1649 default: 1650 goto tr_stalled; 1651 } 1652 break; 1653 1654 case UT_WRITE_CLASS_OTHER: 1655 switch (req->bRequest) { 1656 case UR_CLEAR_FEATURE: 1657 goto tr_handle_clear_port_feature; 1658 case UR_SET_FEATURE: 1659 goto tr_handle_set_port_feature; 1660 case UR_CLEAR_TT_BUFFER: 1661 case UR_RESET_TT: 1662 case UR_STOP_TT: 1663 goto tr_valid; 1664 1665 default: 1666 goto tr_stalled; 1667 } 1668 break; 1669 1670 case UT_READ_CLASS_OTHER: 1671 switch (req->bRequest) { 1672 case UR_GET_TT_STATE: 1673 goto tr_handle_get_tt_state; 1674 case UR_GET_STATUS: 1675 goto tr_handle_get_port_status; 1676 default: 1677 goto tr_stalled; 1678 } 1679 break; 1680 1681 case UT_READ_CLASS_DEVICE: 1682 switch (req->bRequest) { 1683 case UR_GET_DESCRIPTOR: 1684 goto tr_handle_get_class_descriptor; 1685 case UR_GET_STATUS: 1686 goto tr_handle_get_class_status; 1687 1688 default: 1689 goto tr_stalled; 1690 } 1691 break; 1692 default: 1693 goto tr_stalled; 1694 } 1695 goto tr_valid; 1696 1697 tr_handle_get_descriptor: 1698 switch (value >> 8) { 1699 case UDESC_DEVICE: 1700 if (value & 0xff) { 1701 goto tr_stalled; 1702 } 1703 len = sizeof(avr32dci_devd); 1704 ptr = (const void *)&avr32dci_devd; 1705 goto tr_valid; 1706 case UDESC_CONFIG: 1707 if (value & 0xff) { 1708 goto tr_stalled; 1709 } 1710 len = sizeof(avr32dci_confd); 1711 ptr = (const void *)&avr32dci_confd; 1712 goto tr_valid; 1713 case UDESC_STRING: 1714 switch (value & 0xff) { 1715 case 0: /* Language table */ 1716 len = sizeof(usb_string_lang_en); 1717 ptr = (const void *)&usb_string_lang_en; 1718 goto tr_valid; 1719 1720 case 1: /* Vendor */ 1721 len = sizeof(avr32dci_vendor); 1722 ptr = (const void *)&avr32dci_vendor; 1723 goto tr_valid; 1724 1725 case 2: /* Product */ 1726 len = sizeof(avr32dci_product); 1727 ptr = (const void *)&avr32dci_product; 1728 goto tr_valid; 1729 default: 1730 break; 1731 } 1732 break; 1733 default: 1734 goto tr_stalled; 1735 } 1736 goto tr_stalled; 1737 1738 tr_handle_get_config: 1739 len = 1; 1740 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1741 goto tr_valid; 1742 1743 tr_handle_get_status: 1744 len = 2; 1745 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1746 goto tr_valid; 1747 1748 tr_handle_set_address: 1749 if (value & 0xFF00) { 1750 goto tr_stalled; 1751 } 1752 sc->sc_rt_addr = value; 1753 goto tr_valid; 1754 1755 tr_handle_set_config: 1756 if (value >= 2) { 1757 goto tr_stalled; 1758 } 1759 sc->sc_conf = value; 1760 goto tr_valid; 1761 1762 tr_handle_get_interface: 1763 len = 1; 1764 sc->sc_hub_temp.wValue[0] = 0; 1765 goto tr_valid; 1766 1767 tr_handle_get_tt_state: 1768 tr_handle_get_class_status: 1769 tr_handle_get_iface_status: 1770 tr_handle_get_ep_status: 1771 len = 2; 1772 USETW(sc->sc_hub_temp.wValue, 0); 1773 goto tr_valid; 1774 1775 tr_handle_set_halt: 1776 tr_handle_set_interface: 1777 tr_handle_set_wakeup: 1778 tr_handle_clear_wakeup: 1779 tr_handle_clear_halt: 1780 goto tr_valid; 1781 1782 tr_handle_clear_port_feature: 1783 if (index != 1) { 1784 goto tr_stalled; 1785 } 1786 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1787 1788 switch (value) { 1789 case UHF_PORT_SUSPEND: 1790 avr32dci_wakeup_peer(sc); 1791 break; 1792 1793 case UHF_PORT_ENABLE: 1794 sc->sc_flags.port_enabled = 0; 1795 break; 1796 1797 case UHF_PORT_TEST: 1798 case UHF_PORT_INDICATOR: 1799 case UHF_C_PORT_ENABLE: 1800 case UHF_C_PORT_OVER_CURRENT: 1801 case UHF_C_PORT_RESET: 1802 /* nops */ 1803 break; 1804 case UHF_PORT_POWER: 1805 sc->sc_flags.port_powered = 0; 1806 avr32dci_pull_down(sc); 1807 avr32dci_clocks_off(sc); 1808 break; 1809 case UHF_C_PORT_CONNECTION: 1810 /* clear connect change flag */ 1811 sc->sc_flags.change_connect = 0; 1812 1813 if (!sc->sc_flags.status_bus_reset) { 1814 /* we are not connected */ 1815 break; 1816 } 1817 /* configure the control endpoint */ 1818 /* set endpoint reset */ 1819 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1820 1821 /* set stall */ 1822 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1823 1824 /* reset data toggle */ 1825 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1826 1827 /* clear stall */ 1828 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1829 1830 /* configure */ 1831 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1832 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1833 1834 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1835 1836 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1837 device_printf(sc->sc_bus.bdev, 1838 "Chip rejected configuration\n"); 1839 } else { 1840 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1841 AVR32_EPTCTL_EPT_ENABL); 1842 } 1843 break; 1844 case UHF_C_PORT_SUSPEND: 1845 sc->sc_flags.change_suspend = 0; 1846 break; 1847 default: 1848 err = USB_ERR_IOERROR; 1849 goto done; 1850 } 1851 goto tr_valid; 1852 1853 tr_handle_set_port_feature: 1854 if (index != 1) { 1855 goto tr_stalled; 1856 } 1857 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1858 1859 switch (value) { 1860 case UHF_PORT_ENABLE: 1861 sc->sc_flags.port_enabled = 1; 1862 break; 1863 case UHF_PORT_SUSPEND: 1864 case UHF_PORT_RESET: 1865 case UHF_PORT_TEST: 1866 case UHF_PORT_INDICATOR: 1867 /* nops */ 1868 break; 1869 case UHF_PORT_POWER: 1870 sc->sc_flags.port_powered = 1; 1871 break; 1872 default: 1873 err = USB_ERR_IOERROR; 1874 goto done; 1875 } 1876 goto tr_valid; 1877 1878 tr_handle_get_port_status: 1879 1880 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1881 1882 if (index != 1) { 1883 goto tr_stalled; 1884 } 1885 if (sc->sc_flags.status_vbus) { 1886 avr32dci_clocks_on(sc); 1887 avr32dci_pull_up(sc); 1888 } else { 1889 avr32dci_pull_down(sc); 1890 avr32dci_clocks_off(sc); 1891 } 1892 1893 /* Select Device Side Mode */ 1894 1895 value = UPS_PORT_MODE_DEVICE; 1896 1897 /* Check for High Speed */ 1898 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1899 value |= UPS_HIGH_SPEED; 1900 1901 if (sc->sc_flags.port_powered) { 1902 value |= UPS_PORT_POWER; 1903 } 1904 if (sc->sc_flags.port_enabled) { 1905 value |= UPS_PORT_ENABLED; 1906 } 1907 if (sc->sc_flags.status_vbus && 1908 sc->sc_flags.status_bus_reset) { 1909 value |= UPS_CURRENT_CONNECT_STATUS; 1910 } 1911 if (sc->sc_flags.status_suspend) { 1912 value |= UPS_SUSPEND; 1913 } 1914 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1915 1916 value = 0; 1917 1918 if (sc->sc_flags.change_connect) { 1919 value |= UPS_C_CONNECT_STATUS; 1920 } 1921 if (sc->sc_flags.change_suspend) { 1922 value |= UPS_C_SUSPEND; 1923 } 1924 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1925 len = sizeof(sc->sc_hub_temp.ps); 1926 goto tr_valid; 1927 1928 tr_handle_get_class_descriptor: 1929 if (value & 0xFF) { 1930 goto tr_stalled; 1931 } 1932 ptr = (const void *)&avr32dci_hubd; 1933 len = sizeof(avr32dci_hubd); 1934 goto tr_valid; 1935 1936 tr_stalled: 1937 err = USB_ERR_STALLED; 1938 tr_valid: 1939 done: 1940 *plength = len; 1941 *pptr = ptr; 1942 return (err); 1943 } 1944 1945 static void 1946 avr32dci_xfer_setup(struct usb_setup_params *parm) 1947 { 1948 const struct usb_hw_ep_profile *pf; 1949 struct avr32dci_softc *sc; 1950 struct usb_xfer *xfer; 1951 void *last_obj; 1952 uint32_t ntd; 1953 uint32_t n; 1954 uint8_t ep_no; 1955 1956 sc = AVR32_BUS2SC(parm->udev->bus); 1957 xfer = parm->curr_xfer; 1958 1959 /* 1960 * NOTE: This driver does not use any of the parameters that 1961 * are computed from the following values. Just set some 1962 * reasonable dummies: 1963 */ 1964 parm->hc_max_packet_size = 0x400; 1965 parm->hc_max_packet_count = 1; 1966 parm->hc_max_frame_size = 0x400; 1967 1968 usbd_transfer_setup_sub(parm); 1969 1970 /* 1971 * compute maximum number of TDs 1972 */ 1973 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1974 1975 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1976 + 1 /* SYNC 2 */ ; 1977 } else { 1978 1979 ntd = xfer->nframes + 1 /* SYNC */ ; 1980 } 1981 1982 /* 1983 * check if "usbd_transfer_setup_sub" set an error 1984 */ 1985 if (parm->err) 1986 return; 1987 1988 /* 1989 * allocate transfer descriptors 1990 */ 1991 last_obj = NULL; 1992 1993 /* 1994 * get profile stuff 1995 */ 1996 ep_no = xfer->endpointno & UE_ADDR; 1997 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1998 1999 if (pf == NULL) { 2000 /* should not happen */ 2001 parm->err = USB_ERR_INVAL; 2002 return; 2003 } 2004 /* align data */ 2005 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2006 2007 for (n = 0; n != ntd; n++) { 2008 2009 struct avr32dci_td *td; 2010 2011 if (parm->buf) { 2012 uint32_t temp; 2013 2014 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2015 2016 /* init TD */ 2017 td->max_packet_size = xfer->max_packet_size; 2018 td->ep_no = ep_no; 2019 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2020 td->bank_shift = 0; 2021 while ((temp /= 2)) 2022 td->bank_shift++; 2023 if (pf->support_multi_buffer) { 2024 td->support_multi_buffer = 1; 2025 } 2026 td->obj_next = last_obj; 2027 2028 last_obj = td; 2029 } 2030 parm->size[0] += sizeof(*td); 2031 } 2032 2033 xfer->td_start[0] = last_obj; 2034 } 2035 2036 static void 2037 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2038 { 2039 return; 2040 } 2041 2042 static void 2043 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2044 struct usb_endpoint *pipe) 2045 { 2046 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2047 2048 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2049 pipe, udev->address, 2050 edesc->bEndpointAddress, udev->flags.usb_mode, 2051 sc->sc_rt_addr, udev->device_index); 2052 2053 if (udev->device_index != sc->sc_rt_addr) { 2054 2055 if ((udev->speed != USB_SPEED_FULL) && 2056 (udev->speed != USB_SPEED_HIGH)) { 2057 /* not supported */ 2058 return; 2059 } 2060 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2061 pipe->methods = &avr32dci_device_isoc_fs_methods; 2062 else 2063 pipe->methods = &avr32dci_device_non_isoc_methods; 2064 } 2065 } 2066 2067 static void 2068 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2069 { 2070 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2071 2072 switch (state) { 2073 case USB_HW_POWER_SUSPEND: 2074 avr32dci_suspend(sc); 2075 break; 2076 case USB_HW_POWER_SHUTDOWN: 2077 avr32dci_uninit(sc); 2078 break; 2079 case USB_HW_POWER_RESUME: 2080 avr32dci_resume(sc); 2081 break; 2082 default: 2083 break; 2084 } 2085 } 2086 2087 static const struct usb_bus_methods avr32dci_bus_methods = 2088 { 2089 .endpoint_init = &avr32dci_ep_init, 2090 .xfer_setup = &avr32dci_xfer_setup, 2091 .xfer_unsetup = &avr32dci_xfer_unsetup, 2092 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2093 .xfer_stall = &avr32dci_xfer_stall, 2094 .set_stall = &avr32dci_set_stall, 2095 .clear_stall = &avr32dci_clear_stall, 2096 .roothub_exec = &avr32dci_roothub_exec, 2097 .xfer_poll = &avr32dci_do_poll, 2098 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2099 }; 2100