1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This file contains the driver for the AVR32 series USB Device 29 * Controller 30 */ 31 32 /* 33 * NOTE: When the chip detects BUS-reset it will also reset the 34 * endpoints, Function-address and more. 35 */ 36 #ifdef USB_GLOBAL_INCLUDE_FILE 37 #include USB_GLOBAL_INCLUDE_FILE 38 #else 39 #include <sys/stdint.h> 40 #include <sys/stddef.h> 41 #include <sys/param.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sx.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 61 #define USB_DEBUG_VAR avr32dci_debug 62 63 #include <dev/usb/usb_core.h> 64 #include <dev/usb/usb_debug.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_transfer.h> 68 #include <dev/usb/usb_device.h> 69 #include <dev/usb/usb_hub.h> 70 #include <dev/usb/usb_util.h> 71 72 #include <dev/usb/usb_controller.h> 73 #include <dev/usb/usb_bus.h> 74 #endif /* USB_GLOBAL_INCLUDE_FILE */ 75 76 #include <dev/usb/controller/avr32dci.h> 77 78 #define AVR32_BUS2SC(bus) \ 79 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ 80 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) 81 82 #define AVR32_PC2SC(pc) \ 83 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 84 85 #ifdef USB_DEBUG 86 static int avr32dci_debug = 0; 87 88 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI"); 89 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN, 90 &avr32dci_debug, 0, "AVR32 DCI debug level"); 91 #endif 92 93 #define AVR32_INTR_ENDPT 1 94 95 /* prototypes */ 96 97 static const struct usb_bus_methods avr32dci_bus_methods; 98 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods; 99 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 100 101 static avr32dci_cmd_t avr32dci_setup_rx; 102 static avr32dci_cmd_t avr32dci_data_rx; 103 static avr32dci_cmd_t avr32dci_data_tx; 104 static avr32dci_cmd_t avr32dci_data_tx_sync; 105 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 106 static void avr32dci_do_poll(struct usb_bus *); 107 static void avr32dci_standard_done(struct usb_xfer *); 108 static void avr32dci_root_intr(struct avr32dci_softc *sc); 109 110 /* 111 * Here is a list of what the chip supports: 112 */ 113 static const struct usb_hw_ep_profile 114 avr32dci_ep_profile[4] = { 115 116 [0] = { 117 .max_in_frame_size = 64, 118 .max_out_frame_size = 64, 119 .is_simplex = 1, 120 .support_control = 1, 121 }, 122 123 [1] = { 124 .max_in_frame_size = 512, 125 .max_out_frame_size = 512, 126 .is_simplex = 1, 127 .support_bulk = 1, 128 .support_interrupt = 1, 129 .support_isochronous = 1, 130 .support_in = 1, 131 .support_out = 1, 132 }, 133 134 [2] = { 135 .max_in_frame_size = 64, 136 .max_out_frame_size = 64, 137 .is_simplex = 1, 138 .support_bulk = 1, 139 .support_interrupt = 1, 140 .support_in = 1, 141 .support_out = 1, 142 }, 143 144 [3] = { 145 .max_in_frame_size = 1024, 146 .max_out_frame_size = 1024, 147 .is_simplex = 1, 148 .support_bulk = 1, 149 .support_interrupt = 1, 150 .support_isochronous = 1, 151 .support_in = 1, 152 .support_out = 1, 153 }, 154 }; 155 156 static void 157 avr32dci_get_hw_ep_profile(struct usb_device *udev, 158 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 159 { 160 if (ep_addr == 0) 161 *ppf = avr32dci_ep_profile; 162 else if (ep_addr < 3) 163 *ppf = avr32dci_ep_profile + 1; 164 else if (ep_addr < 5) 165 *ppf = avr32dci_ep_profile + 2; 166 else if (ep_addr < 7) 167 *ppf = avr32dci_ep_profile + 3; 168 else 169 *ppf = NULL; 170 } 171 172 static void 173 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 174 { 175 uint32_t temp; 176 177 temp = AVR32_READ_4(sc, AVR32_CTRL); 178 temp |= set; 179 temp &= ~clear; 180 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 181 } 182 183 static void 184 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 185 { 186 uint32_t temp; 187 188 temp = AVR32_READ_4(sc, AVR32_IEN); 189 temp |= set; 190 temp &= ~clear; 191 AVR32_WRITE_4(sc, AVR32_IEN, temp); 192 } 193 194 static void 195 avr32dci_clocks_on(struct avr32dci_softc *sc) 196 { 197 if (sc->sc_flags.clocks_off && 198 sc->sc_flags.port_powered) { 199 200 DPRINTFN(5, "\n"); 201 202 /* turn on clocks */ 203 (sc->sc_clocks_on) (&sc->sc_bus); 204 205 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 206 207 sc->sc_flags.clocks_off = 0; 208 } 209 } 210 211 static void 212 avr32dci_clocks_off(struct avr32dci_softc *sc) 213 { 214 if (!sc->sc_flags.clocks_off) { 215 216 DPRINTFN(5, "\n"); 217 218 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 219 220 /* turn clocks off */ 221 (sc->sc_clocks_off) (&sc->sc_bus); 222 223 sc->sc_flags.clocks_off = 1; 224 } 225 } 226 227 static void 228 avr32dci_pull_up(struct avr32dci_softc *sc) 229 { 230 /* pullup D+, if possible */ 231 232 if (!sc->sc_flags.d_pulled_up && 233 sc->sc_flags.port_powered) { 234 sc->sc_flags.d_pulled_up = 1; 235 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 236 } 237 } 238 239 static void 240 avr32dci_pull_down(struct avr32dci_softc *sc) 241 { 242 /* pulldown D+, if possible */ 243 244 if (sc->sc_flags.d_pulled_up) { 245 sc->sc_flags.d_pulled_up = 0; 246 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 247 } 248 } 249 250 static void 251 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 252 { 253 if (!sc->sc_flags.status_suspend) { 254 return; 255 } 256 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 257 258 /* wait 8 milliseconds */ 259 /* Wait for reset to complete. */ 260 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 261 262 /* hardware should have cleared RMWKUP bit */ 263 } 264 265 static void 266 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 267 { 268 DPRINTFN(5, "addr=%d\n", addr); 269 270 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0); 271 } 272 273 static uint8_t 274 avr32dci_setup_rx(struct avr32dci_td *td) 275 { 276 struct avr32dci_softc *sc; 277 struct usb_device_request req; 278 uint16_t count; 279 uint32_t temp; 280 281 /* get pointer to softc */ 282 sc = AVR32_PC2SC(td->pc); 283 284 /* check endpoint status */ 285 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 286 287 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 288 289 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 290 goto not_complete; 291 } 292 /* clear did stall */ 293 td->did_stall = 0; 294 /* get the packet byte count */ 295 count = AVR32_EPTSTA_BYTE_COUNT(temp); 296 297 /* verify data length */ 298 if (count != td->remainder) { 299 DPRINTFN(0, "Invalid SETUP packet " 300 "length, %d bytes\n", count); 301 goto not_complete; 302 } 303 if (count != sizeof(req)) { 304 DPRINTFN(0, "Unsupported SETUP packet " 305 "length, %d bytes\n", count); 306 goto not_complete; 307 } 308 /* receive data */ 309 memcpy(&req, sc->physdata, sizeof(req)); 310 311 /* copy data into real buffer */ 312 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 313 314 td->offset = sizeof(req); 315 td->remainder = 0; 316 317 /* sneak peek the set address */ 318 if ((req.bmRequestType == UT_WRITE_DEVICE) && 319 (req.bRequest == UR_SET_ADDRESS)) { 320 sc->sc_dv_addr = req.wValue[0] & 0x7F; 321 /* must write address before ZLP */ 322 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 323 AVR32_CTRL_DEV_ADDR); 324 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 325 } else { 326 sc->sc_dv_addr = 0xFF; 327 } 328 329 /* clear SETUP packet interrupt */ 330 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 331 return (0); /* complete */ 332 333 not_complete: 334 if (temp & AVR32_EPTSTA_RX_SETUP) { 335 /* clear SETUP packet interrupt */ 336 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 337 } 338 /* abort any ongoing transfer */ 339 if (!td->did_stall) { 340 DPRINTFN(5, "stalling\n"); 341 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 342 AVR32_EPTSTA_FRCESTALL); 343 td->did_stall = 1; 344 } 345 return (1); /* not complete */ 346 } 347 348 static uint8_t 349 avr32dci_data_rx(struct avr32dci_td *td) 350 { 351 struct avr32dci_softc *sc; 352 struct usb_page_search buf_res; 353 uint16_t count; 354 uint32_t temp; 355 uint8_t to; 356 uint8_t got_short; 357 358 to = 4; /* don't loop forever! */ 359 got_short = 0; 360 361 /* get pointer to softc */ 362 sc = AVR32_PC2SC(td->pc); 363 364 repeat: 365 /* check if any of the FIFO banks have data */ 366 /* check endpoint status */ 367 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 368 369 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 370 371 if (temp & AVR32_EPTSTA_RX_SETUP) { 372 if (td->remainder == 0) { 373 /* 374 * We are actually complete and have 375 * received the next SETUP 376 */ 377 DPRINTFN(5, "faking complete\n"); 378 return (0); /* complete */ 379 } 380 /* 381 * USB Host Aborted the transfer. 382 */ 383 td->error = 1; 384 return (0); /* complete */ 385 } 386 /* check status */ 387 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 388 /* no data */ 389 goto not_complete; 390 } 391 /* get the packet byte count */ 392 count = AVR32_EPTSTA_BYTE_COUNT(temp); 393 394 /* verify the packet byte count */ 395 if (count != td->max_packet_size) { 396 if (count < td->max_packet_size) { 397 /* we have a short packet */ 398 td->short_pkt = 1; 399 got_short = 1; 400 } else { 401 /* invalid USB packet */ 402 td->error = 1; 403 return (0); /* we are complete */ 404 } 405 } 406 /* verify the packet byte count */ 407 if (count > td->remainder) { 408 /* invalid USB packet */ 409 td->error = 1; 410 return (0); /* we are complete */ 411 } 412 while (count > 0) { 413 usbd_get_page(td->pc, td->offset, &buf_res); 414 415 /* get correct length */ 416 if (buf_res.length > count) { 417 buf_res.length = count; 418 } 419 /* receive data */ 420 memcpy(buf_res.buffer, sc->physdata + 421 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 422 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length); 423 /* update counters */ 424 count -= buf_res.length; 425 td->offset += buf_res.length; 426 td->remainder -= buf_res.length; 427 } 428 429 /* clear OUT packet interrupt */ 430 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 431 432 /* check if we are complete */ 433 if ((td->remainder == 0) || got_short) { 434 if (td->short_pkt) { 435 /* we are complete */ 436 return (0); 437 } 438 /* else need to receive a zero length packet */ 439 } 440 if (--to) { 441 goto repeat; 442 } 443 not_complete: 444 return (1); /* not complete */ 445 } 446 447 static uint8_t 448 avr32dci_data_tx(struct avr32dci_td *td) 449 { 450 struct avr32dci_softc *sc; 451 struct usb_page_search buf_res; 452 uint16_t count; 453 uint8_t to; 454 uint32_t temp; 455 456 to = 4; /* don't loop forever! */ 457 458 /* get pointer to softc */ 459 sc = AVR32_PC2SC(td->pc); 460 461 repeat: 462 463 /* check endpoint status */ 464 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 465 466 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 467 468 if (temp & AVR32_EPTSTA_RX_SETUP) { 469 /* 470 * The current transfer was aborted 471 * by the USB Host 472 */ 473 td->error = 1; 474 return (0); /* complete */ 475 } 476 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 477 /* cannot write any data - all banks are busy */ 478 goto not_complete; 479 } 480 count = td->max_packet_size; 481 if (td->remainder < count) { 482 /* we have a short packet */ 483 td->short_pkt = 1; 484 count = td->remainder; 485 } 486 while (count > 0) { 487 488 usbd_get_page(td->pc, td->offset, &buf_res); 489 490 /* get correct length */ 491 if (buf_res.length > count) { 492 buf_res.length = count; 493 } 494 /* transmit data */ 495 memcpy(sc->physdata + 496 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 497 (td->ep_no << 16) + (td->offset % td->max_packet_size), 498 buf_res.buffer, buf_res.length); 499 /* update counters */ 500 count -= buf_res.length; 501 td->offset += buf_res.length; 502 td->remainder -= buf_res.length; 503 } 504 505 /* allocate FIFO bank */ 506 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY); 507 508 /* check remainder */ 509 if (td->remainder == 0) { 510 if (td->short_pkt) { 511 return (0); /* complete */ 512 } 513 /* else we need to transmit a short packet */ 514 } 515 if (--to) { 516 goto repeat; 517 } 518 not_complete: 519 return (1); /* not complete */ 520 } 521 522 static uint8_t 523 avr32dci_data_tx_sync(struct avr32dci_td *td) 524 { 525 struct avr32dci_softc *sc; 526 uint32_t temp; 527 528 /* get pointer to softc */ 529 sc = AVR32_PC2SC(td->pc); 530 531 /* check endpoint status */ 532 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 533 534 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 535 536 if (temp & AVR32_EPTSTA_RX_SETUP) { 537 DPRINTFN(5, "faking complete\n"); 538 /* Race condition */ 539 return (0); /* complete */ 540 } 541 /* 542 * The control endpoint has only got one bank, so if that bank 543 * is free the packet has been transferred! 544 */ 545 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 546 /* cannot write any data - a bank is busy */ 547 goto not_complete; 548 } 549 if (sc->sc_dv_addr != 0xFF) { 550 /* set new address */ 551 avr32dci_set_address(sc, sc->sc_dv_addr); 552 } 553 return (0); /* complete */ 554 555 not_complete: 556 return (1); /* not complete */ 557 } 558 559 static uint8_t 560 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 561 { 562 struct avr32dci_td *td; 563 564 DPRINTFN(9, "\n"); 565 566 td = xfer->td_transfer_cache; 567 while (1) { 568 if ((td->func) (td)) { 569 /* operation in progress */ 570 break; 571 } 572 if (((void *)td) == xfer->td_transfer_last) { 573 goto done; 574 } 575 if (td->error) { 576 goto done; 577 } else if (td->remainder > 0) { 578 /* 579 * We had a short transfer. If there is no alternate 580 * next, stop processing ! 581 */ 582 if (!td->alt_next) { 583 goto done; 584 } 585 } 586 /* 587 * Fetch the next transfer descriptor and transfer 588 * some flags to the next transfer descriptor 589 */ 590 td = td->obj_next; 591 xfer->td_transfer_cache = td; 592 } 593 return (1); /* not complete */ 594 595 done: 596 /* compute all actual lengths */ 597 598 avr32dci_standard_done(xfer); 599 return (0); /* complete */ 600 } 601 602 static void 603 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 604 { 605 struct usb_xfer *xfer; 606 607 repeat: 608 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 609 if (!avr32dci_xfer_do_fifo(xfer)) { 610 /* queue has been modified */ 611 goto repeat; 612 } 613 } 614 } 615 616 void 617 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 618 { 619 DPRINTFN(5, "vbus = %u\n", is_on); 620 621 if (is_on) { 622 if (!sc->sc_flags.status_vbus) { 623 sc->sc_flags.status_vbus = 1; 624 625 /* complete root HUB interrupt endpoint */ 626 627 avr32dci_root_intr(sc); 628 } 629 } else { 630 if (sc->sc_flags.status_vbus) { 631 sc->sc_flags.status_vbus = 0; 632 sc->sc_flags.status_bus_reset = 0; 633 sc->sc_flags.status_suspend = 0; 634 sc->sc_flags.change_suspend = 0; 635 sc->sc_flags.change_connect = 1; 636 637 /* complete root HUB interrupt endpoint */ 638 639 avr32dci_root_intr(sc); 640 } 641 } 642 } 643 644 void 645 avr32dci_interrupt(struct avr32dci_softc *sc) 646 { 647 uint32_t status; 648 649 USB_BUS_LOCK(&sc->sc_bus); 650 651 /* read interrupt status */ 652 status = AVR32_READ_4(sc, AVR32_INTSTA); 653 654 /* clear all set interrupts */ 655 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 656 657 DPRINTFN(14, "INTSTA=0x%08x\n", status); 658 659 /* check for any bus state change interrupts */ 660 if (status & AVR32_INT_ENDRESET) { 661 662 DPRINTFN(5, "end of reset\n"); 663 664 /* set correct state */ 665 sc->sc_flags.status_bus_reset = 1; 666 sc->sc_flags.status_suspend = 0; 667 sc->sc_flags.change_suspend = 0; 668 sc->sc_flags.change_connect = 1; 669 670 /* disable resume interrupt */ 671 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 672 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 673 674 /* complete root HUB interrupt endpoint */ 675 avr32dci_root_intr(sc); 676 } 677 /* 678 * If resume and suspend is set at the same time we interpret 679 * that like RESUME. Resume is set when there is at least 3 680 * milliseconds of inactivity on the USB BUS. 681 */ 682 if (status & AVR32_INT_WAKE_UP) { 683 684 DPRINTFN(5, "resume interrupt\n"); 685 686 if (sc->sc_flags.status_suspend) { 687 /* update status bits */ 688 sc->sc_flags.status_suspend = 0; 689 sc->sc_flags.change_suspend = 1; 690 691 /* disable resume interrupt */ 692 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 693 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 694 695 /* complete root HUB interrupt endpoint */ 696 avr32dci_root_intr(sc); 697 } 698 } else if (status & AVR32_INT_DET_SUSPD) { 699 700 DPRINTFN(5, "suspend interrupt\n"); 701 702 if (!sc->sc_flags.status_suspend) { 703 /* update status bits */ 704 sc->sc_flags.status_suspend = 1; 705 sc->sc_flags.change_suspend = 1; 706 707 /* disable suspend interrupt */ 708 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 709 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 710 711 /* complete root HUB interrupt endpoint */ 712 avr32dci_root_intr(sc); 713 } 714 } 715 /* check for any endpoint interrupts */ 716 if (status & -AVR32_INT_EPT_INT(0)) { 717 718 DPRINTFN(5, "real endpoint interrupt\n"); 719 720 avr32dci_interrupt_poll(sc); 721 } 722 USB_BUS_UNLOCK(&sc->sc_bus); 723 } 724 725 static void 726 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 727 { 728 struct avr32dci_td *td; 729 730 /* get current Transfer Descriptor */ 731 td = temp->td_next; 732 temp->td = td; 733 734 /* prepare for next TD */ 735 temp->td_next = td->obj_next; 736 737 /* fill out the Transfer Descriptor */ 738 td->func = temp->func; 739 td->pc = temp->pc; 740 td->offset = temp->offset; 741 td->remainder = temp->len; 742 td->error = 0; 743 td->did_stall = temp->did_stall; 744 td->short_pkt = temp->short_pkt; 745 td->alt_next = temp->setup_alt_next; 746 } 747 748 static void 749 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 750 { 751 struct avr32dci_std_temp temp; 752 struct avr32dci_softc *sc; 753 struct avr32dci_td *td; 754 uint32_t x; 755 uint8_t ep_no; 756 uint8_t need_sync; 757 758 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 759 xfer->address, UE_GET_ADDR(xfer->endpointno), 760 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 761 762 temp.max_frame_size = xfer->max_frame_size; 763 764 td = xfer->td_start[0]; 765 xfer->td_transfer_first = td; 766 xfer->td_transfer_cache = td; 767 768 /* setup temp */ 769 770 temp.pc = NULL; 771 temp.td = NULL; 772 temp.td_next = xfer->td_start[0]; 773 temp.offset = 0; 774 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 775 xfer->flags_int.isochronous_xfr; 776 temp.did_stall = !xfer->flags_int.control_stall; 777 778 sc = AVR32_BUS2SC(xfer->xroot->bus); 779 ep_no = (xfer->endpointno & UE_ADDR); 780 781 /* check if we should prepend a setup message */ 782 783 if (xfer->flags_int.control_xfr) { 784 if (xfer->flags_int.control_hdr) { 785 786 temp.func = &avr32dci_setup_rx; 787 temp.len = xfer->frlengths[0]; 788 temp.pc = xfer->frbuffers + 0; 789 temp.short_pkt = temp.len ? 1 : 0; 790 /* check for last frame */ 791 if (xfer->nframes == 1) { 792 /* no STATUS stage yet, SETUP is last */ 793 if (xfer->flags_int.control_act) 794 temp.setup_alt_next = 0; 795 } 796 avr32dci_setup_standard_chain_sub(&temp); 797 } 798 x = 1; 799 } else { 800 x = 0; 801 } 802 803 if (x != xfer->nframes) { 804 if (xfer->endpointno & UE_DIR_IN) { 805 temp.func = &avr32dci_data_tx; 806 need_sync = 1; 807 } else { 808 temp.func = &avr32dci_data_rx; 809 need_sync = 0; 810 } 811 812 /* setup "pc" pointer */ 813 temp.pc = xfer->frbuffers + x; 814 } else { 815 need_sync = 0; 816 } 817 while (x != xfer->nframes) { 818 819 /* DATA0 / DATA1 message */ 820 821 temp.len = xfer->frlengths[x]; 822 823 x++; 824 825 if (x == xfer->nframes) { 826 if (xfer->flags_int.control_xfr) { 827 if (xfer->flags_int.control_act) { 828 temp.setup_alt_next = 0; 829 } 830 } else { 831 temp.setup_alt_next = 0; 832 } 833 } 834 if (temp.len == 0) { 835 836 /* make sure that we send an USB packet */ 837 838 temp.short_pkt = 0; 839 840 } else { 841 842 /* regular data transfer */ 843 844 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 845 } 846 847 avr32dci_setup_standard_chain_sub(&temp); 848 849 if (xfer->flags_int.isochronous_xfr) { 850 temp.offset += temp.len; 851 } else { 852 /* get next Page Cache pointer */ 853 temp.pc = xfer->frbuffers + x; 854 } 855 } 856 857 if (xfer->flags_int.control_xfr) { 858 859 /* always setup a valid "pc" pointer for status and sync */ 860 temp.pc = xfer->frbuffers + 0; 861 temp.len = 0; 862 temp.short_pkt = 0; 863 temp.setup_alt_next = 0; 864 865 /* check if we need to sync */ 866 if (need_sync) { 867 /* we need a SYNC point after TX */ 868 temp.func = &avr32dci_data_tx_sync; 869 avr32dci_setup_standard_chain_sub(&temp); 870 } 871 /* check if we should append a status stage */ 872 if (!xfer->flags_int.control_act) { 873 874 /* 875 * Send a DATA1 message and invert the current 876 * endpoint direction. 877 */ 878 if (xfer->endpointno & UE_DIR_IN) { 879 temp.func = &avr32dci_data_rx; 880 need_sync = 0; 881 } else { 882 temp.func = &avr32dci_data_tx; 883 need_sync = 1; 884 } 885 886 avr32dci_setup_standard_chain_sub(&temp); 887 if (need_sync) { 888 /* we need a SYNC point after TX */ 889 temp.func = &avr32dci_data_tx_sync; 890 avr32dci_setup_standard_chain_sub(&temp); 891 } 892 } 893 } 894 /* must have at least one frame! */ 895 td = temp.td; 896 xfer->td_transfer_last = td; 897 } 898 899 static void 900 avr32dci_timeout(void *arg) 901 { 902 struct usb_xfer *xfer = arg; 903 904 DPRINTF("xfer=%p\n", xfer); 905 906 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 907 908 /* transfer is transferred */ 909 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 910 } 911 912 static void 913 avr32dci_start_standard_chain(struct usb_xfer *xfer) 914 { 915 DPRINTFN(9, "\n"); 916 917 /* poll one time - will turn on interrupts */ 918 if (avr32dci_xfer_do_fifo(xfer)) { 919 uint8_t ep_no = xfer->endpointno & UE_ADDR; 920 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 921 922 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 923 924 /* put transfer on interrupt queue */ 925 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 926 927 /* start timeout, if any */ 928 if (xfer->timeout != 0) { 929 usbd_transfer_timeout_ms(xfer, 930 &avr32dci_timeout, xfer->timeout); 931 } 932 } 933 } 934 935 static void 936 avr32dci_root_intr(struct avr32dci_softc *sc) 937 { 938 DPRINTFN(9, "\n"); 939 940 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 941 942 /* set port bit */ 943 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 944 945 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 946 sizeof(sc->sc_hub_idata)); 947 } 948 949 static usb_error_t 950 avr32dci_standard_done_sub(struct usb_xfer *xfer) 951 { 952 struct avr32dci_td *td; 953 uint32_t len; 954 uint8_t error; 955 956 DPRINTFN(9, "\n"); 957 958 td = xfer->td_transfer_cache; 959 960 do { 961 len = td->remainder; 962 963 if (xfer->aframes != xfer->nframes) { 964 /* 965 * Verify the length and subtract 966 * the remainder from "frlengths[]": 967 */ 968 if (len > xfer->frlengths[xfer->aframes]) { 969 td->error = 1; 970 } else { 971 xfer->frlengths[xfer->aframes] -= len; 972 } 973 } 974 /* Check for transfer error */ 975 if (td->error) { 976 /* the transfer is finished */ 977 error = 1; 978 td = NULL; 979 break; 980 } 981 /* Check for short transfer */ 982 if (len > 0) { 983 if (xfer->flags_int.short_frames_ok || 984 xfer->flags_int.isochronous_xfr) { 985 /* follow alt next */ 986 if (td->alt_next) { 987 td = td->obj_next; 988 } else { 989 td = NULL; 990 } 991 } else { 992 /* the transfer is finished */ 993 td = NULL; 994 } 995 error = 0; 996 break; 997 } 998 td = td->obj_next; 999 1000 /* this USB frame is complete */ 1001 error = 0; 1002 break; 1003 1004 } while (0); 1005 1006 /* update transfer cache */ 1007 1008 xfer->td_transfer_cache = td; 1009 1010 return (error ? 1011 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1012 } 1013 1014 static void 1015 avr32dci_standard_done(struct usb_xfer *xfer) 1016 { 1017 usb_error_t err = 0; 1018 1019 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1020 xfer, xfer->endpoint); 1021 1022 /* reset scanner */ 1023 1024 xfer->td_transfer_cache = xfer->td_transfer_first; 1025 1026 if (xfer->flags_int.control_xfr) { 1027 1028 if (xfer->flags_int.control_hdr) { 1029 1030 err = avr32dci_standard_done_sub(xfer); 1031 } 1032 xfer->aframes = 1; 1033 1034 if (xfer->td_transfer_cache == NULL) { 1035 goto done; 1036 } 1037 } 1038 while (xfer->aframes != xfer->nframes) { 1039 1040 err = avr32dci_standard_done_sub(xfer); 1041 xfer->aframes++; 1042 1043 if (xfer->td_transfer_cache == NULL) { 1044 goto done; 1045 } 1046 } 1047 1048 if (xfer->flags_int.control_xfr && 1049 !xfer->flags_int.control_act) { 1050 1051 err = avr32dci_standard_done_sub(xfer); 1052 } 1053 done: 1054 avr32dci_device_done(xfer, err); 1055 } 1056 1057 /*------------------------------------------------------------------------* 1058 * avr32dci_device_done 1059 * 1060 * NOTE: this function can be called more than one time on the 1061 * same USB transfer! 1062 *------------------------------------------------------------------------*/ 1063 static void 1064 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1065 { 1066 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1067 uint8_t ep_no; 1068 1069 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1070 1071 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1072 xfer, xfer->endpoint, error); 1073 1074 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1075 ep_no = (xfer->endpointno & UE_ADDR); 1076 1077 /* disable endpoint interrupt */ 1078 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1079 1080 DPRINTFN(15, "disabled interrupts!\n"); 1081 } 1082 /* dequeue transfer and start next transfer */ 1083 usbd_transfer_done(xfer, error); 1084 } 1085 1086 static void 1087 avr32dci_xfer_stall(struct usb_xfer *xfer) 1088 { 1089 avr32dci_device_done(xfer, USB_ERR_STALLED); 1090 } 1091 1092 static void 1093 avr32dci_set_stall(struct usb_device *udev, 1094 struct usb_endpoint *pipe, uint8_t *did_stall) 1095 { 1096 struct avr32dci_softc *sc; 1097 uint8_t ep_no; 1098 1099 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1100 1101 DPRINTFN(5, "pipe=%p\n", pipe); 1102 1103 sc = AVR32_BUS2SC(udev->bus); 1104 /* get endpoint number */ 1105 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1106 /* set stall */ 1107 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1108 } 1109 1110 static void 1111 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1112 uint8_t ep_type, uint8_t ep_dir) 1113 { 1114 const struct usb_hw_ep_profile *pf; 1115 uint32_t temp; 1116 uint32_t epsize; 1117 uint8_t n; 1118 1119 if (ep_type == UE_CONTROL) { 1120 /* clearing stall is not needed */ 1121 return; 1122 } 1123 /* set endpoint reset */ 1124 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1125 1126 /* set stall */ 1127 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1128 1129 /* reset data toggle */ 1130 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1131 1132 /* clear stall */ 1133 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1134 1135 if (ep_type == UE_BULK) { 1136 temp = AVR32_EPTCFG_TYPE_BULK; 1137 } else if (ep_type == UE_INTERRUPT) { 1138 temp = AVR32_EPTCFG_TYPE_INTR; 1139 } else { 1140 temp = AVR32_EPTCFG_TYPE_ISOC | 1141 AVR32_EPTCFG_NB_TRANS(1); 1142 } 1143 if (ep_dir & UE_DIR_IN) { 1144 temp |= AVR32_EPTCFG_EPDIR_IN; 1145 } 1146 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1147 1148 /* compute endpoint size (use maximum) */ 1149 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1150 n = 0; 1151 while ((epsize /= 2)) 1152 n++; 1153 temp |= AVR32_EPTCFG_EPSIZE(n); 1154 1155 /* use the maximum number of banks supported */ 1156 if (ep_no < 1) 1157 temp |= AVR32_EPTCFG_NBANK(1); 1158 else if (ep_no < 3) 1159 temp |= AVR32_EPTCFG_NBANK(2); 1160 else 1161 temp |= AVR32_EPTCFG_NBANK(3); 1162 1163 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1164 1165 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1166 1167 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1168 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1169 } else { 1170 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1171 AVR32_EPTCTL_EPT_ENABL); 1172 } 1173 } 1174 1175 static void 1176 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe) 1177 { 1178 struct avr32dci_softc *sc; 1179 struct usb_endpoint_descriptor *ed; 1180 1181 DPRINTFN(5, "pipe=%p\n", pipe); 1182 1183 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1184 1185 /* check mode */ 1186 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1187 /* not supported */ 1188 return; 1189 } 1190 /* get softc */ 1191 sc = AVR32_BUS2SC(udev->bus); 1192 1193 /* get endpoint descriptor */ 1194 ed = pipe->edesc; 1195 1196 /* reset endpoint */ 1197 avr32dci_clear_stall_sub(sc, 1198 (ed->bEndpointAddress & UE_ADDR), 1199 (ed->bmAttributes & UE_XFERTYPE), 1200 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1201 } 1202 1203 usb_error_t 1204 avr32dci_init(struct avr32dci_softc *sc) 1205 { 1206 uint8_t n; 1207 1208 DPRINTF("start\n"); 1209 1210 /* set up the bus structure */ 1211 sc->sc_bus.usbrev = USB_REV_1_1; 1212 sc->sc_bus.methods = &avr32dci_bus_methods; 1213 1214 USB_BUS_LOCK(&sc->sc_bus); 1215 1216 /* make sure USB is enabled */ 1217 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1218 1219 /* turn on clocks */ 1220 (sc->sc_clocks_on) (&sc->sc_bus); 1221 1222 /* make sure device is re-enumerated */ 1223 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1224 1225 /* wait a little for things to stabilise */ 1226 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1227 1228 /* disable interrupts */ 1229 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1230 1231 /* enable interrupts */ 1232 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1233 AVR32_INT_ENDRESET, 0); 1234 1235 /* reset all endpoints */ 1236 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1237 1238 /* disable all endpoints */ 1239 for (n = 0; n != AVR32_EP_MAX; n++) { 1240 /* disable endpoint */ 1241 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1242 } 1243 1244 /* turn off clocks */ 1245 1246 avr32dci_clocks_off(sc); 1247 1248 USB_BUS_UNLOCK(&sc->sc_bus); 1249 1250 /* catch any lost interrupts */ 1251 1252 avr32dci_do_poll(&sc->sc_bus); 1253 1254 return (0); /* success */ 1255 } 1256 1257 void 1258 avr32dci_uninit(struct avr32dci_softc *sc) 1259 { 1260 uint8_t n; 1261 1262 USB_BUS_LOCK(&sc->sc_bus); 1263 1264 /* turn on clocks */ 1265 (sc->sc_clocks_on) (&sc->sc_bus); 1266 1267 /* disable interrupts */ 1268 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1269 1270 /* reset all endpoints */ 1271 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1); 1272 1273 /* disable all endpoints */ 1274 for (n = 0; n != AVR32_EP_MAX; n++) { 1275 /* disable endpoint */ 1276 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1277 } 1278 1279 sc->sc_flags.port_powered = 0; 1280 sc->sc_flags.status_vbus = 0; 1281 sc->sc_flags.status_bus_reset = 0; 1282 sc->sc_flags.status_suspend = 0; 1283 sc->sc_flags.change_suspend = 0; 1284 sc->sc_flags.change_connect = 1; 1285 1286 avr32dci_pull_down(sc); 1287 avr32dci_clocks_off(sc); 1288 1289 USB_BUS_UNLOCK(&sc->sc_bus); 1290 } 1291 1292 static void 1293 avr32dci_suspend(struct avr32dci_softc *sc) 1294 { 1295 /* TODO */ 1296 } 1297 1298 static void 1299 avr32dci_resume(struct avr32dci_softc *sc) 1300 { 1301 /* TODO */ 1302 } 1303 1304 static void 1305 avr32dci_do_poll(struct usb_bus *bus) 1306 { 1307 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1308 1309 USB_BUS_LOCK(&sc->sc_bus); 1310 avr32dci_interrupt_poll(sc); 1311 USB_BUS_UNLOCK(&sc->sc_bus); 1312 } 1313 1314 /*------------------------------------------------------------------------* 1315 * avr32dci bulk support 1316 * avr32dci control support 1317 * avr32dci interrupt support 1318 *------------------------------------------------------------------------*/ 1319 static void 1320 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1321 { 1322 return; 1323 } 1324 1325 static void 1326 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1327 { 1328 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1329 } 1330 1331 static void 1332 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1333 { 1334 return; 1335 } 1336 1337 static void 1338 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1339 { 1340 /* setup TDs */ 1341 avr32dci_setup_standard_chain(xfer); 1342 avr32dci_start_standard_chain(xfer); 1343 } 1344 1345 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1346 { 1347 .open = avr32dci_device_non_isoc_open, 1348 .close = avr32dci_device_non_isoc_close, 1349 .enter = avr32dci_device_non_isoc_enter, 1350 .start = avr32dci_device_non_isoc_start, 1351 }; 1352 1353 /*------------------------------------------------------------------------* 1354 * avr32dci full speed isochronous support 1355 *------------------------------------------------------------------------*/ 1356 static void 1357 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1358 { 1359 return; 1360 } 1361 1362 static void 1363 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1364 { 1365 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1366 } 1367 1368 static void 1369 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1370 { 1371 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1372 uint32_t temp; 1373 uint32_t nframes; 1374 uint8_t ep_no; 1375 1376 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1377 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1378 1379 /* get the current frame index */ 1380 ep_no = xfer->endpointno & UE_ADDR; 1381 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1382 1383 nframes &= AVR32_FRAME_MASK; 1384 1385 /* 1386 * check if the frame index is within the window where the frames 1387 * will be inserted 1388 */ 1389 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK; 1390 1391 if ((xfer->endpoint->is_synced == 0) || 1392 (temp < xfer->nframes)) { 1393 /* 1394 * If there is data underflow or the pipe queue is 1395 * empty we schedule the transfer a few frames ahead 1396 * of the current frame position. Else two isochronous 1397 * transfers might overlap. 1398 */ 1399 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1400 xfer->endpoint->is_synced = 1; 1401 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1402 } 1403 /* 1404 * compute how many milliseconds the insertion is ahead of the 1405 * current frame position: 1406 */ 1407 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK; 1408 1409 /* 1410 * pre-compute when the isochronous transfer will be finished: 1411 */ 1412 xfer->isoc_time_complete = 1413 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1414 xfer->nframes; 1415 1416 /* compute frame number for next insertion */ 1417 xfer->endpoint->isoc_next += xfer->nframes; 1418 1419 /* setup TDs */ 1420 avr32dci_setup_standard_chain(xfer); 1421 } 1422 1423 static void 1424 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1425 { 1426 /* start TD chain */ 1427 avr32dci_start_standard_chain(xfer); 1428 } 1429 1430 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1431 { 1432 .open = avr32dci_device_isoc_fs_open, 1433 .close = avr32dci_device_isoc_fs_close, 1434 .enter = avr32dci_device_isoc_fs_enter, 1435 .start = avr32dci_device_isoc_fs_start, 1436 }; 1437 1438 /*------------------------------------------------------------------------* 1439 * avr32dci root control support 1440 *------------------------------------------------------------------------* 1441 * Simulate a hardware HUB by handling all the necessary requests. 1442 *------------------------------------------------------------------------*/ 1443 1444 static const struct usb_device_descriptor avr32dci_devd = { 1445 .bLength = sizeof(struct usb_device_descriptor), 1446 .bDescriptorType = UDESC_DEVICE, 1447 .bcdUSB = {0x00, 0x02}, 1448 .bDeviceClass = UDCLASS_HUB, 1449 .bDeviceSubClass = UDSUBCLASS_HUB, 1450 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1451 .bMaxPacketSize = 64, 1452 .bcdDevice = {0x00, 0x01}, 1453 .iManufacturer = 1, 1454 .iProduct = 2, 1455 .bNumConfigurations = 1, 1456 }; 1457 1458 static const struct usb_device_qualifier avr32dci_odevd = { 1459 .bLength = sizeof(struct usb_device_qualifier), 1460 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1461 .bcdUSB = {0x00, 0x02}, 1462 .bDeviceClass = UDCLASS_HUB, 1463 .bDeviceSubClass = UDSUBCLASS_HUB, 1464 .bDeviceProtocol = UDPROTO_FSHUB, 1465 .bMaxPacketSize0 = 0, 1466 .bNumConfigurations = 0, 1467 }; 1468 1469 static const struct avr32dci_config_desc avr32dci_confd = { 1470 .confd = { 1471 .bLength = sizeof(struct usb_config_descriptor), 1472 .bDescriptorType = UDESC_CONFIG, 1473 .wTotalLength[0] = sizeof(avr32dci_confd), 1474 .bNumInterface = 1, 1475 .bConfigurationValue = 1, 1476 .iConfiguration = 0, 1477 .bmAttributes = UC_SELF_POWERED, 1478 .bMaxPower = 0, 1479 }, 1480 .ifcd = { 1481 .bLength = sizeof(struct usb_interface_descriptor), 1482 .bDescriptorType = UDESC_INTERFACE, 1483 .bNumEndpoints = 1, 1484 .bInterfaceClass = UICLASS_HUB, 1485 .bInterfaceSubClass = UISUBCLASS_HUB, 1486 .bInterfaceProtocol = 0, 1487 }, 1488 .endpd = { 1489 .bLength = sizeof(struct usb_endpoint_descriptor), 1490 .bDescriptorType = UDESC_ENDPOINT, 1491 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1492 .bmAttributes = UE_INTERRUPT, 1493 .wMaxPacketSize[0] = 8, 1494 .bInterval = 255, 1495 }, 1496 }; 1497 1498 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1499 1500 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1501 .bDescLength = sizeof(avr32dci_hubd), 1502 .bDescriptorType = UDESC_HUB, 1503 .bNbrPorts = 1, 1504 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1505 .bPwrOn2PwrGood = 50, 1506 .bHubContrCurrent = 0, 1507 .DeviceRemovable = {0}, /* port is removable */ 1508 }; 1509 1510 #define STRING_VENDOR \ 1511 "A\0V\0R\0003\0002" 1512 1513 #define STRING_PRODUCT \ 1514 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1515 1516 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1517 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1518 1519 static usb_error_t 1520 avr32dci_roothub_exec(struct usb_device *udev, 1521 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1522 { 1523 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1524 const void *ptr; 1525 uint16_t len; 1526 uint16_t value; 1527 uint16_t index; 1528 uint32_t temp; 1529 usb_error_t err; 1530 1531 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1532 1533 /* buffer reset */ 1534 ptr = (const void *)&sc->sc_hub_temp; 1535 len = 0; 1536 err = 0; 1537 1538 value = UGETW(req->wValue); 1539 index = UGETW(req->wIndex); 1540 1541 /* demultiplex the control request */ 1542 1543 switch (req->bmRequestType) { 1544 case UT_READ_DEVICE: 1545 switch (req->bRequest) { 1546 case UR_GET_DESCRIPTOR: 1547 goto tr_handle_get_descriptor; 1548 case UR_GET_CONFIG: 1549 goto tr_handle_get_config; 1550 case UR_GET_STATUS: 1551 goto tr_handle_get_status; 1552 default: 1553 goto tr_stalled; 1554 } 1555 break; 1556 1557 case UT_WRITE_DEVICE: 1558 switch (req->bRequest) { 1559 case UR_SET_ADDRESS: 1560 goto tr_handle_set_address; 1561 case UR_SET_CONFIG: 1562 goto tr_handle_set_config; 1563 case UR_CLEAR_FEATURE: 1564 goto tr_valid; /* nop */ 1565 case UR_SET_DESCRIPTOR: 1566 goto tr_valid; /* nop */ 1567 case UR_SET_FEATURE: 1568 default: 1569 goto tr_stalled; 1570 } 1571 break; 1572 1573 case UT_WRITE_ENDPOINT: 1574 switch (req->bRequest) { 1575 case UR_CLEAR_FEATURE: 1576 switch (UGETW(req->wValue)) { 1577 case UF_ENDPOINT_HALT: 1578 goto tr_handle_clear_halt; 1579 case UF_DEVICE_REMOTE_WAKEUP: 1580 goto tr_handle_clear_wakeup; 1581 default: 1582 goto tr_stalled; 1583 } 1584 break; 1585 case UR_SET_FEATURE: 1586 switch (UGETW(req->wValue)) { 1587 case UF_ENDPOINT_HALT: 1588 goto tr_handle_set_halt; 1589 case UF_DEVICE_REMOTE_WAKEUP: 1590 goto tr_handle_set_wakeup; 1591 default: 1592 goto tr_stalled; 1593 } 1594 break; 1595 case UR_SYNCH_FRAME: 1596 goto tr_valid; /* nop */ 1597 default: 1598 goto tr_stalled; 1599 } 1600 break; 1601 1602 case UT_READ_ENDPOINT: 1603 switch (req->bRequest) { 1604 case UR_GET_STATUS: 1605 goto tr_handle_get_ep_status; 1606 default: 1607 goto tr_stalled; 1608 } 1609 break; 1610 1611 case UT_WRITE_INTERFACE: 1612 switch (req->bRequest) { 1613 case UR_SET_INTERFACE: 1614 goto tr_handle_set_interface; 1615 case UR_CLEAR_FEATURE: 1616 goto tr_valid; /* nop */ 1617 case UR_SET_FEATURE: 1618 default: 1619 goto tr_stalled; 1620 } 1621 break; 1622 1623 case UT_READ_INTERFACE: 1624 switch (req->bRequest) { 1625 case UR_GET_INTERFACE: 1626 goto tr_handle_get_interface; 1627 case UR_GET_STATUS: 1628 goto tr_handle_get_iface_status; 1629 default: 1630 goto tr_stalled; 1631 } 1632 break; 1633 1634 case UT_WRITE_CLASS_INTERFACE: 1635 case UT_WRITE_VENDOR_INTERFACE: 1636 /* XXX forward */ 1637 break; 1638 1639 case UT_READ_CLASS_INTERFACE: 1640 case UT_READ_VENDOR_INTERFACE: 1641 /* XXX forward */ 1642 break; 1643 1644 case UT_WRITE_CLASS_DEVICE: 1645 switch (req->bRequest) { 1646 case UR_CLEAR_FEATURE: 1647 goto tr_valid; 1648 case UR_SET_DESCRIPTOR: 1649 case UR_SET_FEATURE: 1650 break; 1651 default: 1652 goto tr_stalled; 1653 } 1654 break; 1655 1656 case UT_WRITE_CLASS_OTHER: 1657 switch (req->bRequest) { 1658 case UR_CLEAR_FEATURE: 1659 goto tr_handle_clear_port_feature; 1660 case UR_SET_FEATURE: 1661 goto tr_handle_set_port_feature; 1662 case UR_CLEAR_TT_BUFFER: 1663 case UR_RESET_TT: 1664 case UR_STOP_TT: 1665 goto tr_valid; 1666 1667 default: 1668 goto tr_stalled; 1669 } 1670 break; 1671 1672 case UT_READ_CLASS_OTHER: 1673 switch (req->bRequest) { 1674 case UR_GET_TT_STATE: 1675 goto tr_handle_get_tt_state; 1676 case UR_GET_STATUS: 1677 goto tr_handle_get_port_status; 1678 default: 1679 goto tr_stalled; 1680 } 1681 break; 1682 1683 case UT_READ_CLASS_DEVICE: 1684 switch (req->bRequest) { 1685 case UR_GET_DESCRIPTOR: 1686 goto tr_handle_get_class_descriptor; 1687 case UR_GET_STATUS: 1688 goto tr_handle_get_class_status; 1689 1690 default: 1691 goto tr_stalled; 1692 } 1693 break; 1694 default: 1695 goto tr_stalled; 1696 } 1697 goto tr_valid; 1698 1699 tr_handle_get_descriptor: 1700 switch (value >> 8) { 1701 case UDESC_DEVICE: 1702 if (value & 0xff) { 1703 goto tr_stalled; 1704 } 1705 len = sizeof(avr32dci_devd); 1706 ptr = (const void *)&avr32dci_devd; 1707 goto tr_valid; 1708 case UDESC_CONFIG: 1709 if (value & 0xff) { 1710 goto tr_stalled; 1711 } 1712 len = sizeof(avr32dci_confd); 1713 ptr = (const void *)&avr32dci_confd; 1714 goto tr_valid; 1715 case UDESC_STRING: 1716 switch (value & 0xff) { 1717 case 0: /* Language table */ 1718 len = sizeof(usb_string_lang_en); 1719 ptr = (const void *)&usb_string_lang_en; 1720 goto tr_valid; 1721 1722 case 1: /* Vendor */ 1723 len = sizeof(avr32dci_vendor); 1724 ptr = (const void *)&avr32dci_vendor; 1725 goto tr_valid; 1726 1727 case 2: /* Product */ 1728 len = sizeof(avr32dci_product); 1729 ptr = (const void *)&avr32dci_product; 1730 goto tr_valid; 1731 default: 1732 break; 1733 } 1734 break; 1735 default: 1736 goto tr_stalled; 1737 } 1738 goto tr_stalled; 1739 1740 tr_handle_get_config: 1741 len = 1; 1742 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1743 goto tr_valid; 1744 1745 tr_handle_get_status: 1746 len = 2; 1747 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1748 goto tr_valid; 1749 1750 tr_handle_set_address: 1751 if (value & 0xFF00) { 1752 goto tr_stalled; 1753 } 1754 sc->sc_rt_addr = value; 1755 goto tr_valid; 1756 1757 tr_handle_set_config: 1758 if (value >= 2) { 1759 goto tr_stalled; 1760 } 1761 sc->sc_conf = value; 1762 goto tr_valid; 1763 1764 tr_handle_get_interface: 1765 len = 1; 1766 sc->sc_hub_temp.wValue[0] = 0; 1767 goto tr_valid; 1768 1769 tr_handle_get_tt_state: 1770 tr_handle_get_class_status: 1771 tr_handle_get_iface_status: 1772 tr_handle_get_ep_status: 1773 len = 2; 1774 USETW(sc->sc_hub_temp.wValue, 0); 1775 goto tr_valid; 1776 1777 tr_handle_set_halt: 1778 tr_handle_set_interface: 1779 tr_handle_set_wakeup: 1780 tr_handle_clear_wakeup: 1781 tr_handle_clear_halt: 1782 goto tr_valid; 1783 1784 tr_handle_clear_port_feature: 1785 if (index != 1) { 1786 goto tr_stalled; 1787 } 1788 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1789 1790 switch (value) { 1791 case UHF_PORT_SUSPEND: 1792 avr32dci_wakeup_peer(sc); 1793 break; 1794 1795 case UHF_PORT_ENABLE: 1796 sc->sc_flags.port_enabled = 0; 1797 break; 1798 1799 case UHF_PORT_TEST: 1800 case UHF_PORT_INDICATOR: 1801 case UHF_C_PORT_ENABLE: 1802 case UHF_C_PORT_OVER_CURRENT: 1803 case UHF_C_PORT_RESET: 1804 /* nops */ 1805 break; 1806 case UHF_PORT_POWER: 1807 sc->sc_flags.port_powered = 0; 1808 avr32dci_pull_down(sc); 1809 avr32dci_clocks_off(sc); 1810 break; 1811 case UHF_C_PORT_CONNECTION: 1812 /* clear connect change flag */ 1813 sc->sc_flags.change_connect = 0; 1814 1815 if (!sc->sc_flags.status_bus_reset) { 1816 /* we are not connected */ 1817 break; 1818 } 1819 /* configure the control endpoint */ 1820 /* set endpoint reset */ 1821 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1822 1823 /* set stall */ 1824 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1825 1826 /* reset data toggle */ 1827 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1828 1829 /* clear stall */ 1830 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1831 1832 /* configure */ 1833 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL | 1834 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1835 1836 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1837 1838 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1839 device_printf(sc->sc_bus.bdev, 1840 "Chip rejected configuration\n"); 1841 } else { 1842 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1843 AVR32_EPTCTL_EPT_ENABL); 1844 } 1845 break; 1846 case UHF_C_PORT_SUSPEND: 1847 sc->sc_flags.change_suspend = 0; 1848 break; 1849 default: 1850 err = USB_ERR_IOERROR; 1851 goto done; 1852 } 1853 goto tr_valid; 1854 1855 tr_handle_set_port_feature: 1856 if (index != 1) { 1857 goto tr_stalled; 1858 } 1859 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1860 1861 switch (value) { 1862 case UHF_PORT_ENABLE: 1863 sc->sc_flags.port_enabled = 1; 1864 break; 1865 case UHF_PORT_SUSPEND: 1866 case UHF_PORT_RESET: 1867 case UHF_PORT_TEST: 1868 case UHF_PORT_INDICATOR: 1869 /* nops */ 1870 break; 1871 case UHF_PORT_POWER: 1872 sc->sc_flags.port_powered = 1; 1873 break; 1874 default: 1875 err = USB_ERR_IOERROR; 1876 goto done; 1877 } 1878 goto tr_valid; 1879 1880 tr_handle_get_port_status: 1881 1882 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1883 1884 if (index != 1) { 1885 goto tr_stalled; 1886 } 1887 if (sc->sc_flags.status_vbus) { 1888 avr32dci_clocks_on(sc); 1889 avr32dci_pull_up(sc); 1890 } else { 1891 avr32dci_pull_down(sc); 1892 avr32dci_clocks_off(sc); 1893 } 1894 1895 /* Select Device Side Mode */ 1896 1897 value = UPS_PORT_MODE_DEVICE; 1898 1899 /* Check for High Speed */ 1900 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1901 value |= UPS_HIGH_SPEED; 1902 1903 if (sc->sc_flags.port_powered) { 1904 value |= UPS_PORT_POWER; 1905 } 1906 if (sc->sc_flags.port_enabled) { 1907 value |= UPS_PORT_ENABLED; 1908 } 1909 if (sc->sc_flags.status_vbus && 1910 sc->sc_flags.status_bus_reset) { 1911 value |= UPS_CURRENT_CONNECT_STATUS; 1912 } 1913 if (sc->sc_flags.status_suspend) { 1914 value |= UPS_SUSPEND; 1915 } 1916 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1917 1918 value = 0; 1919 1920 if (sc->sc_flags.change_connect) { 1921 value |= UPS_C_CONNECT_STATUS; 1922 } 1923 if (sc->sc_flags.change_suspend) { 1924 value |= UPS_C_SUSPEND; 1925 } 1926 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1927 len = sizeof(sc->sc_hub_temp.ps); 1928 goto tr_valid; 1929 1930 tr_handle_get_class_descriptor: 1931 if (value & 0xFF) { 1932 goto tr_stalled; 1933 } 1934 ptr = (const void *)&avr32dci_hubd; 1935 len = sizeof(avr32dci_hubd); 1936 goto tr_valid; 1937 1938 tr_stalled: 1939 err = USB_ERR_STALLED; 1940 tr_valid: 1941 done: 1942 *plength = len; 1943 *pptr = ptr; 1944 return (err); 1945 } 1946 1947 static void 1948 avr32dci_xfer_setup(struct usb_setup_params *parm) 1949 { 1950 const struct usb_hw_ep_profile *pf; 1951 struct avr32dci_softc *sc; 1952 struct usb_xfer *xfer; 1953 void *last_obj; 1954 uint32_t ntd; 1955 uint32_t n; 1956 uint8_t ep_no; 1957 1958 sc = AVR32_BUS2SC(parm->udev->bus); 1959 xfer = parm->curr_xfer; 1960 1961 /* 1962 * NOTE: This driver does not use any of the parameters that 1963 * are computed from the following values. Just set some 1964 * reasonable dummies: 1965 */ 1966 parm->hc_max_packet_size = 0x400; 1967 parm->hc_max_packet_count = 1; 1968 parm->hc_max_frame_size = 0x400; 1969 1970 usbd_transfer_setup_sub(parm); 1971 1972 /* 1973 * compute maximum number of TDs 1974 */ 1975 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1976 1977 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1978 + 1 /* SYNC 2 */ ; 1979 } else { 1980 1981 ntd = xfer->nframes + 1 /* SYNC */ ; 1982 } 1983 1984 /* 1985 * check if "usbd_transfer_setup_sub" set an error 1986 */ 1987 if (parm->err) 1988 return; 1989 1990 /* 1991 * allocate transfer descriptors 1992 */ 1993 last_obj = NULL; 1994 1995 /* 1996 * get profile stuff 1997 */ 1998 ep_no = xfer->endpointno & UE_ADDR; 1999 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2000 2001 if (pf == NULL) { 2002 /* should not happen */ 2003 parm->err = USB_ERR_INVAL; 2004 return; 2005 } 2006 /* align data */ 2007 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2008 2009 for (n = 0; n != ntd; n++) { 2010 2011 struct avr32dci_td *td; 2012 2013 if (parm->buf) { 2014 uint32_t temp; 2015 2016 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2017 2018 /* init TD */ 2019 td->max_packet_size = xfer->max_packet_size; 2020 td->ep_no = ep_no; 2021 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2022 td->bank_shift = 0; 2023 while ((temp /= 2)) 2024 td->bank_shift++; 2025 if (pf->support_multi_buffer) { 2026 td->support_multi_buffer = 1; 2027 } 2028 td->obj_next = last_obj; 2029 2030 last_obj = td; 2031 } 2032 parm->size[0] += sizeof(*td); 2033 } 2034 2035 xfer->td_start[0] = last_obj; 2036 } 2037 2038 static void 2039 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2040 { 2041 return; 2042 } 2043 2044 static void 2045 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2046 struct usb_endpoint *pipe) 2047 { 2048 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2049 2050 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2051 pipe, udev->address, 2052 edesc->bEndpointAddress, udev->flags.usb_mode, 2053 sc->sc_rt_addr, udev->device_index); 2054 2055 if (udev->device_index != sc->sc_rt_addr) { 2056 2057 if ((udev->speed != USB_SPEED_FULL) && 2058 (udev->speed != USB_SPEED_HIGH)) { 2059 /* not supported */ 2060 return; 2061 } 2062 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2063 pipe->methods = &avr32dci_device_isoc_fs_methods; 2064 else 2065 pipe->methods = &avr32dci_device_non_isoc_methods; 2066 } 2067 } 2068 2069 static void 2070 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2071 { 2072 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 2073 2074 switch (state) { 2075 case USB_HW_POWER_SUSPEND: 2076 avr32dci_suspend(sc); 2077 break; 2078 case USB_HW_POWER_SHUTDOWN: 2079 avr32dci_uninit(sc); 2080 break; 2081 case USB_HW_POWER_RESUME: 2082 avr32dci_resume(sc); 2083 break; 2084 default: 2085 break; 2086 } 2087 } 2088 2089 static const struct usb_bus_methods avr32dci_bus_methods = 2090 { 2091 .endpoint_init = &avr32dci_ep_init, 2092 .xfer_setup = &avr32dci_xfer_setup, 2093 .xfer_unsetup = &avr32dci_xfer_unsetup, 2094 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2095 .xfer_stall = &avr32dci_xfer_stall, 2096 .set_stall = &avr32dci_set_stall, 2097 .clear_stall = &avr32dci_clear_stall, 2098 .roothub_exec = &avr32dci_roothub_exec, 2099 .xfer_poll = &avr32dci_do_poll, 2100 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep, 2101 }; 2102