1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the AVR32 series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <sys/stdint.h> 40 #include <sys/stddef.h> 41 #include <sys/param.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sx.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 61 #define USB_DEBUG_VAR avr32dci_debug 62 63 #include <dev/usb/usb_core.h> 64 #include <dev/usb/usb_debug.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_transfer.h> 68 #include <dev/usb/usb_device.h> 69 #include <dev/usb/usb_hub.h> 70 #include <dev/usb/usb_util.h> 71 72 #include <dev/usb/usb_controller.h> 73 #include <dev/usb/usb_bus.h> 74 #include <dev/usb/controller/avr32dci.h> 75 76 #define AVR32_BUS2SC(bus) \ 77 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \ 78 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus)))) 79 80 #define AVR32_PC2SC(pc) \ 81 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 82 83 #ifdef USB_DEBUG 84 static int avr32dci_debug = 0; 85 86 SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI"); 87 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RW, 88 &avr32dci_debug, 0, "AVR32 DCI debug level"); 89 #endif 90 91 #define AVR32_INTR_ENDPT 1 92 93 /* prototypes */ 94 95 struct usb_bus_methods avr32dci_bus_methods; 96 struct usb_pipe_methods avr32dci_device_non_isoc_methods; 97 struct usb_pipe_methods avr32dci_device_isoc_fs_methods; 98 99 static avr32dci_cmd_t avr32dci_setup_rx; 100 static avr32dci_cmd_t avr32dci_data_rx; 101 static avr32dci_cmd_t avr32dci_data_tx; 102 static avr32dci_cmd_t avr32dci_data_tx_sync; 103 static void avr32dci_device_done(struct usb_xfer *, usb_error_t); 104 static void avr32dci_do_poll(struct usb_bus *); 105 static void avr32dci_standard_done(struct usb_xfer *); 106 static void avr32dci_root_intr(struct avr32dci_softc *sc); 107 108 /* 109 * Here is a list of what the chip supports: 110 */ 111 static const struct usb_hw_ep_profile 112 avr32dci_ep_profile[4] = { 113 114 [0] = { 115 .max_in_frame_size = 64, 116 .max_out_frame_size = 64, 117 .is_simplex = 1, 118 .support_control = 1, 119 }, 120 121 [1] = { 122 .max_in_frame_size = 512, 123 .max_out_frame_size = 512, 124 .is_simplex = 1, 125 .support_bulk = 1, 126 .support_interrupt = 1, 127 .support_isochronous = 1, 128 .support_in = 1, 129 .support_out = 1, 130 }, 131 132 [2] = { 133 .max_in_frame_size = 64, 134 .max_out_frame_size = 64, 135 .is_simplex = 1, 136 .support_bulk = 1, 137 .support_interrupt = 1, 138 .support_in = 1, 139 .support_out = 1, 140 }, 141 142 [3] = { 143 .max_in_frame_size = 1024, 144 .max_out_frame_size = 1024, 145 .is_simplex = 1, 146 .support_bulk = 1, 147 .support_interrupt = 1, 148 .support_isochronous = 1, 149 .support_in = 1, 150 .support_out = 1, 151 }, 152 }; 153 154 static void 155 avr32dci_get_hw_ep_profile(struct usb_device *udev, 156 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 157 { 158 if (ep_addr == 0) 159 *ppf = avr32dci_ep_profile; 160 else if (ep_addr < 3) 161 *ppf = avr32dci_ep_profile + 1; 162 else if (ep_addr < 5) 163 *ppf = avr32dci_ep_profile + 2; 164 else if (ep_addr < 7) 165 *ppf = avr32dci_ep_profile + 3; 166 else 167 *ppf = NULL; 168 } 169 170 static void 171 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 172 { 173 uint32_t temp; 174 175 temp = AVR32_READ_4(sc, AVR32_CTRL); 176 temp |= set; 177 temp &= ~clear; 178 AVR32_WRITE_4(sc, AVR32_CTRL, temp); 179 } 180 181 static void 182 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear) 183 { 184 uint32_t temp; 185 186 temp = AVR32_READ_4(sc, AVR32_IEN); 187 temp |= set; 188 temp &= ~clear; 189 AVR32_WRITE_4(sc, AVR32_IEN, temp); 190 } 191 192 static void 193 avr32dci_clocks_on(struct avr32dci_softc *sc) 194 { 195 if (sc->sc_flags.clocks_off && 196 sc->sc_flags.port_powered) { 197 198 DPRINTFN(5, "\n"); 199 200 /* turn on clocks */ 201 (sc->sc_clocks_on) (&sc->sc_bus); 202 203 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 204 205 sc->sc_flags.clocks_off = 0; 206 } 207 } 208 209 static void 210 avr32dci_clocks_off(struct avr32dci_softc *sc) 211 { 212 if (!sc->sc_flags.clocks_off) { 213 214 DPRINTFN(5, "\n"); 215 216 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA); 217 218 /* turn clocks off */ 219 (sc->sc_clocks_off) (&sc->sc_bus); 220 221 sc->sc_flags.clocks_off = 1; 222 } 223 } 224 225 static void 226 avr32dci_pull_up(struct avr32dci_softc *sc) 227 { 228 /* pullup D+, if possible */ 229 230 if (!sc->sc_flags.d_pulled_up && 231 sc->sc_flags.port_powered) { 232 sc->sc_flags.d_pulled_up = 1; 233 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH); 234 } 235 } 236 237 static void 238 avr32dci_pull_down(struct avr32dci_softc *sc) 239 { 240 /* pulldown D+, if possible */ 241 242 if (sc->sc_flags.d_pulled_up) { 243 sc->sc_flags.d_pulled_up = 0; 244 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 245 } 246 } 247 248 static void 249 avr32dci_wakeup_peer(struct avr32dci_softc *sc) 250 { 251 if (!sc->sc_flags.status_suspend) { 252 return; 253 } 254 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0); 255 256 /* wait 8 milliseconds */ 257 /* Wait for reset to complete. */ 258 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 259 260 /* hardware should have cleared RMWKUP bit */ 261 } 262 263 static void 264 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr) 265 { 266 DPRINTFN(5, "addr=%d\n", addr); 267 268 avr32dci_mod_ctrl(sc, AVR32_UDADDR_ADDEN | addr, 0); 269 } 270 271 static uint8_t 272 avr32dci_setup_rx(struct avr32dci_td *td) 273 { 274 struct avr32dci_softc *sc; 275 struct usb_device_request req; 276 uint16_t count; 277 uint32_t temp; 278 279 /* get pointer to softc */ 280 sc = AVR32_PC2SC(td->pc); 281 282 /* check endpoint status */ 283 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 284 285 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 286 287 if (!(temp & AVR32_EPTSTA_RX_SETUP)) { 288 goto not_complete; 289 } 290 /* clear did stall */ 291 td->did_stall = 0; 292 /* get the packet byte count */ 293 count = AVR32_EPTSTA_BYTE_COUNT(temp); 294 295 /* verify data length */ 296 if (count != td->remainder) { 297 DPRINTFN(0, "Invalid SETUP packet " 298 "length, %d bytes\n", count); 299 goto not_complete; 300 } 301 if (count != sizeof(req)) { 302 DPRINTFN(0, "Unsupported SETUP packet " 303 "length, %d bytes\n", count); 304 goto not_complete; 305 } 306 /* receive data */ 307 memcpy(&req, sc->physdata, sizeof(req)); 308 309 /* copy data into real buffer */ 310 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 311 312 td->offset = sizeof(req); 313 td->remainder = 0; 314 315 /* sneak peek the set address */ 316 if ((req.bmRequestType == UT_WRITE_DEVICE) && 317 (req.bRequest == UR_SET_ADDRESS)) { 318 sc->sc_dv_addr = req.wValue[0] & 0x7F; 319 /* must write address before ZLP */ 320 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN | 321 AVR32_CTRL_DEV_ADDR); 322 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0); 323 } else { 324 sc->sc_dv_addr = 0xFF; 325 } 326 327 /* clear SETUP packet interrupt */ 328 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 329 return (0); /* complete */ 330 331 not_complete: 332 if (temp & AVR32_EPTSTA_RX_SETUP) { 333 /* clear SETUP packet interrupt */ 334 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP); 335 } 336 /* abort any ongoing transfer */ 337 if (!td->did_stall) { 338 DPRINTFN(5, "stalling\n"); 339 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no), 340 AVR32_EPTSTA_FRCESTALL); 341 td->did_stall = 1; 342 } 343 return (1); /* not complete */ 344 } 345 346 static uint8_t 347 avr32dci_data_rx(struct avr32dci_td *td) 348 { 349 struct avr32dci_softc *sc; 350 struct usb_page_search buf_res; 351 uint16_t count; 352 uint32_t temp; 353 uint8_t to; 354 uint8_t got_short; 355 356 to = 4; /* don't loop forever! */ 357 got_short = 0; 358 359 /* get pointer to softc */ 360 sc = AVR32_PC2SC(td->pc); 361 362 repeat: 363 /* check if any of the FIFO banks have data */ 364 /* check endpoint status */ 365 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 366 367 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 368 369 if (temp & AVR32_EPTSTA_RX_SETUP) { 370 if (td->remainder == 0) { 371 /* 372 * We are actually complete and have 373 * received the next SETUP 374 */ 375 DPRINTFN(5, "faking complete\n"); 376 return (0); /* complete */ 377 } 378 /* 379 * USB Host Aborted the transfer. 380 */ 381 td->error = 1; 382 return (0); /* complete */ 383 } 384 /* check status */ 385 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) { 386 /* no data */ 387 goto not_complete; 388 } 389 /* get the packet byte count */ 390 count = AVR32_EPTSTA_BYTE_COUNT(temp); 391 392 /* verify the packet byte count */ 393 if (count != td->max_packet_size) { 394 if (count < td->max_packet_size) { 395 /* we have a short packet */ 396 td->short_pkt = 1; 397 got_short = 1; 398 } else { 399 /* invalid USB packet */ 400 td->error = 1; 401 return (0); /* we are complete */ 402 } 403 } 404 /* verify the packet byte count */ 405 if (count > td->remainder) { 406 /* invalid USB packet */ 407 td->error = 1; 408 return (0); /* we are complete */ 409 } 410 while (count > 0) { 411 usbd_get_page(td->pc, td->offset, &buf_res); 412 413 /* get correct length */ 414 if (buf_res.length > count) { 415 buf_res.length = count; 416 } 417 /* receive data */ 418 bcopy(sc->physdata + 419 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 420 (td->ep_no << 16) + (td->offset % td->max_packet_size), 421 buf_res.buffer, buf_res.length) 422 /* update counters */ 423 count -= buf_res.length; 424 td->offset += buf_res.length; 425 td->remainder -= buf_res.length; 426 } 427 428 /* clear OUT packet interrupt */ 429 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY); 430 431 /* check if we are complete */ 432 if ((td->remainder == 0) || got_short) { 433 if (td->short_pkt) { 434 /* we are complete */ 435 return (0); 436 } 437 /* else need to receive a zero length packet */ 438 } 439 if (--to) { 440 goto repeat; 441 } 442 not_complete: 443 return (1); /* not complete */ 444 } 445 446 static uint8_t 447 avr32dci_data_tx(struct avr32dci_td *td) 448 { 449 struct avr32dci_softc *sc; 450 struct usb_page_search buf_res; 451 uint16_t count; 452 uint8_t to; 453 uint32_t temp; 454 455 to = 4; /* don't loop forever! */ 456 457 /* get pointer to softc */ 458 sc = AVR32_PC2SC(td->pc); 459 460 repeat: 461 462 /* check endpoint status */ 463 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 464 465 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 466 467 if (temp & AVR32_EPTSTA_RX_SETUP) { 468 /* 469 * The current transfer was aborted 470 * by the USB Host 471 */ 472 td->error = 1; 473 return (0); /* complete */ 474 } 475 if (temp & AVR32_EPTSTA_TX_PK_RDY) { 476 /* cannot write any data - all banks are busy */ 477 goto not_complete; 478 } 479 count = td->max_packet_size; 480 if (td->remainder < count) { 481 /* we have a short packet */ 482 td->short_pkt = 1; 483 count = td->remainder; 484 } 485 while (count > 0) { 486 487 usbd_get_page(td->pc, td->offset, &buf_res); 488 489 /* get correct length */ 490 if (buf_res.length > count) { 491 buf_res.length = count; 492 } 493 /* transmit data */ 494 bcopy(buf_res.buffer, sc->physdata + 495 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) + 496 (td->ep_no << 16) + (td->offset % td->max_packet_size), 497 buf_res.length) 498 /* update counters */ 499 count -= buf_res.length; 500 td->offset += buf_res.length; 501 td->remainder -= buf_res.length; 502 } 503 504 /* allocate FIFO bank */ 505 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_TX_BK_RDY); 506 507 /* check remainder */ 508 if (td->remainder == 0) { 509 if (td->short_pkt) { 510 return (0); /* complete */ 511 } 512 /* else we need to transmit a short packet */ 513 } 514 if (--to) { 515 goto repeat; 516 } 517 not_complete: 518 return (1); /* not complete */ 519 } 520 521 static uint8_t 522 avr32dci_data_tx_sync(struct avr32dci_td *td) 523 { 524 struct avr32dci_softc *sc; 525 uint32_t temp; 526 527 /* get pointer to softc */ 528 sc = AVR32_PC2SC(td->pc); 529 530 /* check endpoint status */ 531 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no)); 532 533 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp); 534 535 if (temp & AVR32_EPTSTA_RX_SETUP) { 536 DPRINTFN(5, "faking complete\n"); 537 /* Race condition */ 538 return (0); /* complete */ 539 } 540 /* 541 * The control endpoint has only got one bank, so if that bank 542 * is free the packet has been transferred! 543 */ 544 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) { 545 /* cannot write any data - a bank is busy */ 546 goto not_complete; 547 } 548 if (sc->sc_dv_addr != 0xFF) { 549 /* set new address */ 550 avr32dci_set_address(sc, sc->sc_dv_addr); 551 } 552 return (0); /* complete */ 553 554 not_complete: 555 return (1); /* not complete */ 556 } 557 558 static uint8_t 559 avr32dci_xfer_do_fifo(struct usb_xfer *xfer) 560 { 561 struct avr32dci_td *td; 562 563 DPRINTFN(9, "\n"); 564 565 td = xfer->td_transfer_cache; 566 while (1) { 567 if ((td->func) (td)) { 568 /* operation in progress */ 569 break; 570 } 571 if (((void *)td) == xfer->td_transfer_last) { 572 goto done; 573 } 574 if (td->error) { 575 goto done; 576 } else if (td->remainder > 0) { 577 /* 578 * We had a short transfer. If there is no alternate 579 * next, stop processing ! 580 */ 581 if (!td->alt_next) { 582 goto done; 583 } 584 } 585 /* 586 * Fetch the next transfer descriptor and transfer 587 * some flags to the next transfer descriptor 588 */ 589 td = td->obj_next; 590 xfer->td_transfer_cache = td; 591 } 592 return (1); /* not complete */ 593 594 done: 595 /* compute all actual lengths */ 596 597 avr32dci_standard_done(xfer); 598 return (0); /* complete */ 599 } 600 601 static void 602 avr32dci_interrupt_poll(struct avr32dci_softc *sc) 603 { 604 struct usb_xfer *xfer; 605 606 repeat: 607 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 608 if (!avr32dci_xfer_do_fifo(xfer)) { 609 /* queue has been modified */ 610 goto repeat; 611 } 612 } 613 } 614 615 void 616 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on) 617 { 618 DPRINTFN(5, "vbus = %u\n", is_on); 619 620 if (is_on) { 621 if (!sc->sc_flags.status_vbus) { 622 sc->sc_flags.status_vbus = 1; 623 624 /* complete root HUB interrupt endpoint */ 625 626 avr32dci_root_intr(sc); 627 } 628 } else { 629 if (sc->sc_flags.status_vbus) { 630 sc->sc_flags.status_vbus = 0; 631 sc->sc_flags.status_bus_reset = 0; 632 sc->sc_flags.status_suspend = 0; 633 sc->sc_flags.change_suspend = 0; 634 sc->sc_flags.change_connect = 1; 635 636 /* complete root HUB interrupt endpoint */ 637 638 avr32dci_root_intr(sc); 639 } 640 } 641 } 642 643 void 644 avr32dci_interrupt(struct avr32dci_softc *sc) 645 { 646 uint32_t status; 647 648 USB_BUS_LOCK(&sc->sc_bus); 649 650 /* read interrupt status */ 651 status = AVR32_READ_4(sc, AVR32_INTSTA); 652 653 /* clear all set interrupts */ 654 AVR32_WRITE_4(sc, AVR32_CLRINT, status); 655 656 DPRINTFN(14, "INTSTA=0x%08x\n", status); 657 658 /* check for any bus state change interrupts */ 659 if (status & AVR32_INT_ENDRESET) { 660 661 DPRINTFN(5, "end of reset\n"); 662 663 /* set correct state */ 664 sc->sc_flags.status_bus_reset = 1; 665 sc->sc_flags.status_suspend = 0; 666 sc->sc_flags.change_suspend = 0; 667 sc->sc_flags.change_connect = 1; 668 669 /* disable resume interrupt */ 670 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 671 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 672 673 /* complete root HUB interrupt endpoint */ 674 avr32dci_root_intr(sc); 675 } 676 /* 677 * If resume and suspend is set at the same time we interpret 678 * that like RESUME. Resume is set when there is at least 3 679 * milliseconds of inactivity on the USB BUS. 680 */ 681 if (status & AVR32_INT_WAKE_UP) { 682 683 DPRINTFN(5, "resume interrupt\n"); 684 685 if (sc->sc_flags.status_suspend) { 686 /* update status bits */ 687 sc->sc_flags.status_suspend = 0; 688 sc->sc_flags.change_suspend = 1; 689 690 /* disable resume interrupt */ 691 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 692 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP); 693 694 /* complete root HUB interrupt endpoint */ 695 avr32dci_root_intr(sc); 696 } 697 } else if (status & AVR32_INT_DET_SUSPD) { 698 699 DPRINTFN(5, "suspend interrupt\n"); 700 701 if (!sc->sc_flags.status_suspend) { 702 /* update status bits */ 703 sc->sc_flags.status_suspend = 1; 704 sc->sc_flags.change_suspend = 1; 705 706 /* disable suspend interrupt */ 707 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP | 708 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD); 709 710 /* complete root HUB interrupt endpoint */ 711 avr32dci_root_intr(sc); 712 } 713 } 714 /* check for any endpoint interrupts */ 715 if (status & -AVR32_INT_EPT_INT(0)) { 716 717 DPRINTFN(5, "real endpoint interrupt\n"); 718 719 avr32dci_interrupt_poll(sc); 720 } 721 USB_BUS_UNLOCK(&sc->sc_bus); 722 } 723 724 static void 725 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp) 726 { 727 struct avr32dci_td *td; 728 729 /* get current Transfer Descriptor */ 730 td = temp->td_next; 731 temp->td = td; 732 733 /* prepare for next TD */ 734 temp->td_next = td->obj_next; 735 736 /* fill out the Transfer Descriptor */ 737 td->func = temp->func; 738 td->pc = temp->pc; 739 td->offset = temp->offset; 740 td->remainder = temp->len; 741 td->error = 0; 742 td->did_stall = temp->did_stall; 743 td->short_pkt = temp->short_pkt; 744 td->alt_next = temp->setup_alt_next; 745 } 746 747 static void 748 avr32dci_setup_standard_chain(struct usb_xfer *xfer) 749 { 750 struct avr32dci_std_temp temp; 751 struct avr32dci_softc *sc; 752 struct avr32dci_td *td; 753 uint32_t x; 754 uint8_t ep_no; 755 uint8_t need_sync; 756 757 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 758 xfer->address, UE_GET_ADDR(xfer->endpoint), 759 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 760 761 temp.max_frame_size = xfer->max_frame_size; 762 763 td = xfer->td_start[0]; 764 xfer->td_transfer_first = td; 765 xfer->td_transfer_cache = td; 766 767 /* setup temp */ 768 769 temp.pc = NULL; 770 temp.td = NULL; 771 temp.td_next = xfer->td_start[0]; 772 temp.offset = 0; 773 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 774 temp.did_stall = !xfer->flags_int.control_stall; 775 776 sc = AVR32_BUS2SC(xfer->xroot->bus); 777 ep_no = (xfer->endpoint & UE_ADDR); 778 779 /* check if we should prepend a setup message */ 780 781 if (xfer->flags_int.control_xfr) { 782 if (xfer->flags_int.control_hdr) { 783 784 temp.func = &avr32dci_setup_rx; 785 temp.len = xfer->frlengths[0]; 786 temp.pc = xfer->frbuffers + 0; 787 temp.short_pkt = temp.len ? 1 : 0; 788 /* check for last frame */ 789 if (xfer->nframes == 1) { 790 /* no STATUS stage yet, SETUP is last */ 791 if (xfer->flags_int.control_act) 792 temp.setup_alt_next = 0; 793 } 794 avr32dci_setup_standard_chain_sub(&temp); 795 } 796 x = 1; 797 } else { 798 x = 0; 799 } 800 801 if (x != xfer->nframes) { 802 if (xfer->endpoint & UE_DIR_IN) { 803 temp.func = &avr32dci_data_tx; 804 need_sync = 1; 805 } else { 806 temp.func = &avr32dci_data_rx; 807 need_sync = 0; 808 } 809 810 /* setup "pc" pointer */ 811 temp.pc = xfer->frbuffers + x; 812 } else { 813 need_sync = 0; 814 } 815 while (x != xfer->nframes) { 816 817 /* DATA0 / DATA1 message */ 818 819 temp.len = xfer->frlengths[x]; 820 821 x++; 822 823 if (x == xfer->nframes) { 824 if (xfer->flags_int.control_xfr) { 825 if (xfer->flags_int.control_act) { 826 temp.setup_alt_next = 0; 827 } 828 } else { 829 temp.setup_alt_next = 0; 830 } 831 } 832 if (temp.len == 0) { 833 834 /* make sure that we send an USB packet */ 835 836 temp.short_pkt = 0; 837 838 } else { 839 840 /* regular data transfer */ 841 842 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 843 } 844 845 avr32dci_setup_standard_chain_sub(&temp); 846 847 if (xfer->flags_int.isochronous_xfr) { 848 temp.offset += temp.len; 849 } else { 850 /* get next Page Cache pointer */ 851 temp.pc = xfer->frbuffers + x; 852 } 853 } 854 855 if (xfer->flags_int.control_xfr) { 856 857 /* always setup a valid "pc" pointer for status and sync */ 858 temp.pc = xfer->frbuffers + 0; 859 temp.len = 0; 860 temp.short_pkt = 0; 861 temp.setup_alt_next = 0; 862 863 /* check if we need to sync */ 864 if (need_sync) { 865 /* we need a SYNC point after TX */ 866 temp.func = &avr32dci_data_tx_sync; 867 avr32dci_setup_standard_chain_sub(&temp); 868 } 869 /* check if we should append a status stage */ 870 if (!xfer->flags_int.control_act) { 871 872 /* 873 * Send a DATA1 message and invert the current 874 * endpoint direction. 875 */ 876 if (xfer->endpoint & UE_DIR_IN) { 877 temp.func = &avr32dci_data_rx; 878 need_sync = 0; 879 } else { 880 temp.func = &avr32dci_data_tx; 881 need_sync = 1; 882 } 883 884 avr32dci_setup_standard_chain_sub(&temp); 885 if (need_sync) { 886 /* we need a SYNC point after TX */ 887 temp.func = &avr32dci_data_tx_sync; 888 avr32dci_setup_standard_chain_sub(&temp); 889 } 890 } 891 } 892 /* must have at least one frame! */ 893 td = temp.td; 894 xfer->td_transfer_last = td; 895 } 896 897 static void 898 avr32dci_timeout(void *arg) 899 { 900 struct usb_xfer *xfer = arg; 901 902 DPRINTF("xfer=%p\n", xfer); 903 904 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 905 906 /* transfer is transferred */ 907 avr32dci_device_done(xfer, USB_ERR_TIMEOUT); 908 } 909 910 static void 911 avr32dci_start_standard_chain(struct usb_xfer *xfer) 912 { 913 DPRINTFN(9, "\n"); 914 915 /* poll one time - will turn on interrupts */ 916 if (avr32dci_xfer_do_fifo(xfer)) { 917 uint8_t ep_no = xfer->endpoint & UE_ADDR_MASK; 918 919 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0); 920 921 /* put transfer on interrupt queue */ 922 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 923 924 /* start timeout, if any */ 925 if (xfer->timeout != 0) { 926 usbd_transfer_timeout_ms(xfer, 927 &avr32dci_timeout, xfer->timeout); 928 } 929 } 930 } 931 932 static void 933 avr32dci_root_intr(struct avr32dci_softc *sc) 934 { 935 DPRINTFN(9, "\n"); 936 937 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 938 939 /* set port bit */ 940 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 941 942 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 943 sizeof(sc->sc_hub_idata)); 944 } 945 946 static usb_error_t 947 avr32dci_standard_done_sub(struct usb_xfer *xfer) 948 { 949 struct avr32dci_td *td; 950 uint32_t len; 951 uint8_t error; 952 953 DPRINTFN(9, "\n"); 954 955 td = xfer->td_transfer_cache; 956 957 do { 958 len = td->remainder; 959 960 if (xfer->aframes != xfer->nframes) { 961 /* 962 * Verify the length and subtract 963 * the remainder from "frlengths[]": 964 */ 965 if (len > xfer->frlengths[xfer->aframes]) { 966 td->error = 1; 967 } else { 968 xfer->frlengths[xfer->aframes] -= len; 969 } 970 } 971 /* Check for transfer error */ 972 if (td->error) { 973 /* the transfer is finished */ 974 error = 1; 975 td = NULL; 976 break; 977 } 978 /* Check for short transfer */ 979 if (len > 0) { 980 if (xfer->flags_int.short_frames_ok) { 981 /* follow alt next */ 982 if (td->alt_next) { 983 td = td->obj_next; 984 } else { 985 td = NULL; 986 } 987 } else { 988 /* the transfer is finished */ 989 td = NULL; 990 } 991 error = 0; 992 break; 993 } 994 td = td->obj_next; 995 996 /* this USB frame is complete */ 997 error = 0; 998 break; 999 1000 } while (0); 1001 1002 /* update transfer cache */ 1003 1004 xfer->td_transfer_cache = td; 1005 1006 return (error ? 1007 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1008 } 1009 1010 static void 1011 avr32dci_standard_done(struct usb_xfer *xfer) 1012 { 1013 usb_error_t err = 0; 1014 1015 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1016 xfer, xfer->pipe); 1017 1018 /* reset scanner */ 1019 1020 xfer->td_transfer_cache = xfer->td_transfer_first; 1021 1022 if (xfer->flags_int.control_xfr) { 1023 1024 if (xfer->flags_int.control_hdr) { 1025 1026 err = avr32dci_standard_done_sub(xfer); 1027 } 1028 xfer->aframes = 1; 1029 1030 if (xfer->td_transfer_cache == NULL) { 1031 goto done; 1032 } 1033 } 1034 while (xfer->aframes != xfer->nframes) { 1035 1036 err = avr32dci_standard_done_sub(xfer); 1037 xfer->aframes++; 1038 1039 if (xfer->td_transfer_cache == NULL) { 1040 goto done; 1041 } 1042 } 1043 1044 if (xfer->flags_int.control_xfr && 1045 !xfer->flags_int.control_act) { 1046 1047 err = avr32dci_standard_done_sub(xfer); 1048 } 1049 done: 1050 avr32dci_device_done(xfer, err); 1051 } 1052 1053 /*------------------------------------------------------------------------* 1054 * avr32dci_device_done 1055 * 1056 * NOTE: this function can be called more than one time on the 1057 * same USB transfer! 1058 *------------------------------------------------------------------------*/ 1059 static void 1060 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error) 1061 { 1062 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1063 uint8_t ep_no; 1064 1065 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1066 1067 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1068 xfer, xfer->pipe, error); 1069 1070 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1071 ep_no = (xfer->endpoint & UE_ADDR); 1072 1073 /* disable endpoint interrupt */ 1074 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no)); 1075 1076 DPRINTFN(15, "disabled interrupts!\n"); 1077 } 1078 /* dequeue transfer and start next transfer */ 1079 usbd_transfer_done(xfer, error); 1080 } 1081 1082 static void 1083 avr32dci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1084 struct usb_endpoint *ep, uint8_t *did_stall) 1085 { 1086 struct avr32dci_softc *sc; 1087 uint8_t ep_no; 1088 1089 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1090 1091 DPRINTFN(5, "pipe=%p\n", pipe); 1092 1093 if (xfer) { 1094 /* cancel any ongoing transfers */ 1095 avr32dci_device_done(xfer, USB_ERR_STALLED); 1096 } 1097 sc = AVR32_BUS2SC(udev->bus); 1098 /* get endpoint number */ 1099 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1100 /* set stall */ 1101 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1102 } 1103 1104 static void 1105 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no, 1106 uint8_t ep_type, uint8_t ep_dir) 1107 { 1108 const struct usb_hw_ep_profile *pf; 1109 uint32_t temp; 1110 uint32_t epsize; 1111 uint8_t n; 1112 1113 if (ep_type == UE_CONTROL) { 1114 /* clearing stall is not needed */ 1115 return; 1116 } 1117 /* set endpoint reset */ 1118 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no)); 1119 1120 /* set stall */ 1121 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1122 1123 /* reset data toggle */ 1124 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ); 1125 1126 /* clear stall */ 1127 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL); 1128 1129 if (ep_type == UE_BULK) { 1130 temp = AVR32_EPTCFG_TYPE_BULK; 1131 } else if (ep_type == UE_INTERRUPT) { 1132 temp = AVR32_EPTCFG_TYPE_INTR; 1133 } else { 1134 temp = AVR32_EPTCFG_TYPE_ISOC | 1135 AVR32_EPTCFG_NB_TRANS(1); 1136 } 1137 if (ep_dir & UE_DIR_IN) { 1138 temp |= AVR32_EPTCFG_EPDIR_IN; 1139 } 1140 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no); 1141 1142 /* compute endpoint size (use maximum) */ 1143 epsize = pf->max_in_frame_size | pf->max_out_frame_size; 1144 n = 0; 1145 while ((epsize /= 2)) 1146 n++; 1147 temp |= AVR32_EPTCFG_EPSIZE(n); 1148 1149 /* use the maximum number of banks supported */ 1150 if (ep_no < 1) 1151 temp |= AVR32_EPTCFG_NBANK(1); 1152 else if (ep_no < 3) 1153 temp |= AVR32_EPTCFG_NBANK(2); 1154 else 1155 temp |= AVR32_EPTCFG_NBANK(3); 1156 1157 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp); 1158 1159 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no)); 1160 1161 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1162 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n"); 1163 } else { 1164 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no), 1165 AVR32_EPTCTL_EPT_ENABL); 1166 } 1167 } 1168 1169 static void 1170 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1171 { 1172 struct avr32dci_softc *sc; 1173 struct usb_endpoint_descriptor *ed; 1174 1175 DPRINTFN(5, "pipe=%p\n", pipe); 1176 1177 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1178 1179 /* check mode */ 1180 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1181 /* not supported */ 1182 return; 1183 } 1184 /* get softc */ 1185 sc = AVR32_BUS2SC(udev->bus); 1186 1187 /* get endpoint descriptor */ 1188 ed = pipe->edesc; 1189 1190 /* reset endpoint */ 1191 avr32dci_clear_stall_sub(sc, 1192 (ed->bEndpointAddress & UE_ADDR), 1193 (ed->bmAttributes & UE_XFERTYPE), 1194 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1195 } 1196 1197 usb_error_t 1198 avr32dci_init(struct avr32dci_softc *sc) 1199 { 1200 uint8_t n; 1201 1202 DPRINTF("start\n"); 1203 1204 /* set up the bus structure */ 1205 sc->sc_bus.usbrev = USB_REV_1_1; 1206 sc->sc_bus.methods = &avr32dci_bus_methods; 1207 1208 USB_BUS_LOCK(&sc->sc_bus); 1209 1210 /* make sure USB is enabled */ 1211 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0); 1212 1213 /* turn on clocks */ 1214 (sc->sc_clocks_on) (&sc->sc_bus); 1215 1216 /* make sure device is re-enumerated */ 1217 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0); 1218 1219 /* wait a little for things to stabilise */ 1220 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1221 1222 /* disable interrupts */ 1223 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1224 1225 /* enable interrupts */ 1226 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD | 1227 AVR32_INT_ENDRESET, 0); 1228 1229 /* reset all endpoints */ 1230 /**INDENT** Warning@1207: Extra ) */ 1231 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1)); 1232 1233 /* disable all endpoints */ 1234 for (n = 0; n != AVR32_EP_MAX; n++) { 1235 /* disable endpoint */ 1236 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1237 } 1238 1239 /* turn off clocks */ 1240 1241 avr32dci_clocks_off(sc); 1242 1243 USB_BUS_UNLOCK(&sc->sc_bus); 1244 1245 /* catch any lost interrupts */ 1246 1247 avr32dci_do_poll(&sc->sc_bus); 1248 1249 return (0); /* success */ 1250 } 1251 1252 void 1253 avr32dci_uninit(struct avr32dci_softc *sc) 1254 { 1255 uint8_t n; 1256 1257 USB_BUS_LOCK(&sc->sc_bus); 1258 1259 /* turn on clocks */ 1260 (sc->sc_clocks_on) (&sc->sc_bus); 1261 1262 /* disable interrupts */ 1263 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF); 1264 1265 /* reset all endpoints */ 1266 /**INDENT** Warning@1242: Extra ) */ 1267 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1)); 1268 1269 /* disable all endpoints */ 1270 for (n = 0; n != AVR32_EP_MAX; n++) { 1271 /* disable endpoint */ 1272 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL); 1273 } 1274 1275 sc->sc_flags.port_powered = 0; 1276 sc->sc_flags.status_vbus = 0; 1277 sc->sc_flags.status_bus_reset = 0; 1278 sc->sc_flags.status_suspend = 0; 1279 sc->sc_flags.change_suspend = 0; 1280 sc->sc_flags.change_connect = 1; 1281 1282 avr32dci_pull_down(sc); 1283 avr32dci_clocks_off(sc); 1284 1285 USB_BUS_UNLOCK(&sc->sc_bus); 1286 } 1287 1288 void 1289 avr32dci_suspend(struct avr32dci_softc *sc) 1290 { 1291 return; 1292 } 1293 1294 void 1295 avr32dci_resume(struct avr32dci_softc *sc) 1296 { 1297 return; 1298 } 1299 1300 static void 1301 avr32dci_do_poll(struct usb_bus *bus) 1302 { 1303 struct avr32dci_softc *sc = AVR32_BUS2SC(bus); 1304 1305 USB_BUS_LOCK(&sc->sc_bus); 1306 avr32dci_interrupt_poll(sc); 1307 USB_BUS_UNLOCK(&sc->sc_bus); 1308 } 1309 1310 /*------------------------------------------------------------------------* 1311 * at91dci bulk support 1312 * at91dci control support 1313 * at91dci interrupt support 1314 *------------------------------------------------------------------------*/ 1315 static void 1316 avr32dci_device_non_isoc_open(struct usb_xfer *xfer) 1317 { 1318 return; 1319 } 1320 1321 static void 1322 avr32dci_device_non_isoc_close(struct usb_xfer *xfer) 1323 { 1324 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1325 } 1326 1327 static void 1328 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer) 1329 { 1330 return; 1331 } 1332 1333 static void 1334 avr32dci_device_non_isoc_start(struct usb_xfer *xfer) 1335 { 1336 /* setup TDs */ 1337 avr32dci_setup_standard_chain(xfer); 1338 avr32dci_start_standard_chain(xfer); 1339 } 1340 1341 struct usb_pipe_methods avr32dci_device_non_isoc_methods = 1342 { 1343 .open = avr32dci_device_non_isoc_open, 1344 .close = avr32dci_device_non_isoc_close, 1345 .enter = avr32dci_device_non_isoc_enter, 1346 .start = avr32dci_device_non_isoc_start, 1347 }; 1348 1349 /*------------------------------------------------------------------------* 1350 * at91dci full speed isochronous support 1351 *------------------------------------------------------------------------*/ 1352 static void 1353 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer) 1354 { 1355 return; 1356 } 1357 1358 static void 1359 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer) 1360 { 1361 avr32dci_device_done(xfer, USB_ERR_CANCELLED); 1362 } 1363 1364 static void 1365 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer) 1366 { 1367 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus); 1368 uint32_t temp; 1369 uint32_t nframes; 1370 uint8_t ep_no; 1371 1372 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1373 xfer, xfer->pipe->isoc_next, xfer->nframes); 1374 1375 /* get the current frame index */ 1376 ep_no = xfer->endpoint & UE_ADDR_MASK; 1377 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8); 1378 1379 nframes &= AVR32_FRAME_MASK; 1380 1381 /* 1382 * check if the frame index is within the window where the frames 1383 * will be inserted 1384 */ 1385 temp = (nframes - xfer->pipe->isoc_next) & AVR32_FRAME_MASK; 1386 1387 if ((xfer->pipe->is_synced == 0) || 1388 (temp < xfer->nframes)) { 1389 /* 1390 * If there is data underflow or the pipe queue is 1391 * empty we schedule the transfer a few frames ahead 1392 * of the current frame position. Else two isochronous 1393 * transfers might overlap. 1394 */ 1395 xfer->pipe->isoc_next = (nframes + 3) & AVR32_FRAME_MASK; 1396 xfer->pipe->is_synced = 1; 1397 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1398 } 1399 /* 1400 * compute how many milliseconds the insertion is ahead of the 1401 * current frame position: 1402 */ 1403 temp = (xfer->pipe->isoc_next - nframes) & AVR32_FRAME_MASK; 1404 1405 /* 1406 * pre-compute when the isochronous transfer will be finished: 1407 */ 1408 xfer->isoc_time_complete = 1409 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1410 xfer->nframes; 1411 1412 /* compute frame number for next insertion */ 1413 xfer->pipe->isoc_next += xfer->nframes; 1414 1415 /* setup TDs */ 1416 avr32dci_setup_standard_chain(xfer); 1417 } 1418 1419 static void 1420 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer) 1421 { 1422 /* start TD chain */ 1423 avr32dci_start_standard_chain(xfer); 1424 } 1425 1426 struct usb_pipe_methods avr32dci_device_isoc_fs_methods = 1427 { 1428 .open = avr32dci_device_isoc_fs_open, 1429 .close = avr32dci_device_isoc_fs_close, 1430 .enter = avr32dci_device_isoc_fs_enter, 1431 .start = avr32dci_device_isoc_fs_start, 1432 }; 1433 1434 /*------------------------------------------------------------------------* 1435 * at91dci root control support 1436 *------------------------------------------------------------------------* 1437 * Simulate a hardware HUB by handling all the necessary requests. 1438 *------------------------------------------------------------------------*/ 1439 1440 static const struct usb_device_descriptor avr32dci_devd = { 1441 .bLength = sizeof(struct usb_device_descriptor), 1442 .bDescriptorType = UDESC_DEVICE, 1443 .bcdUSB = {0x00, 0x02}, 1444 .bDeviceClass = UDCLASS_HUB, 1445 .bDeviceSubClass = UDSUBCLASS_HUB, 1446 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1447 .bMaxPacketSize = 64, 1448 .bcdDevice = {0x00, 0x01}, 1449 .iManufacturer = 1, 1450 .iProduct = 2, 1451 .bNumConfigurations = 1, 1452 }; 1453 1454 static const struct usb_device_qualifier avr32dci_odevd = { 1455 .bLength = sizeof(struct usb_device_qualifier), 1456 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1457 .bcdUSB = {0x00, 0x02}, 1458 .bDeviceClass = UDCLASS_HUB, 1459 .bDeviceSubClass = UDSUBCLASS_HUB, 1460 .bDeviceProtocol = UDPROTO_FSHUB, 1461 .bMaxPacketSize0 = 0, 1462 .bNumConfigurations = 0, 1463 }; 1464 1465 static const struct avr32dci_config_desc avr32dci_confd = { 1466 .confd = { 1467 .bLength = sizeof(struct usb_config_descriptor), 1468 .bDescriptorType = UDESC_CONFIG, 1469 .wTotalLength[0] = sizeof(avr32dci_confd), 1470 .bNumInterface = 1, 1471 .bConfigurationValue = 1, 1472 .iConfiguration = 0, 1473 .bmAttributes = UC_SELF_POWERED, 1474 .bMaxPower = 0, 1475 }, 1476 .ifcd = { 1477 .bLength = sizeof(struct usb_interface_descriptor), 1478 .bDescriptorType = UDESC_INTERFACE, 1479 .bNumEndpoints = 1, 1480 .bInterfaceClass = UICLASS_HUB, 1481 .bInterfaceSubClass = UISUBCLASS_HUB, 1482 .bInterfaceProtocol = 0, 1483 }, 1484 .endpd = { 1485 .bLength = sizeof(struct usb_endpoint_descriptor), 1486 .bDescriptorType = UDESC_ENDPOINT, 1487 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT), 1488 .bmAttributes = UE_INTERRUPT, 1489 .wMaxPacketSize[0] = 8, 1490 .bInterval = 255, 1491 }, 1492 }; 1493 1494 static const struct usb_hub_descriptor_min avr32dci_hubd = { 1495 .bDescLength = sizeof(avr32dci_hubd), 1496 .bDescriptorType = UDESC_HUB, 1497 .bNbrPorts = 1, 1498 .wHubCharacteristics[0] = 1499 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1500 .wHubCharacteristics[1] = 1501 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1502 .bPwrOn2PwrGood = 50, 1503 .bHubContrCurrent = 0, 1504 .DeviceRemovable = {0}, /* port is removable */ 1505 }; 1506 1507 #define STRING_LANG \ 1508 0x09, 0x04, /* American English */ 1509 1510 #define STRING_VENDOR \ 1511 'A', 0, 'V', 0, 'R', 0, '3', 0, '2', 0 1512 1513 #define STRING_PRODUCT \ 1514 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1515 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1516 'U', 0, 'B', 0, 1517 1518 USB_MAKE_STRING_DESC(STRING_LANG, avr32dci_langtab); 1519 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor); 1520 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product); 1521 1522 static usb_error_t 1523 avr32dci_roothub_exec(struct usb_device *udev, 1524 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1525 { 1526 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 1527 const void *ptr; 1528 uint16_t len; 1529 uint16_t value; 1530 uint16_t index; 1531 uint32_t temp; 1532 usb_error_t err; 1533 1534 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1535 1536 /* buffer reset */ 1537 ptr = (const void *)&sc->sc_hub_temp; 1538 len = 0; 1539 err = 0; 1540 1541 value = UGETW(req->wValue); 1542 index = UGETW(req->wIndex); 1543 1544 /* demultiplex the control request */ 1545 1546 switch (req->bmRequestType) { 1547 case UT_READ_DEVICE: 1548 switch (req->bRequest) { 1549 case UR_GET_DESCRIPTOR: 1550 goto tr_handle_get_descriptor; 1551 case UR_GET_CONFIG: 1552 goto tr_handle_get_config; 1553 case UR_GET_STATUS: 1554 goto tr_handle_get_status; 1555 default: 1556 goto tr_stalled; 1557 } 1558 break; 1559 1560 case UT_WRITE_DEVICE: 1561 switch (req->bRequest) { 1562 case UR_SET_ADDRESS: 1563 goto tr_handle_set_address; 1564 case UR_SET_CONFIG: 1565 goto tr_handle_set_config; 1566 case UR_CLEAR_FEATURE: 1567 goto tr_valid; /* nop */ 1568 case UR_SET_DESCRIPTOR: 1569 goto tr_valid; /* nop */ 1570 case UR_SET_FEATURE: 1571 default: 1572 goto tr_stalled; 1573 } 1574 break; 1575 1576 case UT_WRITE_ENDPOINT: 1577 switch (req->bRequest) { 1578 case UR_CLEAR_FEATURE: 1579 switch (UGETW(req->wValue)) { 1580 case UF_ENDPOINT_HALT: 1581 goto tr_handle_clear_halt; 1582 case UF_DEVICE_REMOTE_WAKEUP: 1583 goto tr_handle_clear_wakeup; 1584 default: 1585 goto tr_stalled; 1586 } 1587 break; 1588 case UR_SET_FEATURE: 1589 switch (UGETW(req->wValue)) { 1590 case UF_ENDPOINT_HALT: 1591 goto tr_handle_set_halt; 1592 case UF_DEVICE_REMOTE_WAKEUP: 1593 goto tr_handle_set_wakeup; 1594 default: 1595 goto tr_stalled; 1596 } 1597 break; 1598 case UR_SYNCH_FRAME: 1599 goto tr_valid; /* nop */ 1600 default: 1601 goto tr_stalled; 1602 } 1603 break; 1604 1605 case UT_READ_ENDPOINT: 1606 switch (req->bRequest) { 1607 case UR_GET_STATUS: 1608 goto tr_handle_get_ep_status; 1609 default: 1610 goto tr_stalled; 1611 } 1612 break; 1613 1614 case UT_WRITE_INTERFACE: 1615 switch (req->bRequest) { 1616 case UR_SET_INTERFACE: 1617 goto tr_handle_set_interface; 1618 case UR_CLEAR_FEATURE: 1619 goto tr_valid; /* nop */ 1620 case UR_SET_FEATURE: 1621 default: 1622 goto tr_stalled; 1623 } 1624 break; 1625 1626 case UT_READ_INTERFACE: 1627 switch (req->bRequest) { 1628 case UR_GET_INTERFACE: 1629 goto tr_handle_get_interface; 1630 case UR_GET_STATUS: 1631 goto tr_handle_get_iface_status; 1632 default: 1633 goto tr_stalled; 1634 } 1635 break; 1636 1637 case UT_WRITE_CLASS_INTERFACE: 1638 case UT_WRITE_VENDOR_INTERFACE: 1639 /* XXX forward */ 1640 break; 1641 1642 case UT_READ_CLASS_INTERFACE: 1643 case UT_READ_VENDOR_INTERFACE: 1644 /* XXX forward */ 1645 break; 1646 1647 case UT_WRITE_CLASS_DEVICE: 1648 switch (req->bRequest) { 1649 case UR_CLEAR_FEATURE: 1650 goto tr_valid; 1651 case UR_SET_DESCRIPTOR: 1652 case UR_SET_FEATURE: 1653 break; 1654 default: 1655 goto tr_stalled; 1656 } 1657 break; 1658 1659 case UT_WRITE_CLASS_OTHER: 1660 switch (req->bRequest) { 1661 case UR_CLEAR_FEATURE: 1662 goto tr_handle_clear_port_feature; 1663 case UR_SET_FEATURE: 1664 goto tr_handle_set_port_feature; 1665 case UR_CLEAR_TT_BUFFER: 1666 case UR_RESET_TT: 1667 case UR_STOP_TT: 1668 goto tr_valid; 1669 1670 default: 1671 goto tr_stalled; 1672 } 1673 break; 1674 1675 case UT_READ_CLASS_OTHER: 1676 switch (req->bRequest) { 1677 case UR_GET_TT_STATE: 1678 goto tr_handle_get_tt_state; 1679 case UR_GET_STATUS: 1680 goto tr_handle_get_port_status; 1681 default: 1682 goto tr_stalled; 1683 } 1684 break; 1685 1686 case UT_READ_CLASS_DEVICE: 1687 switch (req->bRequest) { 1688 case UR_GET_DESCRIPTOR: 1689 goto tr_handle_get_class_descriptor; 1690 case UR_GET_STATUS: 1691 goto tr_handle_get_class_status; 1692 1693 default: 1694 goto tr_stalled; 1695 } 1696 break; 1697 default: 1698 goto tr_stalled; 1699 } 1700 goto tr_valid; 1701 1702 tr_handle_get_descriptor: 1703 switch (value >> 8) { 1704 case UDESC_DEVICE: 1705 if (value & 0xff) { 1706 goto tr_stalled; 1707 } 1708 len = sizeof(avr32dci_devd); 1709 ptr = (const void *)&avr32dci_devd; 1710 goto tr_valid; 1711 case UDESC_CONFIG: 1712 if (value & 0xff) { 1713 goto tr_stalled; 1714 } 1715 len = sizeof(avr32dci_confd); 1716 ptr = (const void *)&avr32dci_confd; 1717 goto tr_valid; 1718 case UDESC_STRING: 1719 switch (value & 0xff) { 1720 case 0: /* Language table */ 1721 len = sizeof(avr32dci_langtab); 1722 ptr = (const void *)&avr32dci_langtab; 1723 goto tr_valid; 1724 1725 case 1: /* Vendor */ 1726 len = sizeof(avr32dci_vendor); 1727 ptr = (const void *)&avr32dci_vendor; 1728 goto tr_valid; 1729 1730 case 2: /* Product */ 1731 len = sizeof(avr32dci_product); 1732 ptr = (const void *)&avr32dci_product; 1733 goto tr_valid; 1734 default: 1735 break; 1736 } 1737 break; 1738 default: 1739 goto tr_stalled; 1740 } 1741 goto tr_stalled; 1742 1743 tr_handle_get_config: 1744 len = 1; 1745 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1746 goto tr_valid; 1747 1748 tr_handle_get_status: 1749 len = 2; 1750 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1751 goto tr_valid; 1752 1753 tr_handle_set_address: 1754 if (value & 0xFF00) { 1755 goto tr_stalled; 1756 } 1757 sc->sc_rt_addr = value; 1758 goto tr_valid; 1759 1760 tr_handle_set_config: 1761 if (value >= 2) { 1762 goto tr_stalled; 1763 } 1764 sc->sc_conf = value; 1765 goto tr_valid; 1766 1767 tr_handle_get_interface: 1768 len = 1; 1769 sc->sc_hub_temp.wValue[0] = 0; 1770 goto tr_valid; 1771 1772 tr_handle_get_tt_state: 1773 tr_handle_get_class_status: 1774 tr_handle_get_iface_status: 1775 tr_handle_get_ep_status: 1776 len = 2; 1777 USETW(sc->sc_hub_temp.wValue, 0); 1778 goto tr_valid; 1779 1780 tr_handle_set_halt: 1781 tr_handle_set_interface: 1782 tr_handle_set_wakeup: 1783 tr_handle_clear_wakeup: 1784 tr_handle_clear_halt: 1785 goto tr_valid; 1786 1787 tr_handle_clear_port_feature: 1788 if (index != 1) { 1789 goto tr_stalled; 1790 } 1791 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1792 1793 switch (value) { 1794 case UHF_PORT_SUSPEND: 1795 avr32dci_wakeup_peer(sc); 1796 break; 1797 1798 case UHF_PORT_ENABLE: 1799 sc->sc_flags.port_enabled = 0; 1800 break; 1801 1802 case UHF_PORT_TEST: 1803 case UHF_PORT_INDICATOR: 1804 case UHF_C_PORT_ENABLE: 1805 case UHF_C_PORT_OVER_CURRENT: 1806 case UHF_C_PORT_RESET: 1807 /* nops */ 1808 break; 1809 case UHF_PORT_POWER: 1810 sc->sc_flags.port_powered = 0; 1811 avr32dci_pull_down(sc); 1812 avr32dci_clocks_off(sc); 1813 break; 1814 case UHF_C_PORT_CONNECTION: 1815 /* clear connect change flag */ 1816 sc->sc_flags.change_connect = 0; 1817 1818 if (!sc->sc_flags.status_bus_reset) { 1819 /* we are not connected */ 1820 break; 1821 } 1822 /* configure the control endpoint */ 1823 /* set endpoint reset */ 1824 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0)); 1825 1826 /* set stall */ 1827 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL); 1828 1829 /* reset data toggle */ 1830 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ); 1831 1832 /* clear stall */ 1833 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL); 1834 1835 /* configure */ 1836 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CONTROL | 1837 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6)); 1838 1839 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0)); 1840 1841 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) { 1842 device_printf(sc->sc_bus.bdev, 1843 "Chip rejected configuration\n"); 1844 } else { 1845 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0), 1846 AVR32_EPTCTL_EPT_ENABL); 1847 } 1848 break; 1849 case UHF_C_PORT_SUSPEND: 1850 sc->sc_flags.change_suspend = 0; 1851 break; 1852 default: 1853 err = USB_ERR_IOERROR; 1854 goto done; 1855 } 1856 goto tr_valid; 1857 1858 tr_handle_set_port_feature: 1859 if (index != 1) { 1860 goto tr_stalled; 1861 } 1862 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1863 1864 switch (value) { 1865 case UHF_PORT_ENABLE: 1866 sc->sc_flags.port_enabled = 1; 1867 break; 1868 case UHF_PORT_SUSPEND: 1869 case UHF_PORT_RESET: 1870 case UHF_PORT_TEST: 1871 case UHF_PORT_INDICATOR: 1872 /* nops */ 1873 break; 1874 case UHF_PORT_POWER: 1875 sc->sc_flags.port_powered = 1; 1876 break; 1877 default: 1878 err = USB_ERR_IOERROR; 1879 goto done; 1880 } 1881 goto tr_valid; 1882 1883 tr_handle_get_port_status: 1884 1885 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1886 1887 if (index != 1) { 1888 goto tr_stalled; 1889 } 1890 if (sc->sc_flags.status_vbus) { 1891 avr32dci_clocks_on(sc); 1892 avr32dci_pull_up(sc); 1893 } else { 1894 avr32dci_pull_down(sc); 1895 avr32dci_clocks_off(sc); 1896 } 1897 1898 /* Select Device Side Mode */ 1899 1900 value = UPS_PORT_MODE_DEVICE; 1901 1902 /* Check for High Speed */ 1903 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED) 1904 value |= UPS_HIGH_SPEED; 1905 1906 if (sc->sc_flags.port_powered) { 1907 value |= UPS_PORT_POWER; 1908 } 1909 if (sc->sc_flags.port_enabled) { 1910 value |= UPS_PORT_ENABLED; 1911 } 1912 if (sc->sc_flags.status_vbus && 1913 sc->sc_flags.status_bus_reset) { 1914 value |= UPS_CURRENT_CONNECT_STATUS; 1915 } 1916 if (sc->sc_flags.status_suspend) { 1917 value |= UPS_SUSPEND; 1918 } 1919 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1920 1921 value = 0; 1922 1923 if (sc->sc_flags.change_connect) { 1924 value |= UPS_C_CONNECT_STATUS; 1925 } 1926 if (sc->sc_flags.change_suspend) { 1927 value |= UPS_C_SUSPEND; 1928 } 1929 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1930 len = sizeof(sc->sc_hub_temp.ps); 1931 goto tr_valid; 1932 1933 tr_handle_get_class_descriptor: 1934 if (value & 0xFF) { 1935 goto tr_stalled; 1936 } 1937 ptr = (const void *)&avr32dci_hubd; 1938 len = sizeof(avr32dci_hubd); 1939 goto tr_valid; 1940 1941 tr_stalled: 1942 err = USB_ERR_STALLED; 1943 tr_valid: 1944 done: 1945 *plength = len; 1946 *pptr = ptr; 1947 return (err); 1948 } 1949 1950 static void 1951 avr32dci_xfer_setup(struct usb_setup_params *parm) 1952 { 1953 const struct usb_hw_ep_profile *pf; 1954 struct avr32dci_softc *sc; 1955 struct usb_xfer *xfer; 1956 void *last_obj; 1957 uint32_t ntd; 1958 uint32_t n; 1959 uint8_t ep_no; 1960 1961 sc = AVR32_BUS2SC(parm->udev->bus); 1962 xfer = parm->curr_xfer; 1963 1964 /* 1965 * NOTE: This driver does not use any of the parameters that 1966 * are computed from the following values. Just set some 1967 * reasonable dummies: 1968 */ 1969 parm->hc_max_packet_size = 0x400; 1970 parm->hc_max_packet_count = 1; 1971 parm->hc_max_frame_size = 0x400; 1972 1973 usbd_transfer_setup_sub(parm); 1974 1975 /* 1976 * compute maximum number of TDs 1977 */ 1978 if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1979 1980 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1981 + 1 /* SYNC 2 */ ; 1982 } else { 1983 1984 ntd = xfer->nframes + 1 /* SYNC */ ; 1985 } 1986 1987 /* 1988 * check if "usbd_transfer_setup_sub" set an error 1989 */ 1990 if (parm->err) 1991 return; 1992 1993 /* 1994 * allocate transfer descriptors 1995 */ 1996 last_obj = NULL; 1997 1998 /* 1999 * get profile stuff 2000 */ 2001 ep_no = xfer->endpoint & UE_ADDR; 2002 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2003 2004 if (pf == NULL) { 2005 /* should not happen */ 2006 parm->err = USB_ERR_INVAL; 2007 return; 2008 } 2009 /* align data */ 2010 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2011 2012 for (n = 0; n != ntd; n++) { 2013 2014 struct avr32dci_td *td; 2015 2016 if (parm->buf) { 2017 uint32_t temp; 2018 2019 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2020 2021 /* init TD */ 2022 td->max_packet_size = xfer->max_packet_size; 2023 td->ep_no = ep_no; 2024 temp = pf->max_in_frame_size | pf->max_out_frame_size; 2025 td->bank_shift = 0; 2026 while ((temp /= 2)) 2027 td->bank_shift++; 2028 if (pf->support_multi_buffer) { 2029 td->support_multi_buffer = 1; 2030 } 2031 td->obj_next = last_obj; 2032 2033 last_obj = td; 2034 } 2035 parm->size[0] += sizeof(*td); 2036 } 2037 2038 xfer->td_start[0] = last_obj; 2039 } 2040 2041 static void 2042 avr32dci_xfer_unsetup(struct usb_xfer *xfer) 2043 { 2044 return; 2045 } 2046 2047 static void 2048 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2049 struct usb_endpoint *ep) 2050 { 2051 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus); 2052 2053 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2054 pipe, udev->address, 2055 edesc->bEndpointAddress, udev->flags.usb_mode, 2056 sc->sc_rt_addr, udev->device_index); 2057 2058 if (udev->device_index != sc->sc_rt_addr) { 2059 2060 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2061 /* not supported */ 2062 return; 2063 } 2064 if ((udev->speed != USB_SPEED_FULL) && 2065 (udev->speed != USB_SPEED_HIGH)) { 2066 /* not supported */ 2067 return; 2068 } 2069 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2070 pipe->methods = &avr32dci_device_isoc_fs_methods; 2071 else 2072 pipe->methods = &avr32dci_device_non_isoc_methods; 2073 } 2074 } 2075 2076 struct usb_bus_methods avr32dci_bus_methods = 2077 { 2078 .endpoint_init = &avr32dci_ep_init, 2079 .xfer_setup = &avr32dci_xfer_setup, 2080 .xfer_unsetup = &avr32dci_xfer_unsetup, 2081 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile, 2082 .set_stall = &avr32dci_set_stall, 2083 .clear_stall = &avr32dci_clear_stall, 2084 .roothub_exec = &avr32dci_roothub_exec, 2085 .xfer_poll = &avr32dci_do_poll, 2086 }; 2087