1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * USB Device Port register definitions, copied from ATMEGA documentation 31 * provided by ATMEL. 32 */ 33 34 #ifndef _ATMEGADCI_H_ 35 #define _ATMEGADCI_H_ 36 37 #define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1) 38 39 #define ATMEGA_OTGTCON 0xF9 40 #define ATMEGA_OTGTCON_VALUE(x) ((x) << 0) 41 #define ATMEGA_OTGTCON_PAGE(x) ((x) << 5) 42 43 #define ATMEGA_UEINT 0xF4 44 #define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */ 45 46 #define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */ 47 #define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */ 48 #define ATMEGA_UEDATX 0xF1 /* FIFO data */ 49 50 #define ATMEGA_UEIENX 0xF0 /* interrupt enable register */ 51 #define ATMEGA_UEIENX_TXINE (1 << 0) 52 #define ATMEGA_UEIENX_STALLEDE (1 << 1) 53 #define ATMEGA_UEIENX_RXOUTE (1 << 2) 54 #define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */ 55 #define ATMEGA_UEIENX_NAKOUTE (1 << 4) 56 #define ATMEGA_UEIENX_NAKINE (1 << 6) 57 #define ATMEGA_UEIENX_FLERRE (1 << 7) 58 59 #define ATMEGA_UESTA1X 0xEF 60 #define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */ 61 #define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */ 62 63 #define ATMEGA_UESTA0X 0xEE 64 #define ATMEGA_UESTA0X_NBUSYBK (3 << 0) 65 #define ATMEGA_UESTA0X_DTSEQ (3 << 2) 66 #define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */ 67 #define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */ 68 #define ATMEGA_UESTA0X_CFGOK (1 << 7) 69 70 #define ATMEGA_UECFG1X 0xED /* endpoint config register */ 71 #define ATMEGA_UECFG1X_ALLOC (1 << 1) 72 #define ATMEGA_UECFG1X_EPBK0 (0 << 2) 73 #define ATMEGA_UECFG1X_EPBK1 (1 << 2) 74 #define ATMEGA_UECFG1X_EPBK2 (2 << 2) 75 #define ATMEGA_UECFG1X_EPBK3 (3 << 2) 76 #define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4) 77 78 #define ATMEGA_UECFG0X 0xEC 79 #define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */ 80 #define ATMEGA_UECFG0X_EPTYPE0 (0 << 6) 81 #define ATMEGA_UECFG0X_EPTYPE1 (1 << 6) 82 #define ATMEGA_UECFG0X_EPTYPE2 (2 << 6) 83 #define ATMEGA_UECFG0X_EPTYPE3 (3 << 6) 84 85 #define ATMEGA_UECONX 0xEB 86 #define ATMEGA_UECONX_EPEN (1 << 0) 87 #define ATMEGA_UECONX_RSTDT (1 << 3) 88 #define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */ 89 #define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */ 90 91 #define ATMEGA_UERST 0xEA /* endpoint reset register */ 92 #define ATMEGA_UERST_MASK(n) (1 << (n)) 93 94 #define ATMEGA_UENUM 0xE9 /* endpoint number */ 95 96 #define ATMEGA_UEINTX 0xE8 /* interrupt register */ 97 #define ATMEGA_UEINTX_TXINI (1 << 0) 98 #define ATMEGA_UEINTX_STALLEDI (1 << 1) 99 #define ATMEGA_UEINTX_RXOUTI (1 << 2) 100 #define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */ 101 #define ATMEGA_UEINTX_NAKOUTI (1 << 4) 102 #define ATMEGA_UEINTX_RWAL (1 << 5) 103 #define ATMEGA_UEINTX_NAKINI (1 << 6) 104 #define ATMEGA_UEINTX_FIFOCON (1 << 7) 105 106 #define ATMEGA_UDMFN 0xE6 107 #define ATMEGA_UDMFN_FNCERR (1 << 4) 108 109 #define ATMEGA_UDFNUMH 0xE5 /* frame number high */ 110 #define ATMEGA_UDFNUMH_MASK 7 111 112 #define ATMEGA_UDFNUML 0xE4 /* frame number low */ 113 #define ATMEGA_UDFNUML_MASK 0xFF 114 115 #define ATMEGA_FRAME_MASK 0x7FF 116 117 #define ATMEGA_UDADDR 0xE3 /* USB address */ 118 #define ATMEGA_UDADDR_MASK 0x7F 119 #define ATMEGA_UDADDR_ADDEN (1 << 7) 120 121 #define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */ 122 #define ATMEGA_UDINT_SUSPE (1 << 0) 123 #define ATMEGA_UDINT_MSOFE (1 << 1) 124 #define ATMEGA_UDINT_SOFE (1 << 2) 125 #define ATMEGA_UDINT_EORSTE (1 << 3) 126 #define ATMEGA_UDINT_WAKEUPE (1 << 4) 127 #define ATMEGA_UDINT_EORSME (1 << 5) 128 #define ATMEGA_UDINT_UPRSME (1 << 6) 129 130 #define ATMEGA_UDINT 0xE1 /* USB device interrupt status */ 131 #define ATMEGA_UDINT_SUSPI (1 << 0) 132 #define ATMEGA_UDINT_MSOFI (1 << 1) 133 #define ATMEGA_UDINT_SOFI (1 << 2) 134 #define ATMEGA_UDINT_EORSTI (1 << 3) 135 #define ATMEGA_UDINT_WAKEUPI (1 << 4) 136 #define ATMEGA_UDINT_EORSMI (1 << 5) 137 #define ATMEGA_UDINT_UPRSMI (1 << 6) 138 139 #define ATMEGA_UDCON 0xE0 /* USB device connection register */ 140 #define ATMEGA_UDCON_DETACH (1 << 0) 141 #define ATMEGA_UDCON_RMWKUP (1 << 1) 142 #define ATMEGA_UDCON_LSM (1 << 2) 143 #define ATMEGA_UDCON_RSTCPU (1 << 3) 144 145 #define ATMEGA_OTGINT 0xDF 146 147 #define ATMEGA_OTGCON 0xDD 148 #define ATMEGA_OTGCON_VBUSRQC (1 << 0) 149 #define ATMEGA_OTGCON_VBUSREQ (1 << 1) 150 #define ATMEGA_OTGCON_VBUSHWC (1 << 2) 151 #define ATMEGA_OTGCON_SRPSEL (1 << 3) 152 #define ATMEGA_OTGCON_SRPREQ (1 << 4) 153 #define ATMEGA_OTGCON_HNPREQ (1 << 5) 154 155 #define ATMEGA_USBINT 0xDA 156 #define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */ 157 #define ATMEGA_USBINT_IDI (1 << 1) /* USB ID interrupt */ 158 159 #define ATMEGA_USBSTA 0xD9 160 #define ATMEGA_USBSTA_VBUS (1 << 0) 161 #define ATMEGA_USBSTA_ID (1 << 1) 162 163 #define ATMEGA_USBCON 0xD8 164 #define ATMEGA_USBCON_VBUSTE (1 << 0) 165 #define ATMEGA_USBCON_IDE (1 << 1) 166 #define ATMEGA_USBCON_OTGPADE (1 << 4) 167 #define ATMEGA_USBCON_FRZCLK (1 << 5) 168 #define ATMEGA_USBCON_USBE (1 << 7) 169 170 #define ATMEGA_UHWCON 0xD7 171 #define ATMEGA_UHWCON_UVREGE (1 << 0) 172 #define ATMEGA_UHWCON_UVCONE (1 << 4) 173 #define ATMEGA_UHWCON_UIDE (1 << 6) 174 #define ATMEGA_UHWCON_UIMOD (1 << 7) 175 176 #define ATMEGA_READ_1(sc, reg) \ 177 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 178 179 #define ATMEGA_WRITE_1(sc, reg, data) \ 180 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 181 182 #define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \ 183 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 184 185 #define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \ 186 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 187 188 /* 189 * Maximum number of endpoints supported: 190 */ 191 #define ATMEGA_EP_MAX 7 192 193 struct atmegadci_td; 194 195 typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td); 196 typedef void (atmegadci_clocks_t)(struct usb_bus *); 197 198 struct atmegadci_td { 199 struct atmegadci_td *obj_next; 200 atmegadci_cmd_t *func; 201 struct usb_page_cache *pc; 202 uint32_t offset; 203 uint32_t remainder; 204 uint16_t max_packet_size; 205 uint8_t error:1; 206 uint8_t alt_next:1; 207 uint8_t short_pkt:1; 208 uint8_t support_multi_buffer:1; 209 uint8_t did_stall:1; 210 uint8_t ep_no:3; 211 }; 212 213 struct atmegadci_std_temp { 214 atmegadci_cmd_t *func; 215 struct usb_page_cache *pc; 216 struct atmegadci_td *td; 217 struct atmegadci_td *td_next; 218 uint32_t len; 219 uint32_t offset; 220 uint16_t max_frame_size; 221 uint8_t short_pkt; 222 /* 223 * short_pkt = 0: transfer should be short terminated 224 * short_pkt = 1: transfer should not be short terminated 225 */ 226 uint8_t setup_alt_next; 227 uint8_t did_stall; 228 }; 229 230 struct atmegadci_config_desc { 231 struct usb_config_descriptor confd; 232 struct usb_interface_descriptor ifcd; 233 struct usb_endpoint_descriptor endpd; 234 } __packed; 235 236 union atmegadci_hub_temp { 237 uWord wValue; 238 struct usb_port_status ps; 239 }; 240 241 struct atmegadci_flags { 242 uint8_t change_connect:1; 243 uint8_t change_suspend:1; 244 uint8_t status_suspend:1; /* set if suspended */ 245 uint8_t status_vbus:1; /* set if present */ 246 uint8_t status_bus_reset:1; /* set if reset complete */ 247 uint8_t remote_wakeup:1; 248 uint8_t self_powered:1; 249 uint8_t clocks_off:1; 250 uint8_t port_powered:1; 251 uint8_t port_enabled:1; 252 uint8_t d_pulled_up:1; 253 }; 254 255 struct atmegadci_softc { 256 struct usb_bus sc_bus; 257 union atmegadci_hub_temp sc_hub_temp; 258 259 /* must be set by by the bus interface layer */ 260 atmegadci_clocks_t *sc_clocks_on; 261 atmegadci_clocks_t *sc_clocks_off; 262 263 struct usb_device *sc_devices[ATMEGA_MAX_DEVICES]; 264 struct resource *sc_irq_res; 265 void *sc_intr_hdl; 266 struct resource *sc_io_res; 267 bus_space_tag_t sc_io_tag; 268 bus_space_handle_t sc_io_hdl; 269 270 uint8_t sc_rt_addr; /* root hub address */ 271 uint8_t sc_dv_addr; /* device address */ 272 uint8_t sc_conf; /* root hub config */ 273 274 uint8_t sc_hub_idata[1]; 275 276 struct atmegadci_flags sc_flags; 277 }; 278 279 /* prototypes */ 280 281 usb_error_t atmegadci_init(struct atmegadci_softc *sc); 282 void atmegadci_uninit(struct atmegadci_softc *sc); 283 void atmegadci_interrupt(struct atmegadci_softc *sc); 284 285 #endif /* _ATMEGADCI_H_ */ 286