1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 43 #define USB_DEBUG_VAR atmegadci_debug 44 45 #include <dev/usb/usb_core.h> 46 #include <dev/usb/usb_debug.h> 47 #include <dev/usb/usb_busdma.h> 48 #include <dev/usb/usb_process.h> 49 #include <dev/usb/usb_transfer.h> 50 #include <dev/usb/usb_device.h> 51 #include <dev/usb/usb_hub.h> 52 #include <dev/usb/usb_util.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/atmegadci.h> 57 58 #define ATMEGA_BUS2SC(bus) \ 59 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 60 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 61 62 #define ATMEGA_PC2SC(pc) \ 63 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 64 65 #if USB_DEBUG 66 static int atmegadci_debug = 0; 67 68 SYSCTL_NODE(_hw_usb2, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 69 SYSCTL_INT(_hw_usb2_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 70 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 71 #endif 72 73 #define ATMEGA_INTR_ENDPT 1 74 75 /* prototypes */ 76 77 struct usb2_bus_methods atmegadci_bus_methods; 78 struct usb2_pipe_methods atmegadci_device_non_isoc_methods; 79 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods; 80 81 static atmegadci_cmd_t atmegadci_setup_rx; 82 static atmegadci_cmd_t atmegadci_data_rx; 83 static atmegadci_cmd_t atmegadci_data_tx; 84 static atmegadci_cmd_t atmegadci_data_tx_sync; 85 static void atmegadci_device_done(struct usb2_xfer *, usb2_error_t); 86 static void atmegadci_do_poll(struct usb2_bus *); 87 static void atmegadci_standard_done(struct usb2_xfer *); 88 static void atmegadci_root_intr(struct atmegadci_softc *sc); 89 90 /* 91 * Here is a list of what the chip supports: 92 */ 93 static const struct usb2_hw_ep_profile 94 atmegadci_ep_profile[2] = { 95 96 [0] = { 97 .max_in_frame_size = 64, 98 .max_out_frame_size = 64, 99 .is_simplex = 1, 100 .support_control = 1, 101 }, 102 [1] = { 103 .max_in_frame_size = 64, 104 .max_out_frame_size = 64, 105 .is_simplex = 1, 106 .support_multi_buffer = 1, 107 .support_bulk = 1, 108 .support_interrupt = 1, 109 .support_isochronous = 1, 110 .support_in = 1, 111 .support_out = 1, 112 }, 113 }; 114 115 static void 116 atmegadci_get_hw_ep_profile(struct usb2_device *udev, 117 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 118 { 119 if (ep_addr == 0) 120 *ppf = atmegadci_ep_profile; 121 else if (ep_addr < ATMEGA_EP_MAX) 122 *ppf = atmegadci_ep_profile + 1; 123 else 124 *ppf = NULL; 125 } 126 127 static void 128 atmegadci_clocks_on(struct atmegadci_softc *sc) 129 { 130 if (sc->sc_flags.clocks_off && 131 sc->sc_flags.port_powered) { 132 133 DPRINTFN(5, "\n"); 134 135 /* turn on clocks */ 136 (sc->sc_clocks_on) (&sc->sc_bus); 137 138 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 139 ATMEGA_USBCON_USBE | 140 ATMEGA_USBCON_OTGPADE | 141 ATMEGA_USBCON_VBUSTE); 142 143 sc->sc_flags.clocks_off = 0; 144 145 /* enable transceiver ? */ 146 } 147 } 148 149 static void 150 atmegadci_clocks_off(struct atmegadci_softc *sc) 151 { 152 if (!sc->sc_flags.clocks_off) { 153 154 DPRINTFN(5, "\n"); 155 156 /* disable Transceiver ? */ 157 158 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 159 ATMEGA_USBCON_USBE | 160 ATMEGA_USBCON_OTGPADE | 161 ATMEGA_USBCON_FRZCLK | 162 ATMEGA_USBCON_VBUSTE); 163 164 /* turn clocks off */ 165 (sc->sc_clocks_off) (&sc->sc_bus); 166 167 sc->sc_flags.clocks_off = 1; 168 } 169 } 170 171 static void 172 atmegadci_pull_up(struct atmegadci_softc *sc) 173 { 174 /* pullup D+, if possible */ 175 176 if (!sc->sc_flags.d_pulled_up && 177 sc->sc_flags.port_powered) { 178 sc->sc_flags.d_pulled_up = 1; 179 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 180 } 181 } 182 183 static void 184 atmegadci_pull_down(struct atmegadci_softc *sc) 185 { 186 /* pulldown D+, if possible */ 187 188 if (sc->sc_flags.d_pulled_up) { 189 sc->sc_flags.d_pulled_up = 0; 190 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 191 } 192 } 193 194 static void 195 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 196 { 197 uint8_t temp; 198 199 if (!sc->sc_flags.status_suspend) { 200 return; 201 } 202 203 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 204 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 205 206 /* wait 8 milliseconds */ 207 /* Wait for reset to complete. */ 208 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 209 210 /* hardware should have cleared RMWKUP bit */ 211 } 212 213 static void 214 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 215 { 216 DPRINTFN(5, "addr=%d\n", addr); 217 218 addr |= ATMEGA_UDADDR_ADDEN; 219 220 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 221 } 222 223 static uint8_t 224 atmegadci_setup_rx(struct atmegadci_td *td) 225 { 226 struct atmegadci_softc *sc; 227 struct usb2_device_request req; 228 uint16_t count; 229 uint8_t temp; 230 231 /* get pointer to softc */ 232 sc = ATMEGA_PC2SC(td->pc); 233 234 /* select endpoint number */ 235 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 236 237 /* check endpoint status */ 238 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 239 240 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 241 242 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 243 goto not_complete; 244 } 245 /* clear did stall */ 246 td->did_stall = 0; 247 /* get the packet byte count */ 248 count = 249 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 250 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 251 252 /* mask away undefined bits */ 253 count &= 0x7FF; 254 255 /* verify data length */ 256 if (count != td->remainder) { 257 DPRINTFN(0, "Invalid SETUP packet " 258 "length, %d bytes\n", count); 259 goto not_complete; 260 } 261 if (count != sizeof(req)) { 262 DPRINTFN(0, "Unsupported SETUP packet " 263 "length, %d bytes\n", count); 264 goto not_complete; 265 } 266 /* receive data */ 267 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 268 (void *)&req, sizeof(req)); 269 270 /* copy data into real buffer */ 271 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 272 273 td->offset = sizeof(req); 274 td->remainder = 0; 275 276 /* sneak peek the set address */ 277 if ((req.bmRequestType == UT_WRITE_DEVICE) && 278 (req.bRequest == UR_SET_ADDRESS)) { 279 sc->sc_dv_addr = req.wValue[0] & 0x7F; 280 /* must write address before ZLP */ 281 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 282 } else { 283 sc->sc_dv_addr = 0xFF; 284 } 285 286 /* clear SETUP packet interrupt */ 287 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 288 return (0); /* complete */ 289 290 not_complete: 291 /* abort any ongoing transfer */ 292 if (!td->did_stall) { 293 DPRINTFN(5, "stalling\n"); 294 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 295 ATMEGA_UECONX_EPEN | 296 ATMEGA_UECONX_STALLRQ); 297 td->did_stall = 1; 298 } 299 if (temp & ATMEGA_UEINTX_RXSTPI) { 300 /* clear SETUP packet interrupt */ 301 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 302 } 303 /* we only want to know if there is a SETUP packet */ 304 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 305 return (1); /* not complete */ 306 } 307 308 static uint8_t 309 atmegadci_data_rx(struct atmegadci_td *td) 310 { 311 struct atmegadci_softc *sc; 312 struct usb2_page_search buf_res; 313 uint16_t count; 314 uint8_t temp; 315 uint8_t to; 316 uint8_t got_short; 317 318 to = 3; /* don't loop forever! */ 319 got_short = 0; 320 321 /* get pointer to softc */ 322 sc = ATMEGA_PC2SC(td->pc); 323 324 /* select endpoint number */ 325 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 326 327 repeat: 328 /* check if any of the FIFO banks have data */ 329 /* check endpoint status */ 330 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 331 332 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 333 334 if (temp & ATMEGA_UEINTX_RXSTPI) { 335 if (td->remainder == 0) { 336 /* 337 * We are actually complete and have 338 * received the next SETUP 339 */ 340 DPRINTFN(5, "faking complete\n"); 341 return (0); /* complete */ 342 } 343 /* 344 * USB Host Aborted the transfer. 345 */ 346 td->error = 1; 347 return (0); /* complete */ 348 } 349 /* check status */ 350 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 351 ATMEGA_UEINTX_RXOUTI))) { 352 /* no data */ 353 goto not_complete; 354 } 355 /* get the packet byte count */ 356 count = 357 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 358 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 359 360 /* mask away undefined bits */ 361 count &= 0x7FF; 362 363 /* verify the packet byte count */ 364 if (count != td->max_packet_size) { 365 if (count < td->max_packet_size) { 366 /* we have a short packet */ 367 td->short_pkt = 1; 368 got_short = 1; 369 } else { 370 /* invalid USB packet */ 371 td->error = 1; 372 return (0); /* we are complete */ 373 } 374 } 375 /* verify the packet byte count */ 376 if (count > td->remainder) { 377 /* invalid USB packet */ 378 td->error = 1; 379 return (0); /* we are complete */ 380 } 381 while (count > 0) { 382 usb2_get_page(td->pc, td->offset, &buf_res); 383 384 /* get correct length */ 385 if (buf_res.length > count) { 386 buf_res.length = count; 387 } 388 /* receive data */ 389 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 390 buf_res.buffer, buf_res.length); 391 392 /* update counters */ 393 count -= buf_res.length; 394 td->offset += buf_res.length; 395 td->remainder -= buf_res.length; 396 } 397 398 /* clear OUT packet interrupt */ 399 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 400 401 /* release FIFO bank */ 402 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 403 404 /* check if we are complete */ 405 if ((td->remainder == 0) || got_short) { 406 if (td->short_pkt) { 407 /* we are complete */ 408 return (0); 409 } 410 /* else need to receive a zero length packet */ 411 } 412 if (--to) { 413 goto repeat; 414 } 415 not_complete: 416 /* we only want to know if there is a SETUP packet or OUT packet */ 417 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 418 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 419 return (1); /* not complete */ 420 } 421 422 static uint8_t 423 atmegadci_data_tx(struct atmegadci_td *td) 424 { 425 struct atmegadci_softc *sc; 426 struct usb2_page_search buf_res; 427 uint16_t count; 428 uint8_t to; 429 uint8_t temp; 430 431 to = 3; /* don't loop forever! */ 432 433 /* get pointer to softc */ 434 sc = ATMEGA_PC2SC(td->pc); 435 436 /* select endpoint number */ 437 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 438 439 repeat: 440 441 /* check endpoint status */ 442 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 443 444 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 445 446 if (temp & ATMEGA_UEINTX_RXSTPI) { 447 /* 448 * The current transfer was aborted 449 * by the USB Host 450 */ 451 td->error = 1; 452 return (0); /* complete */ 453 } 454 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 455 ATMEGA_UEINTX_TXINI))) { 456 /* cannot write any data */ 457 goto not_complete; 458 } 459 count = td->max_packet_size; 460 if (td->remainder < count) { 461 /* we have a short packet */ 462 td->short_pkt = 1; 463 count = td->remainder; 464 } 465 while (count > 0) { 466 467 usb2_get_page(td->pc, td->offset, &buf_res); 468 469 /* get correct length */ 470 if (buf_res.length > count) { 471 buf_res.length = count; 472 } 473 /* transmit data */ 474 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 475 buf_res.buffer, buf_res.length); 476 477 /* update counters */ 478 count -= buf_res.length; 479 td->offset += buf_res.length; 480 td->remainder -= buf_res.length; 481 } 482 483 /* clear IN packet interrupt */ 484 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 485 486 /* allocate FIFO bank */ 487 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 488 489 /* check remainder */ 490 if (td->remainder == 0) { 491 if (td->short_pkt) { 492 return (0); /* complete */ 493 } 494 /* else we need to transmit a short packet */ 495 } 496 if (--to) { 497 goto repeat; 498 } 499 not_complete: 500 /* we only want to know if there is a SETUP packet or free IN packet */ 501 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 502 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 503 return (1); /* not complete */ 504 } 505 506 static uint8_t 507 atmegadci_data_tx_sync(struct atmegadci_td *td) 508 { 509 struct atmegadci_softc *sc; 510 uint8_t temp; 511 512 /* get pointer to softc */ 513 sc = ATMEGA_PC2SC(td->pc); 514 515 /* select endpoint number */ 516 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 517 518 /* check endpoint status */ 519 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 520 521 DPRINTFN(5, "temp=0x%02x\n", temp); 522 523 if (temp & ATMEGA_UEINTX_RXSTPI) { 524 DPRINTFN(5, "faking complete\n"); 525 /* Race condition */ 526 return (0); /* complete */ 527 } 528 /* 529 * The control endpoint has only got one bank, so if that bank 530 * is free the packet has been transferred! 531 */ 532 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 533 ATMEGA_UEINTX_TXINI))) { 534 /* cannot write any data */ 535 goto not_complete; 536 } 537 if (sc->sc_dv_addr != 0xFF) { 538 /* set new address */ 539 atmegadci_set_address(sc, sc->sc_dv_addr); 540 } 541 return (0); /* complete */ 542 543 not_complete: 544 /* we only want to know if there is a SETUP packet or free IN packet */ 545 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 546 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 547 return (1); /* not complete */ 548 } 549 550 static uint8_t 551 atmegadci_xfer_do_fifo(struct usb2_xfer *xfer) 552 { 553 struct atmegadci_td *td; 554 555 DPRINTFN(9, "\n"); 556 557 td = xfer->td_transfer_cache; 558 while (1) { 559 if ((td->func) (td)) { 560 /* operation in progress */ 561 break; 562 } 563 if (((void *)td) == xfer->td_transfer_last) { 564 goto done; 565 } 566 if (td->error) { 567 goto done; 568 } else if (td->remainder > 0) { 569 /* 570 * We had a short transfer. If there is no alternate 571 * next, stop processing ! 572 */ 573 if (!td->alt_next) { 574 goto done; 575 } 576 } 577 /* 578 * Fetch the next transfer descriptor and transfer 579 * some flags to the next transfer descriptor 580 */ 581 td = td->obj_next; 582 xfer->td_transfer_cache = td; 583 } 584 return (1); /* not complete */ 585 586 done: 587 /* compute all actual lengths */ 588 589 atmegadci_standard_done(xfer); 590 return (0); /* complete */ 591 } 592 593 static void 594 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 595 { 596 struct usb2_xfer *xfer; 597 598 repeat: 599 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 600 if (!atmegadci_xfer_do_fifo(xfer)) { 601 /* queue has been modified */ 602 goto repeat; 603 } 604 } 605 } 606 607 static void 608 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 609 { 610 DPRINTFN(5, "vbus = %u\n", is_on); 611 612 if (is_on) { 613 if (!sc->sc_flags.status_vbus) { 614 sc->sc_flags.status_vbus = 1; 615 616 /* complete root HUB interrupt endpoint */ 617 618 atmegadci_root_intr(sc); 619 } 620 } else { 621 if (sc->sc_flags.status_vbus) { 622 sc->sc_flags.status_vbus = 0; 623 sc->sc_flags.status_bus_reset = 0; 624 sc->sc_flags.status_suspend = 0; 625 sc->sc_flags.change_suspend = 0; 626 sc->sc_flags.change_connect = 1; 627 628 /* complete root HUB interrupt endpoint */ 629 630 atmegadci_root_intr(sc); 631 } 632 } 633 } 634 635 void 636 atmegadci_interrupt(struct atmegadci_softc *sc) 637 { 638 uint8_t status; 639 640 USB_BUS_LOCK(&sc->sc_bus); 641 642 /* read interrupt status */ 643 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 644 645 /* clear all set interrupts */ 646 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 647 648 DPRINTFN(14, "UDINT=0x%02x\n", status); 649 650 /* check for any bus state change interrupts */ 651 if (status & ATMEGA_UDINT_EORSTI) { 652 653 DPRINTFN(5, "end of reset\n"); 654 655 /* set correct state */ 656 sc->sc_flags.status_bus_reset = 1; 657 sc->sc_flags.status_suspend = 0; 658 sc->sc_flags.change_suspend = 0; 659 sc->sc_flags.change_connect = 1; 660 661 /* disable resume interrupt */ 662 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 663 ATMEGA_UDINT_SUSPE | 664 ATMEGA_UDINT_EORSTE); 665 666 /* complete root HUB interrupt endpoint */ 667 atmegadci_root_intr(sc); 668 } 669 /* 670 * If resume and suspend is set at the same time we interpret 671 * that like RESUME. Resume is set when there is at least 3 672 * milliseconds of inactivity on the USB BUS. 673 */ 674 if (status & ATMEGA_UDINT_EORSMI) { 675 676 DPRINTFN(5, "resume interrupt\n"); 677 678 if (sc->sc_flags.status_suspend) { 679 /* update status bits */ 680 sc->sc_flags.status_suspend = 0; 681 sc->sc_flags.change_suspend = 1; 682 683 /* disable resume interrupt */ 684 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 685 ATMEGA_UDINT_SUSPE | 686 ATMEGA_UDINT_EORSTE); 687 688 /* complete root HUB interrupt endpoint */ 689 atmegadci_root_intr(sc); 690 } 691 } else if (status & ATMEGA_UDINT_SUSPI) { 692 693 DPRINTFN(5, "suspend interrupt\n"); 694 695 if (!sc->sc_flags.status_suspend) { 696 /* update status bits */ 697 sc->sc_flags.status_suspend = 1; 698 sc->sc_flags.change_suspend = 1; 699 700 /* disable suspend interrupt */ 701 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 702 ATMEGA_UDINT_EORSMI | 703 ATMEGA_UDINT_EORSTE); 704 705 /* complete root HUB interrupt endpoint */ 706 atmegadci_root_intr(sc); 707 } 708 } 709 /* check VBUS */ 710 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 711 712 /* clear all set interrupts */ 713 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 714 715 if (status & ATMEGA_USBINT_VBUSTI) { 716 uint8_t temp; 717 718 DPRINTFN(5, "USBINT=0x%02x\n", status); 719 720 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 721 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 722 } 723 /* check for any endpoint interrupts */ 724 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 725 /* the hardware will clear the UEINT bits automatically */ 726 if (status) { 727 728 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 729 730 atmegadci_interrupt_poll(sc); 731 } 732 USB_BUS_UNLOCK(&sc->sc_bus); 733 } 734 735 static void 736 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 737 { 738 struct atmegadci_td *td; 739 740 /* get current Transfer Descriptor */ 741 td = temp->td_next; 742 temp->td = td; 743 744 /* prepare for next TD */ 745 temp->td_next = td->obj_next; 746 747 /* fill out the Transfer Descriptor */ 748 td->func = temp->func; 749 td->pc = temp->pc; 750 td->offset = temp->offset; 751 td->remainder = temp->len; 752 td->error = 0; 753 td->did_stall = 0; 754 td->short_pkt = temp->short_pkt; 755 td->alt_next = temp->setup_alt_next; 756 } 757 758 static void 759 atmegadci_setup_standard_chain(struct usb2_xfer *xfer) 760 { 761 struct atmegadci_std_temp temp; 762 struct atmegadci_softc *sc; 763 struct atmegadci_td *td; 764 uint32_t x; 765 uint8_t ep_no; 766 uint8_t need_sync; 767 768 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 769 xfer->address, UE_GET_ADDR(xfer->endpoint), 770 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 771 772 temp.max_frame_size = xfer->max_frame_size; 773 774 td = xfer->td_start[0]; 775 xfer->td_transfer_first = td; 776 xfer->td_transfer_cache = td; 777 778 /* setup temp */ 779 780 temp.td = NULL; 781 temp.td_next = xfer->td_start[0]; 782 temp.offset = 0; 783 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 784 785 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 786 ep_no = (xfer->endpoint & UE_ADDR); 787 788 /* check if we should prepend a setup message */ 789 790 if (xfer->flags_int.control_xfr) { 791 if (xfer->flags_int.control_hdr) { 792 793 temp.func = &atmegadci_setup_rx; 794 temp.len = xfer->frlengths[0]; 795 temp.pc = xfer->frbuffers + 0; 796 temp.short_pkt = temp.len ? 1 : 0; 797 /* check for last frame */ 798 if (xfer->nframes == 1) { 799 /* no STATUS stage yet, SETUP is last */ 800 if (xfer->flags_int.control_act) 801 temp.setup_alt_next = 0; 802 } 803 804 atmegadci_setup_standard_chain_sub(&temp); 805 } 806 x = 1; 807 } else { 808 x = 0; 809 } 810 811 if (x != xfer->nframes) { 812 if (xfer->endpoint & UE_DIR_IN) { 813 temp.func = &atmegadci_data_tx; 814 need_sync = 1; 815 } else { 816 temp.func = &atmegadci_data_rx; 817 need_sync = 0; 818 } 819 820 /* setup "pc" pointer */ 821 temp.pc = xfer->frbuffers + x; 822 } else { 823 need_sync = 0; 824 } 825 while (x != xfer->nframes) { 826 827 /* DATA0 / DATA1 message */ 828 829 temp.len = xfer->frlengths[x]; 830 831 x++; 832 833 if (x == xfer->nframes) { 834 if (xfer->flags_int.control_xfr) { 835 if (xfer->flags_int.control_act) { 836 temp.setup_alt_next = 0; 837 } 838 } else { 839 temp.setup_alt_next = 0; 840 } 841 } 842 if (temp.len == 0) { 843 844 /* make sure that we send an USB packet */ 845 846 temp.short_pkt = 0; 847 848 } else { 849 850 /* regular data transfer */ 851 852 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 853 } 854 855 atmegadci_setup_standard_chain_sub(&temp); 856 857 if (xfer->flags_int.isochronous_xfr) { 858 temp.offset += temp.len; 859 } else { 860 /* get next Page Cache pointer */ 861 temp.pc = xfer->frbuffers + x; 862 } 863 } 864 865 if (xfer->flags_int.control_xfr) { 866 867 /* always setup a valid "pc" pointer for status and sync */ 868 temp.pc = xfer->frbuffers + 0; 869 temp.len = 0; 870 temp.short_pkt = 0; 871 temp.setup_alt_next = 0; 872 873 /* check if we need to sync */ 874 if (need_sync) { 875 /* we need a SYNC point after TX */ 876 temp.func = &atmegadci_data_tx_sync; 877 atmegadci_setup_standard_chain_sub(&temp); 878 } 879 880 /* check if we should append a status stage */ 881 if (!xfer->flags_int.control_act) { 882 883 /* 884 * Send a DATA1 message and invert the current 885 * endpoint direction. 886 */ 887 if (xfer->endpoint & UE_DIR_IN) { 888 temp.func = &atmegadci_data_rx; 889 need_sync = 0; 890 } else { 891 temp.func = &atmegadci_data_tx; 892 need_sync = 1; 893 } 894 895 atmegadci_setup_standard_chain_sub(&temp); 896 if (need_sync) { 897 /* we need a SYNC point after TX */ 898 temp.func = &atmegadci_data_tx_sync; 899 atmegadci_setup_standard_chain_sub(&temp); 900 } 901 } 902 } 903 /* must have at least one frame! */ 904 td = temp.td; 905 xfer->td_transfer_last = td; 906 } 907 908 static void 909 atmegadci_timeout(void *arg) 910 { 911 struct usb2_xfer *xfer = arg; 912 913 DPRINTF("xfer=%p\n", xfer); 914 915 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 916 917 /* transfer is transferred */ 918 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 919 } 920 921 static void 922 atmegadci_start_standard_chain(struct usb2_xfer *xfer) 923 { 924 DPRINTFN(9, "\n"); 925 926 /* poll one time - will turn on interrupts */ 927 if (atmegadci_xfer_do_fifo(xfer)) { 928 929 /* put transfer on interrupt queue */ 930 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 931 932 /* start timeout, if any */ 933 if (xfer->timeout != 0) { 934 usb2_transfer_timeout_ms(xfer, 935 &atmegadci_timeout, xfer->timeout); 936 } 937 } 938 } 939 940 static void 941 atmegadci_root_intr(struct atmegadci_softc *sc) 942 { 943 DPRINTFN(9, "\n"); 944 945 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 946 947 /* set port bit */ 948 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 949 950 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 951 sizeof(sc->sc_hub_idata)); 952 } 953 954 static usb2_error_t 955 atmegadci_standard_done_sub(struct usb2_xfer *xfer) 956 { 957 struct atmegadci_td *td; 958 uint32_t len; 959 uint8_t error; 960 961 DPRINTFN(9, "\n"); 962 963 td = xfer->td_transfer_cache; 964 965 do { 966 len = td->remainder; 967 968 if (xfer->aframes != xfer->nframes) { 969 /* 970 * Verify the length and subtract 971 * the remainder from "frlengths[]": 972 */ 973 if (len > xfer->frlengths[xfer->aframes]) { 974 td->error = 1; 975 } else { 976 xfer->frlengths[xfer->aframes] -= len; 977 } 978 } 979 /* Check for transfer error */ 980 if (td->error) { 981 /* the transfer is finished */ 982 error = 1; 983 td = NULL; 984 break; 985 } 986 /* Check for short transfer */ 987 if (len > 0) { 988 if (xfer->flags_int.short_frames_ok) { 989 /* follow alt next */ 990 if (td->alt_next) { 991 td = td->obj_next; 992 } else { 993 td = NULL; 994 } 995 } else { 996 /* the transfer is finished */ 997 td = NULL; 998 } 999 error = 0; 1000 break; 1001 } 1002 td = td->obj_next; 1003 1004 /* this USB frame is complete */ 1005 error = 0; 1006 break; 1007 1008 } while (0); 1009 1010 /* update transfer cache */ 1011 1012 xfer->td_transfer_cache = td; 1013 1014 return (error ? 1015 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1016 } 1017 1018 static void 1019 atmegadci_standard_done(struct usb2_xfer *xfer) 1020 { 1021 usb2_error_t err = 0; 1022 1023 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1024 xfer, xfer->pipe); 1025 1026 /* reset scanner */ 1027 1028 xfer->td_transfer_cache = xfer->td_transfer_first; 1029 1030 if (xfer->flags_int.control_xfr) { 1031 1032 if (xfer->flags_int.control_hdr) { 1033 1034 err = atmegadci_standard_done_sub(xfer); 1035 } 1036 xfer->aframes = 1; 1037 1038 if (xfer->td_transfer_cache == NULL) { 1039 goto done; 1040 } 1041 } 1042 while (xfer->aframes != xfer->nframes) { 1043 1044 err = atmegadci_standard_done_sub(xfer); 1045 xfer->aframes++; 1046 1047 if (xfer->td_transfer_cache == NULL) { 1048 goto done; 1049 } 1050 } 1051 1052 if (xfer->flags_int.control_xfr && 1053 !xfer->flags_int.control_act) { 1054 1055 err = atmegadci_standard_done_sub(xfer); 1056 } 1057 done: 1058 atmegadci_device_done(xfer, err); 1059 } 1060 1061 /*------------------------------------------------------------------------* 1062 * atmegadci_device_done 1063 * 1064 * NOTE: this function can be called more than one time on the 1065 * same USB transfer! 1066 *------------------------------------------------------------------------*/ 1067 static void 1068 atmegadci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1069 { 1070 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1071 uint8_t ep_no; 1072 1073 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1074 1075 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1076 xfer, xfer->pipe, error); 1077 1078 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1079 ep_no = (xfer->endpoint & UE_ADDR); 1080 1081 /* select endpoint number */ 1082 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1083 1084 /* disable endpoint interrupt */ 1085 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1086 1087 DPRINTFN(15, "disabled interrupts!\n"); 1088 } 1089 /* dequeue transfer and start next transfer */ 1090 usb2_transfer_done(xfer, error); 1091 } 1092 1093 static void 1094 atmegadci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1095 struct usb2_pipe *pipe) 1096 { 1097 struct atmegadci_softc *sc; 1098 uint8_t ep_no; 1099 1100 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1101 1102 DPRINTFN(5, "pipe=%p\n", pipe); 1103 1104 if (xfer) { 1105 /* cancel any ongoing transfers */ 1106 atmegadci_device_done(xfer, USB_ERR_STALLED); 1107 } 1108 sc = ATMEGA_BUS2SC(udev->bus); 1109 /* get endpoint number */ 1110 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1111 /* select endpoint number */ 1112 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1113 /* set stall */ 1114 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1115 ATMEGA_UECONX_EPEN | 1116 ATMEGA_UECONX_STALLRQ); 1117 } 1118 1119 static void 1120 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1121 uint8_t ep_type, uint8_t ep_dir) 1122 { 1123 uint8_t temp; 1124 1125 if (ep_type == UE_CONTROL) { 1126 /* clearing stall is not needed */ 1127 return; 1128 } 1129 /* select endpoint number */ 1130 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1131 1132 /* set endpoint reset */ 1133 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1134 1135 /* clear endpoint reset */ 1136 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1137 1138 /* set stall */ 1139 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1140 ATMEGA_UECONX_EPEN | 1141 ATMEGA_UECONX_STALLRQ); 1142 1143 /* reset data toggle */ 1144 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1145 ATMEGA_UECONX_EPEN | 1146 ATMEGA_UECONX_RSTDT); 1147 1148 /* clear stall */ 1149 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1150 ATMEGA_UECONX_EPEN | 1151 ATMEGA_UECONX_STALLRQC); 1152 1153 do { 1154 temp = 0; 1155 if (ep_type == UE_BULK) { 1156 temp |= ATMEGA_UECFG0X_EPTYPE2; 1157 } else if (ep_type == UE_INTERRUPT) { 1158 temp |= ATMEGA_UECFG0X_EPTYPE3; 1159 } else { 1160 temp |= ATMEGA_UECFG0X_EPTYPE1; 1161 } 1162 if (ep_dir & UE_DIR_IN) { 1163 temp |= ATMEGA_UECFG0X_EPDIR; 1164 } 1165 /* two banks, 64-bytes wMaxPacket */ 1166 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1167 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1168 ATMEGA_UECFG1X_ALLOC | 1169 ATMEGA_UECFG1X_EPBK1 | 1170 ATMEGA_UECFG1X_EPSIZE(3)); 1171 1172 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1173 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1174 DPRINTFN(0, "Chip rejected configuration\n"); 1175 } 1176 } while (0); 1177 } 1178 1179 static void 1180 atmegadci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1181 { 1182 struct atmegadci_softc *sc; 1183 struct usb2_endpoint_descriptor *ed; 1184 1185 DPRINTFN(5, "pipe=%p\n", pipe); 1186 1187 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1188 1189 /* check mode */ 1190 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1191 /* not supported */ 1192 return; 1193 } 1194 /* get softc */ 1195 sc = ATMEGA_BUS2SC(udev->bus); 1196 1197 /* get endpoint descriptor */ 1198 ed = pipe->edesc; 1199 1200 /* reset endpoint */ 1201 atmegadci_clear_stall_sub(sc, 1202 (ed->bEndpointAddress & UE_ADDR), 1203 (ed->bmAttributes & UE_XFERTYPE), 1204 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1205 } 1206 1207 usb2_error_t 1208 atmegadci_init(struct atmegadci_softc *sc) 1209 { 1210 uint8_t n; 1211 1212 DPRINTF("start\n"); 1213 1214 /* set up the bus structure */ 1215 sc->sc_bus.usbrev = USB_REV_1_1; 1216 sc->sc_bus.methods = &atmegadci_bus_methods; 1217 1218 USB_BUS_LOCK(&sc->sc_bus); 1219 #if 0 1220 /* XXX TODO - currently done by boot strap */ 1221 1222 /* enable USB PAD regulator */ 1223 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1224 ATMEGA_UHWCON_UVREGE | ATMEGA_UHWCON_UIMOD); 1225 #endif 1226 /* make sure USB is enabled */ 1227 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1228 ATMEGA_USBCON_USBE | 1229 ATMEGA_USBCON_OTGPADE | 1230 ATMEGA_USBCON_VBUSTE); 1231 1232 /* turn on clocks */ 1233 (sc->sc_clocks_on) (&sc->sc_bus); 1234 1235 /* make sure device is re-enumerated */ 1236 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1237 1238 /* wait a little for things to stabilise */ 1239 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1240 1241 /* enable interrupts */ 1242 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1243 ATMEGA_UDINT_SUSPE | 1244 ATMEGA_UDINT_EORSTE); 1245 1246 /* reset all endpoints */ 1247 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1248 (1 << ATMEGA_EP_MAX) - 1); 1249 1250 /* disable reset */ 1251 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1252 1253 /* disable all endpoints */ 1254 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1255 1256 /* select endpoint */ 1257 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1258 1259 /* disable endpoint interrupt */ 1260 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1261 1262 /* disable endpoint */ 1263 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1264 } 1265 1266 /* turn off clocks */ 1267 1268 atmegadci_clocks_off(sc); 1269 1270 /* read initial VBUS state */ 1271 1272 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1273 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1274 1275 USB_BUS_UNLOCK(&sc->sc_bus); 1276 1277 /* catch any lost interrupts */ 1278 1279 atmegadci_do_poll(&sc->sc_bus); 1280 1281 return (0); /* success */ 1282 } 1283 1284 void 1285 atmegadci_uninit(struct atmegadci_softc *sc) 1286 { 1287 USB_BUS_LOCK(&sc->sc_bus); 1288 1289 /* turn on clocks */ 1290 (sc->sc_clocks_on) (&sc->sc_bus); 1291 1292 /* disable interrupts */ 1293 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1294 1295 /* reset all endpoints */ 1296 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1297 (1 << ATMEGA_EP_MAX) - 1); 1298 1299 /* disable reset */ 1300 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1301 1302 sc->sc_flags.port_powered = 0; 1303 sc->sc_flags.status_vbus = 0; 1304 sc->sc_flags.status_bus_reset = 0; 1305 sc->sc_flags.status_suspend = 0; 1306 sc->sc_flags.change_suspend = 0; 1307 sc->sc_flags.change_connect = 1; 1308 1309 atmegadci_pull_down(sc); 1310 atmegadci_clocks_off(sc); 1311 1312 /* disable USB PAD regulator */ 1313 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1314 1315 USB_BUS_UNLOCK(&sc->sc_bus); 1316 } 1317 1318 void 1319 atmegadci_suspend(struct atmegadci_softc *sc) 1320 { 1321 return; 1322 } 1323 1324 void 1325 atmegadci_resume(struct atmegadci_softc *sc) 1326 { 1327 return; 1328 } 1329 1330 static void 1331 atmegadci_do_poll(struct usb2_bus *bus) 1332 { 1333 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1334 1335 USB_BUS_LOCK(&sc->sc_bus); 1336 atmegadci_interrupt_poll(sc); 1337 USB_BUS_UNLOCK(&sc->sc_bus); 1338 } 1339 1340 /*------------------------------------------------------------------------* 1341 * at91dci bulk support 1342 * at91dci control support 1343 * at91dci interrupt support 1344 *------------------------------------------------------------------------*/ 1345 static void 1346 atmegadci_device_non_isoc_open(struct usb2_xfer *xfer) 1347 { 1348 return; 1349 } 1350 1351 static void 1352 atmegadci_device_non_isoc_close(struct usb2_xfer *xfer) 1353 { 1354 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1355 } 1356 1357 static void 1358 atmegadci_device_non_isoc_enter(struct usb2_xfer *xfer) 1359 { 1360 return; 1361 } 1362 1363 static void 1364 atmegadci_device_non_isoc_start(struct usb2_xfer *xfer) 1365 { 1366 /* setup TDs */ 1367 atmegadci_setup_standard_chain(xfer); 1368 atmegadci_start_standard_chain(xfer); 1369 } 1370 1371 struct usb2_pipe_methods atmegadci_device_non_isoc_methods = 1372 { 1373 .open = atmegadci_device_non_isoc_open, 1374 .close = atmegadci_device_non_isoc_close, 1375 .enter = atmegadci_device_non_isoc_enter, 1376 .start = atmegadci_device_non_isoc_start, 1377 }; 1378 1379 /*------------------------------------------------------------------------* 1380 * at91dci full speed isochronous support 1381 *------------------------------------------------------------------------*/ 1382 static void 1383 atmegadci_device_isoc_fs_open(struct usb2_xfer *xfer) 1384 { 1385 return; 1386 } 1387 1388 static void 1389 atmegadci_device_isoc_fs_close(struct usb2_xfer *xfer) 1390 { 1391 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1392 } 1393 1394 static void 1395 atmegadci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1396 { 1397 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1398 uint32_t temp; 1399 uint32_t nframes; 1400 1401 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1402 xfer, xfer->pipe->isoc_next, xfer->nframes); 1403 1404 /* get the current frame index */ 1405 1406 nframes = 1407 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1408 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1409 1410 nframes &= ATMEGA_FRAME_MASK; 1411 1412 /* 1413 * check if the frame index is within the window where the frames 1414 * will be inserted 1415 */ 1416 temp = (nframes - xfer->pipe->isoc_next) & ATMEGA_FRAME_MASK; 1417 1418 if ((xfer->pipe->is_synced == 0) || 1419 (temp < xfer->nframes)) { 1420 /* 1421 * If there is data underflow or the pipe queue is 1422 * empty we schedule the transfer a few frames ahead 1423 * of the current frame position. Else two isochronous 1424 * transfers might overlap. 1425 */ 1426 xfer->pipe->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1427 xfer->pipe->is_synced = 1; 1428 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1429 } 1430 /* 1431 * compute how many milliseconds the insertion is ahead of the 1432 * current frame position: 1433 */ 1434 temp = (xfer->pipe->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1435 1436 /* 1437 * pre-compute when the isochronous transfer will be finished: 1438 */ 1439 xfer->isoc_time_complete = 1440 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1441 xfer->nframes; 1442 1443 /* compute frame number for next insertion */ 1444 xfer->pipe->isoc_next += xfer->nframes; 1445 1446 /* setup TDs */ 1447 atmegadci_setup_standard_chain(xfer); 1448 } 1449 1450 static void 1451 atmegadci_device_isoc_fs_start(struct usb2_xfer *xfer) 1452 { 1453 /* start TD chain */ 1454 atmegadci_start_standard_chain(xfer); 1455 } 1456 1457 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods = 1458 { 1459 .open = atmegadci_device_isoc_fs_open, 1460 .close = atmegadci_device_isoc_fs_close, 1461 .enter = atmegadci_device_isoc_fs_enter, 1462 .start = atmegadci_device_isoc_fs_start, 1463 }; 1464 1465 /*------------------------------------------------------------------------* 1466 * at91dci root control support 1467 *------------------------------------------------------------------------* 1468 * Simulate a hardware HUB by handling all the necessary requests. 1469 *------------------------------------------------------------------------*/ 1470 1471 static const struct usb2_device_descriptor atmegadci_devd = { 1472 .bLength = sizeof(struct usb2_device_descriptor), 1473 .bDescriptorType = UDESC_DEVICE, 1474 .bcdUSB = {0x00, 0x02}, 1475 .bDeviceClass = UDCLASS_HUB, 1476 .bDeviceSubClass = UDSUBCLASS_HUB, 1477 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1478 .bMaxPacketSize = 64, 1479 .bcdDevice = {0x00, 0x01}, 1480 .iManufacturer = 1, 1481 .iProduct = 2, 1482 .bNumConfigurations = 1, 1483 }; 1484 1485 static const struct usb2_device_qualifier atmegadci_odevd = { 1486 .bLength = sizeof(struct usb2_device_qualifier), 1487 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1488 .bcdUSB = {0x00, 0x02}, 1489 .bDeviceClass = UDCLASS_HUB, 1490 .bDeviceSubClass = UDSUBCLASS_HUB, 1491 .bDeviceProtocol = UDPROTO_FSHUB, 1492 .bMaxPacketSize0 = 0, 1493 .bNumConfigurations = 0, 1494 }; 1495 1496 static const struct atmegadci_config_desc atmegadci_confd = { 1497 .confd = { 1498 .bLength = sizeof(struct usb2_config_descriptor), 1499 .bDescriptorType = UDESC_CONFIG, 1500 .wTotalLength[0] = sizeof(atmegadci_confd), 1501 .bNumInterface = 1, 1502 .bConfigurationValue = 1, 1503 .iConfiguration = 0, 1504 .bmAttributes = UC_SELF_POWERED, 1505 .bMaxPower = 0, 1506 }, 1507 .ifcd = { 1508 .bLength = sizeof(struct usb2_interface_descriptor), 1509 .bDescriptorType = UDESC_INTERFACE, 1510 .bNumEndpoints = 1, 1511 .bInterfaceClass = UICLASS_HUB, 1512 .bInterfaceSubClass = UISUBCLASS_HUB, 1513 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1514 }, 1515 .endpd = { 1516 .bLength = sizeof(struct usb2_endpoint_descriptor), 1517 .bDescriptorType = UDESC_ENDPOINT, 1518 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1519 .bmAttributes = UE_INTERRUPT, 1520 .wMaxPacketSize[0] = 8, 1521 .bInterval = 255, 1522 }, 1523 }; 1524 1525 static const struct usb2_hub_descriptor_min atmegadci_hubd = { 1526 .bDescLength = sizeof(atmegadci_hubd), 1527 .bDescriptorType = UDESC_HUB, 1528 .bNbrPorts = 1, 1529 .wHubCharacteristics[0] = 1530 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1531 .wHubCharacteristics[1] = 1532 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1533 .bPwrOn2PwrGood = 50, 1534 .bHubContrCurrent = 0, 1535 .DeviceRemovable = {0}, /* port is removable */ 1536 }; 1537 1538 #define STRING_LANG \ 1539 0x09, 0x04, /* American English */ 1540 1541 #define STRING_VENDOR \ 1542 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1543 1544 #define STRING_PRODUCT \ 1545 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1546 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1547 'U', 0, 'B', 0, 1548 1549 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1550 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1551 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1552 1553 static void 1554 atmegadci_roothub_exec(struct usb2_bus *bus) 1555 { 1556 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1557 struct usb2_sw_transfer *std = &sc->sc_bus.roothub_req; 1558 uint16_t value; 1559 uint16_t index; 1560 uint8_t temp; 1561 1562 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1563 1564 /* buffer reset */ 1565 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1566 std->len = 0; 1567 1568 value = UGETW(std->req.wValue); 1569 index = UGETW(std->req.wIndex); 1570 1571 /* demultiplex the control request */ 1572 1573 switch (std->req.bmRequestType) { 1574 case UT_READ_DEVICE: 1575 switch (std->req.bRequest) { 1576 case UR_GET_DESCRIPTOR: 1577 goto tr_handle_get_descriptor; 1578 case UR_GET_CONFIG: 1579 goto tr_handle_get_config; 1580 case UR_GET_STATUS: 1581 goto tr_handle_get_status; 1582 default: 1583 goto tr_stalled; 1584 } 1585 break; 1586 1587 case UT_WRITE_DEVICE: 1588 switch (std->req.bRequest) { 1589 case UR_SET_ADDRESS: 1590 goto tr_handle_set_address; 1591 case UR_SET_CONFIG: 1592 goto tr_handle_set_config; 1593 case UR_CLEAR_FEATURE: 1594 goto tr_valid; /* nop */ 1595 case UR_SET_DESCRIPTOR: 1596 goto tr_valid; /* nop */ 1597 case UR_SET_FEATURE: 1598 default: 1599 goto tr_stalled; 1600 } 1601 break; 1602 1603 case UT_WRITE_ENDPOINT: 1604 switch (std->req.bRequest) { 1605 case UR_CLEAR_FEATURE: 1606 switch (UGETW(std->req.wValue)) { 1607 case UF_ENDPOINT_HALT: 1608 goto tr_handle_clear_halt; 1609 case UF_DEVICE_REMOTE_WAKEUP: 1610 goto tr_handle_clear_wakeup; 1611 default: 1612 goto tr_stalled; 1613 } 1614 break; 1615 case UR_SET_FEATURE: 1616 switch (UGETW(std->req.wValue)) { 1617 case UF_ENDPOINT_HALT: 1618 goto tr_handle_set_halt; 1619 case UF_DEVICE_REMOTE_WAKEUP: 1620 goto tr_handle_set_wakeup; 1621 default: 1622 goto tr_stalled; 1623 } 1624 break; 1625 case UR_SYNCH_FRAME: 1626 goto tr_valid; /* nop */ 1627 default: 1628 goto tr_stalled; 1629 } 1630 break; 1631 1632 case UT_READ_ENDPOINT: 1633 switch (std->req.bRequest) { 1634 case UR_GET_STATUS: 1635 goto tr_handle_get_ep_status; 1636 default: 1637 goto tr_stalled; 1638 } 1639 break; 1640 1641 case UT_WRITE_INTERFACE: 1642 switch (std->req.bRequest) { 1643 case UR_SET_INTERFACE: 1644 goto tr_handle_set_interface; 1645 case UR_CLEAR_FEATURE: 1646 goto tr_valid; /* nop */ 1647 case UR_SET_FEATURE: 1648 default: 1649 goto tr_stalled; 1650 } 1651 break; 1652 1653 case UT_READ_INTERFACE: 1654 switch (std->req.bRequest) { 1655 case UR_GET_INTERFACE: 1656 goto tr_handle_get_interface; 1657 case UR_GET_STATUS: 1658 goto tr_handle_get_iface_status; 1659 default: 1660 goto tr_stalled; 1661 } 1662 break; 1663 1664 case UT_WRITE_CLASS_INTERFACE: 1665 case UT_WRITE_VENDOR_INTERFACE: 1666 /* XXX forward */ 1667 break; 1668 1669 case UT_READ_CLASS_INTERFACE: 1670 case UT_READ_VENDOR_INTERFACE: 1671 /* XXX forward */ 1672 break; 1673 1674 case UT_WRITE_CLASS_DEVICE: 1675 switch (std->req.bRequest) { 1676 case UR_CLEAR_FEATURE: 1677 goto tr_valid; 1678 case UR_SET_DESCRIPTOR: 1679 case UR_SET_FEATURE: 1680 break; 1681 default: 1682 goto tr_stalled; 1683 } 1684 break; 1685 1686 case UT_WRITE_CLASS_OTHER: 1687 switch (std->req.bRequest) { 1688 case UR_CLEAR_FEATURE: 1689 goto tr_handle_clear_port_feature; 1690 case UR_SET_FEATURE: 1691 goto tr_handle_set_port_feature; 1692 case UR_CLEAR_TT_BUFFER: 1693 case UR_RESET_TT: 1694 case UR_STOP_TT: 1695 goto tr_valid; 1696 1697 default: 1698 goto tr_stalled; 1699 } 1700 break; 1701 1702 case UT_READ_CLASS_OTHER: 1703 switch (std->req.bRequest) { 1704 case UR_GET_TT_STATE: 1705 goto tr_handle_get_tt_state; 1706 case UR_GET_STATUS: 1707 goto tr_handle_get_port_status; 1708 default: 1709 goto tr_stalled; 1710 } 1711 break; 1712 1713 case UT_READ_CLASS_DEVICE: 1714 switch (std->req.bRequest) { 1715 case UR_GET_DESCRIPTOR: 1716 goto tr_handle_get_class_descriptor; 1717 case UR_GET_STATUS: 1718 goto tr_handle_get_class_status; 1719 1720 default: 1721 goto tr_stalled; 1722 } 1723 break; 1724 default: 1725 goto tr_stalled; 1726 } 1727 goto tr_valid; 1728 1729 tr_handle_get_descriptor: 1730 switch (value >> 8) { 1731 case UDESC_DEVICE: 1732 if (value & 0xff) { 1733 goto tr_stalled; 1734 } 1735 std->len = sizeof(atmegadci_devd); 1736 std->ptr = USB_ADD_BYTES(&atmegadci_devd, 0); 1737 goto tr_valid; 1738 case UDESC_CONFIG: 1739 if (value & 0xff) { 1740 goto tr_stalled; 1741 } 1742 std->len = sizeof(atmegadci_confd); 1743 std->ptr = USB_ADD_BYTES(&atmegadci_confd, 0); 1744 goto tr_valid; 1745 case UDESC_STRING: 1746 switch (value & 0xff) { 1747 case 0: /* Language table */ 1748 std->len = sizeof(atmegadci_langtab); 1749 std->ptr = USB_ADD_BYTES(&atmegadci_langtab, 0); 1750 goto tr_valid; 1751 1752 case 1: /* Vendor */ 1753 std->len = sizeof(atmegadci_vendor); 1754 std->ptr = USB_ADD_BYTES(&atmegadci_vendor, 0); 1755 goto tr_valid; 1756 1757 case 2: /* Product */ 1758 std->len = sizeof(atmegadci_product); 1759 std->ptr = USB_ADD_BYTES(&atmegadci_product, 0); 1760 goto tr_valid; 1761 default: 1762 break; 1763 } 1764 break; 1765 default: 1766 goto tr_stalled; 1767 } 1768 goto tr_stalled; 1769 1770 tr_handle_get_config: 1771 std->len = 1; 1772 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1773 goto tr_valid; 1774 1775 tr_handle_get_status: 1776 std->len = 2; 1777 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1778 goto tr_valid; 1779 1780 tr_handle_set_address: 1781 if (value & 0xFF00) { 1782 goto tr_stalled; 1783 } 1784 sc->sc_rt_addr = value; 1785 goto tr_valid; 1786 1787 tr_handle_set_config: 1788 if (value >= 2) { 1789 goto tr_stalled; 1790 } 1791 sc->sc_conf = value; 1792 goto tr_valid; 1793 1794 tr_handle_get_interface: 1795 std->len = 1; 1796 sc->sc_hub_temp.wValue[0] = 0; 1797 goto tr_valid; 1798 1799 tr_handle_get_tt_state: 1800 tr_handle_get_class_status: 1801 tr_handle_get_iface_status: 1802 tr_handle_get_ep_status: 1803 std->len = 2; 1804 USETW(sc->sc_hub_temp.wValue, 0); 1805 goto tr_valid; 1806 1807 tr_handle_set_halt: 1808 tr_handle_set_interface: 1809 tr_handle_set_wakeup: 1810 tr_handle_clear_wakeup: 1811 tr_handle_clear_halt: 1812 goto tr_valid; 1813 1814 tr_handle_clear_port_feature: 1815 if (index != 1) { 1816 goto tr_stalled; 1817 } 1818 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1819 1820 switch (value) { 1821 case UHF_PORT_SUSPEND: 1822 atmegadci_wakeup_peer(sc); 1823 break; 1824 1825 case UHF_PORT_ENABLE: 1826 sc->sc_flags.port_enabled = 0; 1827 break; 1828 1829 case UHF_PORT_TEST: 1830 case UHF_PORT_INDICATOR: 1831 case UHF_C_PORT_ENABLE: 1832 case UHF_C_PORT_OVER_CURRENT: 1833 case UHF_C_PORT_RESET: 1834 /* nops */ 1835 break; 1836 case UHF_PORT_POWER: 1837 sc->sc_flags.port_powered = 0; 1838 atmegadci_pull_down(sc); 1839 atmegadci_clocks_off(sc); 1840 break; 1841 case UHF_C_PORT_CONNECTION: 1842 /* clear connect change flag */ 1843 sc->sc_flags.change_connect = 0; 1844 1845 /* configure the control endpoint */ 1846 1847 /* select endpoint number */ 1848 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1849 1850 /* set endpoint reset */ 1851 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1852 1853 /* clear endpoint reset */ 1854 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1855 1856 /* enable and stall endpoint */ 1857 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1858 ATMEGA_UECONX_EPEN | 1859 ATMEGA_UECONX_STALLRQ); 1860 1861 /* one bank, 64-bytes wMaxPacket */ 1862 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1863 ATMEGA_UECFG0X_EPTYPE0); 1864 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1865 ATMEGA_UECFG1X_ALLOC | 1866 ATMEGA_UECFG1X_EPBK0 | 1867 ATMEGA_UECFG1X_EPSIZE(3)); 1868 1869 /* check valid config */ 1870 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1871 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1872 DPRINTFN(0, "Chip rejected EP0 configuration\n"); 1873 } 1874 break; 1875 case UHF_C_PORT_SUSPEND: 1876 sc->sc_flags.change_suspend = 0; 1877 break; 1878 default: 1879 std->err = USB_ERR_IOERROR; 1880 goto done; 1881 } 1882 goto tr_valid; 1883 1884 tr_handle_set_port_feature: 1885 if (index != 1) { 1886 goto tr_stalled; 1887 } 1888 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1889 1890 switch (value) { 1891 case UHF_PORT_ENABLE: 1892 sc->sc_flags.port_enabled = 1; 1893 break; 1894 case UHF_PORT_SUSPEND: 1895 case UHF_PORT_RESET: 1896 case UHF_PORT_TEST: 1897 case UHF_PORT_INDICATOR: 1898 /* nops */ 1899 break; 1900 case UHF_PORT_POWER: 1901 sc->sc_flags.port_powered = 1; 1902 break; 1903 default: 1904 std->err = USB_ERR_IOERROR; 1905 goto done; 1906 } 1907 goto tr_valid; 1908 1909 tr_handle_get_port_status: 1910 1911 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1912 1913 if (index != 1) { 1914 goto tr_stalled; 1915 } 1916 if (sc->sc_flags.status_vbus) { 1917 atmegadci_clocks_on(sc); 1918 atmegadci_pull_up(sc); 1919 } else { 1920 atmegadci_pull_down(sc); 1921 atmegadci_clocks_off(sc); 1922 } 1923 1924 /* Select FULL-speed and Device Side Mode */ 1925 1926 value = UPS_PORT_MODE_DEVICE; 1927 1928 if (sc->sc_flags.port_powered) { 1929 value |= UPS_PORT_POWER; 1930 } 1931 if (sc->sc_flags.port_enabled) { 1932 value |= UPS_PORT_ENABLED; 1933 } 1934 if (sc->sc_flags.status_vbus && 1935 sc->sc_flags.status_bus_reset) { 1936 value |= UPS_CURRENT_CONNECT_STATUS; 1937 } 1938 if (sc->sc_flags.status_suspend) { 1939 value |= UPS_SUSPEND; 1940 } 1941 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1942 1943 value = 0; 1944 1945 if (sc->sc_flags.change_connect) { 1946 value |= UPS_C_CONNECT_STATUS; 1947 } 1948 if (sc->sc_flags.change_suspend) { 1949 value |= UPS_C_SUSPEND; 1950 } 1951 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1952 std->len = sizeof(sc->sc_hub_temp.ps); 1953 goto tr_valid; 1954 1955 tr_handle_get_class_descriptor: 1956 if (value & 0xFF) { 1957 goto tr_stalled; 1958 } 1959 std->ptr = USB_ADD_BYTES(&atmegadci_hubd, 0); 1960 std->len = sizeof(atmegadci_hubd); 1961 goto tr_valid; 1962 1963 tr_stalled: 1964 std->err = USB_ERR_STALLED; 1965 tr_valid: 1966 done: 1967 return; 1968 } 1969 1970 static void 1971 atmegadci_xfer_setup(struct usb2_setup_params *parm) 1972 { 1973 const struct usb2_hw_ep_profile *pf; 1974 struct atmegadci_softc *sc; 1975 struct usb2_xfer *xfer; 1976 void *last_obj; 1977 uint32_t ntd; 1978 uint32_t n; 1979 uint8_t ep_no; 1980 1981 sc = ATMEGA_BUS2SC(parm->udev->bus); 1982 xfer = parm->curr_xfer; 1983 1984 /* 1985 * NOTE: This driver does not use any of the parameters that 1986 * are computed from the following values. Just set some 1987 * reasonable dummies: 1988 */ 1989 parm->hc_max_packet_size = 0x500; 1990 parm->hc_max_packet_count = 1; 1991 parm->hc_max_frame_size = 0x500; 1992 1993 usb2_transfer_setup_sub(parm); 1994 1995 /* 1996 * compute maximum number of TDs 1997 */ 1998 if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1999 2000 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2001 + 1 /* SYNC 2 */ ; 2002 } else { 2003 2004 ntd = xfer->nframes + 1 /* SYNC */ ; 2005 } 2006 2007 /* 2008 * check if "usb2_transfer_setup_sub" set an error 2009 */ 2010 if (parm->err) 2011 return; 2012 2013 /* 2014 * allocate transfer descriptors 2015 */ 2016 last_obj = NULL; 2017 2018 /* 2019 * get profile stuff 2020 */ 2021 ep_no = xfer->endpoint & UE_ADDR; 2022 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2023 2024 if (pf == NULL) { 2025 /* should not happen */ 2026 parm->err = USB_ERR_INVAL; 2027 return; 2028 } 2029 2030 /* align data */ 2031 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2032 2033 for (n = 0; n != ntd; n++) { 2034 2035 struct atmegadci_td *td; 2036 2037 if (parm->buf) { 2038 2039 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2040 2041 /* init TD */ 2042 td->max_packet_size = xfer->max_packet_size; 2043 td->ep_no = ep_no; 2044 if (pf->support_multi_buffer) { 2045 td->support_multi_buffer = 1; 2046 } 2047 td->obj_next = last_obj; 2048 2049 last_obj = td; 2050 } 2051 parm->size[0] += sizeof(*td); 2052 } 2053 2054 xfer->td_start[0] = last_obj; 2055 } 2056 2057 static void 2058 atmegadci_xfer_unsetup(struct usb2_xfer *xfer) 2059 { 2060 return; 2061 } 2062 2063 static void 2064 atmegadci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2065 struct usb2_pipe *pipe) 2066 { 2067 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2068 2069 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2070 pipe, udev->address, 2071 edesc->bEndpointAddress, udev->flags.usb2_mode, 2072 sc->sc_rt_addr, udev->device_index); 2073 2074 if (udev->device_index != sc->sc_rt_addr) { 2075 2076 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2077 /* not supported */ 2078 return; 2079 } 2080 if (udev->speed != USB_SPEED_FULL) { 2081 /* not supported */ 2082 return; 2083 } 2084 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2085 pipe->methods = &atmegadci_device_isoc_fs_methods; 2086 else 2087 pipe->methods = &atmegadci_device_non_isoc_methods; 2088 } 2089 } 2090 2091 struct usb2_bus_methods atmegadci_bus_methods = 2092 { 2093 .pipe_init = &atmegadci_pipe_init, 2094 .xfer_setup = &atmegadci_xfer_setup, 2095 .xfer_unsetup = &atmegadci_xfer_unsetup, 2096 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2097 .set_stall = &atmegadci_set_stall, 2098 .clear_stall = &atmegadci_clear_stall, 2099 .roothub_exec = &atmegadci_roothub_exec, 2100 }; 2101