1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG 31 * Controller. This driver currently only supports the DCI mode of the 32 * USB hardware. 33 */ 34 35 /* 36 * NOTE: When the chip detects BUS-reset it will also reset the 37 * endpoints, Function-address and more. 38 */ 39 40 #include <dev/usb/usb.h> 41 #include <dev/usb/usb_mfunc.h> 42 #include <dev/usb/usb_error.h> 43 44 #define USB_DEBUG_VAR atmegadci_debug 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_debug.h> 48 #include <dev/usb/usb_busdma.h> 49 #include <dev/usb/usb_process.h> 50 #include <dev/usb/usb_sw_transfer.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/atmegadci.h> 59 60 #define ATMEGA_BUS2SC(bus) \ 61 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 62 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 63 64 #define ATMEGA_PC2SC(pc) \ 65 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 66 67 #if USB_DEBUG 68 static int atmegadci_debug = 0; 69 70 SYSCTL_NODE(_hw_usb2, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 71 SYSCTL_INT(_hw_usb2_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 72 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 73 #endif 74 75 #define ATMEGA_INTR_ENDPT 1 76 77 /* prototypes */ 78 79 struct usb2_bus_methods atmegadci_bus_methods; 80 struct usb2_pipe_methods atmegadci_device_bulk_methods; 81 struct usb2_pipe_methods atmegadci_device_ctrl_methods; 82 struct usb2_pipe_methods atmegadci_device_intr_methods; 83 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods; 84 struct usb2_pipe_methods atmegadci_root_ctrl_methods; 85 struct usb2_pipe_methods atmegadci_root_intr_methods; 86 87 static atmegadci_cmd_t atmegadci_setup_rx; 88 static atmegadci_cmd_t atmegadci_data_rx; 89 static atmegadci_cmd_t atmegadci_data_tx; 90 static atmegadci_cmd_t atmegadci_data_tx_sync; 91 static void atmegadci_device_done(struct usb2_xfer *, usb2_error_t); 92 static void atmegadci_do_poll(struct usb2_bus *); 93 static void atmegadci_root_ctrl_poll(struct atmegadci_softc *); 94 static void atmegadci_standard_done(struct usb2_xfer *); 95 96 static usb2_sw_transfer_func_t atmegadci_root_intr_done; 97 static usb2_sw_transfer_func_t atmegadci_root_ctrl_done; 98 99 /* 100 * Here is a list of what the chip supports: 101 */ 102 static const struct usb2_hw_ep_profile 103 atmegadci_ep_profile[2] = { 104 105 [0] = { 106 .max_in_frame_size = 64, 107 .max_out_frame_size = 64, 108 .is_simplex = 1, 109 .support_control = 1, 110 }, 111 [1] = { 112 .max_in_frame_size = 64, 113 .max_out_frame_size = 64, 114 .is_simplex = 1, 115 .support_multi_buffer = 1, 116 .support_bulk = 1, 117 .support_interrupt = 1, 118 .support_isochronous = 1, 119 .support_in = 1, 120 .support_out = 1, 121 }, 122 }; 123 124 static void 125 atmegadci_get_hw_ep_profile(struct usb2_device *udev, 126 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 127 { 128 if (ep_addr == 0) 129 *ppf = atmegadci_ep_profile; 130 else if (ep_addr < ATMEGA_EP_MAX) 131 *ppf = atmegadci_ep_profile + 1; 132 else 133 *ppf = NULL; 134 } 135 136 static void 137 atmegadci_clocks_on(struct atmegadci_softc *sc) 138 { 139 if (sc->sc_flags.clocks_off && 140 sc->sc_flags.port_powered) { 141 142 DPRINTFN(5, "\n"); 143 144 /* turn on clocks */ 145 (sc->sc_clocks_on) (&sc->sc_bus); 146 147 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 148 ATMEGA_USBCON_USBE | 149 ATMEGA_USBCON_OTGPADE | 150 ATMEGA_USBCON_VBUSTE); 151 152 sc->sc_flags.clocks_off = 0; 153 154 /* enable transceiver ? */ 155 } 156 } 157 158 static void 159 atmegadci_clocks_off(struct atmegadci_softc *sc) 160 { 161 if (!sc->sc_flags.clocks_off) { 162 163 DPRINTFN(5, "\n"); 164 165 /* disable Transceiver ? */ 166 167 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 168 ATMEGA_USBCON_USBE | 169 ATMEGA_USBCON_OTGPADE | 170 ATMEGA_USBCON_FRZCLK | 171 ATMEGA_USBCON_VBUSTE); 172 173 /* turn clocks off */ 174 (sc->sc_clocks_off) (&sc->sc_bus); 175 176 sc->sc_flags.clocks_off = 1; 177 } 178 } 179 180 static void 181 atmegadci_pull_up(struct atmegadci_softc *sc) 182 { 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 189 } 190 } 191 192 static void 193 atmegadci_pull_down(struct atmegadci_softc *sc) 194 { 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 200 } 201 } 202 203 static void 204 atmegadci_wakeup_peer(struct usb2_xfer *xfer) 205 { 206 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 207 uint8_t temp; 208 209 if (!sc->sc_flags.status_suspend) { 210 return; 211 } 212 213 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 214 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 215 216 /* wait 8 milliseconds */ 217 /* Wait for reset to complete. */ 218 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 219 220 /* hardware should have cleared RMWKUP bit */ 221 } 222 223 static void 224 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 225 { 226 DPRINTFN(5, "addr=%d\n", addr); 227 228 addr |= ATMEGA_UDADDR_ADDEN; 229 230 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 231 } 232 233 static uint8_t 234 atmegadci_setup_rx(struct atmegadci_td *td) 235 { 236 struct atmegadci_softc *sc; 237 struct usb2_device_request req; 238 uint16_t count; 239 uint8_t temp; 240 241 /* get pointer to softc */ 242 sc = ATMEGA_PC2SC(td->pc); 243 244 /* select endpoint number */ 245 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 246 247 /* check endpoint status */ 248 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 249 250 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 251 252 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 253 /* abort any ongoing transfer */ 254 if (!td->did_stall) { 255 DPRINTFN(5, "stalling\n"); 256 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 257 ATMEGA_UECONX_EPEN | 258 ATMEGA_UECONX_STALLRQ); 259 td->did_stall = 1; 260 } 261 goto not_complete; 262 } 263 /* get the packet byte count */ 264 count = 265 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 266 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 267 268 /* mask away undefined bits */ 269 count &= 0x7FF; 270 271 /* verify data length */ 272 if (count != td->remainder) { 273 DPRINTFN(0, "Invalid SETUP packet " 274 "length, %d bytes\n", count); 275 goto not_complete; 276 } 277 if (count != sizeof(req)) { 278 DPRINTFN(0, "Unsupported SETUP packet " 279 "length, %d bytes\n", count); 280 goto not_complete; 281 } 282 /* receive data */ 283 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 284 (void *)&req, sizeof(req)); 285 286 /* copy data into real buffer */ 287 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 288 289 td->offset = sizeof(req); 290 td->remainder = 0; 291 292 /* sneak peek the set address */ 293 if ((req.bmRequestType == UT_WRITE_DEVICE) && 294 (req.bRequest == UR_SET_ADDRESS)) { 295 sc->sc_dv_addr = req.wValue[0] & 0x7F; 296 /* must write address before ZLP */ 297 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 298 } else { 299 sc->sc_dv_addr = 0xFF; 300 } 301 302 /* clear SETUP packet interrupt */ 303 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 304 return (0); /* complete */ 305 306 not_complete: 307 /* we only want to know if there is a SETUP packet */ 308 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 309 return (1); /* not complete */ 310 } 311 312 static uint8_t 313 atmegadci_data_rx(struct atmegadci_td *td) 314 { 315 struct atmegadci_softc *sc; 316 struct usb2_page_search buf_res; 317 uint16_t count; 318 uint8_t temp; 319 uint8_t to; 320 uint8_t got_short; 321 322 to = 3; /* don't loop forever! */ 323 got_short = 0; 324 325 /* get pointer to softc */ 326 sc = ATMEGA_PC2SC(td->pc); 327 328 /* select endpoint number */ 329 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 330 331 repeat: 332 /* check if any of the FIFO banks have data */ 333 /* check endpoint status */ 334 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 335 336 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 337 338 if (temp & ATMEGA_UEINTX_RXSTPI) { 339 if (td->remainder == 0) { 340 /* 341 * We are actually complete and have 342 * received the next SETUP 343 */ 344 DPRINTFN(5, "faking complete\n"); 345 return (0); /* complete */ 346 } 347 /* 348 * USB Host Aborted the transfer. 349 */ 350 td->error = 1; 351 return (0); /* complete */ 352 } 353 /* check status */ 354 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 355 ATMEGA_UEINTX_RXOUTI))) { 356 /* no data */ 357 goto not_complete; 358 } 359 /* get the packet byte count */ 360 count = 361 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 362 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 363 364 /* mask away undefined bits */ 365 count &= 0x7FF; 366 367 /* verify the packet byte count */ 368 if (count != td->max_packet_size) { 369 if (count < td->max_packet_size) { 370 /* we have a short packet */ 371 td->short_pkt = 1; 372 got_short = 1; 373 } else { 374 /* invalid USB packet */ 375 td->error = 1; 376 return (0); /* we are complete */ 377 } 378 } 379 /* verify the packet byte count */ 380 if (count > td->remainder) { 381 /* invalid USB packet */ 382 td->error = 1; 383 return (0); /* we are complete */ 384 } 385 while (count > 0) { 386 usb2_get_page(td->pc, td->offset, &buf_res); 387 388 /* get correct length */ 389 if (buf_res.length > count) { 390 buf_res.length = count; 391 } 392 /* receive data */ 393 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 394 buf_res.buffer, buf_res.length); 395 396 /* update counters */ 397 count -= buf_res.length; 398 td->offset += buf_res.length; 399 td->remainder -= buf_res.length; 400 } 401 402 /* clear OUT packet interrupt */ 403 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 404 405 /* release FIFO bank */ 406 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 407 408 /* check if we are complete */ 409 if ((td->remainder == 0) || got_short) { 410 if (td->short_pkt) { 411 /* we are complete */ 412 return (0); 413 } 414 /* else need to receive a zero length packet */ 415 } 416 if (--to) { 417 goto repeat; 418 } 419 not_complete: 420 /* we only want to know if there is a SETUP packet or OUT packet */ 421 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 422 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 423 return (1); /* not complete */ 424 } 425 426 static uint8_t 427 atmegadci_data_tx(struct atmegadci_td *td) 428 { 429 struct atmegadci_softc *sc; 430 struct usb2_page_search buf_res; 431 uint16_t count; 432 uint8_t to; 433 uint8_t temp; 434 435 to = 3; /* don't loop forever! */ 436 437 /* get pointer to softc */ 438 sc = ATMEGA_PC2SC(td->pc); 439 440 /* select endpoint number */ 441 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 442 443 repeat: 444 445 /* check endpoint status */ 446 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 447 448 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 449 450 if (temp & ATMEGA_UEINTX_RXSTPI) { 451 /* 452 * The current transfer was aborted 453 * by the USB Host 454 */ 455 td->error = 1; 456 return (0); /* complete */ 457 } 458 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 459 ATMEGA_UEINTX_TXINI))) { 460 /* cannot write any data */ 461 goto not_complete; 462 } 463 count = td->max_packet_size; 464 if (td->remainder < count) { 465 /* we have a short packet */ 466 td->short_pkt = 1; 467 count = td->remainder; 468 } 469 while (count > 0) { 470 471 usb2_get_page(td->pc, td->offset, &buf_res); 472 473 /* get correct length */ 474 if (buf_res.length > count) { 475 buf_res.length = count; 476 } 477 /* transmit data */ 478 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 479 buf_res.buffer, buf_res.length); 480 481 /* update counters */ 482 count -= buf_res.length; 483 td->offset += buf_res.length; 484 td->remainder -= buf_res.length; 485 } 486 487 /* clear IN packet interrupt */ 488 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 489 490 /* allocate FIFO bank */ 491 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 492 493 /* check remainder */ 494 if (td->remainder == 0) { 495 if (td->short_pkt) { 496 return (0); /* complete */ 497 } 498 /* else we need to transmit a short packet */ 499 } 500 if (--to) { 501 goto repeat; 502 } 503 not_complete: 504 /* we only want to know if there is a SETUP packet or free IN packet */ 505 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 506 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 507 return (1); /* not complete */ 508 } 509 510 static uint8_t 511 atmegadci_data_tx_sync(struct atmegadci_td *td) 512 { 513 struct atmegadci_softc *sc; 514 uint8_t temp; 515 516 /* get pointer to softc */ 517 sc = ATMEGA_PC2SC(td->pc); 518 519 /* select endpoint number */ 520 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 521 522 /* check endpoint status */ 523 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 524 525 DPRINTFN(5, "temp=0x%02x\n", temp); 526 527 if (temp & ATMEGA_UEINTX_RXSTPI) { 528 DPRINTFN(5, "faking complete\n"); 529 /* Race condition */ 530 return (0); /* complete */ 531 } 532 /* 533 * The control endpoint has only got one bank, so if that bank 534 * is free the packet has been transferred! 535 */ 536 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 537 ATMEGA_UEINTX_TXINI))) { 538 /* cannot write any data */ 539 goto not_complete; 540 } 541 if (sc->sc_dv_addr != 0xFF) { 542 /* set new address */ 543 atmegadci_set_address(sc, sc->sc_dv_addr); 544 } 545 return (0); /* complete */ 546 547 not_complete: 548 /* we only want to know if there is a SETUP packet or free IN packet */ 549 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 550 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 551 return (1); /* not complete */ 552 } 553 554 static uint8_t 555 atmegadci_xfer_do_fifo(struct usb2_xfer *xfer) 556 { 557 struct atmegadci_td *td; 558 559 DPRINTFN(9, "\n"); 560 561 td = xfer->td_transfer_cache; 562 while (1) { 563 if ((td->func) (td)) { 564 /* operation in progress */ 565 break; 566 } 567 if (((void *)td) == xfer->td_transfer_last) { 568 goto done; 569 } 570 if (td->error) { 571 goto done; 572 } else if (td->remainder > 0) { 573 /* 574 * We had a short transfer. If there is no alternate 575 * next, stop processing ! 576 */ 577 if (!td->alt_next) { 578 goto done; 579 } 580 } 581 /* 582 * Fetch the next transfer descriptor and transfer 583 * some flags to the next transfer descriptor 584 */ 585 td = td->obj_next; 586 xfer->td_transfer_cache = td; 587 } 588 return (1); /* not complete */ 589 590 done: 591 /* compute all actual lengths */ 592 593 atmegadci_standard_done(xfer); 594 return (0); /* complete */ 595 } 596 597 static void 598 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 599 { 600 struct usb2_xfer *xfer; 601 602 repeat: 603 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 604 if (!atmegadci_xfer_do_fifo(xfer)) { 605 /* queue has been modified */ 606 goto repeat; 607 } 608 } 609 } 610 611 static void 612 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 613 { 614 DPRINTFN(5, "vbus = %u\n", is_on); 615 616 if (is_on) { 617 if (!sc->sc_flags.status_vbus) { 618 sc->sc_flags.status_vbus = 1; 619 620 /* complete root HUB interrupt endpoint */ 621 622 usb2_sw_transfer(&sc->sc_root_intr, 623 &atmegadci_root_intr_done); 624 } 625 } else { 626 if (sc->sc_flags.status_vbus) { 627 sc->sc_flags.status_vbus = 0; 628 sc->sc_flags.status_bus_reset = 0; 629 sc->sc_flags.status_suspend = 0; 630 sc->sc_flags.change_suspend = 0; 631 sc->sc_flags.change_connect = 1; 632 633 /* complete root HUB interrupt endpoint */ 634 635 usb2_sw_transfer(&sc->sc_root_intr, 636 &atmegadci_root_intr_done); 637 } 638 } 639 } 640 641 void 642 atmegadci_interrupt(struct atmegadci_softc *sc) 643 { 644 uint8_t status; 645 646 USB_BUS_LOCK(&sc->sc_bus); 647 648 /* read interrupt status */ 649 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 650 651 /* clear all set interrupts */ 652 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, ~status); 653 654 DPRINTFN(14, "UDINT=0x%02x\n", status); 655 656 /* check for any bus state change interrupts */ 657 if (status & ATMEGA_UDINT_EORSTI) { 658 659 DPRINTFN(5, "end of reset\n"); 660 661 /* set correct state */ 662 sc->sc_flags.status_bus_reset = 1; 663 sc->sc_flags.status_suspend = 0; 664 sc->sc_flags.change_suspend = 0; 665 sc->sc_flags.change_connect = 1; 666 667 /* disable resume interrupt */ 668 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 669 ATMEGA_UDINT_SUSPE | 670 ATMEGA_UDINT_EORSTE); 671 672 /* complete root HUB interrupt endpoint */ 673 usb2_sw_transfer(&sc->sc_root_intr, 674 &atmegadci_root_intr_done); 675 } 676 /* 677 * If resume and suspend is set at the same time we interpret 678 * that like RESUME. Resume is set when there is at least 3 679 * milliseconds of inactivity on the USB BUS. 680 */ 681 if (status & ATMEGA_UDINT_EORSMI) { 682 683 DPRINTFN(5, "resume interrupt\n"); 684 685 if (sc->sc_flags.status_suspend) { 686 /* update status bits */ 687 sc->sc_flags.status_suspend = 0; 688 sc->sc_flags.change_suspend = 1; 689 690 /* disable resume interrupt */ 691 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 692 ATMEGA_UDINT_SUSPE | 693 ATMEGA_UDINT_EORSTE); 694 695 /* complete root HUB interrupt endpoint */ 696 usb2_sw_transfer(&sc->sc_root_intr, 697 &atmegadci_root_intr_done); 698 } 699 } else if (status & ATMEGA_UDINT_SUSPI) { 700 701 DPRINTFN(5, "suspend interrupt\n"); 702 703 if (!sc->sc_flags.status_suspend) { 704 /* update status bits */ 705 sc->sc_flags.status_suspend = 1; 706 sc->sc_flags.change_suspend = 1; 707 708 /* disable suspend interrupt */ 709 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 710 ATMEGA_UDINT_EORSMI | 711 ATMEGA_UDINT_EORSTE); 712 713 /* complete root HUB interrupt endpoint */ 714 usb2_sw_transfer(&sc->sc_root_intr, 715 &atmegadci_root_intr_done); 716 } 717 } 718 /* check VBUS */ 719 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 720 721 /* clear all set interrupts */ 722 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, ~status); 723 724 if (status & ATMEGA_USBINT_VBUSTI) { 725 uint8_t temp; 726 727 DPRINTFN(5, "USBINT=0x%02x\n", status); 728 729 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 730 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 731 } 732 /* check for any endpoint interrupts */ 733 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 734 735 /* clear all set interrupts */ 736 ATMEGA_WRITE_1(sc, ATMEGA_UEINT, ~status); 737 738 if (status) { 739 740 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 741 742 atmegadci_interrupt_poll(sc); 743 } 744 USB_BUS_UNLOCK(&sc->sc_bus); 745 } 746 747 static void 748 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 749 { 750 struct atmegadci_td *td; 751 752 /* get current Transfer Descriptor */ 753 td = temp->td_next; 754 temp->td = td; 755 756 /* prepare for next TD */ 757 temp->td_next = td->obj_next; 758 759 /* fill out the Transfer Descriptor */ 760 td->func = temp->func; 761 td->pc = temp->pc; 762 td->offset = temp->offset; 763 td->remainder = temp->len; 764 td->error = 0; 765 td->did_stall = 0; 766 td->short_pkt = temp->short_pkt; 767 td->alt_next = temp->setup_alt_next; 768 } 769 770 static void 771 atmegadci_setup_standard_chain(struct usb2_xfer *xfer) 772 { 773 struct atmegadci_std_temp temp; 774 struct atmegadci_softc *sc; 775 struct atmegadci_td *td; 776 uint32_t x; 777 uint8_t ep_no; 778 uint8_t need_sync; 779 780 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 781 xfer->address, UE_GET_ADDR(xfer->endpoint), 782 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 783 784 temp.max_frame_size = xfer->max_frame_size; 785 786 td = xfer->td_start[0]; 787 xfer->td_transfer_first = td; 788 xfer->td_transfer_cache = td; 789 790 /* setup temp */ 791 792 temp.td = NULL; 793 temp.td_next = xfer->td_start[0]; 794 temp.offset = 0; 795 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 796 797 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 798 ep_no = (xfer->endpoint & UE_ADDR); 799 800 /* check if we should prepend a setup message */ 801 802 if (xfer->flags_int.control_xfr) { 803 if (xfer->flags_int.control_hdr) { 804 805 temp.func = &atmegadci_setup_rx; 806 temp.len = xfer->frlengths[0]; 807 temp.pc = xfer->frbuffers + 0; 808 temp.short_pkt = temp.len ? 1 : 0; 809 /* check for last frame */ 810 if (xfer->nframes == 1) { 811 /* no STATUS stage yet, SETUP is last */ 812 if (xfer->flags_int.control_act) 813 temp.setup_alt_next = 0; 814 } 815 816 atmegadci_setup_standard_chain_sub(&temp); 817 } 818 x = 1; 819 } else { 820 x = 0; 821 } 822 823 if (x != xfer->nframes) { 824 if (xfer->endpoint & UE_DIR_IN) { 825 temp.func = &atmegadci_data_tx; 826 need_sync = 1; 827 } else { 828 temp.func = &atmegadci_data_rx; 829 need_sync = 0; 830 } 831 832 /* setup "pc" pointer */ 833 temp.pc = xfer->frbuffers + x; 834 } else { 835 need_sync = 0; 836 } 837 while (x != xfer->nframes) { 838 839 /* DATA0 / DATA1 message */ 840 841 temp.len = xfer->frlengths[x]; 842 843 x++; 844 845 if (x == xfer->nframes) { 846 if (xfer->flags_int.control_xfr) { 847 if (xfer->flags_int.control_act) { 848 temp.setup_alt_next = 0; 849 } 850 } else { 851 temp.setup_alt_next = 0; 852 } 853 } 854 if (temp.len == 0) { 855 856 /* make sure that we send an USB packet */ 857 858 temp.short_pkt = 0; 859 860 } else { 861 862 /* regular data transfer */ 863 864 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 865 } 866 867 atmegadci_setup_standard_chain_sub(&temp); 868 869 if (xfer->flags_int.isochronous_xfr) { 870 temp.offset += temp.len; 871 } else { 872 /* get next Page Cache pointer */ 873 temp.pc = xfer->frbuffers + x; 874 } 875 } 876 877 if (xfer->flags_int.control_xfr) { 878 879 /* always setup a valid "pc" pointer for status and sync */ 880 temp.pc = xfer->frbuffers + 0; 881 temp.len = 0; 882 temp.short_pkt = 0; 883 temp.setup_alt_next = 0; 884 885 /* check if we need to sync */ 886 if (need_sync) { 887 /* we need a SYNC point after TX */ 888 temp.func = &atmegadci_data_tx_sync; 889 atmegadci_setup_standard_chain_sub(&temp); 890 } 891 892 /* check if we should append a status stage */ 893 if (!xfer->flags_int.control_act) { 894 895 /* 896 * Send a DATA1 message and invert the current 897 * endpoint direction. 898 */ 899 if (xfer->endpoint & UE_DIR_IN) { 900 temp.func = &atmegadci_data_rx; 901 need_sync = 0; 902 } else { 903 temp.func = &atmegadci_data_tx; 904 need_sync = 1; 905 } 906 907 atmegadci_setup_standard_chain_sub(&temp); 908 if (need_sync) { 909 /* we need a SYNC point after TX */ 910 temp.func = &atmegadci_data_tx_sync; 911 atmegadci_setup_standard_chain_sub(&temp); 912 } 913 } 914 } 915 /* must have at least one frame! */ 916 td = temp.td; 917 xfer->td_transfer_last = td; 918 } 919 920 static void 921 atmegadci_timeout(void *arg) 922 { 923 struct usb2_xfer *xfer = arg; 924 925 DPRINTF("xfer=%p\n", xfer); 926 927 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 928 929 /* transfer is transferred */ 930 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 931 } 932 933 static void 934 atmegadci_start_standard_chain(struct usb2_xfer *xfer) 935 { 936 DPRINTFN(9, "\n"); 937 938 /* poll one time - will turn on interrupts */ 939 if (atmegadci_xfer_do_fifo(xfer)) { 940 941 /* put transfer on interrupt queue */ 942 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 943 944 /* start timeout, if any */ 945 if (xfer->timeout != 0) { 946 usb2_transfer_timeout_ms(xfer, 947 &atmegadci_timeout, xfer->timeout); 948 } 949 } 950 } 951 952 static void 953 atmegadci_root_intr_done(struct usb2_xfer *xfer, 954 struct usb2_sw_transfer *std) 955 { 956 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 957 958 DPRINTFN(9, "\n"); 959 960 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 961 962 if (std->state != USB_SW_TR_PRE_DATA) { 963 if (std->state == USB_SW_TR_PRE_CALLBACK) { 964 /* transfer transferred */ 965 atmegadci_device_done(xfer, std->err); 966 } 967 goto done; 968 } 969 /* setup buffer */ 970 std->ptr = sc->sc_hub_idata; 971 std->len = sizeof(sc->sc_hub_idata); 972 973 /* set port bit */ 974 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 975 976 done: 977 return; 978 } 979 980 static usb2_error_t 981 atmegadci_standard_done_sub(struct usb2_xfer *xfer) 982 { 983 struct atmegadci_td *td; 984 uint32_t len; 985 uint8_t error; 986 987 DPRINTFN(9, "\n"); 988 989 td = xfer->td_transfer_cache; 990 991 do { 992 len = td->remainder; 993 994 if (xfer->aframes != xfer->nframes) { 995 /* 996 * Verify the length and subtract 997 * the remainder from "frlengths[]": 998 */ 999 if (len > xfer->frlengths[xfer->aframes]) { 1000 td->error = 1; 1001 } else { 1002 xfer->frlengths[xfer->aframes] -= len; 1003 } 1004 } 1005 /* Check for transfer error */ 1006 if (td->error) { 1007 /* the transfer is finished */ 1008 error = 1; 1009 td = NULL; 1010 break; 1011 } 1012 /* Check for short transfer */ 1013 if (len > 0) { 1014 if (xfer->flags_int.short_frames_ok) { 1015 /* follow alt next */ 1016 if (td->alt_next) { 1017 td = td->obj_next; 1018 } else { 1019 td = NULL; 1020 } 1021 } else { 1022 /* the transfer is finished */ 1023 td = NULL; 1024 } 1025 error = 0; 1026 break; 1027 } 1028 td = td->obj_next; 1029 1030 /* this USB frame is complete */ 1031 error = 0; 1032 break; 1033 1034 } while (0); 1035 1036 /* update transfer cache */ 1037 1038 xfer->td_transfer_cache = td; 1039 1040 return (error ? 1041 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1042 } 1043 1044 static void 1045 atmegadci_standard_done(struct usb2_xfer *xfer) 1046 { 1047 usb2_error_t err = 0; 1048 1049 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1050 xfer, xfer->pipe); 1051 1052 /* reset scanner */ 1053 1054 xfer->td_transfer_cache = xfer->td_transfer_first; 1055 1056 if (xfer->flags_int.control_xfr) { 1057 1058 if (xfer->flags_int.control_hdr) { 1059 1060 err = atmegadci_standard_done_sub(xfer); 1061 } 1062 xfer->aframes = 1; 1063 1064 if (xfer->td_transfer_cache == NULL) { 1065 goto done; 1066 } 1067 } 1068 while (xfer->aframes != xfer->nframes) { 1069 1070 err = atmegadci_standard_done_sub(xfer); 1071 xfer->aframes++; 1072 1073 if (xfer->td_transfer_cache == NULL) { 1074 goto done; 1075 } 1076 } 1077 1078 if (xfer->flags_int.control_xfr && 1079 !xfer->flags_int.control_act) { 1080 1081 err = atmegadci_standard_done_sub(xfer); 1082 } 1083 done: 1084 atmegadci_device_done(xfer, err); 1085 } 1086 1087 /*------------------------------------------------------------------------* 1088 * atmegadci_device_done 1089 * 1090 * NOTE: this function can be called more than one time on the 1091 * same USB transfer! 1092 *------------------------------------------------------------------------*/ 1093 static void 1094 atmegadci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1095 { 1096 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1097 uint8_t ep_no; 1098 1099 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1100 1101 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1102 xfer, xfer->pipe, error); 1103 1104 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1105 ep_no = (xfer->endpoint & UE_ADDR); 1106 1107 /* select endpoint number */ 1108 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1109 1110 /* disable endpoint interrupt */ 1111 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1112 1113 DPRINTFN(15, "disabled interrupts!\n"); 1114 } 1115 /* dequeue transfer and start next transfer */ 1116 usb2_transfer_done(xfer, error); 1117 } 1118 1119 static void 1120 atmegadci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1121 struct usb2_pipe *pipe) 1122 { 1123 struct atmegadci_softc *sc; 1124 uint8_t ep_no; 1125 1126 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1127 1128 DPRINTFN(5, "pipe=%p\n", pipe); 1129 1130 if (xfer) { 1131 /* cancel any ongoing transfers */ 1132 atmegadci_device_done(xfer, USB_ERR_STALLED); 1133 } 1134 sc = ATMEGA_BUS2SC(udev->bus); 1135 /* get endpoint number */ 1136 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1137 /* select endpoint number */ 1138 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1139 /* set stall */ 1140 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1141 ATMEGA_UECONX_EPEN | 1142 ATMEGA_UECONX_STALLRQ); 1143 } 1144 1145 static void 1146 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1147 uint8_t ep_type, uint8_t ep_dir) 1148 { 1149 uint8_t temp; 1150 1151 if (ep_type == UE_CONTROL) { 1152 /* clearing stall is not needed */ 1153 return; 1154 } 1155 /* select endpoint number */ 1156 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1157 1158 /* set endpoint reset */ 1159 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1160 1161 /* clear endpoint reset */ 1162 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1163 1164 /* set stall */ 1165 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1166 ATMEGA_UECONX_EPEN | 1167 ATMEGA_UECONX_STALLRQ); 1168 1169 /* reset data toggle */ 1170 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1171 ATMEGA_UECONX_EPEN | 1172 ATMEGA_UECONX_RSTDT); 1173 1174 /* clear stall */ 1175 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1176 ATMEGA_UECONX_EPEN | 1177 ATMEGA_UECONX_STALLRQC); 1178 1179 do { 1180 temp = 0; 1181 if (ep_type == UE_BULK) { 1182 temp |= ATMEGA_UECFG0X_EPTYPE2; 1183 } else if (ep_type == UE_INTERRUPT) { 1184 temp |= ATMEGA_UECFG0X_EPTYPE3; 1185 } else { 1186 temp |= ATMEGA_UECFG0X_EPTYPE1; 1187 } 1188 if (ep_dir & UE_DIR_IN) { 1189 temp |= ATMEGA_UECFG0X_EPDIR; 1190 } 1191 /* two banks, 64-bytes wMaxPacket */ 1192 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1193 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1194 ATMEGA_UECFG1X_ALLOC | 1195 ATMEGA_UECFG1X_EPBK1 | 1196 ATMEGA_UECFG1X_EPSIZE(3)); 1197 1198 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1199 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1200 DPRINTFN(0, "Chip rejected configuration\n"); 1201 } 1202 } while (0); 1203 } 1204 1205 static void 1206 atmegadci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1207 { 1208 struct atmegadci_softc *sc; 1209 struct usb2_endpoint_descriptor *ed; 1210 1211 DPRINTFN(5, "pipe=%p\n", pipe); 1212 1213 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1214 1215 /* check mode */ 1216 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1217 /* not supported */ 1218 return; 1219 } 1220 /* get softc */ 1221 sc = ATMEGA_BUS2SC(udev->bus); 1222 1223 /* get endpoint descriptor */ 1224 ed = pipe->edesc; 1225 1226 /* reset endpoint */ 1227 atmegadci_clear_stall_sub(sc, 1228 (ed->bEndpointAddress & UE_ADDR), 1229 (ed->bmAttributes & UE_XFERTYPE), 1230 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1231 } 1232 1233 usb2_error_t 1234 atmegadci_init(struct atmegadci_softc *sc) 1235 { 1236 uint8_t n; 1237 1238 DPRINTF("start\n"); 1239 1240 /* set up the bus structure */ 1241 sc->sc_bus.usbrev = USB_REV_1_1; 1242 sc->sc_bus.methods = &atmegadci_bus_methods; 1243 1244 USB_BUS_LOCK(&sc->sc_bus); 1245 #if 0 1246 /* XXX TODO - currently done by boot strap */ 1247 1248 /* enable USB PAD regulator */ 1249 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1250 ATMEGA_UHWCON_UVREGE | ATMEGA_UHWCON_UIMOD); 1251 #endif 1252 /* turn on clocks */ 1253 (sc->sc_clocks_on) (&sc->sc_bus); 1254 1255 /* make sure device is re-enumerated */ 1256 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1257 1258 /* wait a little for things to stabilise */ 1259 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1260 1261 /* enable interrupts */ 1262 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1263 ATMEGA_UDINT_SUSPE | 1264 ATMEGA_UDINT_EORSTE); 1265 1266 /* reset all endpoints */ 1267 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1268 (1 << ATMEGA_EP_MAX) - 1); 1269 1270 /* disable reset */ 1271 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1272 1273 /* disable all endpoints */ 1274 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1275 1276 /* select endpoint */ 1277 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1278 1279 /* disable endpoint interrupt */ 1280 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1281 1282 /* disable endpoint */ 1283 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1284 } 1285 1286 /* turn off clocks */ 1287 1288 atmegadci_clocks_off(sc); 1289 1290 /* read initial VBUS state */ 1291 1292 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1293 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1294 1295 USB_BUS_UNLOCK(&sc->sc_bus); 1296 1297 /* catch any lost interrupts */ 1298 1299 atmegadci_do_poll(&sc->sc_bus); 1300 1301 return (0); /* success */ 1302 } 1303 1304 void 1305 atmegadci_uninit(struct atmegadci_softc *sc) 1306 { 1307 USB_BUS_LOCK(&sc->sc_bus); 1308 1309 /* turn on clocks */ 1310 (sc->sc_clocks_on) (&sc->sc_bus); 1311 1312 /* disable interrupts */ 1313 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1314 1315 /* reset all endpoints */ 1316 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1317 (1 << ATMEGA_EP_MAX) - 1); 1318 1319 /* disable reset */ 1320 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1321 1322 sc->sc_flags.port_powered = 0; 1323 sc->sc_flags.status_vbus = 0; 1324 sc->sc_flags.status_bus_reset = 0; 1325 sc->sc_flags.status_suspend = 0; 1326 sc->sc_flags.change_suspend = 0; 1327 sc->sc_flags.change_connect = 1; 1328 1329 atmegadci_pull_down(sc); 1330 atmegadci_clocks_off(sc); 1331 1332 /* disable USB PAD regulator */ 1333 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1334 1335 USB_BUS_UNLOCK(&sc->sc_bus); 1336 } 1337 1338 void 1339 atmegadci_suspend(struct atmegadci_softc *sc) 1340 { 1341 return; 1342 } 1343 1344 void 1345 atmegadci_resume(struct atmegadci_softc *sc) 1346 { 1347 return; 1348 } 1349 1350 static void 1351 atmegadci_do_poll(struct usb2_bus *bus) 1352 { 1353 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1354 1355 USB_BUS_LOCK(&sc->sc_bus); 1356 atmegadci_interrupt_poll(sc); 1357 atmegadci_root_ctrl_poll(sc); 1358 USB_BUS_UNLOCK(&sc->sc_bus); 1359 } 1360 1361 /*------------------------------------------------------------------------* 1362 * at91dci bulk support 1363 *------------------------------------------------------------------------*/ 1364 static void 1365 atmegadci_device_bulk_open(struct usb2_xfer *xfer) 1366 { 1367 return; 1368 } 1369 1370 static void 1371 atmegadci_device_bulk_close(struct usb2_xfer *xfer) 1372 { 1373 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1374 } 1375 1376 static void 1377 atmegadci_device_bulk_enter(struct usb2_xfer *xfer) 1378 { 1379 return; 1380 } 1381 1382 static void 1383 atmegadci_device_bulk_start(struct usb2_xfer *xfer) 1384 { 1385 /* setup TDs */ 1386 atmegadci_setup_standard_chain(xfer); 1387 atmegadci_start_standard_chain(xfer); 1388 } 1389 1390 struct usb2_pipe_methods atmegadci_device_bulk_methods = 1391 { 1392 .open = atmegadci_device_bulk_open, 1393 .close = atmegadci_device_bulk_close, 1394 .enter = atmegadci_device_bulk_enter, 1395 .start = atmegadci_device_bulk_start, 1396 .enter_is_cancelable = 1, 1397 .start_is_cancelable = 1, 1398 }; 1399 1400 /*------------------------------------------------------------------------* 1401 * at91dci control support 1402 *------------------------------------------------------------------------*/ 1403 static void 1404 atmegadci_device_ctrl_open(struct usb2_xfer *xfer) 1405 { 1406 return; 1407 } 1408 1409 static void 1410 atmegadci_device_ctrl_close(struct usb2_xfer *xfer) 1411 { 1412 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1413 } 1414 1415 static void 1416 atmegadci_device_ctrl_enter(struct usb2_xfer *xfer) 1417 { 1418 return; 1419 } 1420 1421 static void 1422 atmegadci_device_ctrl_start(struct usb2_xfer *xfer) 1423 { 1424 /* setup TDs */ 1425 atmegadci_setup_standard_chain(xfer); 1426 atmegadci_start_standard_chain(xfer); 1427 } 1428 1429 struct usb2_pipe_methods atmegadci_device_ctrl_methods = 1430 { 1431 .open = atmegadci_device_ctrl_open, 1432 .close = atmegadci_device_ctrl_close, 1433 .enter = atmegadci_device_ctrl_enter, 1434 .start = atmegadci_device_ctrl_start, 1435 .enter_is_cancelable = 1, 1436 .start_is_cancelable = 1, 1437 }; 1438 1439 /*------------------------------------------------------------------------* 1440 * at91dci interrupt support 1441 *------------------------------------------------------------------------*/ 1442 static void 1443 atmegadci_device_intr_open(struct usb2_xfer *xfer) 1444 { 1445 return; 1446 } 1447 1448 static void 1449 atmegadci_device_intr_close(struct usb2_xfer *xfer) 1450 { 1451 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1452 } 1453 1454 static void 1455 atmegadci_device_intr_enter(struct usb2_xfer *xfer) 1456 { 1457 return; 1458 } 1459 1460 static void 1461 atmegadci_device_intr_start(struct usb2_xfer *xfer) 1462 { 1463 /* setup TDs */ 1464 atmegadci_setup_standard_chain(xfer); 1465 atmegadci_start_standard_chain(xfer); 1466 } 1467 1468 struct usb2_pipe_methods atmegadci_device_intr_methods = 1469 { 1470 .open = atmegadci_device_intr_open, 1471 .close = atmegadci_device_intr_close, 1472 .enter = atmegadci_device_intr_enter, 1473 .start = atmegadci_device_intr_start, 1474 .enter_is_cancelable = 1, 1475 .start_is_cancelable = 1, 1476 }; 1477 1478 /*------------------------------------------------------------------------* 1479 * at91dci full speed isochronous support 1480 *------------------------------------------------------------------------*/ 1481 static void 1482 atmegadci_device_isoc_fs_open(struct usb2_xfer *xfer) 1483 { 1484 return; 1485 } 1486 1487 static void 1488 atmegadci_device_isoc_fs_close(struct usb2_xfer *xfer) 1489 { 1490 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1491 } 1492 1493 static void 1494 atmegadci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1495 { 1496 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1497 uint32_t temp; 1498 uint32_t nframes; 1499 1500 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1501 xfer, xfer->pipe->isoc_next, xfer->nframes); 1502 1503 /* get the current frame index */ 1504 1505 nframes = 1506 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1507 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1508 1509 nframes &= ATMEGA_FRAME_MASK; 1510 1511 /* 1512 * check if the frame index is within the window where the frames 1513 * will be inserted 1514 */ 1515 temp = (nframes - xfer->pipe->isoc_next) & ATMEGA_FRAME_MASK; 1516 1517 if ((xfer->pipe->is_synced == 0) || 1518 (temp < xfer->nframes)) { 1519 /* 1520 * If there is data underflow or the pipe queue is 1521 * empty we schedule the transfer a few frames ahead 1522 * of the current frame position. Else two isochronous 1523 * transfers might overlap. 1524 */ 1525 xfer->pipe->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1526 xfer->pipe->is_synced = 1; 1527 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1528 } 1529 /* 1530 * compute how many milliseconds the insertion is ahead of the 1531 * current frame position: 1532 */ 1533 temp = (xfer->pipe->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1534 1535 /* 1536 * pre-compute when the isochronous transfer will be finished: 1537 */ 1538 xfer->isoc_time_complete = 1539 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1540 xfer->nframes; 1541 1542 /* compute frame number for next insertion */ 1543 xfer->pipe->isoc_next += xfer->nframes; 1544 1545 /* setup TDs */ 1546 atmegadci_setup_standard_chain(xfer); 1547 } 1548 1549 static void 1550 atmegadci_device_isoc_fs_start(struct usb2_xfer *xfer) 1551 { 1552 /* start TD chain */ 1553 atmegadci_start_standard_chain(xfer); 1554 } 1555 1556 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods = 1557 { 1558 .open = atmegadci_device_isoc_fs_open, 1559 .close = atmegadci_device_isoc_fs_close, 1560 .enter = atmegadci_device_isoc_fs_enter, 1561 .start = atmegadci_device_isoc_fs_start, 1562 .enter_is_cancelable = 1, 1563 .start_is_cancelable = 1, 1564 }; 1565 1566 /*------------------------------------------------------------------------* 1567 * at91dci root control support 1568 *------------------------------------------------------------------------* 1569 * simulate a hardware HUB by handling 1570 * all the necessary requests 1571 *------------------------------------------------------------------------*/ 1572 1573 static void 1574 atmegadci_root_ctrl_open(struct usb2_xfer *xfer) 1575 { 1576 return; 1577 } 1578 1579 static void 1580 atmegadci_root_ctrl_close(struct usb2_xfer *xfer) 1581 { 1582 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1583 1584 if (sc->sc_root_ctrl.xfer == xfer) { 1585 sc->sc_root_ctrl.xfer = NULL; 1586 } 1587 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1588 } 1589 1590 /* 1591 * USB descriptors for the virtual Root HUB: 1592 */ 1593 1594 static const struct usb2_device_descriptor atmegadci_devd = { 1595 .bLength = sizeof(struct usb2_device_descriptor), 1596 .bDescriptorType = UDESC_DEVICE, 1597 .bcdUSB = {0x00, 0x02}, 1598 .bDeviceClass = UDCLASS_HUB, 1599 .bDeviceSubClass = UDSUBCLASS_HUB, 1600 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1601 .bMaxPacketSize = 64, 1602 .bcdDevice = {0x00, 0x01}, 1603 .iManufacturer = 1, 1604 .iProduct = 2, 1605 .bNumConfigurations = 1, 1606 }; 1607 1608 static const struct usb2_device_qualifier atmegadci_odevd = { 1609 .bLength = sizeof(struct usb2_device_qualifier), 1610 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1611 .bcdUSB = {0x00, 0x02}, 1612 .bDeviceClass = UDCLASS_HUB, 1613 .bDeviceSubClass = UDSUBCLASS_HUB, 1614 .bDeviceProtocol = UDPROTO_FSHUB, 1615 .bMaxPacketSize0 = 0, 1616 .bNumConfigurations = 0, 1617 }; 1618 1619 static const struct atmegadci_config_desc atmegadci_confd = { 1620 .confd = { 1621 .bLength = sizeof(struct usb2_config_descriptor), 1622 .bDescriptorType = UDESC_CONFIG, 1623 .wTotalLength[0] = sizeof(atmegadci_confd), 1624 .bNumInterface = 1, 1625 .bConfigurationValue = 1, 1626 .iConfiguration = 0, 1627 .bmAttributes = UC_SELF_POWERED, 1628 .bMaxPower = 0, 1629 }, 1630 .ifcd = { 1631 .bLength = sizeof(struct usb2_interface_descriptor), 1632 .bDescriptorType = UDESC_INTERFACE, 1633 .bNumEndpoints = 1, 1634 .bInterfaceClass = UICLASS_HUB, 1635 .bInterfaceSubClass = UISUBCLASS_HUB, 1636 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1637 }, 1638 1639 .endpd = { 1640 .bLength = sizeof(struct usb2_endpoint_descriptor), 1641 .bDescriptorType = UDESC_ENDPOINT, 1642 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1643 .bmAttributes = UE_INTERRUPT, 1644 .wMaxPacketSize[0] = 8, 1645 .bInterval = 255, 1646 }, 1647 }; 1648 1649 static const struct usb2_hub_descriptor_min atmegadci_hubd = { 1650 .bDescLength = sizeof(atmegadci_hubd), 1651 .bDescriptorType = UDESC_HUB, 1652 .bNbrPorts = 1, 1653 .wHubCharacteristics[0] = 1654 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1655 .wHubCharacteristics[1] = 1656 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1657 .bPwrOn2PwrGood = 50, 1658 .bHubContrCurrent = 0, 1659 .DeviceRemovable = {0}, /* port is removable */ 1660 }; 1661 1662 #define STRING_LANG \ 1663 0x09, 0x04, /* American English */ 1664 1665 #define STRING_VENDOR \ 1666 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1667 1668 #define STRING_PRODUCT \ 1669 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1670 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1671 'U', 0, 'B', 0, 1672 1673 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1674 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1675 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1676 1677 static void 1678 atmegadci_root_ctrl_enter(struct usb2_xfer *xfer) 1679 { 1680 return; 1681 } 1682 1683 static void 1684 atmegadci_root_ctrl_start(struct usb2_xfer *xfer) 1685 { 1686 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1687 1688 sc->sc_root_ctrl.xfer = xfer; 1689 1690 usb2_bus_roothub_exec(xfer->xroot->bus); 1691 } 1692 1693 static void 1694 atmegadci_root_ctrl_task(struct usb2_bus *bus) 1695 { 1696 atmegadci_root_ctrl_poll(ATMEGA_BUS2SC(bus)); 1697 } 1698 1699 static void 1700 atmegadci_root_ctrl_done(struct usb2_xfer *xfer, 1701 struct usb2_sw_transfer *std) 1702 { 1703 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1704 uint16_t value; 1705 uint16_t index; 1706 uint8_t temp; 1707 1708 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1709 1710 if (std->state != USB_SW_TR_SETUP) { 1711 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1712 /* transfer transferred */ 1713 atmegadci_device_done(xfer, std->err); 1714 } 1715 goto done; 1716 } 1717 /* buffer reset */ 1718 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1719 std->len = 0; 1720 1721 value = UGETW(std->req.wValue); 1722 index = UGETW(std->req.wIndex); 1723 1724 /* demultiplex the control request */ 1725 1726 switch (std->req.bmRequestType) { 1727 case UT_READ_DEVICE: 1728 switch (std->req.bRequest) { 1729 case UR_GET_DESCRIPTOR: 1730 goto tr_handle_get_descriptor; 1731 case UR_GET_CONFIG: 1732 goto tr_handle_get_config; 1733 case UR_GET_STATUS: 1734 goto tr_handle_get_status; 1735 default: 1736 goto tr_stalled; 1737 } 1738 break; 1739 1740 case UT_WRITE_DEVICE: 1741 switch (std->req.bRequest) { 1742 case UR_SET_ADDRESS: 1743 goto tr_handle_set_address; 1744 case UR_SET_CONFIG: 1745 goto tr_handle_set_config; 1746 case UR_CLEAR_FEATURE: 1747 goto tr_valid; /* nop */ 1748 case UR_SET_DESCRIPTOR: 1749 goto tr_valid; /* nop */ 1750 case UR_SET_FEATURE: 1751 default: 1752 goto tr_stalled; 1753 } 1754 break; 1755 1756 case UT_WRITE_ENDPOINT: 1757 switch (std->req.bRequest) { 1758 case UR_CLEAR_FEATURE: 1759 switch (UGETW(std->req.wValue)) { 1760 case UF_ENDPOINT_HALT: 1761 goto tr_handle_clear_halt; 1762 case UF_DEVICE_REMOTE_WAKEUP: 1763 goto tr_handle_clear_wakeup; 1764 default: 1765 goto tr_stalled; 1766 } 1767 break; 1768 case UR_SET_FEATURE: 1769 switch (UGETW(std->req.wValue)) { 1770 case UF_ENDPOINT_HALT: 1771 goto tr_handle_set_halt; 1772 case UF_DEVICE_REMOTE_WAKEUP: 1773 goto tr_handle_set_wakeup; 1774 default: 1775 goto tr_stalled; 1776 } 1777 break; 1778 case UR_SYNCH_FRAME: 1779 goto tr_valid; /* nop */ 1780 default: 1781 goto tr_stalled; 1782 } 1783 break; 1784 1785 case UT_READ_ENDPOINT: 1786 switch (std->req.bRequest) { 1787 case UR_GET_STATUS: 1788 goto tr_handle_get_ep_status; 1789 default: 1790 goto tr_stalled; 1791 } 1792 break; 1793 1794 case UT_WRITE_INTERFACE: 1795 switch (std->req.bRequest) { 1796 case UR_SET_INTERFACE: 1797 goto tr_handle_set_interface; 1798 case UR_CLEAR_FEATURE: 1799 goto tr_valid; /* nop */ 1800 case UR_SET_FEATURE: 1801 default: 1802 goto tr_stalled; 1803 } 1804 break; 1805 1806 case UT_READ_INTERFACE: 1807 switch (std->req.bRequest) { 1808 case UR_GET_INTERFACE: 1809 goto tr_handle_get_interface; 1810 case UR_GET_STATUS: 1811 goto tr_handle_get_iface_status; 1812 default: 1813 goto tr_stalled; 1814 } 1815 break; 1816 1817 case UT_WRITE_CLASS_INTERFACE: 1818 case UT_WRITE_VENDOR_INTERFACE: 1819 /* XXX forward */ 1820 break; 1821 1822 case UT_READ_CLASS_INTERFACE: 1823 case UT_READ_VENDOR_INTERFACE: 1824 /* XXX forward */ 1825 break; 1826 1827 case UT_WRITE_CLASS_DEVICE: 1828 switch (std->req.bRequest) { 1829 case UR_CLEAR_FEATURE: 1830 goto tr_valid; 1831 case UR_SET_DESCRIPTOR: 1832 case UR_SET_FEATURE: 1833 break; 1834 default: 1835 goto tr_stalled; 1836 } 1837 break; 1838 1839 case UT_WRITE_CLASS_OTHER: 1840 switch (std->req.bRequest) { 1841 case UR_CLEAR_FEATURE: 1842 goto tr_handle_clear_port_feature; 1843 case UR_SET_FEATURE: 1844 goto tr_handle_set_port_feature; 1845 case UR_CLEAR_TT_BUFFER: 1846 case UR_RESET_TT: 1847 case UR_STOP_TT: 1848 goto tr_valid; 1849 1850 default: 1851 goto tr_stalled; 1852 } 1853 break; 1854 1855 case UT_READ_CLASS_OTHER: 1856 switch (std->req.bRequest) { 1857 case UR_GET_TT_STATE: 1858 goto tr_handle_get_tt_state; 1859 case UR_GET_STATUS: 1860 goto tr_handle_get_port_status; 1861 default: 1862 goto tr_stalled; 1863 } 1864 break; 1865 1866 case UT_READ_CLASS_DEVICE: 1867 switch (std->req.bRequest) { 1868 case UR_GET_DESCRIPTOR: 1869 goto tr_handle_get_class_descriptor; 1870 case UR_GET_STATUS: 1871 goto tr_handle_get_class_status; 1872 1873 default: 1874 goto tr_stalled; 1875 } 1876 break; 1877 default: 1878 goto tr_stalled; 1879 } 1880 goto tr_valid; 1881 1882 tr_handle_get_descriptor: 1883 switch (value >> 8) { 1884 case UDESC_DEVICE: 1885 if (value & 0xff) { 1886 goto tr_stalled; 1887 } 1888 std->len = sizeof(atmegadci_devd); 1889 std->ptr = USB_ADD_BYTES(&atmegadci_devd, 0); 1890 goto tr_valid; 1891 case UDESC_CONFIG: 1892 if (value & 0xff) { 1893 goto tr_stalled; 1894 } 1895 std->len = sizeof(atmegadci_confd); 1896 std->ptr = USB_ADD_BYTES(&atmegadci_confd, 0); 1897 goto tr_valid; 1898 case UDESC_STRING: 1899 switch (value & 0xff) { 1900 case 0: /* Language table */ 1901 std->len = sizeof(atmegadci_langtab); 1902 std->ptr = USB_ADD_BYTES(&atmegadci_langtab, 0); 1903 goto tr_valid; 1904 1905 case 1: /* Vendor */ 1906 std->len = sizeof(atmegadci_vendor); 1907 std->ptr = USB_ADD_BYTES(&atmegadci_vendor, 0); 1908 goto tr_valid; 1909 1910 case 2: /* Product */ 1911 std->len = sizeof(atmegadci_product); 1912 std->ptr = USB_ADD_BYTES(&atmegadci_product, 0); 1913 goto tr_valid; 1914 default: 1915 break; 1916 } 1917 break; 1918 default: 1919 goto tr_stalled; 1920 } 1921 goto tr_stalled; 1922 1923 tr_handle_get_config: 1924 std->len = 1; 1925 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1926 goto tr_valid; 1927 1928 tr_handle_get_status: 1929 std->len = 2; 1930 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1931 goto tr_valid; 1932 1933 tr_handle_set_address: 1934 if (value & 0xFF00) { 1935 goto tr_stalled; 1936 } 1937 sc->sc_rt_addr = value; 1938 goto tr_valid; 1939 1940 tr_handle_set_config: 1941 if (value >= 2) { 1942 goto tr_stalled; 1943 } 1944 sc->sc_conf = value; 1945 goto tr_valid; 1946 1947 tr_handle_get_interface: 1948 std->len = 1; 1949 sc->sc_hub_temp.wValue[0] = 0; 1950 goto tr_valid; 1951 1952 tr_handle_get_tt_state: 1953 tr_handle_get_class_status: 1954 tr_handle_get_iface_status: 1955 tr_handle_get_ep_status: 1956 std->len = 2; 1957 USETW(sc->sc_hub_temp.wValue, 0); 1958 goto tr_valid; 1959 1960 tr_handle_set_halt: 1961 tr_handle_set_interface: 1962 tr_handle_set_wakeup: 1963 tr_handle_clear_wakeup: 1964 tr_handle_clear_halt: 1965 goto tr_valid; 1966 1967 tr_handle_clear_port_feature: 1968 if (index != 1) { 1969 goto tr_stalled; 1970 } 1971 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1972 1973 switch (value) { 1974 case UHF_PORT_SUSPEND: 1975 atmegadci_wakeup_peer(xfer); 1976 break; 1977 1978 case UHF_PORT_ENABLE: 1979 sc->sc_flags.port_enabled = 0; 1980 break; 1981 1982 case UHF_PORT_TEST: 1983 case UHF_PORT_INDICATOR: 1984 case UHF_C_PORT_ENABLE: 1985 case UHF_C_PORT_OVER_CURRENT: 1986 case UHF_C_PORT_RESET: 1987 /* nops */ 1988 break; 1989 case UHF_PORT_POWER: 1990 sc->sc_flags.port_powered = 0; 1991 atmegadci_pull_down(sc); 1992 atmegadci_clocks_off(sc); 1993 break; 1994 case UHF_C_PORT_CONNECTION: 1995 /* clear connect change flag */ 1996 sc->sc_flags.change_connect = 0; 1997 1998 /* configure the control endpoint */ 1999 2000 /* select endpoint number */ 2001 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 2002 2003 /* set endpoint reset */ 2004 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 2005 2006 /* clear endpoint reset */ 2007 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 2008 2009 /* enable and stall endpoint */ 2010 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 2011 ATMEGA_UECONX_EPEN | 2012 ATMEGA_UECONX_STALLRQ); 2013 2014 /* one bank, 64-bytes wMaxPacket */ 2015 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 2016 ATMEGA_UECFG0X_EPTYPE0); 2017 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 2018 ATMEGA_UECFG1X_ALLOC | 2019 ATMEGA_UECFG1X_EPBK0 | 2020 ATMEGA_UECFG1X_EPSIZE(3)); 2021 2022 /* check valid config */ 2023 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 2024 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 2025 DPRINTFN(0, "Chip rejected EP0 configuration\n"); 2026 } 2027 break; 2028 case UHF_C_PORT_SUSPEND: 2029 sc->sc_flags.change_suspend = 0; 2030 break; 2031 default: 2032 std->err = USB_ERR_IOERROR; 2033 goto done; 2034 } 2035 goto tr_valid; 2036 2037 tr_handle_set_port_feature: 2038 if (index != 1) { 2039 goto tr_stalled; 2040 } 2041 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2042 2043 switch (value) { 2044 case UHF_PORT_ENABLE: 2045 sc->sc_flags.port_enabled = 1; 2046 break; 2047 case UHF_PORT_SUSPEND: 2048 case UHF_PORT_RESET: 2049 case UHF_PORT_TEST: 2050 case UHF_PORT_INDICATOR: 2051 /* nops */ 2052 break; 2053 case UHF_PORT_POWER: 2054 sc->sc_flags.port_powered = 1; 2055 break; 2056 default: 2057 std->err = USB_ERR_IOERROR; 2058 goto done; 2059 } 2060 goto tr_valid; 2061 2062 tr_handle_get_port_status: 2063 2064 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2065 2066 if (index != 1) { 2067 goto tr_stalled; 2068 } 2069 if (sc->sc_flags.status_vbus) { 2070 atmegadci_clocks_on(sc); 2071 atmegadci_pull_up(sc); 2072 } else { 2073 atmegadci_pull_down(sc); 2074 atmegadci_clocks_off(sc); 2075 } 2076 2077 /* Select FULL-speed and Device Side Mode */ 2078 2079 value = UPS_PORT_MODE_DEVICE; 2080 2081 if (sc->sc_flags.port_powered) { 2082 value |= UPS_PORT_POWER; 2083 } 2084 if (sc->sc_flags.port_enabled) { 2085 value |= UPS_PORT_ENABLED; 2086 } 2087 if (sc->sc_flags.status_vbus && 2088 sc->sc_flags.status_bus_reset) { 2089 value |= UPS_CURRENT_CONNECT_STATUS; 2090 } 2091 if (sc->sc_flags.status_suspend) { 2092 value |= UPS_SUSPEND; 2093 } 2094 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2095 2096 value = 0; 2097 2098 if (sc->sc_flags.change_connect) { 2099 value |= UPS_C_CONNECT_STATUS; 2100 } 2101 if (sc->sc_flags.change_suspend) { 2102 value |= UPS_C_SUSPEND; 2103 } 2104 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2105 std->len = sizeof(sc->sc_hub_temp.ps); 2106 goto tr_valid; 2107 2108 tr_handle_get_class_descriptor: 2109 if (value & 0xFF) { 2110 goto tr_stalled; 2111 } 2112 std->ptr = USB_ADD_BYTES(&atmegadci_hubd, 0); 2113 std->len = sizeof(atmegadci_hubd); 2114 goto tr_valid; 2115 2116 tr_stalled: 2117 std->err = USB_ERR_STALLED; 2118 tr_valid: 2119 done: 2120 return; 2121 } 2122 2123 static void 2124 atmegadci_root_ctrl_poll(struct atmegadci_softc *sc) 2125 { 2126 usb2_sw_transfer(&sc->sc_root_ctrl, 2127 &atmegadci_root_ctrl_done); 2128 } 2129 2130 struct usb2_pipe_methods atmegadci_root_ctrl_methods = 2131 { 2132 .open = atmegadci_root_ctrl_open, 2133 .close = atmegadci_root_ctrl_close, 2134 .enter = atmegadci_root_ctrl_enter, 2135 .start = atmegadci_root_ctrl_start, 2136 .enter_is_cancelable = 1, 2137 .start_is_cancelable = 0, 2138 }; 2139 2140 /*------------------------------------------------------------------------* 2141 * at91dci root interrupt support 2142 *------------------------------------------------------------------------*/ 2143 static void 2144 atmegadci_root_intr_open(struct usb2_xfer *xfer) 2145 { 2146 return; 2147 } 2148 2149 static void 2150 atmegadci_root_intr_close(struct usb2_xfer *xfer) 2151 { 2152 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2153 2154 if (sc->sc_root_intr.xfer == xfer) { 2155 sc->sc_root_intr.xfer = NULL; 2156 } 2157 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 2158 } 2159 2160 static void 2161 atmegadci_root_intr_enter(struct usb2_xfer *xfer) 2162 { 2163 return; 2164 } 2165 2166 static void 2167 atmegadci_root_intr_start(struct usb2_xfer *xfer) 2168 { 2169 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2170 2171 sc->sc_root_intr.xfer = xfer; 2172 } 2173 2174 struct usb2_pipe_methods atmegadci_root_intr_methods = 2175 { 2176 .open = atmegadci_root_intr_open, 2177 .close = atmegadci_root_intr_close, 2178 .enter = atmegadci_root_intr_enter, 2179 .start = atmegadci_root_intr_start, 2180 .enter_is_cancelable = 1, 2181 .start_is_cancelable = 1, 2182 }; 2183 2184 static void 2185 atmegadci_xfer_setup(struct usb2_setup_params *parm) 2186 { 2187 const struct usb2_hw_ep_profile *pf; 2188 struct atmegadci_softc *sc; 2189 struct usb2_xfer *xfer; 2190 void *last_obj; 2191 uint32_t ntd; 2192 uint32_t n; 2193 uint8_t ep_no; 2194 2195 sc = ATMEGA_BUS2SC(parm->udev->bus); 2196 xfer = parm->curr_xfer; 2197 2198 /* 2199 * NOTE: This driver does not use any of the parameters that 2200 * are computed from the following values. Just set some 2201 * reasonable dummies: 2202 */ 2203 parm->hc_max_packet_size = 0x500; 2204 parm->hc_max_packet_count = 1; 2205 parm->hc_max_frame_size = 0x500; 2206 2207 usb2_transfer_setup_sub(parm); 2208 2209 /* 2210 * compute maximum number of TDs 2211 */ 2212 if (parm->methods == &atmegadci_device_ctrl_methods) { 2213 2214 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2215 + 1 /* SYNC 2 */ ; 2216 2217 } else if (parm->methods == &atmegadci_device_bulk_methods) { 2218 2219 ntd = xfer->nframes + 1 /* SYNC */ ; 2220 2221 } else if (parm->methods == &atmegadci_device_intr_methods) { 2222 2223 ntd = xfer->nframes + 1 /* SYNC */ ; 2224 2225 } else if (parm->methods == &atmegadci_device_isoc_fs_methods) { 2226 2227 ntd = xfer->nframes + 1 /* SYNC */ ; 2228 2229 } else { 2230 2231 ntd = 0; 2232 } 2233 2234 /* 2235 * check if "usb2_transfer_setup_sub" set an error 2236 */ 2237 if (parm->err) { 2238 return; 2239 } 2240 /* 2241 * allocate transfer descriptors 2242 */ 2243 last_obj = NULL; 2244 2245 /* 2246 * get profile stuff 2247 */ 2248 if (ntd) { 2249 2250 ep_no = xfer->endpoint & UE_ADDR; 2251 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2252 2253 if (pf == NULL) { 2254 /* should not happen */ 2255 parm->err = USB_ERR_INVAL; 2256 return; 2257 } 2258 } else { 2259 ep_no = 0; 2260 pf = NULL; 2261 } 2262 2263 /* align data */ 2264 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2265 2266 for (n = 0; n != ntd; n++) { 2267 2268 struct atmegadci_td *td; 2269 2270 if (parm->buf) { 2271 2272 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2273 2274 /* init TD */ 2275 td->max_packet_size = xfer->max_packet_size; 2276 td->ep_no = ep_no; 2277 if (pf->support_multi_buffer) { 2278 td->support_multi_buffer = 1; 2279 } 2280 td->obj_next = last_obj; 2281 2282 last_obj = td; 2283 } 2284 parm->size[0] += sizeof(*td); 2285 } 2286 2287 xfer->td_start[0] = last_obj; 2288 } 2289 2290 static void 2291 atmegadci_xfer_unsetup(struct usb2_xfer *xfer) 2292 { 2293 return; 2294 } 2295 2296 static void 2297 atmegadci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2298 struct usb2_pipe *pipe) 2299 { 2300 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2301 2302 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2303 pipe, udev->address, 2304 edesc->bEndpointAddress, udev->flags.usb2_mode, 2305 sc->sc_rt_addr, udev->device_index); 2306 2307 if (udev->device_index == sc->sc_rt_addr) { 2308 2309 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2310 /* not supported */ 2311 return; 2312 } 2313 switch (edesc->bEndpointAddress) { 2314 case USB_CONTROL_ENDPOINT: 2315 pipe->methods = &atmegadci_root_ctrl_methods; 2316 break; 2317 case UE_DIR_IN | ATMEGA_INTR_ENDPT: 2318 pipe->methods = &atmegadci_root_intr_methods; 2319 break; 2320 default: 2321 /* do nothing */ 2322 break; 2323 } 2324 } else { 2325 2326 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2327 /* not supported */ 2328 return; 2329 } 2330 if (udev->speed != USB_SPEED_FULL) { 2331 /* not supported */ 2332 return; 2333 } 2334 switch (edesc->bmAttributes & UE_XFERTYPE) { 2335 case UE_CONTROL: 2336 pipe->methods = &atmegadci_device_ctrl_methods; 2337 break; 2338 case UE_INTERRUPT: 2339 pipe->methods = &atmegadci_device_intr_methods; 2340 break; 2341 case UE_ISOCHRONOUS: 2342 pipe->methods = &atmegadci_device_isoc_fs_methods; 2343 break; 2344 case UE_BULK: 2345 pipe->methods = &atmegadci_device_bulk_methods; 2346 break; 2347 default: 2348 /* do nothing */ 2349 break; 2350 } 2351 } 2352 } 2353 2354 struct usb2_bus_methods atmegadci_bus_methods = 2355 { 2356 .pipe_init = &atmegadci_pipe_init, 2357 .xfer_setup = &atmegadci_xfer_setup, 2358 .xfer_unsetup = &atmegadci_xfer_unsetup, 2359 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2360 .set_stall = &atmegadci_set_stall, 2361 .clear_stall = &atmegadci_clear_stall, 2362 .roothub_exec = &atmegadci_root_ctrl_task, 2363 }; 2364