1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 43 #define USB_DEBUG_VAR atmegadci_debug 44 45 #include <dev/usb/usb_core.h> 46 #include <dev/usb/usb_debug.h> 47 #include <dev/usb/usb_busdma.h> 48 #include <dev/usb/usb_process.h> 49 #include <dev/usb/usb_transfer.h> 50 #include <dev/usb/usb_device.h> 51 #include <dev/usb/usb_hub.h> 52 #include <dev/usb/usb_util.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/atmegadci.h> 57 58 #define ATMEGA_BUS2SC(bus) \ 59 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 60 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 61 62 #define ATMEGA_PC2SC(pc) \ 63 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 64 65 #if USB_DEBUG 66 static int atmegadci_debug = 0; 67 68 SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 69 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 70 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 71 #endif 72 73 #define ATMEGA_INTR_ENDPT 1 74 75 /* prototypes */ 76 77 struct usb_bus_methods atmegadci_bus_methods; 78 struct usb_pipe_methods atmegadci_device_non_isoc_methods; 79 struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 80 81 static atmegadci_cmd_t atmegadci_setup_rx; 82 static atmegadci_cmd_t atmegadci_data_rx; 83 static atmegadci_cmd_t atmegadci_data_tx; 84 static atmegadci_cmd_t atmegadci_data_tx_sync; 85 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 86 static void atmegadci_do_poll(struct usb_bus *); 87 static void atmegadci_standard_done(struct usb_xfer *); 88 static void atmegadci_root_intr(struct atmegadci_softc *sc); 89 90 /* 91 * Here is a list of what the chip supports: 92 */ 93 static const struct usb_hw_ep_profile 94 atmegadci_ep_profile[2] = { 95 96 [0] = { 97 .max_in_frame_size = 64, 98 .max_out_frame_size = 64, 99 .is_simplex = 1, 100 .support_control = 1, 101 }, 102 [1] = { 103 .max_in_frame_size = 64, 104 .max_out_frame_size = 64, 105 .is_simplex = 1, 106 .support_bulk = 1, 107 .support_interrupt = 1, 108 .support_isochronous = 1, 109 .support_in = 1, 110 .support_out = 1, 111 }, 112 }; 113 114 static void 115 atmegadci_get_hw_ep_profile(struct usb_device *udev, 116 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 117 { 118 if (ep_addr == 0) 119 *ppf = atmegadci_ep_profile; 120 else if (ep_addr < ATMEGA_EP_MAX) 121 *ppf = atmegadci_ep_profile + 1; 122 else 123 *ppf = NULL; 124 } 125 126 static void 127 atmegadci_clocks_on(struct atmegadci_softc *sc) 128 { 129 if (sc->sc_flags.clocks_off && 130 sc->sc_flags.port_powered) { 131 132 DPRINTFN(5, "\n"); 133 134 /* turn on clocks */ 135 (sc->sc_clocks_on) (&sc->sc_bus); 136 137 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 138 ATMEGA_USBCON_USBE | 139 ATMEGA_USBCON_OTGPADE | 140 ATMEGA_USBCON_VBUSTE); 141 142 sc->sc_flags.clocks_off = 0; 143 144 /* enable transceiver ? */ 145 } 146 } 147 148 static void 149 atmegadci_clocks_off(struct atmegadci_softc *sc) 150 { 151 if (!sc->sc_flags.clocks_off) { 152 153 DPRINTFN(5, "\n"); 154 155 /* disable Transceiver ? */ 156 157 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 158 ATMEGA_USBCON_USBE | 159 ATMEGA_USBCON_OTGPADE | 160 ATMEGA_USBCON_FRZCLK | 161 ATMEGA_USBCON_VBUSTE); 162 163 /* turn clocks off */ 164 (sc->sc_clocks_off) (&sc->sc_bus); 165 166 sc->sc_flags.clocks_off = 1; 167 } 168 } 169 170 static void 171 atmegadci_pull_up(struct atmegadci_softc *sc) 172 { 173 /* pullup D+, if possible */ 174 175 if (!sc->sc_flags.d_pulled_up && 176 sc->sc_flags.port_powered) { 177 sc->sc_flags.d_pulled_up = 1; 178 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 179 } 180 } 181 182 static void 183 atmegadci_pull_down(struct atmegadci_softc *sc) 184 { 185 /* pulldown D+, if possible */ 186 187 if (sc->sc_flags.d_pulled_up) { 188 sc->sc_flags.d_pulled_up = 0; 189 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 190 } 191 } 192 193 static void 194 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 195 { 196 uint8_t temp; 197 198 if (!sc->sc_flags.status_suspend) { 199 return; 200 } 201 202 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 203 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 204 205 /* wait 8 milliseconds */ 206 /* Wait for reset to complete. */ 207 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 208 209 /* hardware should have cleared RMWKUP bit */ 210 } 211 212 static void 213 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 214 { 215 DPRINTFN(5, "addr=%d\n", addr); 216 217 addr |= ATMEGA_UDADDR_ADDEN; 218 219 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 220 } 221 222 static uint8_t 223 atmegadci_setup_rx(struct atmegadci_td *td) 224 { 225 struct atmegadci_softc *sc; 226 struct usb_device_request req; 227 uint16_t count; 228 uint8_t temp; 229 230 /* get pointer to softc */ 231 sc = ATMEGA_PC2SC(td->pc); 232 233 /* select endpoint number */ 234 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 235 236 /* check endpoint status */ 237 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 238 239 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 240 241 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 242 goto not_complete; 243 } 244 /* clear did stall */ 245 td->did_stall = 0; 246 /* get the packet byte count */ 247 count = 248 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 249 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 250 251 /* mask away undefined bits */ 252 count &= 0x7FF; 253 254 /* verify data length */ 255 if (count != td->remainder) { 256 DPRINTFN(0, "Invalid SETUP packet " 257 "length, %d bytes\n", count); 258 goto not_complete; 259 } 260 if (count != sizeof(req)) { 261 DPRINTFN(0, "Unsupported SETUP packet " 262 "length, %d bytes\n", count); 263 goto not_complete; 264 } 265 /* receive data */ 266 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 267 (void *)&req, sizeof(req)); 268 269 /* copy data into real buffer */ 270 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 271 272 td->offset = sizeof(req); 273 td->remainder = 0; 274 275 /* sneak peek the set address */ 276 if ((req.bmRequestType == UT_WRITE_DEVICE) && 277 (req.bRequest == UR_SET_ADDRESS)) { 278 sc->sc_dv_addr = req.wValue[0] & 0x7F; 279 /* must write address before ZLP */ 280 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 281 } else { 282 sc->sc_dv_addr = 0xFF; 283 } 284 285 /* clear SETUP packet interrupt */ 286 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 287 return (0); /* complete */ 288 289 not_complete: 290 /* abort any ongoing transfer */ 291 if (!td->did_stall) { 292 DPRINTFN(5, "stalling\n"); 293 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 294 ATMEGA_UECONX_EPEN | 295 ATMEGA_UECONX_STALLRQ); 296 td->did_stall = 1; 297 } 298 if (temp & ATMEGA_UEINTX_RXSTPI) { 299 /* clear SETUP packet interrupt */ 300 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 301 } 302 /* we only want to know if there is a SETUP packet */ 303 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 304 return (1); /* not complete */ 305 } 306 307 static uint8_t 308 atmegadci_data_rx(struct atmegadci_td *td) 309 { 310 struct atmegadci_softc *sc; 311 struct usb_page_search buf_res; 312 uint16_t count; 313 uint8_t temp; 314 uint8_t to; 315 uint8_t got_short; 316 317 to = 3; /* don't loop forever! */ 318 got_short = 0; 319 320 /* get pointer to softc */ 321 sc = ATMEGA_PC2SC(td->pc); 322 323 /* select endpoint number */ 324 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 325 326 repeat: 327 /* check if any of the FIFO banks have data */ 328 /* check endpoint status */ 329 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 330 331 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 332 333 if (temp & ATMEGA_UEINTX_RXSTPI) { 334 if (td->remainder == 0) { 335 /* 336 * We are actually complete and have 337 * received the next SETUP 338 */ 339 DPRINTFN(5, "faking complete\n"); 340 return (0); /* complete */ 341 } 342 /* 343 * USB Host Aborted the transfer. 344 */ 345 td->error = 1; 346 return (0); /* complete */ 347 } 348 /* check status */ 349 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 350 ATMEGA_UEINTX_RXOUTI))) { 351 /* no data */ 352 goto not_complete; 353 } 354 /* get the packet byte count */ 355 count = 356 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 357 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 358 359 /* mask away undefined bits */ 360 count &= 0x7FF; 361 362 /* verify the packet byte count */ 363 if (count != td->max_packet_size) { 364 if (count < td->max_packet_size) { 365 /* we have a short packet */ 366 td->short_pkt = 1; 367 got_short = 1; 368 } else { 369 /* invalid USB packet */ 370 td->error = 1; 371 return (0); /* we are complete */ 372 } 373 } 374 /* verify the packet byte count */ 375 if (count > td->remainder) { 376 /* invalid USB packet */ 377 td->error = 1; 378 return (0); /* we are complete */ 379 } 380 while (count > 0) { 381 usbd_get_page(td->pc, td->offset, &buf_res); 382 383 /* get correct length */ 384 if (buf_res.length > count) { 385 buf_res.length = count; 386 } 387 /* receive data */ 388 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 389 buf_res.buffer, buf_res.length); 390 391 /* update counters */ 392 count -= buf_res.length; 393 td->offset += buf_res.length; 394 td->remainder -= buf_res.length; 395 } 396 397 /* clear OUT packet interrupt */ 398 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 399 400 /* release FIFO bank */ 401 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 402 403 /* check if we are complete */ 404 if ((td->remainder == 0) || got_short) { 405 if (td->short_pkt) { 406 /* we are complete */ 407 return (0); 408 } 409 /* else need to receive a zero length packet */ 410 } 411 if (--to) { 412 goto repeat; 413 } 414 not_complete: 415 /* we only want to know if there is a SETUP packet or OUT packet */ 416 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 417 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 418 return (1); /* not complete */ 419 } 420 421 static uint8_t 422 atmegadci_data_tx(struct atmegadci_td *td) 423 { 424 struct atmegadci_softc *sc; 425 struct usb_page_search buf_res; 426 uint16_t count; 427 uint8_t to; 428 uint8_t temp; 429 430 to = 3; /* don't loop forever! */ 431 432 /* get pointer to softc */ 433 sc = ATMEGA_PC2SC(td->pc); 434 435 /* select endpoint number */ 436 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 437 438 repeat: 439 440 /* check endpoint status */ 441 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 442 443 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 444 445 if (temp & ATMEGA_UEINTX_RXSTPI) { 446 /* 447 * The current transfer was aborted 448 * by the USB Host 449 */ 450 td->error = 1; 451 return (0); /* complete */ 452 } 453 454 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 455 if (temp & 3) { 456 /* cannot write any data - a bank is busy */ 457 goto not_complete; 458 } 459 460 count = td->max_packet_size; 461 if (td->remainder < count) { 462 /* we have a short packet */ 463 td->short_pkt = 1; 464 count = td->remainder; 465 } 466 while (count > 0) { 467 468 usbd_get_page(td->pc, td->offset, &buf_res); 469 470 /* get correct length */ 471 if (buf_res.length > count) { 472 buf_res.length = count; 473 } 474 /* transmit data */ 475 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 476 buf_res.buffer, buf_res.length); 477 478 /* update counters */ 479 count -= buf_res.length; 480 td->offset += buf_res.length; 481 td->remainder -= buf_res.length; 482 } 483 484 /* clear IN packet interrupt */ 485 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 486 487 /* allocate FIFO bank */ 488 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 489 490 /* check remainder */ 491 if (td->remainder == 0) { 492 if (td->short_pkt) { 493 return (0); /* complete */ 494 } 495 /* else we need to transmit a short packet */ 496 } 497 if (--to) { 498 goto repeat; 499 } 500 not_complete: 501 /* we only want to know if there is a SETUP packet or free IN packet */ 502 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 503 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 504 return (1); /* not complete */ 505 } 506 507 static uint8_t 508 atmegadci_data_tx_sync(struct atmegadci_td *td) 509 { 510 struct atmegadci_softc *sc; 511 uint8_t temp; 512 513 /* get pointer to softc */ 514 sc = ATMEGA_PC2SC(td->pc); 515 516 /* select endpoint number */ 517 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 518 519 /* check endpoint status */ 520 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 521 522 DPRINTFN(5, "temp=0x%02x\n", temp); 523 524 if (temp & ATMEGA_UEINTX_RXSTPI) { 525 DPRINTFN(5, "faking complete\n"); 526 /* Race condition */ 527 return (0); /* complete */ 528 } 529 /* 530 * The control endpoint has only got one bank, so if that bank 531 * is free the packet has been transferred! 532 */ 533 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 534 if (temp & 3) { 535 /* cannot write any data - a bank is busy */ 536 goto not_complete; 537 } 538 if (sc->sc_dv_addr != 0xFF) { 539 /* set new address */ 540 atmegadci_set_address(sc, sc->sc_dv_addr); 541 } 542 return (0); /* complete */ 543 544 not_complete: 545 /* we only want to know if there is a SETUP packet or free IN packet */ 546 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 547 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 548 return (1); /* not complete */ 549 } 550 551 static uint8_t 552 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 553 { 554 struct atmegadci_td *td; 555 556 DPRINTFN(9, "\n"); 557 558 td = xfer->td_transfer_cache; 559 while (1) { 560 if ((td->func) (td)) { 561 /* operation in progress */ 562 break; 563 } 564 if (((void *)td) == xfer->td_transfer_last) { 565 goto done; 566 } 567 if (td->error) { 568 goto done; 569 } else if (td->remainder > 0) { 570 /* 571 * We had a short transfer. If there is no alternate 572 * next, stop processing ! 573 */ 574 if (!td->alt_next) { 575 goto done; 576 } 577 } 578 /* 579 * Fetch the next transfer descriptor and transfer 580 * some flags to the next transfer descriptor 581 */ 582 td = td->obj_next; 583 xfer->td_transfer_cache = td; 584 } 585 return (1); /* not complete */ 586 587 done: 588 /* compute all actual lengths */ 589 590 atmegadci_standard_done(xfer); 591 return (0); /* complete */ 592 } 593 594 static void 595 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 596 { 597 struct usb_xfer *xfer; 598 599 repeat: 600 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 601 if (!atmegadci_xfer_do_fifo(xfer)) { 602 /* queue has been modified */ 603 goto repeat; 604 } 605 } 606 } 607 608 static void 609 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 610 { 611 DPRINTFN(5, "vbus = %u\n", is_on); 612 613 if (is_on) { 614 if (!sc->sc_flags.status_vbus) { 615 sc->sc_flags.status_vbus = 1; 616 617 /* complete root HUB interrupt endpoint */ 618 619 atmegadci_root_intr(sc); 620 } 621 } else { 622 if (sc->sc_flags.status_vbus) { 623 sc->sc_flags.status_vbus = 0; 624 sc->sc_flags.status_bus_reset = 0; 625 sc->sc_flags.status_suspend = 0; 626 sc->sc_flags.change_suspend = 0; 627 sc->sc_flags.change_connect = 1; 628 629 /* complete root HUB interrupt endpoint */ 630 631 atmegadci_root_intr(sc); 632 } 633 } 634 } 635 636 void 637 atmegadci_interrupt(struct atmegadci_softc *sc) 638 { 639 uint8_t status; 640 641 USB_BUS_LOCK(&sc->sc_bus); 642 643 /* read interrupt status */ 644 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 645 646 /* clear all set interrupts */ 647 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 648 649 DPRINTFN(14, "UDINT=0x%02x\n", status); 650 651 /* check for any bus state change interrupts */ 652 if (status & ATMEGA_UDINT_EORSTI) { 653 654 DPRINTFN(5, "end of reset\n"); 655 656 /* set correct state */ 657 sc->sc_flags.status_bus_reset = 1; 658 sc->sc_flags.status_suspend = 0; 659 sc->sc_flags.change_suspend = 0; 660 sc->sc_flags.change_connect = 1; 661 662 /* disable resume interrupt */ 663 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 664 ATMEGA_UDINT_SUSPE | 665 ATMEGA_UDINT_EORSTE); 666 667 /* complete root HUB interrupt endpoint */ 668 atmegadci_root_intr(sc); 669 } 670 /* 671 * If resume and suspend is set at the same time we interpret 672 * that like RESUME. Resume is set when there is at least 3 673 * milliseconds of inactivity on the USB BUS. 674 */ 675 if (status & ATMEGA_UDINT_WAKEUPI) { 676 677 DPRINTFN(5, "resume interrupt\n"); 678 679 if (sc->sc_flags.status_suspend) { 680 /* update status bits */ 681 sc->sc_flags.status_suspend = 0; 682 sc->sc_flags.change_suspend = 1; 683 684 /* disable resume interrupt */ 685 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 686 ATMEGA_UDINT_SUSPE | 687 ATMEGA_UDINT_EORSTE); 688 689 /* complete root HUB interrupt endpoint */ 690 atmegadci_root_intr(sc); 691 } 692 } else if (status & ATMEGA_UDINT_SUSPI) { 693 694 DPRINTFN(5, "suspend interrupt\n"); 695 696 if (!sc->sc_flags.status_suspend) { 697 /* update status bits */ 698 sc->sc_flags.status_suspend = 1; 699 sc->sc_flags.change_suspend = 1; 700 701 /* disable suspend interrupt */ 702 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 703 ATMEGA_UDINT_WAKEUPE | 704 ATMEGA_UDINT_EORSTE); 705 706 /* complete root HUB interrupt endpoint */ 707 atmegadci_root_intr(sc); 708 } 709 } 710 /* check VBUS */ 711 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 712 713 /* clear all set interrupts */ 714 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 715 716 if (status & ATMEGA_USBINT_VBUSTI) { 717 uint8_t temp; 718 719 DPRINTFN(5, "USBINT=0x%02x\n", status); 720 721 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 722 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 723 } 724 /* check for any endpoint interrupts */ 725 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 726 /* the hardware will clear the UEINT bits automatically */ 727 if (status) { 728 729 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 730 731 atmegadci_interrupt_poll(sc); 732 } 733 USB_BUS_UNLOCK(&sc->sc_bus); 734 } 735 736 static void 737 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 738 { 739 struct atmegadci_td *td; 740 741 /* get current Transfer Descriptor */ 742 td = temp->td_next; 743 temp->td = td; 744 745 /* prepare for next TD */ 746 temp->td_next = td->obj_next; 747 748 /* fill out the Transfer Descriptor */ 749 td->func = temp->func; 750 td->pc = temp->pc; 751 td->offset = temp->offset; 752 td->remainder = temp->len; 753 td->error = 0; 754 td->did_stall = temp->did_stall; 755 td->short_pkt = temp->short_pkt; 756 td->alt_next = temp->setup_alt_next; 757 } 758 759 static void 760 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 761 { 762 struct atmegadci_std_temp temp; 763 struct atmegadci_softc *sc; 764 struct atmegadci_td *td; 765 uint32_t x; 766 uint8_t ep_no; 767 uint8_t need_sync; 768 769 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 770 xfer->address, UE_GET_ADDR(xfer->endpointno), 771 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 772 773 temp.max_frame_size = xfer->max_frame_size; 774 775 td = xfer->td_start[0]; 776 xfer->td_transfer_first = td; 777 xfer->td_transfer_cache = td; 778 779 /* setup temp */ 780 781 temp.td = NULL; 782 temp.td_next = xfer->td_start[0]; 783 temp.offset = 0; 784 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 785 temp.did_stall = !xfer->flags_int.control_stall; 786 787 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 788 ep_no = (xfer->endpointno & UE_ADDR); 789 790 /* check if we should prepend a setup message */ 791 792 if (xfer->flags_int.control_xfr) { 793 if (xfer->flags_int.control_hdr) { 794 795 temp.func = &atmegadci_setup_rx; 796 temp.len = xfer->frlengths[0]; 797 temp.pc = xfer->frbuffers + 0; 798 temp.short_pkt = temp.len ? 1 : 0; 799 /* check for last frame */ 800 if (xfer->nframes == 1) { 801 /* no STATUS stage yet, SETUP is last */ 802 if (xfer->flags_int.control_act) 803 temp.setup_alt_next = 0; 804 } 805 806 atmegadci_setup_standard_chain_sub(&temp); 807 } 808 x = 1; 809 } else { 810 x = 0; 811 } 812 813 if (x != xfer->nframes) { 814 if (xfer->endpointno & UE_DIR_IN) { 815 temp.func = &atmegadci_data_tx; 816 need_sync = 1; 817 } else { 818 temp.func = &atmegadci_data_rx; 819 need_sync = 0; 820 } 821 822 /* setup "pc" pointer */ 823 temp.pc = xfer->frbuffers + x; 824 } else { 825 need_sync = 0; 826 } 827 while (x != xfer->nframes) { 828 829 /* DATA0 / DATA1 message */ 830 831 temp.len = xfer->frlengths[x]; 832 833 x++; 834 835 if (x == xfer->nframes) { 836 if (xfer->flags_int.control_xfr) { 837 if (xfer->flags_int.control_act) { 838 temp.setup_alt_next = 0; 839 } 840 } else { 841 temp.setup_alt_next = 0; 842 } 843 } 844 if (temp.len == 0) { 845 846 /* make sure that we send an USB packet */ 847 848 temp.short_pkt = 0; 849 850 } else { 851 852 /* regular data transfer */ 853 854 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 855 } 856 857 atmegadci_setup_standard_chain_sub(&temp); 858 859 if (xfer->flags_int.isochronous_xfr) { 860 temp.offset += temp.len; 861 } else { 862 /* get next Page Cache pointer */ 863 temp.pc = xfer->frbuffers + x; 864 } 865 } 866 867 if (xfer->flags_int.control_xfr) { 868 869 /* always setup a valid "pc" pointer for status and sync */ 870 temp.pc = xfer->frbuffers + 0; 871 temp.len = 0; 872 temp.short_pkt = 0; 873 temp.setup_alt_next = 0; 874 875 /* check if we need to sync */ 876 if (need_sync) { 877 /* we need a SYNC point after TX */ 878 temp.func = &atmegadci_data_tx_sync; 879 atmegadci_setup_standard_chain_sub(&temp); 880 } 881 882 /* check if we should append a status stage */ 883 if (!xfer->flags_int.control_act) { 884 885 /* 886 * Send a DATA1 message and invert the current 887 * endpoint direction. 888 */ 889 if (xfer->endpointno & UE_DIR_IN) { 890 temp.func = &atmegadci_data_rx; 891 need_sync = 0; 892 } else { 893 temp.func = &atmegadci_data_tx; 894 need_sync = 1; 895 } 896 897 atmegadci_setup_standard_chain_sub(&temp); 898 if (need_sync) { 899 /* we need a SYNC point after TX */ 900 temp.func = &atmegadci_data_tx_sync; 901 atmegadci_setup_standard_chain_sub(&temp); 902 } 903 } 904 } 905 /* must have at least one frame! */ 906 td = temp.td; 907 xfer->td_transfer_last = td; 908 } 909 910 static void 911 atmegadci_timeout(void *arg) 912 { 913 struct usb_xfer *xfer = arg; 914 915 DPRINTF("xfer=%p\n", xfer); 916 917 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 918 919 /* transfer is transferred */ 920 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 921 } 922 923 static void 924 atmegadci_start_standard_chain(struct usb_xfer *xfer) 925 { 926 DPRINTFN(9, "\n"); 927 928 /* poll one time - will turn on interrupts */ 929 if (atmegadci_xfer_do_fifo(xfer)) { 930 931 /* put transfer on interrupt queue */ 932 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 933 934 /* start timeout, if any */ 935 if (xfer->timeout != 0) { 936 usbd_transfer_timeout_ms(xfer, 937 &atmegadci_timeout, xfer->timeout); 938 } 939 } 940 } 941 942 static void 943 atmegadci_root_intr(struct atmegadci_softc *sc) 944 { 945 DPRINTFN(9, "\n"); 946 947 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 948 949 /* set port bit */ 950 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 951 952 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 953 sizeof(sc->sc_hub_idata)); 954 } 955 956 static usb_error_t 957 atmegadci_standard_done_sub(struct usb_xfer *xfer) 958 { 959 struct atmegadci_td *td; 960 uint32_t len; 961 uint8_t error; 962 963 DPRINTFN(9, "\n"); 964 965 td = xfer->td_transfer_cache; 966 967 do { 968 len = td->remainder; 969 970 if (xfer->aframes != xfer->nframes) { 971 /* 972 * Verify the length and subtract 973 * the remainder from "frlengths[]": 974 */ 975 if (len > xfer->frlengths[xfer->aframes]) { 976 td->error = 1; 977 } else { 978 xfer->frlengths[xfer->aframes] -= len; 979 } 980 } 981 /* Check for transfer error */ 982 if (td->error) { 983 /* the transfer is finished */ 984 error = 1; 985 td = NULL; 986 break; 987 } 988 /* Check for short transfer */ 989 if (len > 0) { 990 if (xfer->flags_int.short_frames_ok) { 991 /* follow alt next */ 992 if (td->alt_next) { 993 td = td->obj_next; 994 } else { 995 td = NULL; 996 } 997 } else { 998 /* the transfer is finished */ 999 td = NULL; 1000 } 1001 error = 0; 1002 break; 1003 } 1004 td = td->obj_next; 1005 1006 /* this USB frame is complete */ 1007 error = 0; 1008 break; 1009 1010 } while (0); 1011 1012 /* update transfer cache */ 1013 1014 xfer->td_transfer_cache = td; 1015 1016 return (error ? 1017 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1018 } 1019 1020 static void 1021 atmegadci_standard_done(struct usb_xfer *xfer) 1022 { 1023 usb_error_t err = 0; 1024 1025 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1026 xfer, xfer->endpoint); 1027 1028 /* reset scanner */ 1029 1030 xfer->td_transfer_cache = xfer->td_transfer_first; 1031 1032 if (xfer->flags_int.control_xfr) { 1033 1034 if (xfer->flags_int.control_hdr) { 1035 1036 err = atmegadci_standard_done_sub(xfer); 1037 } 1038 xfer->aframes = 1; 1039 1040 if (xfer->td_transfer_cache == NULL) { 1041 goto done; 1042 } 1043 } 1044 while (xfer->aframes != xfer->nframes) { 1045 1046 err = atmegadci_standard_done_sub(xfer); 1047 xfer->aframes++; 1048 1049 if (xfer->td_transfer_cache == NULL) { 1050 goto done; 1051 } 1052 } 1053 1054 if (xfer->flags_int.control_xfr && 1055 !xfer->flags_int.control_act) { 1056 1057 err = atmegadci_standard_done_sub(xfer); 1058 } 1059 done: 1060 atmegadci_device_done(xfer, err); 1061 } 1062 1063 /*------------------------------------------------------------------------* 1064 * atmegadci_device_done 1065 * 1066 * NOTE: this function can be called more than one time on the 1067 * same USB transfer! 1068 *------------------------------------------------------------------------*/ 1069 static void 1070 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1071 { 1072 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1073 uint8_t ep_no; 1074 1075 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1076 1077 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1078 xfer, xfer->endpoint, error); 1079 1080 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1081 ep_no = (xfer->endpointno & UE_ADDR); 1082 1083 /* select endpoint number */ 1084 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1085 1086 /* disable endpoint interrupt */ 1087 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1088 1089 DPRINTFN(15, "disabled interrupts!\n"); 1090 } 1091 /* dequeue transfer and start next transfer */ 1092 usbd_transfer_done(xfer, error); 1093 } 1094 1095 static void 1096 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1097 struct usb_endpoint *ep) 1098 { 1099 struct atmegadci_softc *sc; 1100 uint8_t ep_no; 1101 1102 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1103 1104 DPRINTFN(5, "endpoint=%p\n", ep); 1105 1106 if (xfer) { 1107 /* cancel any ongoing transfers */ 1108 atmegadci_device_done(xfer, USB_ERR_STALLED); 1109 } 1110 sc = ATMEGA_BUS2SC(udev->bus); 1111 /* get endpoint number */ 1112 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1113 /* select endpoint number */ 1114 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1115 /* set stall */ 1116 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1117 ATMEGA_UECONX_EPEN | 1118 ATMEGA_UECONX_STALLRQ); 1119 } 1120 1121 static void 1122 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1123 uint8_t ep_type, uint8_t ep_dir) 1124 { 1125 uint8_t temp; 1126 1127 if (ep_type == UE_CONTROL) { 1128 /* clearing stall is not needed */ 1129 return; 1130 } 1131 /* select endpoint number */ 1132 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1133 1134 /* set endpoint reset */ 1135 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1136 1137 /* clear endpoint reset */ 1138 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1139 1140 /* set stall */ 1141 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1142 ATMEGA_UECONX_EPEN | 1143 ATMEGA_UECONX_STALLRQ); 1144 1145 /* reset data toggle */ 1146 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1147 ATMEGA_UECONX_EPEN | 1148 ATMEGA_UECONX_RSTDT); 1149 1150 /* clear stall */ 1151 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1152 ATMEGA_UECONX_EPEN | 1153 ATMEGA_UECONX_STALLRQC); 1154 1155 do { 1156 if (ep_type == UE_BULK) { 1157 temp = ATMEGA_UECFG0X_EPTYPE2; 1158 } else if (ep_type == UE_INTERRUPT) { 1159 temp = ATMEGA_UECFG0X_EPTYPE3; 1160 } else { 1161 temp = ATMEGA_UECFG0X_EPTYPE1; 1162 } 1163 if (ep_dir & UE_DIR_IN) { 1164 temp |= ATMEGA_UECFG0X_EPDIR; 1165 } 1166 /* two banks, 64-bytes wMaxPacket */ 1167 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1168 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1169 ATMEGA_UECFG1X_ALLOC | 1170 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1171 ATMEGA_UECFG1X_EPSIZE(3)); 1172 1173 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1174 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1175 DPRINTFN(0, "Chip rejected configuration\n"); 1176 } 1177 } while (0); 1178 } 1179 1180 static void 1181 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1182 { 1183 struct atmegadci_softc *sc; 1184 struct usb_endpoint_descriptor *ed; 1185 1186 DPRINTFN(5, "endpoint=%p\n", ep); 1187 1188 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1189 1190 /* check mode */ 1191 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1192 /* not supported */ 1193 return; 1194 } 1195 /* get softc */ 1196 sc = ATMEGA_BUS2SC(udev->bus); 1197 1198 /* get endpoint descriptor */ 1199 ed = ep->edesc; 1200 1201 /* reset endpoint */ 1202 atmegadci_clear_stall_sub(sc, 1203 (ed->bEndpointAddress & UE_ADDR), 1204 (ed->bmAttributes & UE_XFERTYPE), 1205 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1206 } 1207 1208 usb_error_t 1209 atmegadci_init(struct atmegadci_softc *sc) 1210 { 1211 uint8_t n; 1212 1213 DPRINTF("start\n"); 1214 1215 /* set up the bus structure */ 1216 sc->sc_bus.usbrev = USB_REV_1_1; 1217 sc->sc_bus.methods = &atmegadci_bus_methods; 1218 1219 USB_BUS_LOCK(&sc->sc_bus); 1220 1221 /* make sure USB is enabled */ 1222 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1223 ATMEGA_USBCON_USBE | 1224 ATMEGA_USBCON_FRZCLK); 1225 1226 /* enable USB PAD regulator */ 1227 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1228 ATMEGA_UHWCON_UVREGE | 1229 ATMEGA_UHWCON_UIMOD); 1230 1231 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1232 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1233 1234 /* wait for PLL to lock */ 1235 for (n = 0; n != 20; n++) { 1236 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1237 break; 1238 /* wait a little bit for PLL to start */ 1239 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1240 } 1241 1242 /* make sure USB is enabled */ 1243 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1244 ATMEGA_USBCON_USBE | 1245 ATMEGA_USBCON_OTGPADE | 1246 ATMEGA_USBCON_VBUSTE); 1247 1248 /* turn on clocks */ 1249 (sc->sc_clocks_on) (&sc->sc_bus); 1250 1251 /* make sure device is re-enumerated */ 1252 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1253 1254 /* wait a little for things to stabilise */ 1255 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1256 1257 /* enable interrupts */ 1258 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1259 ATMEGA_UDINT_SUSPE | 1260 ATMEGA_UDINT_EORSTE); 1261 1262 /* reset all endpoints */ 1263 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1264 (1 << ATMEGA_EP_MAX) - 1); 1265 1266 /* disable reset */ 1267 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1268 1269 /* disable all endpoints */ 1270 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1271 1272 /* select endpoint */ 1273 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1274 1275 /* disable endpoint interrupt */ 1276 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1277 1278 /* disable endpoint */ 1279 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1280 } 1281 1282 /* turn off clocks */ 1283 1284 atmegadci_clocks_off(sc); 1285 1286 /* read initial VBUS state */ 1287 1288 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1289 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1290 1291 USB_BUS_UNLOCK(&sc->sc_bus); 1292 1293 /* catch any lost interrupts */ 1294 1295 atmegadci_do_poll(&sc->sc_bus); 1296 1297 return (0); /* success */ 1298 } 1299 1300 void 1301 atmegadci_uninit(struct atmegadci_softc *sc) 1302 { 1303 USB_BUS_LOCK(&sc->sc_bus); 1304 1305 /* turn on clocks */ 1306 (sc->sc_clocks_on) (&sc->sc_bus); 1307 1308 /* disable interrupts */ 1309 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1310 1311 /* reset all endpoints */ 1312 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1313 (1 << ATMEGA_EP_MAX) - 1); 1314 1315 /* disable reset */ 1316 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1317 1318 sc->sc_flags.port_powered = 0; 1319 sc->sc_flags.status_vbus = 0; 1320 sc->sc_flags.status_bus_reset = 0; 1321 sc->sc_flags.status_suspend = 0; 1322 sc->sc_flags.change_suspend = 0; 1323 sc->sc_flags.change_connect = 1; 1324 1325 atmegadci_pull_down(sc); 1326 atmegadci_clocks_off(sc); 1327 1328 /* disable USB PAD regulator */ 1329 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1330 1331 USB_BUS_UNLOCK(&sc->sc_bus); 1332 } 1333 1334 void 1335 atmegadci_suspend(struct atmegadci_softc *sc) 1336 { 1337 return; 1338 } 1339 1340 void 1341 atmegadci_resume(struct atmegadci_softc *sc) 1342 { 1343 return; 1344 } 1345 1346 static void 1347 atmegadci_do_poll(struct usb_bus *bus) 1348 { 1349 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1350 1351 USB_BUS_LOCK(&sc->sc_bus); 1352 atmegadci_interrupt_poll(sc); 1353 USB_BUS_UNLOCK(&sc->sc_bus); 1354 } 1355 1356 /*------------------------------------------------------------------------* 1357 * at91dci bulk support 1358 * at91dci control support 1359 * at91dci interrupt support 1360 *------------------------------------------------------------------------*/ 1361 static void 1362 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1363 { 1364 return; 1365 } 1366 1367 static void 1368 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1369 { 1370 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1371 } 1372 1373 static void 1374 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1375 { 1376 return; 1377 } 1378 1379 static void 1380 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1381 { 1382 /* setup TDs */ 1383 atmegadci_setup_standard_chain(xfer); 1384 atmegadci_start_standard_chain(xfer); 1385 } 1386 1387 struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1388 { 1389 .open = atmegadci_device_non_isoc_open, 1390 .close = atmegadci_device_non_isoc_close, 1391 .enter = atmegadci_device_non_isoc_enter, 1392 .start = atmegadci_device_non_isoc_start, 1393 }; 1394 1395 /*------------------------------------------------------------------------* 1396 * at91dci full speed isochronous support 1397 *------------------------------------------------------------------------*/ 1398 static void 1399 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1400 { 1401 return; 1402 } 1403 1404 static void 1405 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1406 { 1407 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1408 } 1409 1410 static void 1411 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1412 { 1413 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1414 uint32_t temp; 1415 uint32_t nframes; 1416 1417 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1418 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1419 1420 /* get the current frame index */ 1421 1422 nframes = 1423 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1424 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1425 1426 nframes &= ATMEGA_FRAME_MASK; 1427 1428 /* 1429 * check if the frame index is within the window where the frames 1430 * will be inserted 1431 */ 1432 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK; 1433 1434 if ((xfer->endpoint->is_synced == 0) || 1435 (temp < xfer->nframes)) { 1436 /* 1437 * If there is data underflow or the pipe queue is 1438 * empty we schedule the transfer a few frames ahead 1439 * of the current frame position. Else two isochronous 1440 * transfers might overlap. 1441 */ 1442 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1443 xfer->endpoint->is_synced = 1; 1444 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1445 } 1446 /* 1447 * compute how many milliseconds the insertion is ahead of the 1448 * current frame position: 1449 */ 1450 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1451 1452 /* 1453 * pre-compute when the isochronous transfer will be finished: 1454 */ 1455 xfer->isoc_time_complete = 1456 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1457 xfer->nframes; 1458 1459 /* compute frame number for next insertion */ 1460 xfer->endpoint->isoc_next += xfer->nframes; 1461 1462 /* setup TDs */ 1463 atmegadci_setup_standard_chain(xfer); 1464 } 1465 1466 static void 1467 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1468 { 1469 /* start TD chain */ 1470 atmegadci_start_standard_chain(xfer); 1471 } 1472 1473 struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1474 { 1475 .open = atmegadci_device_isoc_fs_open, 1476 .close = atmegadci_device_isoc_fs_close, 1477 .enter = atmegadci_device_isoc_fs_enter, 1478 .start = atmegadci_device_isoc_fs_start, 1479 }; 1480 1481 /*------------------------------------------------------------------------* 1482 * at91dci root control support 1483 *------------------------------------------------------------------------* 1484 * Simulate a hardware HUB by handling all the necessary requests. 1485 *------------------------------------------------------------------------*/ 1486 1487 static const struct usb_device_descriptor atmegadci_devd = { 1488 .bLength = sizeof(struct usb_device_descriptor), 1489 .bDescriptorType = UDESC_DEVICE, 1490 .bcdUSB = {0x00, 0x02}, 1491 .bDeviceClass = UDCLASS_HUB, 1492 .bDeviceSubClass = UDSUBCLASS_HUB, 1493 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1494 .bMaxPacketSize = 64, 1495 .bcdDevice = {0x00, 0x01}, 1496 .iManufacturer = 1, 1497 .iProduct = 2, 1498 .bNumConfigurations = 1, 1499 }; 1500 1501 static const struct usb_device_qualifier atmegadci_odevd = { 1502 .bLength = sizeof(struct usb_device_qualifier), 1503 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1504 .bcdUSB = {0x00, 0x02}, 1505 .bDeviceClass = UDCLASS_HUB, 1506 .bDeviceSubClass = UDSUBCLASS_HUB, 1507 .bDeviceProtocol = UDPROTO_FSHUB, 1508 .bMaxPacketSize0 = 0, 1509 .bNumConfigurations = 0, 1510 }; 1511 1512 static const struct atmegadci_config_desc atmegadci_confd = { 1513 .confd = { 1514 .bLength = sizeof(struct usb_config_descriptor), 1515 .bDescriptorType = UDESC_CONFIG, 1516 .wTotalLength[0] = sizeof(atmegadci_confd), 1517 .bNumInterface = 1, 1518 .bConfigurationValue = 1, 1519 .iConfiguration = 0, 1520 .bmAttributes = UC_SELF_POWERED, 1521 .bMaxPower = 0, 1522 }, 1523 .ifcd = { 1524 .bLength = sizeof(struct usb_interface_descriptor), 1525 .bDescriptorType = UDESC_INTERFACE, 1526 .bNumEndpoints = 1, 1527 .bInterfaceClass = UICLASS_HUB, 1528 .bInterfaceSubClass = UISUBCLASS_HUB, 1529 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1530 }, 1531 .endpd = { 1532 .bLength = sizeof(struct usb_endpoint_descriptor), 1533 .bDescriptorType = UDESC_ENDPOINT, 1534 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1535 .bmAttributes = UE_INTERRUPT, 1536 .wMaxPacketSize[0] = 8, 1537 .bInterval = 255, 1538 }, 1539 }; 1540 1541 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1542 .bDescLength = sizeof(atmegadci_hubd), 1543 .bDescriptorType = UDESC_HUB, 1544 .bNbrPorts = 1, 1545 .wHubCharacteristics[0] = 1546 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1547 .wHubCharacteristics[1] = 1548 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1549 .bPwrOn2PwrGood = 50, 1550 .bHubContrCurrent = 0, 1551 .DeviceRemovable = {0}, /* port is removable */ 1552 }; 1553 1554 #define STRING_LANG \ 1555 0x09, 0x04, /* American English */ 1556 1557 #define STRING_VENDOR \ 1558 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1559 1560 #define STRING_PRODUCT \ 1561 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1562 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1563 'U', 0, 'B', 0, 1564 1565 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1566 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1567 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1568 1569 static usb_error_t 1570 atmegadci_roothub_exec(struct usb_device *udev, 1571 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1572 { 1573 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1574 const void *ptr; 1575 uint16_t len; 1576 uint16_t value; 1577 uint16_t index; 1578 uint8_t temp; 1579 usb_error_t err; 1580 1581 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1582 1583 /* buffer reset */ 1584 ptr = (const void *)&sc->sc_hub_temp; 1585 len = 0; 1586 err = 0; 1587 1588 value = UGETW(req->wValue); 1589 index = UGETW(req->wIndex); 1590 1591 /* demultiplex the control request */ 1592 1593 switch (req->bmRequestType) { 1594 case UT_READ_DEVICE: 1595 switch (req->bRequest) { 1596 case UR_GET_DESCRIPTOR: 1597 goto tr_handle_get_descriptor; 1598 case UR_GET_CONFIG: 1599 goto tr_handle_get_config; 1600 case UR_GET_STATUS: 1601 goto tr_handle_get_status; 1602 default: 1603 goto tr_stalled; 1604 } 1605 break; 1606 1607 case UT_WRITE_DEVICE: 1608 switch (req->bRequest) { 1609 case UR_SET_ADDRESS: 1610 goto tr_handle_set_address; 1611 case UR_SET_CONFIG: 1612 goto tr_handle_set_config; 1613 case UR_CLEAR_FEATURE: 1614 goto tr_valid; /* nop */ 1615 case UR_SET_DESCRIPTOR: 1616 goto tr_valid; /* nop */ 1617 case UR_SET_FEATURE: 1618 default: 1619 goto tr_stalled; 1620 } 1621 break; 1622 1623 case UT_WRITE_ENDPOINT: 1624 switch (req->bRequest) { 1625 case UR_CLEAR_FEATURE: 1626 switch (UGETW(req->wValue)) { 1627 case UF_ENDPOINT_HALT: 1628 goto tr_handle_clear_halt; 1629 case UF_DEVICE_REMOTE_WAKEUP: 1630 goto tr_handle_clear_wakeup; 1631 default: 1632 goto tr_stalled; 1633 } 1634 break; 1635 case UR_SET_FEATURE: 1636 switch (UGETW(req->wValue)) { 1637 case UF_ENDPOINT_HALT: 1638 goto tr_handle_set_halt; 1639 case UF_DEVICE_REMOTE_WAKEUP: 1640 goto tr_handle_set_wakeup; 1641 default: 1642 goto tr_stalled; 1643 } 1644 break; 1645 case UR_SYNCH_FRAME: 1646 goto tr_valid; /* nop */ 1647 default: 1648 goto tr_stalled; 1649 } 1650 break; 1651 1652 case UT_READ_ENDPOINT: 1653 switch (req->bRequest) { 1654 case UR_GET_STATUS: 1655 goto tr_handle_get_ep_status; 1656 default: 1657 goto tr_stalled; 1658 } 1659 break; 1660 1661 case UT_WRITE_INTERFACE: 1662 switch (req->bRequest) { 1663 case UR_SET_INTERFACE: 1664 goto tr_handle_set_interface; 1665 case UR_CLEAR_FEATURE: 1666 goto tr_valid; /* nop */ 1667 case UR_SET_FEATURE: 1668 default: 1669 goto tr_stalled; 1670 } 1671 break; 1672 1673 case UT_READ_INTERFACE: 1674 switch (req->bRequest) { 1675 case UR_GET_INTERFACE: 1676 goto tr_handle_get_interface; 1677 case UR_GET_STATUS: 1678 goto tr_handle_get_iface_status; 1679 default: 1680 goto tr_stalled; 1681 } 1682 break; 1683 1684 case UT_WRITE_CLASS_INTERFACE: 1685 case UT_WRITE_VENDOR_INTERFACE: 1686 /* XXX forward */ 1687 break; 1688 1689 case UT_READ_CLASS_INTERFACE: 1690 case UT_READ_VENDOR_INTERFACE: 1691 /* XXX forward */ 1692 break; 1693 1694 case UT_WRITE_CLASS_DEVICE: 1695 switch (req->bRequest) { 1696 case UR_CLEAR_FEATURE: 1697 goto tr_valid; 1698 case UR_SET_DESCRIPTOR: 1699 case UR_SET_FEATURE: 1700 break; 1701 default: 1702 goto tr_stalled; 1703 } 1704 break; 1705 1706 case UT_WRITE_CLASS_OTHER: 1707 switch (req->bRequest) { 1708 case UR_CLEAR_FEATURE: 1709 goto tr_handle_clear_port_feature; 1710 case UR_SET_FEATURE: 1711 goto tr_handle_set_port_feature; 1712 case UR_CLEAR_TT_BUFFER: 1713 case UR_RESET_TT: 1714 case UR_STOP_TT: 1715 goto tr_valid; 1716 1717 default: 1718 goto tr_stalled; 1719 } 1720 break; 1721 1722 case UT_READ_CLASS_OTHER: 1723 switch (req->bRequest) { 1724 case UR_GET_TT_STATE: 1725 goto tr_handle_get_tt_state; 1726 case UR_GET_STATUS: 1727 goto tr_handle_get_port_status; 1728 default: 1729 goto tr_stalled; 1730 } 1731 break; 1732 1733 case UT_READ_CLASS_DEVICE: 1734 switch (req->bRequest) { 1735 case UR_GET_DESCRIPTOR: 1736 goto tr_handle_get_class_descriptor; 1737 case UR_GET_STATUS: 1738 goto tr_handle_get_class_status; 1739 1740 default: 1741 goto tr_stalled; 1742 } 1743 break; 1744 default: 1745 goto tr_stalled; 1746 } 1747 goto tr_valid; 1748 1749 tr_handle_get_descriptor: 1750 switch (value >> 8) { 1751 case UDESC_DEVICE: 1752 if (value & 0xff) { 1753 goto tr_stalled; 1754 } 1755 len = sizeof(atmegadci_devd); 1756 ptr = (const void *)&atmegadci_devd; 1757 goto tr_valid; 1758 case UDESC_CONFIG: 1759 if (value & 0xff) { 1760 goto tr_stalled; 1761 } 1762 len = sizeof(atmegadci_confd); 1763 ptr = (const void *)&atmegadci_confd; 1764 goto tr_valid; 1765 case UDESC_STRING: 1766 switch (value & 0xff) { 1767 case 0: /* Language table */ 1768 len = sizeof(atmegadci_langtab); 1769 ptr = (const void *)&atmegadci_langtab; 1770 goto tr_valid; 1771 1772 case 1: /* Vendor */ 1773 len = sizeof(atmegadci_vendor); 1774 ptr = (const void *)&atmegadci_vendor; 1775 goto tr_valid; 1776 1777 case 2: /* Product */ 1778 len = sizeof(atmegadci_product); 1779 ptr = (const void *)&atmegadci_product; 1780 goto tr_valid; 1781 default: 1782 break; 1783 } 1784 break; 1785 default: 1786 goto tr_stalled; 1787 } 1788 goto tr_stalled; 1789 1790 tr_handle_get_config: 1791 len = 1; 1792 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1793 goto tr_valid; 1794 1795 tr_handle_get_status: 1796 len = 2; 1797 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1798 goto tr_valid; 1799 1800 tr_handle_set_address: 1801 if (value & 0xFF00) { 1802 goto tr_stalled; 1803 } 1804 sc->sc_rt_addr = value; 1805 goto tr_valid; 1806 1807 tr_handle_set_config: 1808 if (value >= 2) { 1809 goto tr_stalled; 1810 } 1811 sc->sc_conf = value; 1812 goto tr_valid; 1813 1814 tr_handle_get_interface: 1815 len = 1; 1816 sc->sc_hub_temp.wValue[0] = 0; 1817 goto tr_valid; 1818 1819 tr_handle_get_tt_state: 1820 tr_handle_get_class_status: 1821 tr_handle_get_iface_status: 1822 tr_handle_get_ep_status: 1823 len = 2; 1824 USETW(sc->sc_hub_temp.wValue, 0); 1825 goto tr_valid; 1826 1827 tr_handle_set_halt: 1828 tr_handle_set_interface: 1829 tr_handle_set_wakeup: 1830 tr_handle_clear_wakeup: 1831 tr_handle_clear_halt: 1832 goto tr_valid; 1833 1834 tr_handle_clear_port_feature: 1835 if (index != 1) { 1836 goto tr_stalled; 1837 } 1838 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1839 1840 switch (value) { 1841 case UHF_PORT_SUSPEND: 1842 atmegadci_wakeup_peer(sc); 1843 break; 1844 1845 case UHF_PORT_ENABLE: 1846 sc->sc_flags.port_enabled = 0; 1847 break; 1848 1849 case UHF_PORT_TEST: 1850 case UHF_PORT_INDICATOR: 1851 case UHF_C_PORT_ENABLE: 1852 case UHF_C_PORT_OVER_CURRENT: 1853 case UHF_C_PORT_RESET: 1854 /* nops */ 1855 break; 1856 case UHF_PORT_POWER: 1857 sc->sc_flags.port_powered = 0; 1858 atmegadci_pull_down(sc); 1859 atmegadci_clocks_off(sc); 1860 break; 1861 case UHF_C_PORT_CONNECTION: 1862 /* clear connect change flag */ 1863 sc->sc_flags.change_connect = 0; 1864 1865 if (!sc->sc_flags.status_bus_reset) { 1866 /* we are not connected */ 1867 break; 1868 } 1869 1870 /* configure the control endpoint */ 1871 1872 /* select endpoint number */ 1873 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1874 1875 /* set endpoint reset */ 1876 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1877 1878 /* clear endpoint reset */ 1879 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1880 1881 /* enable and stall endpoint */ 1882 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1883 ATMEGA_UECONX_EPEN | 1884 ATMEGA_UECONX_STALLRQ); 1885 1886 /* one bank, 64-bytes wMaxPacket */ 1887 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1888 ATMEGA_UECFG0X_EPTYPE0); 1889 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1890 ATMEGA_UECFG1X_ALLOC | 1891 ATMEGA_UECFG1X_EPBK0 | 1892 ATMEGA_UECFG1X_EPSIZE(3)); 1893 1894 /* check valid config */ 1895 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1896 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1897 DPRINTFN(0, "Chip rejected EP0 configuration\n"); 1898 } 1899 break; 1900 case UHF_C_PORT_SUSPEND: 1901 sc->sc_flags.change_suspend = 0; 1902 break; 1903 default: 1904 err = USB_ERR_IOERROR; 1905 goto done; 1906 } 1907 goto tr_valid; 1908 1909 tr_handle_set_port_feature: 1910 if (index != 1) { 1911 goto tr_stalled; 1912 } 1913 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1914 1915 switch (value) { 1916 case UHF_PORT_ENABLE: 1917 sc->sc_flags.port_enabled = 1; 1918 break; 1919 case UHF_PORT_SUSPEND: 1920 case UHF_PORT_RESET: 1921 case UHF_PORT_TEST: 1922 case UHF_PORT_INDICATOR: 1923 /* nops */ 1924 break; 1925 case UHF_PORT_POWER: 1926 sc->sc_flags.port_powered = 1; 1927 break; 1928 default: 1929 err = USB_ERR_IOERROR; 1930 goto done; 1931 } 1932 goto tr_valid; 1933 1934 tr_handle_get_port_status: 1935 1936 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1937 1938 if (index != 1) { 1939 goto tr_stalled; 1940 } 1941 if (sc->sc_flags.status_vbus) { 1942 atmegadci_clocks_on(sc); 1943 atmegadci_pull_up(sc); 1944 } else { 1945 atmegadci_pull_down(sc); 1946 atmegadci_clocks_off(sc); 1947 } 1948 1949 /* Select FULL-speed and Device Side Mode */ 1950 1951 value = UPS_PORT_MODE_DEVICE; 1952 1953 if (sc->sc_flags.port_powered) { 1954 value |= UPS_PORT_POWER; 1955 } 1956 if (sc->sc_flags.port_enabled) { 1957 value |= UPS_PORT_ENABLED; 1958 } 1959 if (sc->sc_flags.status_vbus && 1960 sc->sc_flags.status_bus_reset) { 1961 value |= UPS_CURRENT_CONNECT_STATUS; 1962 } 1963 if (sc->sc_flags.status_suspend) { 1964 value |= UPS_SUSPEND; 1965 } 1966 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1967 1968 value = 0; 1969 1970 if (sc->sc_flags.change_connect) { 1971 value |= UPS_C_CONNECT_STATUS; 1972 } 1973 if (sc->sc_flags.change_suspend) { 1974 value |= UPS_C_SUSPEND; 1975 } 1976 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1977 len = sizeof(sc->sc_hub_temp.ps); 1978 goto tr_valid; 1979 1980 tr_handle_get_class_descriptor: 1981 if (value & 0xFF) { 1982 goto tr_stalled; 1983 } 1984 ptr = (const void *)&atmegadci_hubd; 1985 len = sizeof(atmegadci_hubd); 1986 goto tr_valid; 1987 1988 tr_stalled: 1989 err = USB_ERR_STALLED; 1990 tr_valid: 1991 done: 1992 *plength = len; 1993 *pptr = ptr; 1994 return (err); 1995 } 1996 1997 static void 1998 atmegadci_xfer_setup(struct usb_setup_params *parm) 1999 { 2000 const struct usb_hw_ep_profile *pf; 2001 struct atmegadci_softc *sc; 2002 struct usb_xfer *xfer; 2003 void *last_obj; 2004 uint32_t ntd; 2005 uint32_t n; 2006 uint8_t ep_no; 2007 2008 sc = ATMEGA_BUS2SC(parm->udev->bus); 2009 xfer = parm->curr_xfer; 2010 2011 /* 2012 * NOTE: This driver does not use any of the parameters that 2013 * are computed from the following values. Just set some 2014 * reasonable dummies: 2015 */ 2016 parm->hc_max_packet_size = 0x500; 2017 parm->hc_max_packet_count = 1; 2018 parm->hc_max_frame_size = 0x500; 2019 2020 usbd_transfer_setup_sub(parm); 2021 2022 /* 2023 * compute maximum number of TDs 2024 */ 2025 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2026 2027 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2028 + 1 /* SYNC 2 */ ; 2029 } else { 2030 2031 ntd = xfer->nframes + 1 /* SYNC */ ; 2032 } 2033 2034 /* 2035 * check if "usbd_transfer_setup_sub" set an error 2036 */ 2037 if (parm->err) 2038 return; 2039 2040 /* 2041 * allocate transfer descriptors 2042 */ 2043 last_obj = NULL; 2044 2045 /* 2046 * get profile stuff 2047 */ 2048 ep_no = xfer->endpointno & UE_ADDR; 2049 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2050 2051 if (pf == NULL) { 2052 /* should not happen */ 2053 parm->err = USB_ERR_INVAL; 2054 return; 2055 } 2056 2057 /* align data */ 2058 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2059 2060 for (n = 0; n != ntd; n++) { 2061 2062 struct atmegadci_td *td; 2063 2064 if (parm->buf) { 2065 2066 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2067 2068 /* init TD */ 2069 td->max_packet_size = xfer->max_packet_size; 2070 td->ep_no = ep_no; 2071 if (pf->support_multi_buffer) { 2072 td->support_multi_buffer = 1; 2073 } 2074 td->obj_next = last_obj; 2075 2076 last_obj = td; 2077 } 2078 parm->size[0] += sizeof(*td); 2079 } 2080 2081 xfer->td_start[0] = last_obj; 2082 } 2083 2084 static void 2085 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2086 { 2087 return; 2088 } 2089 2090 static void 2091 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2092 struct usb_endpoint *ep) 2093 { 2094 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2095 2096 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2097 ep, udev->address, 2098 edesc->bEndpointAddress, udev->flags.usb_mode, 2099 sc->sc_rt_addr, udev->device_index); 2100 2101 if (udev->device_index != sc->sc_rt_addr) { 2102 2103 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2104 /* not supported */ 2105 return; 2106 } 2107 if (udev->speed != USB_SPEED_FULL) { 2108 /* not supported */ 2109 return; 2110 } 2111 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2112 ep->methods = &atmegadci_device_isoc_fs_methods; 2113 else 2114 ep->methods = &atmegadci_device_non_isoc_methods; 2115 } 2116 } 2117 2118 struct usb_bus_methods atmegadci_bus_methods = 2119 { 2120 .endpoint_init = &atmegadci_ep_init, 2121 .xfer_setup = &atmegadci_xfer_setup, 2122 .xfer_unsetup = &atmegadci_xfer_unsetup, 2123 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2124 .set_stall = &atmegadci_set_stall, 2125 .clear_stall = &atmegadci_clear_stall, 2126 .roothub_exec = &atmegadci_roothub_exec, 2127 }; 2128