1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the ATMEGA series USB OTG Controller. This 30 * driver currently only supports the DCI mode of the USB hardware. 31 */ 32 33 /* 34 * NOTE: When the chip detects BUS-reset it will also reset the 35 * endpoints, Function-address and more. 36 */ 37 38 #ifdef USB_GLOBAL_INCLUDE_FILE 39 #include USB_GLOBAL_INCLUDE_FILE 40 #else 41 #include <sys/stdint.h> 42 #include <sys/stddef.h> 43 #include <sys/param.h> 44 #include <sys/queue.h> 45 #include <sys/types.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/bus.h> 49 #include <sys/module.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/sysctl.h> 54 #include <sys/sx.h> 55 #include <sys/unistd.h> 56 #include <sys/callout.h> 57 #include <sys/malloc.h> 58 #include <sys/priv.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 63 #define USB_DEBUG_VAR atmegadci_debug 64 65 #include <dev/usb/usb_core.h> 66 #include <dev/usb/usb_debug.h> 67 #include <dev/usb/usb_busdma.h> 68 #include <dev/usb/usb_process.h> 69 #include <dev/usb/usb_transfer.h> 70 #include <dev/usb/usb_device.h> 71 #include <dev/usb/usb_hub.h> 72 #include <dev/usb/usb_util.h> 73 74 #include <dev/usb/usb_controller.h> 75 #include <dev/usb/usb_bus.h> 76 #endif /* USB_GLOBAL_INCLUDE_FILE */ 77 78 #include <dev/usb/controller/atmegadci.h> 79 80 #define ATMEGA_BUS2SC(bus) \ 81 __containerof(bus, struct atmegadci_softc, sc_bus) 82 83 #define ATMEGA_PC2SC(pc) \ 84 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 85 86 #ifdef USB_DEBUG 87 static int atmegadci_debug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 90 "USB ATMEGA DCI"); 91 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN, 92 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 93 #endif 94 95 #define ATMEGA_INTR_ENDPT 1 96 97 /* prototypes */ 98 99 static const struct usb_bus_methods atmegadci_bus_methods; 100 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods; 101 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 102 103 static atmegadci_cmd_t atmegadci_setup_rx; 104 static atmegadci_cmd_t atmegadci_data_rx; 105 static atmegadci_cmd_t atmegadci_data_tx; 106 static atmegadci_cmd_t atmegadci_data_tx_sync; 107 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 108 static void atmegadci_do_poll(struct usb_bus *); 109 static void atmegadci_standard_done(struct usb_xfer *); 110 static void atmegadci_root_intr(struct atmegadci_softc *sc); 111 112 /* 113 * Here is a list of what the chip supports: 114 */ 115 static const struct usb_hw_ep_profile 116 atmegadci_ep_profile[2] = { 117 [0] = { 118 .max_in_frame_size = 64, 119 .max_out_frame_size = 64, 120 .is_simplex = 1, 121 .support_control = 1, 122 }, 123 [1] = { 124 .max_in_frame_size = 64, 125 .max_out_frame_size = 64, 126 .is_simplex = 1, 127 .support_bulk = 1, 128 .support_interrupt = 1, 129 .support_isochronous = 1, 130 .support_in = 1, 131 .support_out = 1, 132 }, 133 }; 134 135 static void 136 atmegadci_get_hw_ep_profile(struct usb_device *udev, 137 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 138 { 139 if (ep_addr == 0) 140 *ppf = atmegadci_ep_profile; 141 else if (ep_addr < ATMEGA_EP_MAX) 142 *ppf = atmegadci_ep_profile + 1; 143 else 144 *ppf = NULL; 145 } 146 147 static void 148 atmegadci_clocks_on(struct atmegadci_softc *sc) 149 { 150 if (sc->sc_flags.clocks_off && 151 sc->sc_flags.port_powered) { 152 DPRINTFN(5, "\n"); 153 154 /* turn on clocks */ 155 (sc->sc_clocks_on) (&sc->sc_bus); 156 157 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 158 ATMEGA_USBCON_USBE | 159 ATMEGA_USBCON_OTGPADE | 160 ATMEGA_USBCON_VBUSTE); 161 162 sc->sc_flags.clocks_off = 0; 163 164 /* enable transceiver ? */ 165 } 166 } 167 168 static void 169 atmegadci_clocks_off(struct atmegadci_softc *sc) 170 { 171 if (!sc->sc_flags.clocks_off) { 172 DPRINTFN(5, "\n"); 173 174 /* disable Transceiver ? */ 175 176 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 177 ATMEGA_USBCON_USBE | 178 ATMEGA_USBCON_OTGPADE | 179 ATMEGA_USBCON_FRZCLK | 180 ATMEGA_USBCON_VBUSTE); 181 182 /* turn clocks off */ 183 (sc->sc_clocks_off) (&sc->sc_bus); 184 185 sc->sc_flags.clocks_off = 1; 186 } 187 } 188 189 static void 190 atmegadci_pull_up(struct atmegadci_softc *sc) 191 { 192 /* pullup D+, if possible */ 193 194 if (!sc->sc_flags.d_pulled_up && 195 sc->sc_flags.port_powered) { 196 sc->sc_flags.d_pulled_up = 1; 197 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 198 } 199 } 200 201 static void 202 atmegadci_pull_down(struct atmegadci_softc *sc) 203 { 204 /* pulldown D+, if possible */ 205 206 if (sc->sc_flags.d_pulled_up) { 207 sc->sc_flags.d_pulled_up = 0; 208 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 209 } 210 } 211 212 static void 213 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 214 { 215 uint8_t temp; 216 217 if (!sc->sc_flags.status_suspend) { 218 return; 219 } 220 221 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 222 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 223 224 /* wait 8 milliseconds */ 225 /* Wait for reset to complete. */ 226 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 227 228 /* hardware should have cleared RMWKUP bit */ 229 } 230 231 static void 232 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 233 { 234 DPRINTFN(5, "addr=%d\n", addr); 235 236 addr |= ATMEGA_UDADDR_ADDEN; 237 238 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 239 } 240 241 static uint8_t 242 atmegadci_setup_rx(struct atmegadci_td *td) 243 { 244 struct atmegadci_softc *sc; 245 struct usb_device_request req; 246 uint16_t count; 247 uint8_t temp; 248 249 /* get pointer to softc */ 250 sc = ATMEGA_PC2SC(td->pc); 251 252 /* select endpoint number */ 253 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 254 255 /* check endpoint status */ 256 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 257 258 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 259 260 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 261 goto not_complete; 262 } 263 /* clear did stall */ 264 td->did_stall = 0; 265 /* get the packet byte count */ 266 count = 267 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 268 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 269 270 /* mask away undefined bits */ 271 count &= 0x7FF; 272 273 /* verify data length */ 274 if (count != td->remainder) { 275 DPRINTFN(0, "Invalid SETUP packet " 276 "length, %d bytes\n", count); 277 goto not_complete; 278 } 279 if (count != sizeof(req)) { 280 DPRINTFN(0, "Unsupported SETUP packet " 281 "length, %d bytes\n", count); 282 goto not_complete; 283 } 284 /* receive data */ 285 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 286 (void *)&req, sizeof(req)); 287 288 /* copy data into real buffer */ 289 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 290 291 td->offset = sizeof(req); 292 td->remainder = 0; 293 294 /* sneak peek the set address */ 295 if ((req.bmRequestType == UT_WRITE_DEVICE) && 296 (req.bRequest == UR_SET_ADDRESS)) { 297 sc->sc_dv_addr = req.wValue[0] & 0x7F; 298 /* must write address before ZLP */ 299 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 300 } else { 301 sc->sc_dv_addr = 0xFF; 302 } 303 304 /* Clear SETUP packet interrupt and all other previous interrupts */ 305 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 306 return (0); /* complete */ 307 308 not_complete: 309 /* abort any ongoing transfer */ 310 if (!td->did_stall) { 311 DPRINTFN(5, "stalling\n"); 312 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 313 ATMEGA_UECONX_EPEN | 314 ATMEGA_UECONX_STALLRQ); 315 td->did_stall = 1; 316 } 317 if (temp & ATMEGA_UEINTX_RXSTPI) { 318 /* clear SETUP packet interrupt */ 319 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 320 } 321 /* we only want to know if there is a SETUP packet */ 322 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 323 return (1); /* not complete */ 324 } 325 326 static uint8_t 327 atmegadci_data_rx(struct atmegadci_td *td) 328 { 329 struct atmegadci_softc *sc; 330 struct usb_page_search buf_res; 331 uint16_t count; 332 uint8_t temp; 333 uint8_t to; 334 uint8_t got_short; 335 336 to = 3; /* don't loop forever! */ 337 got_short = 0; 338 339 /* get pointer to softc */ 340 sc = ATMEGA_PC2SC(td->pc); 341 342 /* select endpoint number */ 343 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 344 345 repeat: 346 /* check if any of the FIFO banks have data */ 347 /* check endpoint status */ 348 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 349 350 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 351 352 if (temp & ATMEGA_UEINTX_RXSTPI) { 353 if (td->remainder == 0) { 354 /* 355 * We are actually complete and have 356 * received the next SETUP 357 */ 358 DPRINTFN(5, "faking complete\n"); 359 return (0); /* complete */ 360 } 361 /* 362 * USB Host Aborted the transfer. 363 */ 364 td->error = 1; 365 return (0); /* complete */ 366 } 367 /* check status */ 368 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 369 ATMEGA_UEINTX_RXOUTI))) { 370 /* no data */ 371 goto not_complete; 372 } 373 /* get the packet byte count */ 374 count = 375 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 376 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 377 378 /* mask away undefined bits */ 379 count &= 0x7FF; 380 381 /* verify the packet byte count */ 382 if (count != td->max_packet_size) { 383 if (count < td->max_packet_size) { 384 /* we have a short packet */ 385 td->short_pkt = 1; 386 got_short = 1; 387 } else { 388 /* invalid USB packet */ 389 td->error = 1; 390 return (0); /* we are complete */ 391 } 392 } 393 /* verify the packet byte count */ 394 if (count > td->remainder) { 395 /* invalid USB packet */ 396 td->error = 1; 397 return (0); /* we are complete */ 398 } 399 while (count > 0) { 400 usbd_get_page(td->pc, td->offset, &buf_res); 401 402 /* get correct length */ 403 if (buf_res.length > count) { 404 buf_res.length = count; 405 } 406 /* receive data */ 407 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 408 buf_res.buffer, buf_res.length); 409 410 /* update counters */ 411 count -= buf_res.length; 412 td->offset += buf_res.length; 413 td->remainder -= buf_res.length; 414 } 415 416 /* clear OUT packet interrupt */ 417 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 418 419 /* release FIFO bank */ 420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 421 422 /* check if we are complete */ 423 if ((td->remainder == 0) || got_short) { 424 if (td->short_pkt) { 425 /* we are complete */ 426 return (0); 427 } 428 /* else need to receive a zero length packet */ 429 } 430 if (--to) { 431 goto repeat; 432 } 433 not_complete: 434 /* we only want to know if there is a SETUP packet or OUT packet */ 435 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 436 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 437 return (1); /* not complete */ 438 } 439 440 static uint8_t 441 atmegadci_data_tx(struct atmegadci_td *td) 442 { 443 struct atmegadci_softc *sc; 444 struct usb_page_search buf_res; 445 uint16_t count; 446 uint8_t to; 447 uint8_t temp; 448 449 to = 3; /* don't loop forever! */ 450 451 /* get pointer to softc */ 452 sc = ATMEGA_PC2SC(td->pc); 453 454 /* select endpoint number */ 455 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 456 457 repeat: 458 459 /* check endpoint status */ 460 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 461 462 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 463 464 if (temp & ATMEGA_UEINTX_RXSTPI) { 465 /* 466 * The current transfer was aborted 467 * by the USB Host 468 */ 469 td->error = 1; 470 return (0); /* complete */ 471 } 472 473 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 474 if (temp & 3) { 475 /* cannot write any data - a bank is busy */ 476 goto not_complete; 477 } 478 479 count = td->max_packet_size; 480 if (td->remainder < count) { 481 /* we have a short packet */ 482 td->short_pkt = 1; 483 count = td->remainder; 484 } 485 while (count > 0) { 486 usbd_get_page(td->pc, td->offset, &buf_res); 487 488 /* get correct length */ 489 if (buf_res.length > count) { 490 buf_res.length = count; 491 } 492 /* transmit data */ 493 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 494 buf_res.buffer, buf_res.length); 495 496 /* update counters */ 497 count -= buf_res.length; 498 td->offset += buf_res.length; 499 td->remainder -= buf_res.length; 500 } 501 502 /* clear IN packet interrupt */ 503 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 504 505 /* allocate FIFO bank */ 506 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 507 508 /* check remainder */ 509 if (td->remainder == 0) { 510 if (td->short_pkt) { 511 return (0); /* complete */ 512 } 513 /* else we need to transmit a short packet */ 514 } 515 if (--to) { 516 goto repeat; 517 } 518 not_complete: 519 /* we only want to know if there is a SETUP packet or free IN packet */ 520 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 521 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 522 return (1); /* not complete */ 523 } 524 525 static uint8_t 526 atmegadci_data_tx_sync(struct atmegadci_td *td) 527 { 528 struct atmegadci_softc *sc; 529 uint8_t temp; 530 531 /* get pointer to softc */ 532 sc = ATMEGA_PC2SC(td->pc); 533 534 /* select endpoint number */ 535 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 536 537 /* check endpoint status */ 538 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 539 540 DPRINTFN(5, "temp=0x%02x\n", temp); 541 542 if (temp & ATMEGA_UEINTX_RXSTPI) { 543 DPRINTFN(5, "faking complete\n"); 544 /* Race condition */ 545 return (0); /* complete */ 546 } 547 /* 548 * The control endpoint has only got one bank, so if that bank 549 * is free the packet has been transferred! 550 */ 551 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 552 if (temp & 3) { 553 /* cannot write any data - a bank is busy */ 554 goto not_complete; 555 } 556 if (sc->sc_dv_addr != 0xFF) { 557 /* set new address */ 558 atmegadci_set_address(sc, sc->sc_dv_addr); 559 } 560 return (0); /* complete */ 561 562 not_complete: 563 /* we only want to know if there is a SETUP packet or free IN packet */ 564 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 565 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 566 return (1); /* not complete */ 567 } 568 569 static uint8_t 570 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 571 { 572 struct atmegadci_td *td; 573 574 DPRINTFN(9, "\n"); 575 576 td = xfer->td_transfer_cache; 577 while (1) { 578 if ((td->func) (td)) { 579 /* operation in progress */ 580 break; 581 } 582 if (((void *)td) == xfer->td_transfer_last) { 583 goto done; 584 } 585 if (td->error) { 586 goto done; 587 } else if (td->remainder > 0) { 588 /* 589 * We had a short transfer. If there is no alternate 590 * next, stop processing ! 591 */ 592 if (!td->alt_next) { 593 goto done; 594 } 595 } 596 /* 597 * Fetch the next transfer descriptor and transfer 598 * some flags to the next transfer descriptor 599 */ 600 td = td->obj_next; 601 xfer->td_transfer_cache = td; 602 } 603 return (1); /* not complete */ 604 605 done: 606 /* compute all actual lengths */ 607 608 atmegadci_standard_done(xfer); 609 return (0); /* complete */ 610 } 611 612 static void 613 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 614 { 615 struct usb_xfer *xfer; 616 617 repeat: 618 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 619 if (!atmegadci_xfer_do_fifo(xfer)) { 620 /* queue has been modified */ 621 goto repeat; 622 } 623 } 624 } 625 626 static void 627 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 628 { 629 DPRINTFN(5, "vbus = %u\n", is_on); 630 631 if (is_on) { 632 if (!sc->sc_flags.status_vbus) { 633 sc->sc_flags.status_vbus = 1; 634 635 /* complete root HUB interrupt endpoint */ 636 637 atmegadci_root_intr(sc); 638 } 639 } else { 640 if (sc->sc_flags.status_vbus) { 641 sc->sc_flags.status_vbus = 0; 642 sc->sc_flags.status_bus_reset = 0; 643 sc->sc_flags.status_suspend = 0; 644 sc->sc_flags.change_suspend = 0; 645 sc->sc_flags.change_connect = 1; 646 647 /* complete root HUB interrupt endpoint */ 648 649 atmegadci_root_intr(sc); 650 } 651 } 652 } 653 654 void 655 atmegadci_interrupt(struct atmegadci_softc *sc) 656 { 657 uint8_t status; 658 659 USB_BUS_LOCK(&sc->sc_bus); 660 661 /* read interrupt status */ 662 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 663 664 /* clear all set interrupts */ 665 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 666 667 DPRINTFN(14, "UDINT=0x%02x\n", status); 668 669 /* check for any bus state change interrupts */ 670 if (status & ATMEGA_UDINT_EORSTI) { 671 DPRINTFN(5, "end of reset\n"); 672 673 /* set correct state */ 674 sc->sc_flags.status_bus_reset = 1; 675 sc->sc_flags.status_suspend = 0; 676 sc->sc_flags.change_suspend = 0; 677 sc->sc_flags.change_connect = 1; 678 679 /* disable resume interrupt */ 680 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 681 ATMEGA_UDINT_SUSPE | 682 ATMEGA_UDINT_EORSTE); 683 684 /* complete root HUB interrupt endpoint */ 685 atmegadci_root_intr(sc); 686 } 687 /* 688 * If resume and suspend is set at the same time we interpret 689 * that like RESUME. Resume is set when there is at least 3 690 * milliseconds of inactivity on the USB BUS. 691 */ 692 if (status & ATMEGA_UDINT_WAKEUPI) { 693 DPRINTFN(5, "resume interrupt\n"); 694 695 if (sc->sc_flags.status_suspend) { 696 /* update status bits */ 697 sc->sc_flags.status_suspend = 0; 698 sc->sc_flags.change_suspend = 1; 699 700 /* disable resume interrupt */ 701 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 702 ATMEGA_UDINT_SUSPE | 703 ATMEGA_UDINT_EORSTE); 704 705 /* complete root HUB interrupt endpoint */ 706 atmegadci_root_intr(sc); 707 } 708 } else if (status & ATMEGA_UDINT_SUSPI) { 709 DPRINTFN(5, "suspend interrupt\n"); 710 711 if (!sc->sc_flags.status_suspend) { 712 /* update status bits */ 713 sc->sc_flags.status_suspend = 1; 714 sc->sc_flags.change_suspend = 1; 715 716 /* disable suspend interrupt */ 717 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 718 ATMEGA_UDINT_WAKEUPE | 719 ATMEGA_UDINT_EORSTE); 720 721 /* complete root HUB interrupt endpoint */ 722 atmegadci_root_intr(sc); 723 } 724 } 725 /* check VBUS */ 726 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 727 728 /* clear all set interrupts */ 729 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 730 731 if (status & ATMEGA_USBINT_VBUSTI) { 732 uint8_t temp; 733 734 DPRINTFN(5, "USBINT=0x%02x\n", status); 735 736 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 737 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 738 } 739 /* check for any endpoint interrupts */ 740 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 741 /* the hardware will clear the UEINT bits automatically */ 742 if (status) { 743 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 744 745 atmegadci_interrupt_poll(sc); 746 } 747 USB_BUS_UNLOCK(&sc->sc_bus); 748 } 749 750 static void 751 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 752 { 753 struct atmegadci_td *td; 754 755 /* get current Transfer Descriptor */ 756 td = temp->td_next; 757 temp->td = td; 758 759 /* prepare for next TD */ 760 temp->td_next = td->obj_next; 761 762 /* fill out the Transfer Descriptor */ 763 td->func = temp->func; 764 td->pc = temp->pc; 765 td->offset = temp->offset; 766 td->remainder = temp->len; 767 td->error = 0; 768 td->did_stall = temp->did_stall; 769 td->short_pkt = temp->short_pkt; 770 td->alt_next = temp->setup_alt_next; 771 } 772 773 static void 774 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 775 { 776 struct atmegadci_std_temp temp; 777 struct atmegadci_td *td; 778 uint32_t x; 779 uint8_t need_sync; 780 781 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 782 xfer->address, UE_GET_ADDR(xfer->endpointno), 783 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 784 785 temp.max_frame_size = xfer->max_frame_size; 786 787 td = xfer->td_start[0]; 788 xfer->td_transfer_first = td; 789 xfer->td_transfer_cache = td; 790 791 /* setup temp */ 792 793 temp.pc = NULL; 794 temp.td = NULL; 795 temp.td_next = xfer->td_start[0]; 796 temp.offset = 0; 797 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 798 xfer->flags_int.isochronous_xfr; 799 temp.did_stall = !xfer->flags_int.control_stall; 800 801 /* check if we should prepend a setup message */ 802 803 if (xfer->flags_int.control_xfr) { 804 if (xfer->flags_int.control_hdr) { 805 temp.func = &atmegadci_setup_rx; 806 temp.len = xfer->frlengths[0]; 807 temp.pc = xfer->frbuffers + 0; 808 temp.short_pkt = temp.len ? 1 : 0; 809 /* check for last frame */ 810 if (xfer->nframes == 1) { 811 /* no STATUS stage yet, SETUP is last */ 812 if (xfer->flags_int.control_act) 813 temp.setup_alt_next = 0; 814 } 815 816 atmegadci_setup_standard_chain_sub(&temp); 817 } 818 x = 1; 819 } else { 820 x = 0; 821 } 822 823 if (x != xfer->nframes) { 824 if (xfer->endpointno & UE_DIR_IN) { 825 temp.func = &atmegadci_data_tx; 826 need_sync = 1; 827 } else { 828 temp.func = &atmegadci_data_rx; 829 need_sync = 0; 830 } 831 832 /* setup "pc" pointer */ 833 temp.pc = xfer->frbuffers + x; 834 } else { 835 need_sync = 0; 836 } 837 while (x != xfer->nframes) { 838 /* DATA0 / DATA1 message */ 839 840 temp.len = xfer->frlengths[x]; 841 842 x++; 843 844 if (x == xfer->nframes) { 845 if (xfer->flags_int.control_xfr) { 846 if (xfer->flags_int.control_act) { 847 temp.setup_alt_next = 0; 848 } 849 } else { 850 temp.setup_alt_next = 0; 851 } 852 } 853 if (temp.len == 0) { 854 /* make sure that we send an USB packet */ 855 856 temp.short_pkt = 0; 857 858 } else { 859 /* regular data transfer */ 860 861 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 862 } 863 864 atmegadci_setup_standard_chain_sub(&temp); 865 866 if (xfer->flags_int.isochronous_xfr) { 867 temp.offset += temp.len; 868 } else { 869 /* get next Page Cache pointer */ 870 temp.pc = xfer->frbuffers + x; 871 } 872 } 873 874 if (xfer->flags_int.control_xfr) { 875 /* always setup a valid "pc" pointer for status and sync */ 876 temp.pc = xfer->frbuffers + 0; 877 temp.len = 0; 878 temp.short_pkt = 0; 879 temp.setup_alt_next = 0; 880 881 /* check if we need to sync */ 882 if (need_sync) { 883 /* we need a SYNC point after TX */ 884 temp.func = &atmegadci_data_tx_sync; 885 atmegadci_setup_standard_chain_sub(&temp); 886 } 887 888 /* check if we should append a status stage */ 889 if (!xfer->flags_int.control_act) { 890 /* 891 * Send a DATA1 message and invert the current 892 * endpoint direction. 893 */ 894 if (xfer->endpointno & UE_DIR_IN) { 895 temp.func = &atmegadci_data_rx; 896 need_sync = 0; 897 } else { 898 temp.func = &atmegadci_data_tx; 899 need_sync = 1; 900 } 901 902 atmegadci_setup_standard_chain_sub(&temp); 903 if (need_sync) { 904 /* we need a SYNC point after TX */ 905 temp.func = &atmegadci_data_tx_sync; 906 atmegadci_setup_standard_chain_sub(&temp); 907 } 908 } 909 } 910 /* must have at least one frame! */ 911 td = temp.td; 912 xfer->td_transfer_last = td; 913 } 914 915 static void 916 atmegadci_timeout(void *arg) 917 { 918 struct usb_xfer *xfer = arg; 919 920 DPRINTF("xfer=%p\n", xfer); 921 922 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 923 924 /* transfer is transferred */ 925 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 926 } 927 928 static void 929 atmegadci_start_standard_chain(struct usb_xfer *xfer) 930 { 931 DPRINTFN(9, "\n"); 932 933 /* poll one time - will turn on interrupts */ 934 if (atmegadci_xfer_do_fifo(xfer)) { 935 /* put transfer on interrupt queue */ 936 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 937 938 /* start timeout, if any */ 939 if (xfer->timeout != 0) { 940 usbd_transfer_timeout_ms(xfer, 941 &atmegadci_timeout, xfer->timeout); 942 } 943 } 944 } 945 946 static void 947 atmegadci_root_intr(struct atmegadci_softc *sc) 948 { 949 DPRINTFN(9, "\n"); 950 951 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 952 953 /* set port bit */ 954 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 955 956 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 957 sizeof(sc->sc_hub_idata)); 958 } 959 960 static usb_error_t 961 atmegadci_standard_done_sub(struct usb_xfer *xfer) 962 { 963 struct atmegadci_td *td; 964 uint32_t len; 965 uint8_t error; 966 967 DPRINTFN(9, "\n"); 968 969 td = xfer->td_transfer_cache; 970 971 do { 972 len = td->remainder; 973 974 if (xfer->aframes != xfer->nframes) { 975 /* 976 * Verify the length and subtract 977 * the remainder from "frlengths[]": 978 */ 979 if (len > xfer->frlengths[xfer->aframes]) { 980 td->error = 1; 981 } else { 982 xfer->frlengths[xfer->aframes] -= len; 983 } 984 } 985 /* Check for transfer error */ 986 if (td->error) { 987 /* the transfer is finished */ 988 error = 1; 989 td = NULL; 990 break; 991 } 992 /* Check for short transfer */ 993 if (len > 0) { 994 if (xfer->flags_int.short_frames_ok || 995 xfer->flags_int.isochronous_xfr) { 996 /* follow alt next */ 997 if (td->alt_next) { 998 td = td->obj_next; 999 } else { 1000 td = NULL; 1001 } 1002 } else { 1003 /* the transfer is finished */ 1004 td = NULL; 1005 } 1006 error = 0; 1007 break; 1008 } 1009 td = td->obj_next; 1010 1011 /* this USB frame is complete */ 1012 error = 0; 1013 break; 1014 1015 } while (0); 1016 1017 /* update transfer cache */ 1018 1019 xfer->td_transfer_cache = td; 1020 1021 return (error ? 1022 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1023 } 1024 1025 static void 1026 atmegadci_standard_done(struct usb_xfer *xfer) 1027 { 1028 usb_error_t err = 0; 1029 1030 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1031 xfer, xfer->endpoint); 1032 1033 /* reset scanner */ 1034 1035 xfer->td_transfer_cache = xfer->td_transfer_first; 1036 1037 if (xfer->flags_int.control_xfr) { 1038 if (xfer->flags_int.control_hdr) { 1039 err = atmegadci_standard_done_sub(xfer); 1040 } 1041 xfer->aframes = 1; 1042 1043 if (xfer->td_transfer_cache == NULL) { 1044 goto done; 1045 } 1046 } 1047 while (xfer->aframes != xfer->nframes) { 1048 err = atmegadci_standard_done_sub(xfer); 1049 xfer->aframes++; 1050 1051 if (xfer->td_transfer_cache == NULL) { 1052 goto done; 1053 } 1054 } 1055 1056 if (xfer->flags_int.control_xfr && 1057 !xfer->flags_int.control_act) { 1058 err = atmegadci_standard_done_sub(xfer); 1059 } 1060 done: 1061 atmegadci_device_done(xfer, err); 1062 } 1063 1064 /*------------------------------------------------------------------------* 1065 * atmegadci_device_done 1066 * 1067 * NOTE: this function can be called more than one time on the 1068 * same USB transfer! 1069 *------------------------------------------------------------------------*/ 1070 static void 1071 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1072 { 1073 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1074 uint8_t ep_no; 1075 1076 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1077 1078 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1079 xfer, xfer->endpoint, error); 1080 1081 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1082 ep_no = (xfer->endpointno & UE_ADDR); 1083 1084 /* select endpoint number */ 1085 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1086 1087 /* disable endpoint interrupt */ 1088 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1089 1090 DPRINTFN(15, "disabled interrupts!\n"); 1091 } 1092 /* dequeue transfer and start next transfer */ 1093 usbd_transfer_done(xfer, error); 1094 } 1095 1096 static void 1097 atmegadci_xfer_stall(struct usb_xfer *xfer) 1098 { 1099 atmegadci_device_done(xfer, USB_ERR_STALLED); 1100 } 1101 1102 static void 1103 atmegadci_set_stall(struct usb_device *udev, 1104 struct usb_endpoint *ep, uint8_t *did_stall) 1105 { 1106 struct atmegadci_softc *sc; 1107 uint8_t ep_no; 1108 1109 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1110 1111 DPRINTFN(5, "endpoint=%p\n", ep); 1112 1113 sc = ATMEGA_BUS2SC(udev->bus); 1114 /* get endpoint number */ 1115 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1116 /* select endpoint number */ 1117 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1118 /* set stall */ 1119 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1120 ATMEGA_UECONX_EPEN | 1121 ATMEGA_UECONX_STALLRQ); 1122 } 1123 1124 static void 1125 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1126 uint8_t ep_type, uint8_t ep_dir) 1127 { 1128 uint8_t temp; 1129 1130 if (ep_type == UE_CONTROL) { 1131 /* clearing stall is not needed */ 1132 return; 1133 } 1134 /* select endpoint number */ 1135 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1136 1137 /* set endpoint reset */ 1138 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1139 1140 /* clear endpoint reset */ 1141 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1142 1143 /* set stall */ 1144 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1145 ATMEGA_UECONX_EPEN | 1146 ATMEGA_UECONX_STALLRQ); 1147 1148 /* reset data toggle */ 1149 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1150 ATMEGA_UECONX_EPEN | 1151 ATMEGA_UECONX_RSTDT); 1152 1153 /* clear stall */ 1154 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1155 ATMEGA_UECONX_EPEN | 1156 ATMEGA_UECONX_STALLRQC); 1157 1158 do { 1159 if (ep_type == UE_BULK) { 1160 temp = ATMEGA_UECFG0X_EPTYPE2; 1161 } else if (ep_type == UE_INTERRUPT) { 1162 temp = ATMEGA_UECFG0X_EPTYPE3; 1163 } else { 1164 temp = ATMEGA_UECFG0X_EPTYPE1; 1165 } 1166 if (ep_dir & UE_DIR_IN) { 1167 temp |= ATMEGA_UECFG0X_EPDIR; 1168 } 1169 /* two banks, 64-bytes wMaxPacket */ 1170 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1171 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1172 ATMEGA_UECFG1X_ALLOC | 1173 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1174 ATMEGA_UECFG1X_EPSIZE(3)); 1175 1176 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1177 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1178 device_printf(sc->sc_bus.bdev, 1179 "Chip rejected configuration\n"); 1180 } 1181 } while (0); 1182 } 1183 1184 static void 1185 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1186 { 1187 struct atmegadci_softc *sc; 1188 struct usb_endpoint_descriptor *ed; 1189 1190 DPRINTFN(5, "endpoint=%p\n", ep); 1191 1192 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1193 1194 /* check mode */ 1195 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1196 /* not supported */ 1197 return; 1198 } 1199 /* get softc */ 1200 sc = ATMEGA_BUS2SC(udev->bus); 1201 1202 /* get endpoint descriptor */ 1203 ed = ep->edesc; 1204 1205 /* reset endpoint */ 1206 atmegadci_clear_stall_sub(sc, 1207 (ed->bEndpointAddress & UE_ADDR), 1208 (ed->bmAttributes & UE_XFERTYPE), 1209 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1210 } 1211 1212 usb_error_t 1213 atmegadci_init(struct atmegadci_softc *sc) 1214 { 1215 uint8_t n; 1216 1217 DPRINTF("start\n"); 1218 1219 /* set up the bus structure */ 1220 sc->sc_bus.usbrev = USB_REV_1_1; 1221 sc->sc_bus.methods = &atmegadci_bus_methods; 1222 1223 USB_BUS_LOCK(&sc->sc_bus); 1224 1225 /* make sure USB is enabled */ 1226 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1227 ATMEGA_USBCON_USBE | 1228 ATMEGA_USBCON_FRZCLK); 1229 1230 /* enable USB PAD regulator */ 1231 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1232 ATMEGA_UHWCON_UVREGE | 1233 ATMEGA_UHWCON_UIMOD); 1234 1235 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1236 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1237 1238 /* wait for PLL to lock */ 1239 for (n = 0; n != 20; n++) { 1240 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1241 break; 1242 /* wait a little bit for PLL to start */ 1243 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1244 } 1245 1246 /* make sure USB is enabled */ 1247 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1248 ATMEGA_USBCON_USBE | 1249 ATMEGA_USBCON_OTGPADE | 1250 ATMEGA_USBCON_VBUSTE); 1251 1252 /* turn on clocks */ 1253 (sc->sc_clocks_on) (&sc->sc_bus); 1254 1255 /* make sure device is re-enumerated */ 1256 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1257 1258 /* wait a little for things to stabilise */ 1259 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1260 1261 /* enable interrupts */ 1262 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1263 ATMEGA_UDINT_SUSPE | 1264 ATMEGA_UDINT_EORSTE); 1265 1266 /* reset all endpoints */ 1267 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1268 (1 << ATMEGA_EP_MAX) - 1); 1269 1270 /* disable reset */ 1271 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1272 1273 /* disable all endpoints */ 1274 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1275 /* select endpoint */ 1276 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1277 1278 /* disable endpoint interrupt */ 1279 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1280 1281 /* disable endpoint */ 1282 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1283 } 1284 1285 /* turn off clocks */ 1286 1287 atmegadci_clocks_off(sc); 1288 1289 /* read initial VBUS state */ 1290 1291 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1292 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1293 1294 USB_BUS_UNLOCK(&sc->sc_bus); 1295 1296 /* catch any lost interrupts */ 1297 1298 atmegadci_do_poll(&sc->sc_bus); 1299 1300 return (0); /* success */ 1301 } 1302 1303 void 1304 atmegadci_uninit(struct atmegadci_softc *sc) 1305 { 1306 USB_BUS_LOCK(&sc->sc_bus); 1307 1308 /* turn on clocks */ 1309 (sc->sc_clocks_on) (&sc->sc_bus); 1310 1311 /* disable interrupts */ 1312 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1313 1314 /* reset all endpoints */ 1315 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1316 (1 << ATMEGA_EP_MAX) - 1); 1317 1318 /* disable reset */ 1319 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1320 1321 sc->sc_flags.port_powered = 0; 1322 sc->sc_flags.status_vbus = 0; 1323 sc->sc_flags.status_bus_reset = 0; 1324 sc->sc_flags.status_suspend = 0; 1325 sc->sc_flags.change_suspend = 0; 1326 sc->sc_flags.change_connect = 1; 1327 1328 atmegadci_pull_down(sc); 1329 atmegadci_clocks_off(sc); 1330 1331 /* disable USB PAD regulator */ 1332 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1333 1334 USB_BUS_UNLOCK(&sc->sc_bus); 1335 } 1336 1337 static void 1338 atmegadci_suspend(struct atmegadci_softc *sc) 1339 { 1340 /* TODO */ 1341 } 1342 1343 static void 1344 atmegadci_resume(struct atmegadci_softc *sc) 1345 { 1346 /* TODO */ 1347 } 1348 1349 static void 1350 atmegadci_do_poll(struct usb_bus *bus) 1351 { 1352 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1353 1354 USB_BUS_LOCK(&sc->sc_bus); 1355 atmegadci_interrupt_poll(sc); 1356 USB_BUS_UNLOCK(&sc->sc_bus); 1357 } 1358 1359 /*------------------------------------------------------------------------* 1360 * atmegadci bulk support 1361 * atmegadci control support 1362 * atmegadci interrupt support 1363 *------------------------------------------------------------------------*/ 1364 static void 1365 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1366 { 1367 return; 1368 } 1369 1370 static void 1371 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1372 { 1373 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1374 } 1375 1376 static void 1377 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1378 { 1379 return; 1380 } 1381 1382 static void 1383 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1384 { 1385 /* setup TDs */ 1386 atmegadci_setup_standard_chain(xfer); 1387 atmegadci_start_standard_chain(xfer); 1388 } 1389 1390 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1391 { 1392 .open = atmegadci_device_non_isoc_open, 1393 .close = atmegadci_device_non_isoc_close, 1394 .enter = atmegadci_device_non_isoc_enter, 1395 .start = atmegadci_device_non_isoc_start, 1396 }; 1397 1398 /*------------------------------------------------------------------------* 1399 * atmegadci full speed isochronous support 1400 *------------------------------------------------------------------------*/ 1401 static void 1402 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1403 { 1404 return; 1405 } 1406 1407 static void 1408 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1409 { 1410 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1411 } 1412 1413 static void 1414 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1415 { 1416 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1417 uint32_t nframes; 1418 1419 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1420 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1421 1422 /* get the current frame index */ 1423 1424 nframes = 1425 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1426 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1427 1428 if (usbd_xfer_get_isochronous_start_frame( 1429 xfer, nframes, 0, 1, ATMEGA_FRAME_MASK, NULL)) 1430 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1431 1432 /* setup TDs */ 1433 atmegadci_setup_standard_chain(xfer); 1434 } 1435 1436 static void 1437 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1438 { 1439 /* start TD chain */ 1440 atmegadci_start_standard_chain(xfer); 1441 } 1442 1443 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1444 { 1445 .open = atmegadci_device_isoc_fs_open, 1446 .close = atmegadci_device_isoc_fs_close, 1447 .enter = atmegadci_device_isoc_fs_enter, 1448 .start = atmegadci_device_isoc_fs_start, 1449 }; 1450 1451 /*------------------------------------------------------------------------* 1452 * atmegadci root control support 1453 *------------------------------------------------------------------------* 1454 * Simulate a hardware HUB by handling all the necessary requests. 1455 *------------------------------------------------------------------------*/ 1456 1457 static const struct usb_device_descriptor atmegadci_devd = { 1458 .bLength = sizeof(struct usb_device_descriptor), 1459 .bDescriptorType = UDESC_DEVICE, 1460 .bcdUSB = {0x00, 0x02}, 1461 .bDeviceClass = UDCLASS_HUB, 1462 .bDeviceSubClass = UDSUBCLASS_HUB, 1463 .bDeviceProtocol = UDPROTO_FSHUB, 1464 .bMaxPacketSize = 64, 1465 .bcdDevice = {0x00, 0x01}, 1466 .iManufacturer = 1, 1467 .iProduct = 2, 1468 .bNumConfigurations = 1, 1469 }; 1470 1471 static const struct atmegadci_config_desc atmegadci_confd = { 1472 .confd = { 1473 .bLength = sizeof(struct usb_config_descriptor), 1474 .bDescriptorType = UDESC_CONFIG, 1475 .wTotalLength[0] = sizeof(atmegadci_confd), 1476 .bNumInterface = 1, 1477 .bConfigurationValue = 1, 1478 .iConfiguration = 0, 1479 .bmAttributes = UC_SELF_POWERED, 1480 .bMaxPower = 0, 1481 }, 1482 .ifcd = { 1483 .bLength = sizeof(struct usb_interface_descriptor), 1484 .bDescriptorType = UDESC_INTERFACE, 1485 .bNumEndpoints = 1, 1486 .bInterfaceClass = UICLASS_HUB, 1487 .bInterfaceSubClass = UISUBCLASS_HUB, 1488 .bInterfaceProtocol = 0, 1489 }, 1490 .endpd = { 1491 .bLength = sizeof(struct usb_endpoint_descriptor), 1492 .bDescriptorType = UDESC_ENDPOINT, 1493 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1494 .bmAttributes = UE_INTERRUPT, 1495 .wMaxPacketSize[0] = 8, 1496 .bInterval = 255, 1497 }, 1498 }; 1499 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 1500 1501 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1502 .bDescLength = sizeof(atmegadci_hubd), 1503 .bDescriptorType = UDESC_HUB, 1504 .bNbrPorts = 1, 1505 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 1506 .bPwrOn2PwrGood = 50, 1507 .bHubContrCurrent = 0, 1508 .DeviceRemovable = {0}, /* port is removable */ 1509 }; 1510 1511 #define STRING_VENDOR \ 1512 "A\0T\0M\0E\0G\0A" 1513 1514 #define STRING_PRODUCT \ 1515 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B" 1516 1517 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1518 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1519 1520 static usb_error_t 1521 atmegadci_roothub_exec(struct usb_device *udev, 1522 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1523 { 1524 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1525 const void *ptr; 1526 uint16_t len; 1527 uint16_t value; 1528 uint16_t index; 1529 uint8_t temp; 1530 usb_error_t err; 1531 1532 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1533 1534 /* buffer reset */ 1535 ptr = (const void *)&sc->sc_hub_temp; 1536 len = 0; 1537 err = 0; 1538 1539 value = UGETW(req->wValue); 1540 index = UGETW(req->wIndex); 1541 1542 /* demultiplex the control request */ 1543 1544 switch (req->bmRequestType) { 1545 case UT_READ_DEVICE: 1546 switch (req->bRequest) { 1547 case UR_GET_DESCRIPTOR: 1548 goto tr_handle_get_descriptor; 1549 case UR_GET_CONFIG: 1550 goto tr_handle_get_config; 1551 case UR_GET_STATUS: 1552 goto tr_handle_get_status; 1553 default: 1554 goto tr_stalled; 1555 } 1556 break; 1557 1558 case UT_WRITE_DEVICE: 1559 switch (req->bRequest) { 1560 case UR_SET_ADDRESS: 1561 goto tr_handle_set_address; 1562 case UR_SET_CONFIG: 1563 goto tr_handle_set_config; 1564 case UR_CLEAR_FEATURE: 1565 goto tr_valid; /* nop */ 1566 case UR_SET_DESCRIPTOR: 1567 goto tr_valid; /* nop */ 1568 case UR_SET_FEATURE: 1569 default: 1570 goto tr_stalled; 1571 } 1572 break; 1573 1574 case UT_WRITE_ENDPOINT: 1575 switch (req->bRequest) { 1576 case UR_CLEAR_FEATURE: 1577 switch (UGETW(req->wValue)) { 1578 case UF_ENDPOINT_HALT: 1579 goto tr_handle_clear_halt; 1580 case UF_DEVICE_REMOTE_WAKEUP: 1581 goto tr_handle_clear_wakeup; 1582 default: 1583 goto tr_stalled; 1584 } 1585 break; 1586 case UR_SET_FEATURE: 1587 switch (UGETW(req->wValue)) { 1588 case UF_ENDPOINT_HALT: 1589 goto tr_handle_set_halt; 1590 case UF_DEVICE_REMOTE_WAKEUP: 1591 goto tr_handle_set_wakeup; 1592 default: 1593 goto tr_stalled; 1594 } 1595 break; 1596 case UR_SYNCH_FRAME: 1597 goto tr_valid; /* nop */ 1598 default: 1599 goto tr_stalled; 1600 } 1601 break; 1602 1603 case UT_READ_ENDPOINT: 1604 switch (req->bRequest) { 1605 case UR_GET_STATUS: 1606 goto tr_handle_get_ep_status; 1607 default: 1608 goto tr_stalled; 1609 } 1610 break; 1611 1612 case UT_WRITE_INTERFACE: 1613 switch (req->bRequest) { 1614 case UR_SET_INTERFACE: 1615 goto tr_handle_set_interface; 1616 case UR_CLEAR_FEATURE: 1617 goto tr_valid; /* nop */ 1618 case UR_SET_FEATURE: 1619 default: 1620 goto tr_stalled; 1621 } 1622 break; 1623 1624 case UT_READ_INTERFACE: 1625 switch (req->bRequest) { 1626 case UR_GET_INTERFACE: 1627 goto tr_handle_get_interface; 1628 case UR_GET_STATUS: 1629 goto tr_handle_get_iface_status; 1630 default: 1631 goto tr_stalled; 1632 } 1633 break; 1634 1635 case UT_WRITE_CLASS_INTERFACE: 1636 case UT_WRITE_VENDOR_INTERFACE: 1637 /* XXX forward */ 1638 break; 1639 1640 case UT_READ_CLASS_INTERFACE: 1641 case UT_READ_VENDOR_INTERFACE: 1642 /* XXX forward */ 1643 break; 1644 1645 case UT_WRITE_CLASS_DEVICE: 1646 switch (req->bRequest) { 1647 case UR_CLEAR_FEATURE: 1648 goto tr_valid; 1649 case UR_SET_DESCRIPTOR: 1650 case UR_SET_FEATURE: 1651 break; 1652 default: 1653 goto tr_stalled; 1654 } 1655 break; 1656 1657 case UT_WRITE_CLASS_OTHER: 1658 switch (req->bRequest) { 1659 case UR_CLEAR_FEATURE: 1660 goto tr_handle_clear_port_feature; 1661 case UR_SET_FEATURE: 1662 goto tr_handle_set_port_feature; 1663 case UR_CLEAR_TT_BUFFER: 1664 case UR_RESET_TT: 1665 case UR_STOP_TT: 1666 goto tr_valid; 1667 1668 default: 1669 goto tr_stalled; 1670 } 1671 break; 1672 1673 case UT_READ_CLASS_OTHER: 1674 switch (req->bRequest) { 1675 case UR_GET_TT_STATE: 1676 goto tr_handle_get_tt_state; 1677 case UR_GET_STATUS: 1678 goto tr_handle_get_port_status; 1679 default: 1680 goto tr_stalled; 1681 } 1682 break; 1683 1684 case UT_READ_CLASS_DEVICE: 1685 switch (req->bRequest) { 1686 case UR_GET_DESCRIPTOR: 1687 goto tr_handle_get_class_descriptor; 1688 case UR_GET_STATUS: 1689 goto tr_handle_get_class_status; 1690 1691 default: 1692 goto tr_stalled; 1693 } 1694 break; 1695 default: 1696 goto tr_stalled; 1697 } 1698 goto tr_valid; 1699 1700 tr_handle_get_descriptor: 1701 switch (value >> 8) { 1702 case UDESC_DEVICE: 1703 if (value & 0xff) { 1704 goto tr_stalled; 1705 } 1706 len = sizeof(atmegadci_devd); 1707 ptr = (const void *)&atmegadci_devd; 1708 goto tr_valid; 1709 case UDESC_CONFIG: 1710 if (value & 0xff) { 1711 goto tr_stalled; 1712 } 1713 len = sizeof(atmegadci_confd); 1714 ptr = (const void *)&atmegadci_confd; 1715 goto tr_valid; 1716 case UDESC_STRING: 1717 switch (value & 0xff) { 1718 case 0: /* Language table */ 1719 len = sizeof(usb_string_lang_en); 1720 ptr = (const void *)&usb_string_lang_en; 1721 goto tr_valid; 1722 1723 case 1: /* Vendor */ 1724 len = sizeof(atmegadci_vendor); 1725 ptr = (const void *)&atmegadci_vendor; 1726 goto tr_valid; 1727 1728 case 2: /* Product */ 1729 len = sizeof(atmegadci_product); 1730 ptr = (const void *)&atmegadci_product; 1731 goto tr_valid; 1732 default: 1733 break; 1734 } 1735 break; 1736 default: 1737 goto tr_stalled; 1738 } 1739 goto tr_stalled; 1740 1741 tr_handle_get_config: 1742 len = 1; 1743 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1744 goto tr_valid; 1745 1746 tr_handle_get_status: 1747 len = 2; 1748 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1749 goto tr_valid; 1750 1751 tr_handle_set_address: 1752 if (value & 0xFF00) { 1753 goto tr_stalled; 1754 } 1755 sc->sc_rt_addr = value; 1756 goto tr_valid; 1757 1758 tr_handle_set_config: 1759 if (value >= 2) { 1760 goto tr_stalled; 1761 } 1762 sc->sc_conf = value; 1763 goto tr_valid; 1764 1765 tr_handle_get_interface: 1766 len = 1; 1767 sc->sc_hub_temp.wValue[0] = 0; 1768 goto tr_valid; 1769 1770 tr_handle_get_tt_state: 1771 tr_handle_get_class_status: 1772 tr_handle_get_iface_status: 1773 tr_handle_get_ep_status: 1774 len = 2; 1775 USETW(sc->sc_hub_temp.wValue, 0); 1776 goto tr_valid; 1777 1778 tr_handle_set_halt: 1779 tr_handle_set_interface: 1780 tr_handle_set_wakeup: 1781 tr_handle_clear_wakeup: 1782 tr_handle_clear_halt: 1783 goto tr_valid; 1784 1785 tr_handle_clear_port_feature: 1786 if (index != 1) { 1787 goto tr_stalled; 1788 } 1789 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1790 1791 switch (value) { 1792 case UHF_PORT_SUSPEND: 1793 atmegadci_wakeup_peer(sc); 1794 break; 1795 1796 case UHF_PORT_ENABLE: 1797 sc->sc_flags.port_enabled = 0; 1798 break; 1799 1800 case UHF_PORT_TEST: 1801 case UHF_PORT_INDICATOR: 1802 case UHF_C_PORT_ENABLE: 1803 case UHF_C_PORT_OVER_CURRENT: 1804 case UHF_C_PORT_RESET: 1805 /* nops */ 1806 break; 1807 case UHF_PORT_POWER: 1808 sc->sc_flags.port_powered = 0; 1809 atmegadci_pull_down(sc); 1810 atmegadci_clocks_off(sc); 1811 break; 1812 case UHF_C_PORT_CONNECTION: 1813 /* clear connect change flag */ 1814 sc->sc_flags.change_connect = 0; 1815 1816 if (!sc->sc_flags.status_bus_reset) { 1817 /* we are not connected */ 1818 break; 1819 } 1820 1821 /* configure the control endpoint */ 1822 1823 /* select endpoint number */ 1824 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1825 1826 /* set endpoint reset */ 1827 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1828 1829 /* clear endpoint reset */ 1830 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1831 1832 /* enable and stall endpoint */ 1833 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1834 ATMEGA_UECONX_EPEN | 1835 ATMEGA_UECONX_STALLRQ); 1836 1837 /* one bank, 64-bytes wMaxPacket */ 1838 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1839 ATMEGA_UECFG0X_EPTYPE0); 1840 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1841 ATMEGA_UECFG1X_ALLOC | 1842 ATMEGA_UECFG1X_EPBK0 | 1843 ATMEGA_UECFG1X_EPSIZE(3)); 1844 1845 /* check valid config */ 1846 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1847 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1848 device_printf(sc->sc_bus.bdev, 1849 "Chip rejected EP0 configuration\n"); 1850 } 1851 break; 1852 case UHF_C_PORT_SUSPEND: 1853 sc->sc_flags.change_suspend = 0; 1854 break; 1855 default: 1856 err = USB_ERR_IOERROR; 1857 goto done; 1858 } 1859 goto tr_valid; 1860 1861 tr_handle_set_port_feature: 1862 if (index != 1) { 1863 goto tr_stalled; 1864 } 1865 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1866 1867 switch (value) { 1868 case UHF_PORT_ENABLE: 1869 sc->sc_flags.port_enabled = 1; 1870 break; 1871 case UHF_PORT_SUSPEND: 1872 case UHF_PORT_RESET: 1873 case UHF_PORT_TEST: 1874 case UHF_PORT_INDICATOR: 1875 /* nops */ 1876 break; 1877 case UHF_PORT_POWER: 1878 sc->sc_flags.port_powered = 1; 1879 break; 1880 default: 1881 err = USB_ERR_IOERROR; 1882 goto done; 1883 } 1884 goto tr_valid; 1885 1886 tr_handle_get_port_status: 1887 1888 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1889 1890 if (index != 1) { 1891 goto tr_stalled; 1892 } 1893 if (sc->sc_flags.status_vbus) { 1894 atmegadci_clocks_on(sc); 1895 atmegadci_pull_up(sc); 1896 } else { 1897 atmegadci_pull_down(sc); 1898 atmegadci_clocks_off(sc); 1899 } 1900 1901 /* Select FULL-speed and Device Side Mode */ 1902 1903 value = UPS_PORT_MODE_DEVICE; 1904 1905 if (sc->sc_flags.port_powered) { 1906 value |= UPS_PORT_POWER; 1907 } 1908 if (sc->sc_flags.port_enabled) { 1909 value |= UPS_PORT_ENABLED; 1910 } 1911 if (sc->sc_flags.status_vbus && 1912 sc->sc_flags.status_bus_reset) { 1913 value |= UPS_CURRENT_CONNECT_STATUS; 1914 } 1915 if (sc->sc_flags.status_suspend) { 1916 value |= UPS_SUSPEND; 1917 } 1918 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1919 1920 value = 0; 1921 1922 if (sc->sc_flags.change_connect) { 1923 value |= UPS_C_CONNECT_STATUS; 1924 } 1925 if (sc->sc_flags.change_suspend) { 1926 value |= UPS_C_SUSPEND; 1927 } 1928 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1929 len = sizeof(sc->sc_hub_temp.ps); 1930 goto tr_valid; 1931 1932 tr_handle_get_class_descriptor: 1933 if (value & 0xFF) { 1934 goto tr_stalled; 1935 } 1936 ptr = (const void *)&atmegadci_hubd; 1937 len = sizeof(atmegadci_hubd); 1938 goto tr_valid; 1939 1940 tr_stalled: 1941 err = USB_ERR_STALLED; 1942 tr_valid: 1943 done: 1944 *plength = len; 1945 *pptr = ptr; 1946 return (err); 1947 } 1948 1949 static void 1950 atmegadci_xfer_setup(struct usb_setup_params *parm) 1951 { 1952 const struct usb_hw_ep_profile *pf; 1953 struct usb_xfer *xfer; 1954 void *last_obj; 1955 uint32_t ntd; 1956 uint32_t n; 1957 uint8_t ep_no; 1958 1959 xfer = parm->curr_xfer; 1960 1961 /* 1962 * NOTE: This driver does not use any of the parameters that 1963 * are computed from the following values. Just set some 1964 * reasonable dummies: 1965 */ 1966 parm->hc_max_packet_size = 0x500; 1967 parm->hc_max_packet_count = 1; 1968 parm->hc_max_frame_size = 0x500; 1969 1970 usbd_transfer_setup_sub(parm); 1971 1972 /* 1973 * compute maximum number of TDs 1974 */ 1975 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 1976 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 1977 + 1 /* SYNC 2 */ ; 1978 } else { 1979 ntd = xfer->nframes + 1 /* SYNC */ ; 1980 } 1981 1982 /* 1983 * check if "usbd_transfer_setup_sub" set an error 1984 */ 1985 if (parm->err) 1986 return; 1987 1988 /* 1989 * allocate transfer descriptors 1990 */ 1991 last_obj = NULL; 1992 1993 /* 1994 * get profile stuff 1995 */ 1996 ep_no = xfer->endpointno & UE_ADDR; 1997 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 1998 1999 if (pf == NULL) { 2000 /* should not happen */ 2001 parm->err = USB_ERR_INVAL; 2002 return; 2003 } 2004 2005 /* align data */ 2006 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2007 2008 for (n = 0; n != ntd; n++) { 2009 struct atmegadci_td *td; 2010 2011 if (parm->buf) { 2012 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2013 2014 /* init TD */ 2015 td->max_packet_size = xfer->max_packet_size; 2016 td->ep_no = ep_no; 2017 if (pf->support_multi_buffer) { 2018 td->support_multi_buffer = 1; 2019 } 2020 td->obj_next = last_obj; 2021 2022 last_obj = td; 2023 } 2024 parm->size[0] += sizeof(*td); 2025 } 2026 2027 xfer->td_start[0] = last_obj; 2028 } 2029 2030 static void 2031 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2032 { 2033 return; 2034 } 2035 2036 static void 2037 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2038 struct usb_endpoint *ep) 2039 { 2040 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2041 2042 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2043 ep, udev->address, 2044 edesc->bEndpointAddress, udev->flags.usb_mode, 2045 sc->sc_rt_addr, udev->device_index); 2046 2047 if (udev->device_index != sc->sc_rt_addr) { 2048 if (udev->speed != USB_SPEED_FULL) { 2049 /* not supported */ 2050 return; 2051 } 2052 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2053 ep->methods = &atmegadci_device_isoc_fs_methods; 2054 else 2055 ep->methods = &atmegadci_device_non_isoc_methods; 2056 } 2057 } 2058 2059 static void 2060 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2061 { 2062 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 2063 2064 switch (state) { 2065 case USB_HW_POWER_SUSPEND: 2066 atmegadci_suspend(sc); 2067 break; 2068 case USB_HW_POWER_SHUTDOWN: 2069 atmegadci_uninit(sc); 2070 break; 2071 case USB_HW_POWER_RESUME: 2072 atmegadci_resume(sc); 2073 break; 2074 default: 2075 break; 2076 } 2077 } 2078 2079 static const struct usb_bus_methods atmegadci_bus_methods = 2080 { 2081 .endpoint_init = &atmegadci_ep_init, 2082 .xfer_setup = &atmegadci_xfer_setup, 2083 .xfer_unsetup = &atmegadci_xfer_unsetup, 2084 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2085 .xfer_stall = &atmegadci_xfer_stall, 2086 .set_stall = &atmegadci_set_stall, 2087 .clear_stall = &atmegadci_clear_stall, 2088 .roothub_exec = &atmegadci_roothub_exec, 2089 .xfer_poll = &atmegadci_do_poll, 2090 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep, 2091 }; 2092