1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 43 #define USB_DEBUG_VAR atmegadci_debug 44 45 #include <dev/usb/usb_core.h> 46 #include <dev/usb/usb_debug.h> 47 #include <dev/usb/usb_busdma.h> 48 #include <dev/usb/usb_process.h> 49 #include <dev/usb/usb_transfer.h> 50 #include <dev/usb/usb_device.h> 51 #include <dev/usb/usb_hub.h> 52 #include <dev/usb/usb_util.h> 53 54 #include <dev/usb/usb_controller.h> 55 #include <dev/usb/usb_bus.h> 56 #include <dev/usb/controller/atmegadci.h> 57 58 #define ATMEGA_BUS2SC(bus) \ 59 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 60 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 61 62 #define ATMEGA_PC2SC(pc) \ 63 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 64 65 #if USB_DEBUG 66 static int atmegadci_debug = 0; 67 68 SYSCTL_NODE(_hw_usb2, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 69 SYSCTL_INT(_hw_usb2_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 70 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 71 #endif 72 73 #define ATMEGA_INTR_ENDPT 1 74 75 /* prototypes */ 76 77 struct usb2_bus_methods atmegadci_bus_methods; 78 struct usb2_pipe_methods atmegadci_device_non_isoc_methods; 79 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods; 80 81 static atmegadci_cmd_t atmegadci_setup_rx; 82 static atmegadci_cmd_t atmegadci_data_rx; 83 static atmegadci_cmd_t atmegadci_data_tx; 84 static atmegadci_cmd_t atmegadci_data_tx_sync; 85 static void atmegadci_device_done(struct usb2_xfer *, usb2_error_t); 86 static void atmegadci_do_poll(struct usb2_bus *); 87 static void atmegadci_standard_done(struct usb2_xfer *); 88 static void atmegadci_root_intr(struct atmegadci_softc *sc); 89 90 /* 91 * Here is a list of what the chip supports: 92 */ 93 static const struct usb2_hw_ep_profile 94 atmegadci_ep_profile[2] = { 95 96 [0] = { 97 .max_in_frame_size = 64, 98 .max_out_frame_size = 64, 99 .is_simplex = 1, 100 .support_control = 1, 101 }, 102 [1] = { 103 .max_in_frame_size = 64, 104 .max_out_frame_size = 64, 105 .is_simplex = 1, 106 .support_bulk = 1, 107 .support_interrupt = 1, 108 .support_isochronous = 1, 109 .support_in = 1, 110 .support_out = 1, 111 }, 112 }; 113 114 static void 115 atmegadci_get_hw_ep_profile(struct usb2_device *udev, 116 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 117 { 118 if (ep_addr == 0) 119 *ppf = atmegadci_ep_profile; 120 else if (ep_addr < ATMEGA_EP_MAX) 121 *ppf = atmegadci_ep_profile + 1; 122 else 123 *ppf = NULL; 124 } 125 126 static void 127 atmegadci_clocks_on(struct atmegadci_softc *sc) 128 { 129 if (sc->sc_flags.clocks_off && 130 sc->sc_flags.port_powered) { 131 132 DPRINTFN(5, "\n"); 133 134 /* turn on clocks */ 135 (sc->sc_clocks_on) (&sc->sc_bus); 136 137 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 138 ATMEGA_USBCON_USBE | 139 ATMEGA_USBCON_OTGPADE | 140 ATMEGA_USBCON_VBUSTE); 141 142 sc->sc_flags.clocks_off = 0; 143 144 /* enable transceiver ? */ 145 } 146 } 147 148 static void 149 atmegadci_clocks_off(struct atmegadci_softc *sc) 150 { 151 if (!sc->sc_flags.clocks_off) { 152 153 DPRINTFN(5, "\n"); 154 155 /* disable Transceiver ? */ 156 157 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 158 ATMEGA_USBCON_USBE | 159 ATMEGA_USBCON_OTGPADE | 160 ATMEGA_USBCON_FRZCLK | 161 ATMEGA_USBCON_VBUSTE); 162 163 /* turn clocks off */ 164 (sc->sc_clocks_off) (&sc->sc_bus); 165 166 sc->sc_flags.clocks_off = 1; 167 } 168 } 169 170 static void 171 atmegadci_pull_up(struct atmegadci_softc *sc) 172 { 173 /* pullup D+, if possible */ 174 175 if (!sc->sc_flags.d_pulled_up && 176 sc->sc_flags.port_powered) { 177 sc->sc_flags.d_pulled_up = 1; 178 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 179 } 180 } 181 182 static void 183 atmegadci_pull_down(struct atmegadci_softc *sc) 184 { 185 /* pulldown D+, if possible */ 186 187 if (sc->sc_flags.d_pulled_up) { 188 sc->sc_flags.d_pulled_up = 0; 189 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 190 } 191 } 192 193 static void 194 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 195 { 196 uint8_t temp; 197 198 if (!sc->sc_flags.status_suspend) { 199 return; 200 } 201 202 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 203 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 204 205 /* wait 8 milliseconds */ 206 /* Wait for reset to complete. */ 207 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 208 209 /* hardware should have cleared RMWKUP bit */ 210 } 211 212 static void 213 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 214 { 215 DPRINTFN(5, "addr=%d\n", addr); 216 217 addr |= ATMEGA_UDADDR_ADDEN; 218 219 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 220 } 221 222 static uint8_t 223 atmegadci_setup_rx(struct atmegadci_td *td) 224 { 225 struct atmegadci_softc *sc; 226 struct usb2_device_request req; 227 uint16_t count; 228 uint8_t temp; 229 230 /* get pointer to softc */ 231 sc = ATMEGA_PC2SC(td->pc); 232 233 /* select endpoint number */ 234 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 235 236 /* check endpoint status */ 237 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 238 239 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 240 241 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 242 goto not_complete; 243 } 244 /* clear did stall */ 245 td->did_stall = 0; 246 /* get the packet byte count */ 247 count = 248 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 249 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 250 251 /* mask away undefined bits */ 252 count &= 0x7FF; 253 254 /* verify data length */ 255 if (count != td->remainder) { 256 DPRINTFN(0, "Invalid SETUP packet " 257 "length, %d bytes\n", count); 258 goto not_complete; 259 } 260 if (count != sizeof(req)) { 261 DPRINTFN(0, "Unsupported SETUP packet " 262 "length, %d bytes\n", count); 263 goto not_complete; 264 } 265 /* receive data */ 266 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 267 (void *)&req, sizeof(req)); 268 269 /* copy data into real buffer */ 270 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 271 272 td->offset = sizeof(req); 273 td->remainder = 0; 274 275 /* sneak peek the set address */ 276 if ((req.bmRequestType == UT_WRITE_DEVICE) && 277 (req.bRequest == UR_SET_ADDRESS)) { 278 sc->sc_dv_addr = req.wValue[0] & 0x7F; 279 /* must write address before ZLP */ 280 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 281 } else { 282 sc->sc_dv_addr = 0xFF; 283 } 284 285 /* clear SETUP packet interrupt */ 286 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 287 return (0); /* complete */ 288 289 not_complete: 290 /* abort any ongoing transfer */ 291 if (!td->did_stall) { 292 DPRINTFN(5, "stalling\n"); 293 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 294 ATMEGA_UECONX_EPEN | 295 ATMEGA_UECONX_STALLRQ); 296 td->did_stall = 1; 297 } 298 if (temp & ATMEGA_UEINTX_RXSTPI) { 299 /* clear SETUP packet interrupt */ 300 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 301 } 302 /* we only want to know if there is a SETUP packet */ 303 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 304 return (1); /* not complete */ 305 } 306 307 static uint8_t 308 atmegadci_data_rx(struct atmegadci_td *td) 309 { 310 struct atmegadci_softc *sc; 311 struct usb2_page_search buf_res; 312 uint16_t count; 313 uint8_t temp; 314 uint8_t to; 315 uint8_t got_short; 316 317 to = 3; /* don't loop forever! */ 318 got_short = 0; 319 320 /* get pointer to softc */ 321 sc = ATMEGA_PC2SC(td->pc); 322 323 /* select endpoint number */ 324 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 325 326 repeat: 327 /* check if any of the FIFO banks have data */ 328 /* check endpoint status */ 329 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 330 331 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 332 333 if (temp & ATMEGA_UEINTX_RXSTPI) { 334 if (td->remainder == 0) { 335 /* 336 * We are actually complete and have 337 * received the next SETUP 338 */ 339 DPRINTFN(5, "faking complete\n"); 340 return (0); /* complete */ 341 } 342 /* 343 * USB Host Aborted the transfer. 344 */ 345 td->error = 1; 346 return (0); /* complete */ 347 } 348 /* check status */ 349 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 350 ATMEGA_UEINTX_RXOUTI))) { 351 /* no data */ 352 goto not_complete; 353 } 354 /* get the packet byte count */ 355 count = 356 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 357 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 358 359 /* mask away undefined bits */ 360 count &= 0x7FF; 361 362 /* verify the packet byte count */ 363 if (count != td->max_packet_size) { 364 if (count < td->max_packet_size) { 365 /* we have a short packet */ 366 td->short_pkt = 1; 367 got_short = 1; 368 } else { 369 /* invalid USB packet */ 370 td->error = 1; 371 return (0); /* we are complete */ 372 } 373 } 374 /* verify the packet byte count */ 375 if (count > td->remainder) { 376 /* invalid USB packet */ 377 td->error = 1; 378 return (0); /* we are complete */ 379 } 380 while (count > 0) { 381 usb2_get_page(td->pc, td->offset, &buf_res); 382 383 /* get correct length */ 384 if (buf_res.length > count) { 385 buf_res.length = count; 386 } 387 /* receive data */ 388 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 389 buf_res.buffer, buf_res.length); 390 391 /* update counters */ 392 count -= buf_res.length; 393 td->offset += buf_res.length; 394 td->remainder -= buf_res.length; 395 } 396 397 /* clear OUT packet interrupt */ 398 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 399 400 /* release FIFO bank */ 401 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 402 403 /* check if we are complete */ 404 if ((td->remainder == 0) || got_short) { 405 if (td->short_pkt) { 406 /* we are complete */ 407 return (0); 408 } 409 /* else need to receive a zero length packet */ 410 } 411 if (--to) { 412 goto repeat; 413 } 414 not_complete: 415 /* we only want to know if there is a SETUP packet or OUT packet */ 416 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 417 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 418 return (1); /* not complete */ 419 } 420 421 static uint8_t 422 atmegadci_data_tx(struct atmegadci_td *td) 423 { 424 struct atmegadci_softc *sc; 425 struct usb2_page_search buf_res; 426 uint16_t count; 427 uint8_t to; 428 uint8_t temp; 429 430 to = 3; /* don't loop forever! */ 431 432 /* get pointer to softc */ 433 sc = ATMEGA_PC2SC(td->pc); 434 435 /* select endpoint number */ 436 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 437 438 repeat: 439 440 /* check endpoint status */ 441 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 442 443 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 444 445 if (temp & ATMEGA_UEINTX_RXSTPI) { 446 /* 447 * The current transfer was aborted 448 * by the USB Host 449 */ 450 td->error = 1; 451 return (0); /* complete */ 452 } 453 454 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 455 if (temp & 3) { 456 /* cannot write any data - a bank is busy */ 457 goto not_complete; 458 } 459 460 count = td->max_packet_size; 461 if (td->remainder < count) { 462 /* we have a short packet */ 463 td->short_pkt = 1; 464 count = td->remainder; 465 } 466 while (count > 0) { 467 468 usb2_get_page(td->pc, td->offset, &buf_res); 469 470 /* get correct length */ 471 if (buf_res.length > count) { 472 buf_res.length = count; 473 } 474 /* transmit data */ 475 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 476 buf_res.buffer, buf_res.length); 477 478 /* update counters */ 479 count -= buf_res.length; 480 td->offset += buf_res.length; 481 td->remainder -= buf_res.length; 482 } 483 484 /* clear IN packet interrupt */ 485 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 486 487 /* allocate FIFO bank */ 488 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 489 490 /* check remainder */ 491 if (td->remainder == 0) { 492 if (td->short_pkt) { 493 return (0); /* complete */ 494 } 495 /* else we need to transmit a short packet */ 496 } 497 if (--to) { 498 goto repeat; 499 } 500 not_complete: 501 /* we only want to know if there is a SETUP packet or free IN packet */ 502 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 503 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 504 return (1); /* not complete */ 505 } 506 507 static uint8_t 508 atmegadci_data_tx_sync(struct atmegadci_td *td) 509 { 510 struct atmegadci_softc *sc; 511 uint8_t temp; 512 513 /* get pointer to softc */ 514 sc = ATMEGA_PC2SC(td->pc); 515 516 /* select endpoint number */ 517 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 518 519 /* check endpoint status */ 520 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 521 522 DPRINTFN(5, "temp=0x%02x\n", temp); 523 524 if (temp & ATMEGA_UEINTX_RXSTPI) { 525 DPRINTFN(5, "faking complete\n"); 526 /* Race condition */ 527 return (0); /* complete */ 528 } 529 /* 530 * The control endpoint has only got one bank, so if that bank 531 * is free the packet has been transferred! 532 */ 533 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 534 if (temp & 3) { 535 /* cannot write any data - a bank is busy */ 536 goto not_complete; 537 } 538 if (sc->sc_dv_addr != 0xFF) { 539 /* set new address */ 540 atmegadci_set_address(sc, sc->sc_dv_addr); 541 } 542 return (0); /* complete */ 543 544 not_complete: 545 /* we only want to know if there is a SETUP packet or free IN packet */ 546 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 547 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 548 return (1); /* not complete */ 549 } 550 551 static uint8_t 552 atmegadci_xfer_do_fifo(struct usb2_xfer *xfer) 553 { 554 struct atmegadci_td *td; 555 556 DPRINTFN(9, "\n"); 557 558 td = xfer->td_transfer_cache; 559 while (1) { 560 if ((td->func) (td)) { 561 /* operation in progress */ 562 break; 563 } 564 if (((void *)td) == xfer->td_transfer_last) { 565 goto done; 566 } 567 if (td->error) { 568 goto done; 569 } else if (td->remainder > 0) { 570 /* 571 * We had a short transfer. If there is no alternate 572 * next, stop processing ! 573 */ 574 if (!td->alt_next) { 575 goto done; 576 } 577 } 578 /* 579 * Fetch the next transfer descriptor and transfer 580 * some flags to the next transfer descriptor 581 */ 582 td = td->obj_next; 583 xfer->td_transfer_cache = td; 584 } 585 return (1); /* not complete */ 586 587 done: 588 /* compute all actual lengths */ 589 590 atmegadci_standard_done(xfer); 591 return (0); /* complete */ 592 } 593 594 static void 595 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 596 { 597 struct usb2_xfer *xfer; 598 599 repeat: 600 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 601 if (!atmegadci_xfer_do_fifo(xfer)) { 602 /* queue has been modified */ 603 goto repeat; 604 } 605 } 606 } 607 608 static void 609 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 610 { 611 DPRINTFN(5, "vbus = %u\n", is_on); 612 613 if (is_on) { 614 if (!sc->sc_flags.status_vbus) { 615 sc->sc_flags.status_vbus = 1; 616 617 /* complete root HUB interrupt endpoint */ 618 619 atmegadci_root_intr(sc); 620 } 621 } else { 622 if (sc->sc_flags.status_vbus) { 623 sc->sc_flags.status_vbus = 0; 624 sc->sc_flags.status_bus_reset = 0; 625 sc->sc_flags.status_suspend = 0; 626 sc->sc_flags.change_suspend = 0; 627 sc->sc_flags.change_connect = 1; 628 629 /* complete root HUB interrupt endpoint */ 630 631 atmegadci_root_intr(sc); 632 } 633 } 634 } 635 636 void 637 atmegadci_interrupt(struct atmegadci_softc *sc) 638 { 639 uint8_t status; 640 641 USB_BUS_LOCK(&sc->sc_bus); 642 643 /* read interrupt status */ 644 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 645 646 /* clear all set interrupts */ 647 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 648 649 DPRINTFN(14, "UDINT=0x%02x\n", status); 650 651 /* check for any bus state change interrupts */ 652 if (status & ATMEGA_UDINT_EORSTI) { 653 654 DPRINTFN(5, "end of reset\n"); 655 656 /* set correct state */ 657 sc->sc_flags.status_bus_reset = 1; 658 sc->sc_flags.status_suspend = 0; 659 sc->sc_flags.change_suspend = 0; 660 sc->sc_flags.change_connect = 1; 661 662 /* disable resume interrupt */ 663 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 664 ATMEGA_UDINT_SUSPE | 665 ATMEGA_UDINT_EORSTE); 666 667 /* complete root HUB interrupt endpoint */ 668 atmegadci_root_intr(sc); 669 } 670 /* 671 * If resume and suspend is set at the same time we interpret 672 * that like RESUME. Resume is set when there is at least 3 673 * milliseconds of inactivity on the USB BUS. 674 */ 675 if (status & ATMEGA_UDINT_EORSMI) { 676 677 DPRINTFN(5, "resume interrupt\n"); 678 679 if (sc->sc_flags.status_suspend) { 680 /* update status bits */ 681 sc->sc_flags.status_suspend = 0; 682 sc->sc_flags.change_suspend = 1; 683 684 /* disable resume interrupt */ 685 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 686 ATMEGA_UDINT_SUSPE | 687 ATMEGA_UDINT_EORSTE); 688 689 /* complete root HUB interrupt endpoint */ 690 atmegadci_root_intr(sc); 691 } 692 } else if (status & ATMEGA_UDINT_SUSPI) { 693 694 DPRINTFN(5, "suspend interrupt\n"); 695 696 if (!sc->sc_flags.status_suspend) { 697 /* update status bits */ 698 sc->sc_flags.status_suspend = 1; 699 sc->sc_flags.change_suspend = 1; 700 701 /* disable suspend interrupt */ 702 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 703 ATMEGA_UDINT_EORSMI | 704 ATMEGA_UDINT_EORSTE); 705 706 /* complete root HUB interrupt endpoint */ 707 atmegadci_root_intr(sc); 708 } 709 } 710 /* check VBUS */ 711 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 712 713 /* clear all set interrupts */ 714 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 715 716 if (status & ATMEGA_USBINT_VBUSTI) { 717 uint8_t temp; 718 719 DPRINTFN(5, "USBINT=0x%02x\n", status); 720 721 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 722 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 723 } 724 /* check for any endpoint interrupts */ 725 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 726 /* the hardware will clear the UEINT bits automatically */ 727 if (status) { 728 729 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 730 731 atmegadci_interrupt_poll(sc); 732 } 733 USB_BUS_UNLOCK(&sc->sc_bus); 734 } 735 736 static void 737 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 738 { 739 struct atmegadci_td *td; 740 741 /* get current Transfer Descriptor */ 742 td = temp->td_next; 743 temp->td = td; 744 745 /* prepare for next TD */ 746 temp->td_next = td->obj_next; 747 748 /* fill out the Transfer Descriptor */ 749 td->func = temp->func; 750 td->pc = temp->pc; 751 td->offset = temp->offset; 752 td->remainder = temp->len; 753 td->error = 0; 754 td->did_stall = 0; 755 td->short_pkt = temp->short_pkt; 756 td->alt_next = temp->setup_alt_next; 757 } 758 759 static void 760 atmegadci_setup_standard_chain(struct usb2_xfer *xfer) 761 { 762 struct atmegadci_std_temp temp; 763 struct atmegadci_softc *sc; 764 struct atmegadci_td *td; 765 uint32_t x; 766 uint8_t ep_no; 767 uint8_t need_sync; 768 769 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 770 xfer->address, UE_GET_ADDR(xfer->endpoint), 771 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 772 773 temp.max_frame_size = xfer->max_frame_size; 774 775 td = xfer->td_start[0]; 776 xfer->td_transfer_first = td; 777 xfer->td_transfer_cache = td; 778 779 /* setup temp */ 780 781 temp.td = NULL; 782 temp.td_next = xfer->td_start[0]; 783 temp.offset = 0; 784 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 785 786 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 787 ep_no = (xfer->endpoint & UE_ADDR); 788 789 /* check if we should prepend a setup message */ 790 791 if (xfer->flags_int.control_xfr) { 792 if (xfer->flags_int.control_hdr) { 793 794 temp.func = &atmegadci_setup_rx; 795 temp.len = xfer->frlengths[0]; 796 temp.pc = xfer->frbuffers + 0; 797 temp.short_pkt = temp.len ? 1 : 0; 798 /* check for last frame */ 799 if (xfer->nframes == 1) { 800 /* no STATUS stage yet, SETUP is last */ 801 if (xfer->flags_int.control_act) 802 temp.setup_alt_next = 0; 803 } 804 805 atmegadci_setup_standard_chain_sub(&temp); 806 } 807 x = 1; 808 } else { 809 x = 0; 810 } 811 812 if (x != xfer->nframes) { 813 if (xfer->endpoint & UE_DIR_IN) { 814 temp.func = &atmegadci_data_tx; 815 need_sync = 1; 816 } else { 817 temp.func = &atmegadci_data_rx; 818 need_sync = 0; 819 } 820 821 /* setup "pc" pointer */ 822 temp.pc = xfer->frbuffers + x; 823 } else { 824 need_sync = 0; 825 } 826 while (x != xfer->nframes) { 827 828 /* DATA0 / DATA1 message */ 829 830 temp.len = xfer->frlengths[x]; 831 832 x++; 833 834 if (x == xfer->nframes) { 835 if (xfer->flags_int.control_xfr) { 836 if (xfer->flags_int.control_act) { 837 temp.setup_alt_next = 0; 838 } 839 } else { 840 temp.setup_alt_next = 0; 841 } 842 } 843 if (temp.len == 0) { 844 845 /* make sure that we send an USB packet */ 846 847 temp.short_pkt = 0; 848 849 } else { 850 851 /* regular data transfer */ 852 853 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 854 } 855 856 atmegadci_setup_standard_chain_sub(&temp); 857 858 if (xfer->flags_int.isochronous_xfr) { 859 temp.offset += temp.len; 860 } else { 861 /* get next Page Cache pointer */ 862 temp.pc = xfer->frbuffers + x; 863 } 864 } 865 866 if (xfer->flags_int.control_xfr) { 867 868 /* always setup a valid "pc" pointer for status and sync */ 869 temp.pc = xfer->frbuffers + 0; 870 temp.len = 0; 871 temp.short_pkt = 0; 872 temp.setup_alt_next = 0; 873 874 /* check if we need to sync */ 875 if (need_sync) { 876 /* we need a SYNC point after TX */ 877 temp.func = &atmegadci_data_tx_sync; 878 atmegadci_setup_standard_chain_sub(&temp); 879 } 880 881 /* check if we should append a status stage */ 882 if (!xfer->flags_int.control_act) { 883 884 /* 885 * Send a DATA1 message and invert the current 886 * endpoint direction. 887 */ 888 if (xfer->endpoint & UE_DIR_IN) { 889 temp.func = &atmegadci_data_rx; 890 need_sync = 0; 891 } else { 892 temp.func = &atmegadci_data_tx; 893 need_sync = 1; 894 } 895 896 atmegadci_setup_standard_chain_sub(&temp); 897 if (need_sync) { 898 /* we need a SYNC point after TX */ 899 temp.func = &atmegadci_data_tx_sync; 900 atmegadci_setup_standard_chain_sub(&temp); 901 } 902 } 903 } 904 /* must have at least one frame! */ 905 td = temp.td; 906 xfer->td_transfer_last = td; 907 } 908 909 static void 910 atmegadci_timeout(void *arg) 911 { 912 struct usb2_xfer *xfer = arg; 913 914 DPRINTF("xfer=%p\n", xfer); 915 916 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 917 918 /* transfer is transferred */ 919 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 920 } 921 922 static void 923 atmegadci_start_standard_chain(struct usb2_xfer *xfer) 924 { 925 DPRINTFN(9, "\n"); 926 927 /* poll one time - will turn on interrupts */ 928 if (atmegadci_xfer_do_fifo(xfer)) { 929 930 /* put transfer on interrupt queue */ 931 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 932 933 /* start timeout, if any */ 934 if (xfer->timeout != 0) { 935 usb2_transfer_timeout_ms(xfer, 936 &atmegadci_timeout, xfer->timeout); 937 } 938 } 939 } 940 941 static void 942 atmegadci_root_intr(struct atmegadci_softc *sc) 943 { 944 DPRINTFN(9, "\n"); 945 946 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 947 948 /* set port bit */ 949 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 950 951 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 952 sizeof(sc->sc_hub_idata)); 953 } 954 955 static usb2_error_t 956 atmegadci_standard_done_sub(struct usb2_xfer *xfer) 957 { 958 struct atmegadci_td *td; 959 uint32_t len; 960 uint8_t error; 961 962 DPRINTFN(9, "\n"); 963 964 td = xfer->td_transfer_cache; 965 966 do { 967 len = td->remainder; 968 969 if (xfer->aframes != xfer->nframes) { 970 /* 971 * Verify the length and subtract 972 * the remainder from "frlengths[]": 973 */ 974 if (len > xfer->frlengths[xfer->aframes]) { 975 td->error = 1; 976 } else { 977 xfer->frlengths[xfer->aframes] -= len; 978 } 979 } 980 /* Check for transfer error */ 981 if (td->error) { 982 /* the transfer is finished */ 983 error = 1; 984 td = NULL; 985 break; 986 } 987 /* Check for short transfer */ 988 if (len > 0) { 989 if (xfer->flags_int.short_frames_ok) { 990 /* follow alt next */ 991 if (td->alt_next) { 992 td = td->obj_next; 993 } else { 994 td = NULL; 995 } 996 } else { 997 /* the transfer is finished */ 998 td = NULL; 999 } 1000 error = 0; 1001 break; 1002 } 1003 td = td->obj_next; 1004 1005 /* this USB frame is complete */ 1006 error = 0; 1007 break; 1008 1009 } while (0); 1010 1011 /* update transfer cache */ 1012 1013 xfer->td_transfer_cache = td; 1014 1015 return (error ? 1016 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1017 } 1018 1019 static void 1020 atmegadci_standard_done(struct usb2_xfer *xfer) 1021 { 1022 usb2_error_t err = 0; 1023 1024 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1025 xfer, xfer->pipe); 1026 1027 /* reset scanner */ 1028 1029 xfer->td_transfer_cache = xfer->td_transfer_first; 1030 1031 if (xfer->flags_int.control_xfr) { 1032 1033 if (xfer->flags_int.control_hdr) { 1034 1035 err = atmegadci_standard_done_sub(xfer); 1036 } 1037 xfer->aframes = 1; 1038 1039 if (xfer->td_transfer_cache == NULL) { 1040 goto done; 1041 } 1042 } 1043 while (xfer->aframes != xfer->nframes) { 1044 1045 err = atmegadci_standard_done_sub(xfer); 1046 xfer->aframes++; 1047 1048 if (xfer->td_transfer_cache == NULL) { 1049 goto done; 1050 } 1051 } 1052 1053 if (xfer->flags_int.control_xfr && 1054 !xfer->flags_int.control_act) { 1055 1056 err = atmegadci_standard_done_sub(xfer); 1057 } 1058 done: 1059 atmegadci_device_done(xfer, err); 1060 } 1061 1062 /*------------------------------------------------------------------------* 1063 * atmegadci_device_done 1064 * 1065 * NOTE: this function can be called more than one time on the 1066 * same USB transfer! 1067 *------------------------------------------------------------------------*/ 1068 static void 1069 atmegadci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1070 { 1071 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1072 uint8_t ep_no; 1073 1074 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1075 1076 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n", 1077 xfer, xfer->pipe, error); 1078 1079 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1080 ep_no = (xfer->endpoint & UE_ADDR); 1081 1082 /* select endpoint number */ 1083 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1084 1085 /* disable endpoint interrupt */ 1086 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1087 1088 DPRINTFN(15, "disabled interrupts!\n"); 1089 } 1090 /* dequeue transfer and start next transfer */ 1091 usb2_transfer_done(xfer, error); 1092 } 1093 1094 static void 1095 atmegadci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1096 struct usb2_pipe *pipe) 1097 { 1098 struct atmegadci_softc *sc; 1099 uint8_t ep_no; 1100 1101 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1102 1103 DPRINTFN(5, "pipe=%p\n", pipe); 1104 1105 if (xfer) { 1106 /* cancel any ongoing transfers */ 1107 atmegadci_device_done(xfer, USB_ERR_STALLED); 1108 } 1109 sc = ATMEGA_BUS2SC(udev->bus); 1110 /* get endpoint number */ 1111 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1112 /* select endpoint number */ 1113 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1114 /* set stall */ 1115 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1116 ATMEGA_UECONX_EPEN | 1117 ATMEGA_UECONX_STALLRQ); 1118 } 1119 1120 static void 1121 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1122 uint8_t ep_type, uint8_t ep_dir) 1123 { 1124 uint8_t temp; 1125 1126 if (ep_type == UE_CONTROL) { 1127 /* clearing stall is not needed */ 1128 return; 1129 } 1130 /* select endpoint number */ 1131 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1132 1133 /* set endpoint reset */ 1134 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1135 1136 /* clear endpoint reset */ 1137 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1138 1139 /* set stall */ 1140 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1141 ATMEGA_UECONX_EPEN | 1142 ATMEGA_UECONX_STALLRQ); 1143 1144 /* reset data toggle */ 1145 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1146 ATMEGA_UECONX_EPEN | 1147 ATMEGA_UECONX_RSTDT); 1148 1149 /* clear stall */ 1150 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1151 ATMEGA_UECONX_EPEN | 1152 ATMEGA_UECONX_STALLRQC); 1153 1154 do { 1155 temp = 0; 1156 if (ep_type == UE_BULK) { 1157 temp |= ATMEGA_UECFG0X_EPTYPE2; 1158 } else if (ep_type == UE_INTERRUPT) { 1159 temp |= ATMEGA_UECFG0X_EPTYPE3; 1160 } else { 1161 temp |= ATMEGA_UECFG0X_EPTYPE1; 1162 } 1163 if (ep_dir & UE_DIR_IN) { 1164 temp |= ATMEGA_UECFG0X_EPDIR; 1165 } 1166 /* two banks, 64-bytes wMaxPacket */ 1167 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1168 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1169 ATMEGA_UECFG1X_ALLOC | 1170 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1171 ATMEGA_UECFG1X_EPSIZE(3)); 1172 1173 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1174 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1175 DPRINTFN(0, "Chip rejected configuration\n"); 1176 } 1177 } while (0); 1178 } 1179 1180 static void 1181 atmegadci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1182 { 1183 struct atmegadci_softc *sc; 1184 struct usb2_endpoint_descriptor *ed; 1185 1186 DPRINTFN(5, "pipe=%p\n", pipe); 1187 1188 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1189 1190 /* check mode */ 1191 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1192 /* not supported */ 1193 return; 1194 } 1195 /* get softc */ 1196 sc = ATMEGA_BUS2SC(udev->bus); 1197 1198 /* get endpoint descriptor */ 1199 ed = pipe->edesc; 1200 1201 /* reset endpoint */ 1202 atmegadci_clear_stall_sub(sc, 1203 (ed->bEndpointAddress & UE_ADDR), 1204 (ed->bmAttributes & UE_XFERTYPE), 1205 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1206 } 1207 1208 usb2_error_t 1209 atmegadci_init(struct atmegadci_softc *sc) 1210 { 1211 uint8_t n; 1212 1213 DPRINTF("start\n"); 1214 1215 /* set up the bus structure */ 1216 sc->sc_bus.usbrev = USB_REV_1_1; 1217 sc->sc_bus.methods = &atmegadci_bus_methods; 1218 1219 USB_BUS_LOCK(&sc->sc_bus); 1220 #if 0 1221 /* XXX TODO - currently done by boot strap */ 1222 1223 /* enable USB PAD regulator */ 1224 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1225 ATMEGA_UHWCON_UVREGE | ATMEGA_UHWCON_UIMOD); 1226 #endif 1227 /* make sure USB is enabled */ 1228 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1229 ATMEGA_USBCON_USBE | 1230 ATMEGA_USBCON_OTGPADE | 1231 ATMEGA_USBCON_VBUSTE); 1232 1233 /* turn on clocks */ 1234 (sc->sc_clocks_on) (&sc->sc_bus); 1235 1236 /* make sure device is re-enumerated */ 1237 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1238 1239 /* wait a little for things to stabilise */ 1240 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1241 1242 /* enable interrupts */ 1243 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1244 ATMEGA_UDINT_SUSPE | 1245 ATMEGA_UDINT_EORSTE); 1246 1247 /* reset all endpoints */ 1248 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1249 (1 << ATMEGA_EP_MAX) - 1); 1250 1251 /* disable reset */ 1252 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1253 1254 /* disable all endpoints */ 1255 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1256 1257 /* select endpoint */ 1258 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1259 1260 /* disable endpoint interrupt */ 1261 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1262 1263 /* disable endpoint */ 1264 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1265 } 1266 1267 /* turn off clocks */ 1268 1269 atmegadci_clocks_off(sc); 1270 1271 /* read initial VBUS state */ 1272 1273 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1274 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1275 1276 USB_BUS_UNLOCK(&sc->sc_bus); 1277 1278 /* catch any lost interrupts */ 1279 1280 atmegadci_do_poll(&sc->sc_bus); 1281 1282 return (0); /* success */ 1283 } 1284 1285 void 1286 atmegadci_uninit(struct atmegadci_softc *sc) 1287 { 1288 USB_BUS_LOCK(&sc->sc_bus); 1289 1290 /* turn on clocks */ 1291 (sc->sc_clocks_on) (&sc->sc_bus); 1292 1293 /* disable interrupts */ 1294 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1295 1296 /* reset all endpoints */ 1297 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1298 (1 << ATMEGA_EP_MAX) - 1); 1299 1300 /* disable reset */ 1301 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1302 1303 sc->sc_flags.port_powered = 0; 1304 sc->sc_flags.status_vbus = 0; 1305 sc->sc_flags.status_bus_reset = 0; 1306 sc->sc_flags.status_suspend = 0; 1307 sc->sc_flags.change_suspend = 0; 1308 sc->sc_flags.change_connect = 1; 1309 1310 atmegadci_pull_down(sc); 1311 atmegadci_clocks_off(sc); 1312 1313 /* disable USB PAD regulator */ 1314 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1315 1316 USB_BUS_UNLOCK(&sc->sc_bus); 1317 } 1318 1319 void 1320 atmegadci_suspend(struct atmegadci_softc *sc) 1321 { 1322 return; 1323 } 1324 1325 void 1326 atmegadci_resume(struct atmegadci_softc *sc) 1327 { 1328 return; 1329 } 1330 1331 static void 1332 atmegadci_do_poll(struct usb2_bus *bus) 1333 { 1334 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1335 1336 USB_BUS_LOCK(&sc->sc_bus); 1337 atmegadci_interrupt_poll(sc); 1338 USB_BUS_UNLOCK(&sc->sc_bus); 1339 } 1340 1341 /*------------------------------------------------------------------------* 1342 * at91dci bulk support 1343 * at91dci control support 1344 * at91dci interrupt support 1345 *------------------------------------------------------------------------*/ 1346 static void 1347 atmegadci_device_non_isoc_open(struct usb2_xfer *xfer) 1348 { 1349 return; 1350 } 1351 1352 static void 1353 atmegadci_device_non_isoc_close(struct usb2_xfer *xfer) 1354 { 1355 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1356 } 1357 1358 static void 1359 atmegadci_device_non_isoc_enter(struct usb2_xfer *xfer) 1360 { 1361 return; 1362 } 1363 1364 static void 1365 atmegadci_device_non_isoc_start(struct usb2_xfer *xfer) 1366 { 1367 /* setup TDs */ 1368 atmegadci_setup_standard_chain(xfer); 1369 atmegadci_start_standard_chain(xfer); 1370 } 1371 1372 struct usb2_pipe_methods atmegadci_device_non_isoc_methods = 1373 { 1374 .open = atmegadci_device_non_isoc_open, 1375 .close = atmegadci_device_non_isoc_close, 1376 .enter = atmegadci_device_non_isoc_enter, 1377 .start = atmegadci_device_non_isoc_start, 1378 }; 1379 1380 /*------------------------------------------------------------------------* 1381 * at91dci full speed isochronous support 1382 *------------------------------------------------------------------------*/ 1383 static void 1384 atmegadci_device_isoc_fs_open(struct usb2_xfer *xfer) 1385 { 1386 return; 1387 } 1388 1389 static void 1390 atmegadci_device_isoc_fs_close(struct usb2_xfer *xfer) 1391 { 1392 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1393 } 1394 1395 static void 1396 atmegadci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1397 { 1398 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1399 uint32_t temp; 1400 uint32_t nframes; 1401 1402 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1403 xfer, xfer->pipe->isoc_next, xfer->nframes); 1404 1405 /* get the current frame index */ 1406 1407 nframes = 1408 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1409 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1410 1411 nframes &= ATMEGA_FRAME_MASK; 1412 1413 /* 1414 * check if the frame index is within the window where the frames 1415 * will be inserted 1416 */ 1417 temp = (nframes - xfer->pipe->isoc_next) & ATMEGA_FRAME_MASK; 1418 1419 if ((xfer->pipe->is_synced == 0) || 1420 (temp < xfer->nframes)) { 1421 /* 1422 * If there is data underflow or the pipe queue is 1423 * empty we schedule the transfer a few frames ahead 1424 * of the current frame position. Else two isochronous 1425 * transfers might overlap. 1426 */ 1427 xfer->pipe->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1428 xfer->pipe->is_synced = 1; 1429 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1430 } 1431 /* 1432 * compute how many milliseconds the insertion is ahead of the 1433 * current frame position: 1434 */ 1435 temp = (xfer->pipe->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1436 1437 /* 1438 * pre-compute when the isochronous transfer will be finished: 1439 */ 1440 xfer->isoc_time_complete = 1441 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1442 xfer->nframes; 1443 1444 /* compute frame number for next insertion */ 1445 xfer->pipe->isoc_next += xfer->nframes; 1446 1447 /* setup TDs */ 1448 atmegadci_setup_standard_chain(xfer); 1449 } 1450 1451 static void 1452 atmegadci_device_isoc_fs_start(struct usb2_xfer *xfer) 1453 { 1454 /* start TD chain */ 1455 atmegadci_start_standard_chain(xfer); 1456 } 1457 1458 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods = 1459 { 1460 .open = atmegadci_device_isoc_fs_open, 1461 .close = atmegadci_device_isoc_fs_close, 1462 .enter = atmegadci_device_isoc_fs_enter, 1463 .start = atmegadci_device_isoc_fs_start, 1464 }; 1465 1466 /*------------------------------------------------------------------------* 1467 * at91dci root control support 1468 *------------------------------------------------------------------------* 1469 * Simulate a hardware HUB by handling all the necessary requests. 1470 *------------------------------------------------------------------------*/ 1471 1472 static const struct usb2_device_descriptor atmegadci_devd = { 1473 .bLength = sizeof(struct usb2_device_descriptor), 1474 .bDescriptorType = UDESC_DEVICE, 1475 .bcdUSB = {0x00, 0x02}, 1476 .bDeviceClass = UDCLASS_HUB, 1477 .bDeviceSubClass = UDSUBCLASS_HUB, 1478 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1479 .bMaxPacketSize = 64, 1480 .bcdDevice = {0x00, 0x01}, 1481 .iManufacturer = 1, 1482 .iProduct = 2, 1483 .bNumConfigurations = 1, 1484 }; 1485 1486 static const struct usb2_device_qualifier atmegadci_odevd = { 1487 .bLength = sizeof(struct usb2_device_qualifier), 1488 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1489 .bcdUSB = {0x00, 0x02}, 1490 .bDeviceClass = UDCLASS_HUB, 1491 .bDeviceSubClass = UDSUBCLASS_HUB, 1492 .bDeviceProtocol = UDPROTO_FSHUB, 1493 .bMaxPacketSize0 = 0, 1494 .bNumConfigurations = 0, 1495 }; 1496 1497 static const struct atmegadci_config_desc atmegadci_confd = { 1498 .confd = { 1499 .bLength = sizeof(struct usb2_config_descriptor), 1500 .bDescriptorType = UDESC_CONFIG, 1501 .wTotalLength[0] = sizeof(atmegadci_confd), 1502 .bNumInterface = 1, 1503 .bConfigurationValue = 1, 1504 .iConfiguration = 0, 1505 .bmAttributes = UC_SELF_POWERED, 1506 .bMaxPower = 0, 1507 }, 1508 .ifcd = { 1509 .bLength = sizeof(struct usb2_interface_descriptor), 1510 .bDescriptorType = UDESC_INTERFACE, 1511 .bNumEndpoints = 1, 1512 .bInterfaceClass = UICLASS_HUB, 1513 .bInterfaceSubClass = UISUBCLASS_HUB, 1514 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1515 }, 1516 .endpd = { 1517 .bLength = sizeof(struct usb2_endpoint_descriptor), 1518 .bDescriptorType = UDESC_ENDPOINT, 1519 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1520 .bmAttributes = UE_INTERRUPT, 1521 .wMaxPacketSize[0] = 8, 1522 .bInterval = 255, 1523 }, 1524 }; 1525 1526 static const struct usb2_hub_descriptor_min atmegadci_hubd = { 1527 .bDescLength = sizeof(atmegadci_hubd), 1528 .bDescriptorType = UDESC_HUB, 1529 .bNbrPorts = 1, 1530 .wHubCharacteristics[0] = 1531 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1532 .wHubCharacteristics[1] = 1533 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1534 .bPwrOn2PwrGood = 50, 1535 .bHubContrCurrent = 0, 1536 .DeviceRemovable = {0}, /* port is removable */ 1537 }; 1538 1539 #define STRING_LANG \ 1540 0x09, 0x04, /* American English */ 1541 1542 #define STRING_VENDOR \ 1543 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1544 1545 #define STRING_PRODUCT \ 1546 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1547 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1548 'U', 0, 'B', 0, 1549 1550 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1551 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1552 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1553 1554 static usb2_error_t 1555 atmegadci_roothub_exec(struct usb2_device *udev, 1556 struct usb2_device_request *req, const void **pptr, uint16_t *plength) 1557 { 1558 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1559 const void *ptr; 1560 uint16_t len; 1561 uint16_t value; 1562 uint16_t index; 1563 uint8_t temp; 1564 usb2_error_t err; 1565 1566 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1567 1568 /* buffer reset */ 1569 ptr = (const void *)&sc->sc_hub_temp; 1570 len = 0; 1571 err = 0; 1572 1573 value = UGETW(req->wValue); 1574 index = UGETW(req->wIndex); 1575 1576 /* demultiplex the control request */ 1577 1578 switch (req->bmRequestType) { 1579 case UT_READ_DEVICE: 1580 switch (req->bRequest) { 1581 case UR_GET_DESCRIPTOR: 1582 goto tr_handle_get_descriptor; 1583 case UR_GET_CONFIG: 1584 goto tr_handle_get_config; 1585 case UR_GET_STATUS: 1586 goto tr_handle_get_status; 1587 default: 1588 goto tr_stalled; 1589 } 1590 break; 1591 1592 case UT_WRITE_DEVICE: 1593 switch (req->bRequest) { 1594 case UR_SET_ADDRESS: 1595 goto tr_handle_set_address; 1596 case UR_SET_CONFIG: 1597 goto tr_handle_set_config; 1598 case UR_CLEAR_FEATURE: 1599 goto tr_valid; /* nop */ 1600 case UR_SET_DESCRIPTOR: 1601 goto tr_valid; /* nop */ 1602 case UR_SET_FEATURE: 1603 default: 1604 goto tr_stalled; 1605 } 1606 break; 1607 1608 case UT_WRITE_ENDPOINT: 1609 switch (req->bRequest) { 1610 case UR_CLEAR_FEATURE: 1611 switch (UGETW(req->wValue)) { 1612 case UF_ENDPOINT_HALT: 1613 goto tr_handle_clear_halt; 1614 case UF_DEVICE_REMOTE_WAKEUP: 1615 goto tr_handle_clear_wakeup; 1616 default: 1617 goto tr_stalled; 1618 } 1619 break; 1620 case UR_SET_FEATURE: 1621 switch (UGETW(req->wValue)) { 1622 case UF_ENDPOINT_HALT: 1623 goto tr_handle_set_halt; 1624 case UF_DEVICE_REMOTE_WAKEUP: 1625 goto tr_handle_set_wakeup; 1626 default: 1627 goto tr_stalled; 1628 } 1629 break; 1630 case UR_SYNCH_FRAME: 1631 goto tr_valid; /* nop */ 1632 default: 1633 goto tr_stalled; 1634 } 1635 break; 1636 1637 case UT_READ_ENDPOINT: 1638 switch (req->bRequest) { 1639 case UR_GET_STATUS: 1640 goto tr_handle_get_ep_status; 1641 default: 1642 goto tr_stalled; 1643 } 1644 break; 1645 1646 case UT_WRITE_INTERFACE: 1647 switch (req->bRequest) { 1648 case UR_SET_INTERFACE: 1649 goto tr_handle_set_interface; 1650 case UR_CLEAR_FEATURE: 1651 goto tr_valid; /* nop */ 1652 case UR_SET_FEATURE: 1653 default: 1654 goto tr_stalled; 1655 } 1656 break; 1657 1658 case UT_READ_INTERFACE: 1659 switch (req->bRequest) { 1660 case UR_GET_INTERFACE: 1661 goto tr_handle_get_interface; 1662 case UR_GET_STATUS: 1663 goto tr_handle_get_iface_status; 1664 default: 1665 goto tr_stalled; 1666 } 1667 break; 1668 1669 case UT_WRITE_CLASS_INTERFACE: 1670 case UT_WRITE_VENDOR_INTERFACE: 1671 /* XXX forward */ 1672 break; 1673 1674 case UT_READ_CLASS_INTERFACE: 1675 case UT_READ_VENDOR_INTERFACE: 1676 /* XXX forward */ 1677 break; 1678 1679 case UT_WRITE_CLASS_DEVICE: 1680 switch (req->bRequest) { 1681 case UR_CLEAR_FEATURE: 1682 goto tr_valid; 1683 case UR_SET_DESCRIPTOR: 1684 case UR_SET_FEATURE: 1685 break; 1686 default: 1687 goto tr_stalled; 1688 } 1689 break; 1690 1691 case UT_WRITE_CLASS_OTHER: 1692 switch (req->bRequest) { 1693 case UR_CLEAR_FEATURE: 1694 goto tr_handle_clear_port_feature; 1695 case UR_SET_FEATURE: 1696 goto tr_handle_set_port_feature; 1697 case UR_CLEAR_TT_BUFFER: 1698 case UR_RESET_TT: 1699 case UR_STOP_TT: 1700 goto tr_valid; 1701 1702 default: 1703 goto tr_stalled; 1704 } 1705 break; 1706 1707 case UT_READ_CLASS_OTHER: 1708 switch (req->bRequest) { 1709 case UR_GET_TT_STATE: 1710 goto tr_handle_get_tt_state; 1711 case UR_GET_STATUS: 1712 goto tr_handle_get_port_status; 1713 default: 1714 goto tr_stalled; 1715 } 1716 break; 1717 1718 case UT_READ_CLASS_DEVICE: 1719 switch (req->bRequest) { 1720 case UR_GET_DESCRIPTOR: 1721 goto tr_handle_get_class_descriptor; 1722 case UR_GET_STATUS: 1723 goto tr_handle_get_class_status; 1724 1725 default: 1726 goto tr_stalled; 1727 } 1728 break; 1729 default: 1730 goto tr_stalled; 1731 } 1732 goto tr_valid; 1733 1734 tr_handle_get_descriptor: 1735 switch (value >> 8) { 1736 case UDESC_DEVICE: 1737 if (value & 0xff) { 1738 goto tr_stalled; 1739 } 1740 len = sizeof(atmegadci_devd); 1741 ptr = (const void *)&atmegadci_devd; 1742 goto tr_valid; 1743 case UDESC_CONFIG: 1744 if (value & 0xff) { 1745 goto tr_stalled; 1746 } 1747 len = sizeof(atmegadci_confd); 1748 ptr = (const void *)&atmegadci_confd; 1749 goto tr_valid; 1750 case UDESC_STRING: 1751 switch (value & 0xff) { 1752 case 0: /* Language table */ 1753 len = sizeof(atmegadci_langtab); 1754 ptr = (const void *)&atmegadci_langtab; 1755 goto tr_valid; 1756 1757 case 1: /* Vendor */ 1758 len = sizeof(atmegadci_vendor); 1759 ptr = (const void *)&atmegadci_vendor; 1760 goto tr_valid; 1761 1762 case 2: /* Product */ 1763 len = sizeof(atmegadci_product); 1764 ptr = (const void *)&atmegadci_product; 1765 goto tr_valid; 1766 default: 1767 break; 1768 } 1769 break; 1770 default: 1771 goto tr_stalled; 1772 } 1773 goto tr_stalled; 1774 1775 tr_handle_get_config: 1776 len = 1; 1777 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1778 goto tr_valid; 1779 1780 tr_handle_get_status: 1781 len = 2; 1782 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1783 goto tr_valid; 1784 1785 tr_handle_set_address: 1786 if (value & 0xFF00) { 1787 goto tr_stalled; 1788 } 1789 sc->sc_rt_addr = value; 1790 goto tr_valid; 1791 1792 tr_handle_set_config: 1793 if (value >= 2) { 1794 goto tr_stalled; 1795 } 1796 sc->sc_conf = value; 1797 goto tr_valid; 1798 1799 tr_handle_get_interface: 1800 len = 1; 1801 sc->sc_hub_temp.wValue[0] = 0; 1802 goto tr_valid; 1803 1804 tr_handle_get_tt_state: 1805 tr_handle_get_class_status: 1806 tr_handle_get_iface_status: 1807 tr_handle_get_ep_status: 1808 len = 2; 1809 USETW(sc->sc_hub_temp.wValue, 0); 1810 goto tr_valid; 1811 1812 tr_handle_set_halt: 1813 tr_handle_set_interface: 1814 tr_handle_set_wakeup: 1815 tr_handle_clear_wakeup: 1816 tr_handle_clear_halt: 1817 goto tr_valid; 1818 1819 tr_handle_clear_port_feature: 1820 if (index != 1) { 1821 goto tr_stalled; 1822 } 1823 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1824 1825 switch (value) { 1826 case UHF_PORT_SUSPEND: 1827 atmegadci_wakeup_peer(sc); 1828 break; 1829 1830 case UHF_PORT_ENABLE: 1831 sc->sc_flags.port_enabled = 0; 1832 break; 1833 1834 case UHF_PORT_TEST: 1835 case UHF_PORT_INDICATOR: 1836 case UHF_C_PORT_ENABLE: 1837 case UHF_C_PORT_OVER_CURRENT: 1838 case UHF_C_PORT_RESET: 1839 /* nops */ 1840 break; 1841 case UHF_PORT_POWER: 1842 sc->sc_flags.port_powered = 0; 1843 atmegadci_pull_down(sc); 1844 atmegadci_clocks_off(sc); 1845 break; 1846 case UHF_C_PORT_CONNECTION: 1847 /* clear connect change flag */ 1848 sc->sc_flags.change_connect = 0; 1849 1850 /* configure the control endpoint */ 1851 1852 /* select endpoint number */ 1853 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1854 1855 /* set endpoint reset */ 1856 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1857 1858 /* clear endpoint reset */ 1859 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1860 1861 /* enable and stall endpoint */ 1862 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1863 ATMEGA_UECONX_EPEN | 1864 ATMEGA_UECONX_STALLRQ); 1865 1866 /* one bank, 64-bytes wMaxPacket */ 1867 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1868 ATMEGA_UECFG0X_EPTYPE0); 1869 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1870 ATMEGA_UECFG1X_ALLOC | 1871 ATMEGA_UECFG1X_EPBK0 | 1872 ATMEGA_UECFG1X_EPSIZE(3)); 1873 1874 /* check valid config */ 1875 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1876 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1877 DPRINTFN(0, "Chip rejected EP0 configuration\n"); 1878 } 1879 break; 1880 case UHF_C_PORT_SUSPEND: 1881 sc->sc_flags.change_suspend = 0; 1882 break; 1883 default: 1884 err = USB_ERR_IOERROR; 1885 goto done; 1886 } 1887 goto tr_valid; 1888 1889 tr_handle_set_port_feature: 1890 if (index != 1) { 1891 goto tr_stalled; 1892 } 1893 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1894 1895 switch (value) { 1896 case UHF_PORT_ENABLE: 1897 sc->sc_flags.port_enabled = 1; 1898 break; 1899 case UHF_PORT_SUSPEND: 1900 case UHF_PORT_RESET: 1901 case UHF_PORT_TEST: 1902 case UHF_PORT_INDICATOR: 1903 /* nops */ 1904 break; 1905 case UHF_PORT_POWER: 1906 sc->sc_flags.port_powered = 1; 1907 break; 1908 default: 1909 err = USB_ERR_IOERROR; 1910 goto done; 1911 } 1912 goto tr_valid; 1913 1914 tr_handle_get_port_status: 1915 1916 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1917 1918 if (index != 1) { 1919 goto tr_stalled; 1920 } 1921 if (sc->sc_flags.status_vbus) { 1922 atmegadci_clocks_on(sc); 1923 atmegadci_pull_up(sc); 1924 } else { 1925 atmegadci_pull_down(sc); 1926 atmegadci_clocks_off(sc); 1927 } 1928 1929 /* Select FULL-speed and Device Side Mode */ 1930 1931 value = UPS_PORT_MODE_DEVICE; 1932 1933 if (sc->sc_flags.port_powered) { 1934 value |= UPS_PORT_POWER; 1935 } 1936 if (sc->sc_flags.port_enabled) { 1937 value |= UPS_PORT_ENABLED; 1938 } 1939 if (sc->sc_flags.status_vbus && 1940 sc->sc_flags.status_bus_reset) { 1941 value |= UPS_CURRENT_CONNECT_STATUS; 1942 } 1943 if (sc->sc_flags.status_suspend) { 1944 value |= UPS_SUSPEND; 1945 } 1946 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1947 1948 value = 0; 1949 1950 if (sc->sc_flags.change_connect) { 1951 value |= UPS_C_CONNECT_STATUS; 1952 } 1953 if (sc->sc_flags.change_suspend) { 1954 value |= UPS_C_SUSPEND; 1955 } 1956 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1957 len = sizeof(sc->sc_hub_temp.ps); 1958 goto tr_valid; 1959 1960 tr_handle_get_class_descriptor: 1961 if (value & 0xFF) { 1962 goto tr_stalled; 1963 } 1964 ptr = (const void *)&atmegadci_hubd; 1965 len = sizeof(atmegadci_hubd); 1966 goto tr_valid; 1967 1968 tr_stalled: 1969 err = USB_ERR_STALLED; 1970 tr_valid: 1971 done: 1972 *plength = len; 1973 *pptr = ptr; 1974 return (err); 1975 } 1976 1977 static void 1978 atmegadci_xfer_setup(struct usb2_setup_params *parm) 1979 { 1980 const struct usb2_hw_ep_profile *pf; 1981 struct atmegadci_softc *sc; 1982 struct usb2_xfer *xfer; 1983 void *last_obj; 1984 uint32_t ntd; 1985 uint32_t n; 1986 uint8_t ep_no; 1987 1988 sc = ATMEGA_BUS2SC(parm->udev->bus); 1989 xfer = parm->curr_xfer; 1990 1991 /* 1992 * NOTE: This driver does not use any of the parameters that 1993 * are computed from the following values. Just set some 1994 * reasonable dummies: 1995 */ 1996 parm->hc_max_packet_size = 0x500; 1997 parm->hc_max_packet_count = 1; 1998 parm->hc_max_frame_size = 0x500; 1999 2000 usb2_transfer_setup_sub(parm); 2001 2002 /* 2003 * compute maximum number of TDs 2004 */ 2005 if ((xfer->pipe->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2006 2007 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2008 + 1 /* SYNC 2 */ ; 2009 } else { 2010 2011 ntd = xfer->nframes + 1 /* SYNC */ ; 2012 } 2013 2014 /* 2015 * check if "usb2_transfer_setup_sub" set an error 2016 */ 2017 if (parm->err) 2018 return; 2019 2020 /* 2021 * allocate transfer descriptors 2022 */ 2023 last_obj = NULL; 2024 2025 /* 2026 * get profile stuff 2027 */ 2028 ep_no = xfer->endpoint & UE_ADDR; 2029 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2030 2031 if (pf == NULL) { 2032 /* should not happen */ 2033 parm->err = USB_ERR_INVAL; 2034 return; 2035 } 2036 2037 /* align data */ 2038 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2039 2040 for (n = 0; n != ntd; n++) { 2041 2042 struct atmegadci_td *td; 2043 2044 if (parm->buf) { 2045 2046 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2047 2048 /* init TD */ 2049 td->max_packet_size = xfer->max_packet_size; 2050 td->ep_no = ep_no; 2051 if (pf->support_multi_buffer) { 2052 td->support_multi_buffer = 1; 2053 } 2054 td->obj_next = last_obj; 2055 2056 last_obj = td; 2057 } 2058 parm->size[0] += sizeof(*td); 2059 } 2060 2061 xfer->td_start[0] = last_obj; 2062 } 2063 2064 static void 2065 atmegadci_xfer_unsetup(struct usb2_xfer *xfer) 2066 { 2067 return; 2068 } 2069 2070 static void 2071 atmegadci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2072 struct usb2_pipe *pipe) 2073 { 2074 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2075 2076 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2077 pipe, udev->address, 2078 edesc->bEndpointAddress, udev->flags.usb2_mode, 2079 sc->sc_rt_addr, udev->device_index); 2080 2081 if (udev->device_index != sc->sc_rt_addr) { 2082 2083 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2084 /* not supported */ 2085 return; 2086 } 2087 if (udev->speed != USB_SPEED_FULL) { 2088 /* not supported */ 2089 return; 2090 } 2091 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2092 pipe->methods = &atmegadci_device_isoc_fs_methods; 2093 else 2094 pipe->methods = &atmegadci_device_non_isoc_methods; 2095 } 2096 } 2097 2098 struct usb2_bus_methods atmegadci_bus_methods = 2099 { 2100 .pipe_init = &atmegadci_pipe_init, 2101 .xfer_setup = &atmegadci_xfer_setup, 2102 .xfer_unsetup = &atmegadci_xfer_unsetup, 2103 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2104 .set_stall = &atmegadci_set_stall, 2105 .clear_stall = &atmegadci_clear_stall, 2106 .roothub_exec = &atmegadci_roothub_exec, 2107 }; 2108