1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB OTG Controller. This 31 * driver currently only supports the DCI mode of the USB hardware. 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <sys/stdint.h> 40 #include <sys/stddef.h> 41 #include <sys/param.h> 42 #include <sys/queue.h> 43 #include <sys/types.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sx.h> 53 #include <sys/unistd.h> 54 #include <sys/callout.h> 55 #include <sys/malloc.h> 56 #include <sys/priv.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 61 #define USB_DEBUG_VAR atmegadci_debug 62 63 #include <dev/usb/usb_core.h> 64 #include <dev/usb/usb_debug.h> 65 #include <dev/usb/usb_busdma.h> 66 #include <dev/usb/usb_process.h> 67 #include <dev/usb/usb_transfer.h> 68 #include <dev/usb/usb_device.h> 69 #include <dev/usb/usb_hub.h> 70 #include <dev/usb/usb_util.h> 71 72 #include <dev/usb/usb_controller.h> 73 #include <dev/usb/usb_bus.h> 74 #include <dev/usb/controller/atmegadci.h> 75 76 #define ATMEGA_BUS2SC(bus) \ 77 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 78 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus)))) 79 80 #define ATMEGA_PC2SC(pc) \ 81 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 82 83 #ifdef USB_DEBUG 84 static int atmegadci_debug = 0; 85 86 SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 87 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 88 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 89 #endif 90 91 #define ATMEGA_INTR_ENDPT 1 92 93 /* prototypes */ 94 95 struct usb_bus_methods atmegadci_bus_methods; 96 struct usb_pipe_methods atmegadci_device_non_isoc_methods; 97 struct usb_pipe_methods atmegadci_device_isoc_fs_methods; 98 99 static atmegadci_cmd_t atmegadci_setup_rx; 100 static atmegadci_cmd_t atmegadci_data_rx; 101 static atmegadci_cmd_t atmegadci_data_tx; 102 static atmegadci_cmd_t atmegadci_data_tx_sync; 103 static void atmegadci_device_done(struct usb_xfer *, usb_error_t); 104 static void atmegadci_do_poll(struct usb_bus *); 105 static void atmegadci_standard_done(struct usb_xfer *); 106 static void atmegadci_root_intr(struct atmegadci_softc *sc); 107 108 /* 109 * Here is a list of what the chip supports: 110 */ 111 static const struct usb_hw_ep_profile 112 atmegadci_ep_profile[2] = { 113 114 [0] = { 115 .max_in_frame_size = 64, 116 .max_out_frame_size = 64, 117 .is_simplex = 1, 118 .support_control = 1, 119 }, 120 [1] = { 121 .max_in_frame_size = 64, 122 .max_out_frame_size = 64, 123 .is_simplex = 1, 124 .support_bulk = 1, 125 .support_interrupt = 1, 126 .support_isochronous = 1, 127 .support_in = 1, 128 .support_out = 1, 129 }, 130 }; 131 132 static void 133 atmegadci_get_hw_ep_profile(struct usb_device *udev, 134 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 135 { 136 if (ep_addr == 0) 137 *ppf = atmegadci_ep_profile; 138 else if (ep_addr < ATMEGA_EP_MAX) 139 *ppf = atmegadci_ep_profile + 1; 140 else 141 *ppf = NULL; 142 } 143 144 static void 145 atmegadci_clocks_on(struct atmegadci_softc *sc) 146 { 147 if (sc->sc_flags.clocks_off && 148 sc->sc_flags.port_powered) { 149 150 DPRINTFN(5, "\n"); 151 152 /* turn on clocks */ 153 (sc->sc_clocks_on) (&sc->sc_bus); 154 155 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 156 ATMEGA_USBCON_USBE | 157 ATMEGA_USBCON_OTGPADE | 158 ATMEGA_USBCON_VBUSTE); 159 160 sc->sc_flags.clocks_off = 0; 161 162 /* enable transceiver ? */ 163 } 164 } 165 166 static void 167 atmegadci_clocks_off(struct atmegadci_softc *sc) 168 { 169 if (!sc->sc_flags.clocks_off) { 170 171 DPRINTFN(5, "\n"); 172 173 /* disable Transceiver ? */ 174 175 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 176 ATMEGA_USBCON_USBE | 177 ATMEGA_USBCON_OTGPADE | 178 ATMEGA_USBCON_FRZCLK | 179 ATMEGA_USBCON_VBUSTE); 180 181 /* turn clocks off */ 182 (sc->sc_clocks_off) (&sc->sc_bus); 183 184 sc->sc_flags.clocks_off = 1; 185 } 186 } 187 188 static void 189 atmegadci_pull_up(struct atmegadci_softc *sc) 190 { 191 /* pullup D+, if possible */ 192 193 if (!sc->sc_flags.d_pulled_up && 194 sc->sc_flags.port_powered) { 195 sc->sc_flags.d_pulled_up = 1; 196 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 197 } 198 } 199 200 static void 201 atmegadci_pull_down(struct atmegadci_softc *sc) 202 { 203 /* pulldown D+, if possible */ 204 205 if (sc->sc_flags.d_pulled_up) { 206 sc->sc_flags.d_pulled_up = 0; 207 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 208 } 209 } 210 211 static void 212 atmegadci_wakeup_peer(struct atmegadci_softc *sc) 213 { 214 uint8_t temp; 215 216 if (!sc->sc_flags.status_suspend) { 217 return; 218 } 219 220 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 221 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 222 223 /* wait 8 milliseconds */ 224 /* Wait for reset to complete. */ 225 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 226 227 /* hardware should have cleared RMWKUP bit */ 228 } 229 230 static void 231 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 232 { 233 DPRINTFN(5, "addr=%d\n", addr); 234 235 addr |= ATMEGA_UDADDR_ADDEN; 236 237 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 238 } 239 240 static uint8_t 241 atmegadci_setup_rx(struct atmegadci_td *td) 242 { 243 struct atmegadci_softc *sc; 244 struct usb_device_request req; 245 uint16_t count; 246 uint8_t temp; 247 248 /* get pointer to softc */ 249 sc = ATMEGA_PC2SC(td->pc); 250 251 /* select endpoint number */ 252 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 253 254 /* check endpoint status */ 255 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 256 257 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 258 259 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 260 goto not_complete; 261 } 262 /* clear did stall */ 263 td->did_stall = 0; 264 /* get the packet byte count */ 265 count = 266 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 267 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 268 269 /* mask away undefined bits */ 270 count &= 0x7FF; 271 272 /* verify data length */ 273 if (count != td->remainder) { 274 DPRINTFN(0, "Invalid SETUP packet " 275 "length, %d bytes\n", count); 276 goto not_complete; 277 } 278 if (count != sizeof(req)) { 279 DPRINTFN(0, "Unsupported SETUP packet " 280 "length, %d bytes\n", count); 281 goto not_complete; 282 } 283 /* receive data */ 284 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 285 (void *)&req, sizeof(req)); 286 287 /* copy data into real buffer */ 288 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 289 290 td->offset = sizeof(req); 291 td->remainder = 0; 292 293 /* sneak peek the set address */ 294 if ((req.bmRequestType == UT_WRITE_DEVICE) && 295 (req.bRequest == UR_SET_ADDRESS)) { 296 sc->sc_dv_addr = req.wValue[0] & 0x7F; 297 /* must write address before ZLP */ 298 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr); 299 } else { 300 sc->sc_dv_addr = 0xFF; 301 } 302 303 /* Clear SETUP packet interrupt and all other previous interrupts */ 304 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0); 305 return (0); /* complete */ 306 307 not_complete: 308 /* abort any ongoing transfer */ 309 if (!td->did_stall) { 310 DPRINTFN(5, "stalling\n"); 311 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 312 ATMEGA_UECONX_EPEN | 313 ATMEGA_UECONX_STALLRQ); 314 td->did_stall = 1; 315 } 316 if (temp & ATMEGA_UEINTX_RXSTPI) { 317 /* clear SETUP packet interrupt */ 318 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 319 } 320 /* we only want to know if there is a SETUP packet */ 321 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 322 return (1); /* not complete */ 323 } 324 325 static uint8_t 326 atmegadci_data_rx(struct atmegadci_td *td) 327 { 328 struct atmegadci_softc *sc; 329 struct usb_page_search buf_res; 330 uint16_t count; 331 uint8_t temp; 332 uint8_t to; 333 uint8_t got_short; 334 335 to = 3; /* don't loop forever! */ 336 got_short = 0; 337 338 /* get pointer to softc */ 339 sc = ATMEGA_PC2SC(td->pc); 340 341 /* select endpoint number */ 342 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 343 344 repeat: 345 /* check if any of the FIFO banks have data */ 346 /* check endpoint status */ 347 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 348 349 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 350 351 if (temp & ATMEGA_UEINTX_RXSTPI) { 352 if (td->remainder == 0) { 353 /* 354 * We are actually complete and have 355 * received the next SETUP 356 */ 357 DPRINTFN(5, "faking complete\n"); 358 return (0); /* complete */ 359 } 360 /* 361 * USB Host Aborted the transfer. 362 */ 363 td->error = 1; 364 return (0); /* complete */ 365 } 366 /* check status */ 367 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 368 ATMEGA_UEINTX_RXOUTI))) { 369 /* no data */ 370 goto not_complete; 371 } 372 /* get the packet byte count */ 373 count = 374 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 375 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 376 377 /* mask away undefined bits */ 378 count &= 0x7FF; 379 380 /* verify the packet byte count */ 381 if (count != td->max_packet_size) { 382 if (count < td->max_packet_size) { 383 /* we have a short packet */ 384 td->short_pkt = 1; 385 got_short = 1; 386 } else { 387 /* invalid USB packet */ 388 td->error = 1; 389 return (0); /* we are complete */ 390 } 391 } 392 /* verify the packet byte count */ 393 if (count > td->remainder) { 394 /* invalid USB packet */ 395 td->error = 1; 396 return (0); /* we are complete */ 397 } 398 while (count > 0) { 399 usbd_get_page(td->pc, td->offset, &buf_res); 400 401 /* get correct length */ 402 if (buf_res.length > count) { 403 buf_res.length = count; 404 } 405 /* receive data */ 406 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 407 buf_res.buffer, buf_res.length); 408 409 /* update counters */ 410 count -= buf_res.length; 411 td->offset += buf_res.length; 412 td->remainder -= buf_res.length; 413 } 414 415 /* clear OUT packet interrupt */ 416 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 417 418 /* release FIFO bank */ 419 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 420 421 /* check if we are complete */ 422 if ((td->remainder == 0) || got_short) { 423 if (td->short_pkt) { 424 /* we are complete */ 425 return (0); 426 } 427 /* else need to receive a zero length packet */ 428 } 429 if (--to) { 430 goto repeat; 431 } 432 not_complete: 433 /* we only want to know if there is a SETUP packet or OUT packet */ 434 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 435 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 436 return (1); /* not complete */ 437 } 438 439 static uint8_t 440 atmegadci_data_tx(struct atmegadci_td *td) 441 { 442 struct atmegadci_softc *sc; 443 struct usb_page_search buf_res; 444 uint16_t count; 445 uint8_t to; 446 uint8_t temp; 447 448 to = 3; /* don't loop forever! */ 449 450 /* get pointer to softc */ 451 sc = ATMEGA_PC2SC(td->pc); 452 453 /* select endpoint number */ 454 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 455 456 repeat: 457 458 /* check endpoint status */ 459 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 460 461 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 462 463 if (temp & ATMEGA_UEINTX_RXSTPI) { 464 /* 465 * The current transfer was aborted 466 * by the USB Host 467 */ 468 td->error = 1; 469 return (0); /* complete */ 470 } 471 472 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 473 if (temp & 3) { 474 /* cannot write any data - a bank is busy */ 475 goto not_complete; 476 } 477 478 count = td->max_packet_size; 479 if (td->remainder < count) { 480 /* we have a short packet */ 481 td->short_pkt = 1; 482 count = td->remainder; 483 } 484 while (count > 0) { 485 486 usbd_get_page(td->pc, td->offset, &buf_res); 487 488 /* get correct length */ 489 if (buf_res.length > count) { 490 buf_res.length = count; 491 } 492 /* transmit data */ 493 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 494 buf_res.buffer, buf_res.length); 495 496 /* update counters */ 497 count -= buf_res.length; 498 td->offset += buf_res.length; 499 td->remainder -= buf_res.length; 500 } 501 502 /* clear IN packet interrupt */ 503 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 504 505 /* allocate FIFO bank */ 506 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 507 508 /* check remainder */ 509 if (td->remainder == 0) { 510 if (td->short_pkt) { 511 return (0); /* complete */ 512 } 513 /* else we need to transmit a short packet */ 514 } 515 if (--to) { 516 goto repeat; 517 } 518 not_complete: 519 /* we only want to know if there is a SETUP packet or free IN packet */ 520 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 521 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 522 return (1); /* not complete */ 523 } 524 525 static uint8_t 526 atmegadci_data_tx_sync(struct atmegadci_td *td) 527 { 528 struct atmegadci_softc *sc; 529 uint8_t temp; 530 531 /* get pointer to softc */ 532 sc = ATMEGA_PC2SC(td->pc); 533 534 /* select endpoint number */ 535 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 536 537 /* check endpoint status */ 538 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 539 540 DPRINTFN(5, "temp=0x%02x\n", temp); 541 542 if (temp & ATMEGA_UEINTX_RXSTPI) { 543 DPRINTFN(5, "faking complete\n"); 544 /* Race condition */ 545 return (0); /* complete */ 546 } 547 /* 548 * The control endpoint has only got one bank, so if that bank 549 * is free the packet has been transferred! 550 */ 551 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 552 if (temp & 3) { 553 /* cannot write any data - a bank is busy */ 554 goto not_complete; 555 } 556 if (sc->sc_dv_addr != 0xFF) { 557 /* set new address */ 558 atmegadci_set_address(sc, sc->sc_dv_addr); 559 } 560 return (0); /* complete */ 561 562 not_complete: 563 /* we only want to know if there is a SETUP packet or free IN packet */ 564 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 565 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 566 return (1); /* not complete */ 567 } 568 569 static uint8_t 570 atmegadci_xfer_do_fifo(struct usb_xfer *xfer) 571 { 572 struct atmegadci_td *td; 573 574 DPRINTFN(9, "\n"); 575 576 td = xfer->td_transfer_cache; 577 while (1) { 578 if ((td->func) (td)) { 579 /* operation in progress */ 580 break; 581 } 582 if (((void *)td) == xfer->td_transfer_last) { 583 goto done; 584 } 585 if (td->error) { 586 goto done; 587 } else if (td->remainder > 0) { 588 /* 589 * We had a short transfer. If there is no alternate 590 * next, stop processing ! 591 */ 592 if (!td->alt_next) { 593 goto done; 594 } 595 } 596 /* 597 * Fetch the next transfer descriptor and transfer 598 * some flags to the next transfer descriptor 599 */ 600 td = td->obj_next; 601 xfer->td_transfer_cache = td; 602 } 603 return (1); /* not complete */ 604 605 done: 606 /* compute all actual lengths */ 607 608 atmegadci_standard_done(xfer); 609 return (0); /* complete */ 610 } 611 612 static void 613 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 614 { 615 struct usb_xfer *xfer; 616 617 repeat: 618 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 619 if (!atmegadci_xfer_do_fifo(xfer)) { 620 /* queue has been modified */ 621 goto repeat; 622 } 623 } 624 } 625 626 static void 627 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 628 { 629 DPRINTFN(5, "vbus = %u\n", is_on); 630 631 if (is_on) { 632 if (!sc->sc_flags.status_vbus) { 633 sc->sc_flags.status_vbus = 1; 634 635 /* complete root HUB interrupt endpoint */ 636 637 atmegadci_root_intr(sc); 638 } 639 } else { 640 if (sc->sc_flags.status_vbus) { 641 sc->sc_flags.status_vbus = 0; 642 sc->sc_flags.status_bus_reset = 0; 643 sc->sc_flags.status_suspend = 0; 644 sc->sc_flags.change_suspend = 0; 645 sc->sc_flags.change_connect = 1; 646 647 /* complete root HUB interrupt endpoint */ 648 649 atmegadci_root_intr(sc); 650 } 651 } 652 } 653 654 void 655 atmegadci_interrupt(struct atmegadci_softc *sc) 656 { 657 uint8_t status; 658 659 USB_BUS_LOCK(&sc->sc_bus); 660 661 /* read interrupt status */ 662 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 663 664 /* clear all set interrupts */ 665 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D); 666 667 DPRINTFN(14, "UDINT=0x%02x\n", status); 668 669 /* check for any bus state change interrupts */ 670 if (status & ATMEGA_UDINT_EORSTI) { 671 672 DPRINTFN(5, "end of reset\n"); 673 674 /* set correct state */ 675 sc->sc_flags.status_bus_reset = 1; 676 sc->sc_flags.status_suspend = 0; 677 sc->sc_flags.change_suspend = 0; 678 sc->sc_flags.change_connect = 1; 679 680 /* disable resume interrupt */ 681 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 682 ATMEGA_UDINT_SUSPE | 683 ATMEGA_UDINT_EORSTE); 684 685 /* complete root HUB interrupt endpoint */ 686 atmegadci_root_intr(sc); 687 } 688 /* 689 * If resume and suspend is set at the same time we interpret 690 * that like RESUME. Resume is set when there is at least 3 691 * milliseconds of inactivity on the USB BUS. 692 */ 693 if (status & ATMEGA_UDINT_WAKEUPI) { 694 695 DPRINTFN(5, "resume interrupt\n"); 696 697 if (sc->sc_flags.status_suspend) { 698 /* update status bits */ 699 sc->sc_flags.status_suspend = 0; 700 sc->sc_flags.change_suspend = 1; 701 702 /* disable resume interrupt */ 703 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 704 ATMEGA_UDINT_SUSPE | 705 ATMEGA_UDINT_EORSTE); 706 707 /* complete root HUB interrupt endpoint */ 708 atmegadci_root_intr(sc); 709 } 710 } else if (status & ATMEGA_UDINT_SUSPI) { 711 712 DPRINTFN(5, "suspend interrupt\n"); 713 714 if (!sc->sc_flags.status_suspend) { 715 /* update status bits */ 716 sc->sc_flags.status_suspend = 1; 717 sc->sc_flags.change_suspend = 1; 718 719 /* disable suspend interrupt */ 720 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 721 ATMEGA_UDINT_WAKEUPE | 722 ATMEGA_UDINT_EORSTE); 723 724 /* complete root HUB interrupt endpoint */ 725 atmegadci_root_intr(sc); 726 } 727 } 728 /* check VBUS */ 729 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 730 731 /* clear all set interrupts */ 732 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03); 733 734 if (status & ATMEGA_USBINT_VBUSTI) { 735 uint8_t temp; 736 737 DPRINTFN(5, "USBINT=0x%02x\n", status); 738 739 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 740 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 741 } 742 /* check for any endpoint interrupts */ 743 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 744 /* the hardware will clear the UEINT bits automatically */ 745 if (status) { 746 747 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status); 748 749 atmegadci_interrupt_poll(sc); 750 } 751 USB_BUS_UNLOCK(&sc->sc_bus); 752 } 753 754 static void 755 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 756 { 757 struct atmegadci_td *td; 758 759 /* get current Transfer Descriptor */ 760 td = temp->td_next; 761 temp->td = td; 762 763 /* prepare for next TD */ 764 temp->td_next = td->obj_next; 765 766 /* fill out the Transfer Descriptor */ 767 td->func = temp->func; 768 td->pc = temp->pc; 769 td->offset = temp->offset; 770 td->remainder = temp->len; 771 td->error = 0; 772 td->did_stall = temp->did_stall; 773 td->short_pkt = temp->short_pkt; 774 td->alt_next = temp->setup_alt_next; 775 } 776 777 static void 778 atmegadci_setup_standard_chain(struct usb_xfer *xfer) 779 { 780 struct atmegadci_std_temp temp; 781 struct atmegadci_softc *sc; 782 struct atmegadci_td *td; 783 uint32_t x; 784 uint8_t ep_no; 785 uint8_t need_sync; 786 787 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 788 xfer->address, UE_GET_ADDR(xfer->endpointno), 789 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 790 791 temp.max_frame_size = xfer->max_frame_size; 792 793 td = xfer->td_start[0]; 794 xfer->td_transfer_first = td; 795 xfer->td_transfer_cache = td; 796 797 /* setup temp */ 798 799 temp.pc = NULL; 800 temp.td = NULL; 801 temp.td_next = xfer->td_start[0]; 802 temp.offset = 0; 803 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 804 temp.did_stall = !xfer->flags_int.control_stall; 805 806 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 807 ep_no = (xfer->endpointno & UE_ADDR); 808 809 /* check if we should prepend a setup message */ 810 811 if (xfer->flags_int.control_xfr) { 812 if (xfer->flags_int.control_hdr) { 813 814 temp.func = &atmegadci_setup_rx; 815 temp.len = xfer->frlengths[0]; 816 temp.pc = xfer->frbuffers + 0; 817 temp.short_pkt = temp.len ? 1 : 0; 818 /* check for last frame */ 819 if (xfer->nframes == 1) { 820 /* no STATUS stage yet, SETUP is last */ 821 if (xfer->flags_int.control_act) 822 temp.setup_alt_next = 0; 823 } 824 825 atmegadci_setup_standard_chain_sub(&temp); 826 } 827 x = 1; 828 } else { 829 x = 0; 830 } 831 832 if (x != xfer->nframes) { 833 if (xfer->endpointno & UE_DIR_IN) { 834 temp.func = &atmegadci_data_tx; 835 need_sync = 1; 836 } else { 837 temp.func = &atmegadci_data_rx; 838 need_sync = 0; 839 } 840 841 /* setup "pc" pointer */ 842 temp.pc = xfer->frbuffers + x; 843 } else { 844 need_sync = 0; 845 } 846 while (x != xfer->nframes) { 847 848 /* DATA0 / DATA1 message */ 849 850 temp.len = xfer->frlengths[x]; 851 852 x++; 853 854 if (x == xfer->nframes) { 855 if (xfer->flags_int.control_xfr) { 856 if (xfer->flags_int.control_act) { 857 temp.setup_alt_next = 0; 858 } 859 } else { 860 temp.setup_alt_next = 0; 861 } 862 } 863 if (temp.len == 0) { 864 865 /* make sure that we send an USB packet */ 866 867 temp.short_pkt = 0; 868 869 } else { 870 871 /* regular data transfer */ 872 873 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 874 } 875 876 atmegadci_setup_standard_chain_sub(&temp); 877 878 if (xfer->flags_int.isochronous_xfr) { 879 temp.offset += temp.len; 880 } else { 881 /* get next Page Cache pointer */ 882 temp.pc = xfer->frbuffers + x; 883 } 884 } 885 886 if (xfer->flags_int.control_xfr) { 887 888 /* always setup a valid "pc" pointer for status and sync */ 889 temp.pc = xfer->frbuffers + 0; 890 temp.len = 0; 891 temp.short_pkt = 0; 892 temp.setup_alt_next = 0; 893 894 /* check if we need to sync */ 895 if (need_sync) { 896 /* we need a SYNC point after TX */ 897 temp.func = &atmegadci_data_tx_sync; 898 atmegadci_setup_standard_chain_sub(&temp); 899 } 900 901 /* check if we should append a status stage */ 902 if (!xfer->flags_int.control_act) { 903 904 /* 905 * Send a DATA1 message and invert the current 906 * endpoint direction. 907 */ 908 if (xfer->endpointno & UE_DIR_IN) { 909 temp.func = &atmegadci_data_rx; 910 need_sync = 0; 911 } else { 912 temp.func = &atmegadci_data_tx; 913 need_sync = 1; 914 } 915 916 atmegadci_setup_standard_chain_sub(&temp); 917 if (need_sync) { 918 /* we need a SYNC point after TX */ 919 temp.func = &atmegadci_data_tx_sync; 920 atmegadci_setup_standard_chain_sub(&temp); 921 } 922 } 923 } 924 /* must have at least one frame! */ 925 td = temp.td; 926 xfer->td_transfer_last = td; 927 } 928 929 static void 930 atmegadci_timeout(void *arg) 931 { 932 struct usb_xfer *xfer = arg; 933 934 DPRINTF("xfer=%p\n", xfer); 935 936 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 937 938 /* transfer is transferred */ 939 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 940 } 941 942 static void 943 atmegadci_start_standard_chain(struct usb_xfer *xfer) 944 { 945 DPRINTFN(9, "\n"); 946 947 /* poll one time - will turn on interrupts */ 948 if (atmegadci_xfer_do_fifo(xfer)) { 949 950 /* put transfer on interrupt queue */ 951 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 952 953 /* start timeout, if any */ 954 if (xfer->timeout != 0) { 955 usbd_transfer_timeout_ms(xfer, 956 &atmegadci_timeout, xfer->timeout); 957 } 958 } 959 } 960 961 static void 962 atmegadci_root_intr(struct atmegadci_softc *sc) 963 { 964 DPRINTFN(9, "\n"); 965 966 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 967 968 /* set port bit */ 969 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 970 971 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 972 sizeof(sc->sc_hub_idata)); 973 } 974 975 static usb_error_t 976 atmegadci_standard_done_sub(struct usb_xfer *xfer) 977 { 978 struct atmegadci_td *td; 979 uint32_t len; 980 uint8_t error; 981 982 DPRINTFN(9, "\n"); 983 984 td = xfer->td_transfer_cache; 985 986 do { 987 len = td->remainder; 988 989 if (xfer->aframes != xfer->nframes) { 990 /* 991 * Verify the length and subtract 992 * the remainder from "frlengths[]": 993 */ 994 if (len > xfer->frlengths[xfer->aframes]) { 995 td->error = 1; 996 } else { 997 xfer->frlengths[xfer->aframes] -= len; 998 } 999 } 1000 /* Check for transfer error */ 1001 if (td->error) { 1002 /* the transfer is finished */ 1003 error = 1; 1004 td = NULL; 1005 break; 1006 } 1007 /* Check for short transfer */ 1008 if (len > 0) { 1009 if (xfer->flags_int.short_frames_ok) { 1010 /* follow alt next */ 1011 if (td->alt_next) { 1012 td = td->obj_next; 1013 } else { 1014 td = NULL; 1015 } 1016 } else { 1017 /* the transfer is finished */ 1018 td = NULL; 1019 } 1020 error = 0; 1021 break; 1022 } 1023 td = td->obj_next; 1024 1025 /* this USB frame is complete */ 1026 error = 0; 1027 break; 1028 1029 } while (0); 1030 1031 /* update transfer cache */ 1032 1033 xfer->td_transfer_cache = td; 1034 1035 return (error ? 1036 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1037 } 1038 1039 static void 1040 atmegadci_standard_done(struct usb_xfer *xfer) 1041 { 1042 usb_error_t err = 0; 1043 1044 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1045 xfer, xfer->endpoint); 1046 1047 /* reset scanner */ 1048 1049 xfer->td_transfer_cache = xfer->td_transfer_first; 1050 1051 if (xfer->flags_int.control_xfr) { 1052 1053 if (xfer->flags_int.control_hdr) { 1054 1055 err = atmegadci_standard_done_sub(xfer); 1056 } 1057 xfer->aframes = 1; 1058 1059 if (xfer->td_transfer_cache == NULL) { 1060 goto done; 1061 } 1062 } 1063 while (xfer->aframes != xfer->nframes) { 1064 1065 err = atmegadci_standard_done_sub(xfer); 1066 xfer->aframes++; 1067 1068 if (xfer->td_transfer_cache == NULL) { 1069 goto done; 1070 } 1071 } 1072 1073 if (xfer->flags_int.control_xfr && 1074 !xfer->flags_int.control_act) { 1075 1076 err = atmegadci_standard_done_sub(xfer); 1077 } 1078 done: 1079 atmegadci_device_done(xfer, err); 1080 } 1081 1082 /*------------------------------------------------------------------------* 1083 * atmegadci_device_done 1084 * 1085 * NOTE: this function can be called more than one time on the 1086 * same USB transfer! 1087 *------------------------------------------------------------------------*/ 1088 static void 1089 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error) 1090 { 1091 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1092 uint8_t ep_no; 1093 1094 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1095 1096 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1097 xfer, xfer->endpoint, error); 1098 1099 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1100 ep_no = (xfer->endpointno & UE_ADDR); 1101 1102 /* select endpoint number */ 1103 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1104 1105 /* disable endpoint interrupt */ 1106 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1107 1108 DPRINTFN(15, "disabled interrupts!\n"); 1109 } 1110 /* dequeue transfer and start next transfer */ 1111 usbd_transfer_done(xfer, error); 1112 } 1113 1114 static void 1115 atmegadci_set_stall(struct usb_device *udev, struct usb_xfer *xfer, 1116 struct usb_endpoint *ep, uint8_t *did_stall) 1117 { 1118 struct atmegadci_softc *sc; 1119 uint8_t ep_no; 1120 1121 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1122 1123 DPRINTFN(5, "endpoint=%p\n", ep); 1124 1125 if (xfer) { 1126 /* cancel any ongoing transfers */ 1127 atmegadci_device_done(xfer, USB_ERR_STALLED); 1128 } 1129 sc = ATMEGA_BUS2SC(udev->bus); 1130 /* get endpoint number */ 1131 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR); 1132 /* select endpoint number */ 1133 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1134 /* set stall */ 1135 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1136 ATMEGA_UECONX_EPEN | 1137 ATMEGA_UECONX_STALLRQ); 1138 } 1139 1140 static void 1141 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1142 uint8_t ep_type, uint8_t ep_dir) 1143 { 1144 uint8_t temp; 1145 1146 if (ep_type == UE_CONTROL) { 1147 /* clearing stall is not needed */ 1148 return; 1149 } 1150 /* select endpoint number */ 1151 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1152 1153 /* set endpoint reset */ 1154 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1155 1156 /* clear endpoint reset */ 1157 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1158 1159 /* set stall */ 1160 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1161 ATMEGA_UECONX_EPEN | 1162 ATMEGA_UECONX_STALLRQ); 1163 1164 /* reset data toggle */ 1165 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1166 ATMEGA_UECONX_EPEN | 1167 ATMEGA_UECONX_RSTDT); 1168 1169 /* clear stall */ 1170 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1171 ATMEGA_UECONX_EPEN | 1172 ATMEGA_UECONX_STALLRQC); 1173 1174 do { 1175 if (ep_type == UE_BULK) { 1176 temp = ATMEGA_UECFG0X_EPTYPE2; 1177 } else if (ep_type == UE_INTERRUPT) { 1178 temp = ATMEGA_UECFG0X_EPTYPE3; 1179 } else { 1180 temp = ATMEGA_UECFG0X_EPTYPE1; 1181 } 1182 if (ep_dir & UE_DIR_IN) { 1183 temp |= ATMEGA_UECFG0X_EPDIR; 1184 } 1185 /* two banks, 64-bytes wMaxPacket */ 1186 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1187 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1188 ATMEGA_UECFG1X_ALLOC | 1189 ATMEGA_UECFG1X_EPBK0 | /* one bank */ 1190 ATMEGA_UECFG1X_EPSIZE(3)); 1191 1192 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1193 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1194 device_printf(sc->sc_bus.bdev, 1195 "Chip rejected configuration\n"); 1196 } 1197 } while (0); 1198 } 1199 1200 static void 1201 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1202 { 1203 struct atmegadci_softc *sc; 1204 struct usb_endpoint_descriptor *ed; 1205 1206 DPRINTFN(5, "endpoint=%p\n", ep); 1207 1208 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1209 1210 /* check mode */ 1211 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1212 /* not supported */ 1213 return; 1214 } 1215 /* get softc */ 1216 sc = ATMEGA_BUS2SC(udev->bus); 1217 1218 /* get endpoint descriptor */ 1219 ed = ep->edesc; 1220 1221 /* reset endpoint */ 1222 atmegadci_clear_stall_sub(sc, 1223 (ed->bEndpointAddress & UE_ADDR), 1224 (ed->bmAttributes & UE_XFERTYPE), 1225 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1226 } 1227 1228 usb_error_t 1229 atmegadci_init(struct atmegadci_softc *sc) 1230 { 1231 uint8_t n; 1232 1233 DPRINTF("start\n"); 1234 1235 /* set up the bus structure */ 1236 sc->sc_bus.usbrev = USB_REV_1_1; 1237 sc->sc_bus.methods = &atmegadci_bus_methods; 1238 1239 USB_BUS_LOCK(&sc->sc_bus); 1240 1241 /* make sure USB is enabled */ 1242 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1243 ATMEGA_USBCON_USBE | 1244 ATMEGA_USBCON_FRZCLK); 1245 1246 /* enable USB PAD regulator */ 1247 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1248 ATMEGA_UHWCON_UVREGE | 1249 ATMEGA_UHWCON_UIMOD); 1250 1251 /* the following register sets up the USB PLL, assuming 16MHz X-tal */ 1252 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02); 1253 1254 /* wait for PLL to lock */ 1255 for (n = 0; n != 20; n++) { 1256 if (ATMEGA_READ_1(sc, 0x49) & 0x01) 1257 break; 1258 /* wait a little bit for PLL to start */ 1259 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 1260 } 1261 1262 /* make sure USB is enabled */ 1263 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 1264 ATMEGA_USBCON_USBE | 1265 ATMEGA_USBCON_OTGPADE | 1266 ATMEGA_USBCON_VBUSTE); 1267 1268 /* turn on clocks */ 1269 (sc->sc_clocks_on) (&sc->sc_bus); 1270 1271 /* make sure device is re-enumerated */ 1272 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 1273 1274 /* wait a little for things to stabilise */ 1275 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20); 1276 1277 /* enable interrupts */ 1278 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1279 ATMEGA_UDINT_SUSPE | 1280 ATMEGA_UDINT_EORSTE); 1281 1282 /* reset all endpoints */ 1283 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1284 (1 << ATMEGA_EP_MAX) - 1); 1285 1286 /* disable reset */ 1287 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1288 1289 /* disable all endpoints */ 1290 for (n = 0; n != ATMEGA_EP_MAX; n++) { 1291 1292 /* select endpoint */ 1293 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1294 1295 /* disable endpoint interrupt */ 1296 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1297 1298 /* disable endpoint */ 1299 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1300 } 1301 1302 /* turn off clocks */ 1303 1304 atmegadci_clocks_off(sc); 1305 1306 /* read initial VBUS state */ 1307 1308 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 1309 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS); 1310 1311 USB_BUS_UNLOCK(&sc->sc_bus); 1312 1313 /* catch any lost interrupts */ 1314 1315 atmegadci_do_poll(&sc->sc_bus); 1316 1317 return (0); /* success */ 1318 } 1319 1320 void 1321 atmegadci_uninit(struct atmegadci_softc *sc) 1322 { 1323 USB_BUS_LOCK(&sc->sc_bus); 1324 1325 /* turn on clocks */ 1326 (sc->sc_clocks_on) (&sc->sc_bus); 1327 1328 /* disable interrupts */ 1329 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1330 1331 /* reset all endpoints */ 1332 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1333 (1 << ATMEGA_EP_MAX) - 1); 1334 1335 /* disable reset */ 1336 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1337 1338 sc->sc_flags.port_powered = 0; 1339 sc->sc_flags.status_vbus = 0; 1340 sc->sc_flags.status_bus_reset = 0; 1341 sc->sc_flags.status_suspend = 0; 1342 sc->sc_flags.change_suspend = 0; 1343 sc->sc_flags.change_connect = 1; 1344 1345 atmegadci_pull_down(sc); 1346 atmegadci_clocks_off(sc); 1347 1348 /* disable USB PAD regulator */ 1349 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1350 1351 USB_BUS_UNLOCK(&sc->sc_bus); 1352 } 1353 1354 void 1355 atmegadci_suspend(struct atmegadci_softc *sc) 1356 { 1357 return; 1358 } 1359 1360 void 1361 atmegadci_resume(struct atmegadci_softc *sc) 1362 { 1363 return; 1364 } 1365 1366 static void 1367 atmegadci_do_poll(struct usb_bus *bus) 1368 { 1369 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1370 1371 USB_BUS_LOCK(&sc->sc_bus); 1372 atmegadci_interrupt_poll(sc); 1373 USB_BUS_UNLOCK(&sc->sc_bus); 1374 } 1375 1376 /*------------------------------------------------------------------------* 1377 * at91dci bulk support 1378 * at91dci control support 1379 * at91dci interrupt support 1380 *------------------------------------------------------------------------*/ 1381 static void 1382 atmegadci_device_non_isoc_open(struct usb_xfer *xfer) 1383 { 1384 return; 1385 } 1386 1387 static void 1388 atmegadci_device_non_isoc_close(struct usb_xfer *xfer) 1389 { 1390 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1391 } 1392 1393 static void 1394 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer) 1395 { 1396 return; 1397 } 1398 1399 static void 1400 atmegadci_device_non_isoc_start(struct usb_xfer *xfer) 1401 { 1402 /* setup TDs */ 1403 atmegadci_setup_standard_chain(xfer); 1404 atmegadci_start_standard_chain(xfer); 1405 } 1406 1407 struct usb_pipe_methods atmegadci_device_non_isoc_methods = 1408 { 1409 .open = atmegadci_device_non_isoc_open, 1410 .close = atmegadci_device_non_isoc_close, 1411 .enter = atmegadci_device_non_isoc_enter, 1412 .start = atmegadci_device_non_isoc_start, 1413 }; 1414 1415 /*------------------------------------------------------------------------* 1416 * at91dci full speed isochronous support 1417 *------------------------------------------------------------------------*/ 1418 static void 1419 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer) 1420 { 1421 return; 1422 } 1423 1424 static void 1425 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer) 1426 { 1427 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1428 } 1429 1430 static void 1431 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer) 1432 { 1433 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1434 uint32_t temp; 1435 uint32_t nframes; 1436 1437 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1438 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1439 1440 /* get the current frame index */ 1441 1442 nframes = 1443 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1444 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1445 1446 nframes &= ATMEGA_FRAME_MASK; 1447 1448 /* 1449 * check if the frame index is within the window where the frames 1450 * will be inserted 1451 */ 1452 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK; 1453 1454 if ((xfer->endpoint->is_synced == 0) || 1455 (temp < xfer->nframes)) { 1456 /* 1457 * If there is data underflow or the pipe queue is 1458 * empty we schedule the transfer a few frames ahead 1459 * of the current frame position. Else two isochronous 1460 * transfers might overlap. 1461 */ 1462 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1463 xfer->endpoint->is_synced = 1; 1464 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1465 } 1466 /* 1467 * compute how many milliseconds the insertion is ahead of the 1468 * current frame position: 1469 */ 1470 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1471 1472 /* 1473 * pre-compute when the isochronous transfer will be finished: 1474 */ 1475 xfer->isoc_time_complete = 1476 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1477 xfer->nframes; 1478 1479 /* compute frame number for next insertion */ 1480 xfer->endpoint->isoc_next += xfer->nframes; 1481 1482 /* setup TDs */ 1483 atmegadci_setup_standard_chain(xfer); 1484 } 1485 1486 static void 1487 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer) 1488 { 1489 /* start TD chain */ 1490 atmegadci_start_standard_chain(xfer); 1491 } 1492 1493 struct usb_pipe_methods atmegadci_device_isoc_fs_methods = 1494 { 1495 .open = atmegadci_device_isoc_fs_open, 1496 .close = atmegadci_device_isoc_fs_close, 1497 .enter = atmegadci_device_isoc_fs_enter, 1498 .start = atmegadci_device_isoc_fs_start, 1499 }; 1500 1501 /*------------------------------------------------------------------------* 1502 * at91dci root control support 1503 *------------------------------------------------------------------------* 1504 * Simulate a hardware HUB by handling all the necessary requests. 1505 *------------------------------------------------------------------------*/ 1506 1507 static const struct usb_device_descriptor atmegadci_devd = { 1508 .bLength = sizeof(struct usb_device_descriptor), 1509 .bDescriptorType = UDESC_DEVICE, 1510 .bcdUSB = {0x00, 0x02}, 1511 .bDeviceClass = UDCLASS_HUB, 1512 .bDeviceSubClass = UDSUBCLASS_HUB, 1513 .bDeviceProtocol = UDPROTO_FSHUB, 1514 .bMaxPacketSize = 64, 1515 .bcdDevice = {0x00, 0x01}, 1516 .iManufacturer = 1, 1517 .iProduct = 2, 1518 .bNumConfigurations = 1, 1519 }; 1520 1521 static const struct atmegadci_config_desc atmegadci_confd = { 1522 .confd = { 1523 .bLength = sizeof(struct usb_config_descriptor), 1524 .bDescriptorType = UDESC_CONFIG, 1525 .wTotalLength[0] = sizeof(atmegadci_confd), 1526 .bNumInterface = 1, 1527 .bConfigurationValue = 1, 1528 .iConfiguration = 0, 1529 .bmAttributes = UC_SELF_POWERED, 1530 .bMaxPower = 0, 1531 }, 1532 .ifcd = { 1533 .bLength = sizeof(struct usb_interface_descriptor), 1534 .bDescriptorType = UDESC_INTERFACE, 1535 .bNumEndpoints = 1, 1536 .bInterfaceClass = UICLASS_HUB, 1537 .bInterfaceSubClass = UISUBCLASS_HUB, 1538 .bInterfaceProtocol = 0, 1539 }, 1540 .endpd = { 1541 .bLength = sizeof(struct usb_endpoint_descriptor), 1542 .bDescriptorType = UDESC_ENDPOINT, 1543 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1544 .bmAttributes = UE_INTERRUPT, 1545 .wMaxPacketSize[0] = 8, 1546 .bInterval = 255, 1547 }, 1548 }; 1549 1550 static const struct usb_hub_descriptor_min atmegadci_hubd = { 1551 .bDescLength = sizeof(atmegadci_hubd), 1552 .bDescriptorType = UDESC_HUB, 1553 .bNbrPorts = 1, 1554 .wHubCharacteristics[0] = 1555 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1556 .wHubCharacteristics[1] = 1557 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1558 .bPwrOn2PwrGood = 50, 1559 .bHubContrCurrent = 0, 1560 .DeviceRemovable = {0}, /* port is removable */ 1561 }; 1562 1563 #define STRING_LANG \ 1564 0x09, 0x04, /* American English */ 1565 1566 #define STRING_VENDOR \ 1567 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1568 1569 #define STRING_PRODUCT \ 1570 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1571 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1572 'U', 0, 'B', 0, 1573 1574 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1575 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1576 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1577 1578 static usb_error_t 1579 atmegadci_roothub_exec(struct usb_device *udev, 1580 struct usb_device_request *req, const void **pptr, uint16_t *plength) 1581 { 1582 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 1583 const void *ptr; 1584 uint16_t len; 1585 uint16_t value; 1586 uint16_t index; 1587 uint8_t temp; 1588 usb_error_t err; 1589 1590 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1591 1592 /* buffer reset */ 1593 ptr = (const void *)&sc->sc_hub_temp; 1594 len = 0; 1595 err = 0; 1596 1597 value = UGETW(req->wValue); 1598 index = UGETW(req->wIndex); 1599 1600 /* demultiplex the control request */ 1601 1602 switch (req->bmRequestType) { 1603 case UT_READ_DEVICE: 1604 switch (req->bRequest) { 1605 case UR_GET_DESCRIPTOR: 1606 goto tr_handle_get_descriptor; 1607 case UR_GET_CONFIG: 1608 goto tr_handle_get_config; 1609 case UR_GET_STATUS: 1610 goto tr_handle_get_status; 1611 default: 1612 goto tr_stalled; 1613 } 1614 break; 1615 1616 case UT_WRITE_DEVICE: 1617 switch (req->bRequest) { 1618 case UR_SET_ADDRESS: 1619 goto tr_handle_set_address; 1620 case UR_SET_CONFIG: 1621 goto tr_handle_set_config; 1622 case UR_CLEAR_FEATURE: 1623 goto tr_valid; /* nop */ 1624 case UR_SET_DESCRIPTOR: 1625 goto tr_valid; /* nop */ 1626 case UR_SET_FEATURE: 1627 default: 1628 goto tr_stalled; 1629 } 1630 break; 1631 1632 case UT_WRITE_ENDPOINT: 1633 switch (req->bRequest) { 1634 case UR_CLEAR_FEATURE: 1635 switch (UGETW(req->wValue)) { 1636 case UF_ENDPOINT_HALT: 1637 goto tr_handle_clear_halt; 1638 case UF_DEVICE_REMOTE_WAKEUP: 1639 goto tr_handle_clear_wakeup; 1640 default: 1641 goto tr_stalled; 1642 } 1643 break; 1644 case UR_SET_FEATURE: 1645 switch (UGETW(req->wValue)) { 1646 case UF_ENDPOINT_HALT: 1647 goto tr_handle_set_halt; 1648 case UF_DEVICE_REMOTE_WAKEUP: 1649 goto tr_handle_set_wakeup; 1650 default: 1651 goto tr_stalled; 1652 } 1653 break; 1654 case UR_SYNCH_FRAME: 1655 goto tr_valid; /* nop */ 1656 default: 1657 goto tr_stalled; 1658 } 1659 break; 1660 1661 case UT_READ_ENDPOINT: 1662 switch (req->bRequest) { 1663 case UR_GET_STATUS: 1664 goto tr_handle_get_ep_status; 1665 default: 1666 goto tr_stalled; 1667 } 1668 break; 1669 1670 case UT_WRITE_INTERFACE: 1671 switch (req->bRequest) { 1672 case UR_SET_INTERFACE: 1673 goto tr_handle_set_interface; 1674 case UR_CLEAR_FEATURE: 1675 goto tr_valid; /* nop */ 1676 case UR_SET_FEATURE: 1677 default: 1678 goto tr_stalled; 1679 } 1680 break; 1681 1682 case UT_READ_INTERFACE: 1683 switch (req->bRequest) { 1684 case UR_GET_INTERFACE: 1685 goto tr_handle_get_interface; 1686 case UR_GET_STATUS: 1687 goto tr_handle_get_iface_status; 1688 default: 1689 goto tr_stalled; 1690 } 1691 break; 1692 1693 case UT_WRITE_CLASS_INTERFACE: 1694 case UT_WRITE_VENDOR_INTERFACE: 1695 /* XXX forward */ 1696 break; 1697 1698 case UT_READ_CLASS_INTERFACE: 1699 case UT_READ_VENDOR_INTERFACE: 1700 /* XXX forward */ 1701 break; 1702 1703 case UT_WRITE_CLASS_DEVICE: 1704 switch (req->bRequest) { 1705 case UR_CLEAR_FEATURE: 1706 goto tr_valid; 1707 case UR_SET_DESCRIPTOR: 1708 case UR_SET_FEATURE: 1709 break; 1710 default: 1711 goto tr_stalled; 1712 } 1713 break; 1714 1715 case UT_WRITE_CLASS_OTHER: 1716 switch (req->bRequest) { 1717 case UR_CLEAR_FEATURE: 1718 goto tr_handle_clear_port_feature; 1719 case UR_SET_FEATURE: 1720 goto tr_handle_set_port_feature; 1721 case UR_CLEAR_TT_BUFFER: 1722 case UR_RESET_TT: 1723 case UR_STOP_TT: 1724 goto tr_valid; 1725 1726 default: 1727 goto tr_stalled; 1728 } 1729 break; 1730 1731 case UT_READ_CLASS_OTHER: 1732 switch (req->bRequest) { 1733 case UR_GET_TT_STATE: 1734 goto tr_handle_get_tt_state; 1735 case UR_GET_STATUS: 1736 goto tr_handle_get_port_status; 1737 default: 1738 goto tr_stalled; 1739 } 1740 break; 1741 1742 case UT_READ_CLASS_DEVICE: 1743 switch (req->bRequest) { 1744 case UR_GET_DESCRIPTOR: 1745 goto tr_handle_get_class_descriptor; 1746 case UR_GET_STATUS: 1747 goto tr_handle_get_class_status; 1748 1749 default: 1750 goto tr_stalled; 1751 } 1752 break; 1753 default: 1754 goto tr_stalled; 1755 } 1756 goto tr_valid; 1757 1758 tr_handle_get_descriptor: 1759 switch (value >> 8) { 1760 case UDESC_DEVICE: 1761 if (value & 0xff) { 1762 goto tr_stalled; 1763 } 1764 len = sizeof(atmegadci_devd); 1765 ptr = (const void *)&atmegadci_devd; 1766 goto tr_valid; 1767 case UDESC_CONFIG: 1768 if (value & 0xff) { 1769 goto tr_stalled; 1770 } 1771 len = sizeof(atmegadci_confd); 1772 ptr = (const void *)&atmegadci_confd; 1773 goto tr_valid; 1774 case UDESC_STRING: 1775 switch (value & 0xff) { 1776 case 0: /* Language table */ 1777 len = sizeof(atmegadci_langtab); 1778 ptr = (const void *)&atmegadci_langtab; 1779 goto tr_valid; 1780 1781 case 1: /* Vendor */ 1782 len = sizeof(atmegadci_vendor); 1783 ptr = (const void *)&atmegadci_vendor; 1784 goto tr_valid; 1785 1786 case 2: /* Product */ 1787 len = sizeof(atmegadci_product); 1788 ptr = (const void *)&atmegadci_product; 1789 goto tr_valid; 1790 default: 1791 break; 1792 } 1793 break; 1794 default: 1795 goto tr_stalled; 1796 } 1797 goto tr_stalled; 1798 1799 tr_handle_get_config: 1800 len = 1; 1801 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1802 goto tr_valid; 1803 1804 tr_handle_get_status: 1805 len = 2; 1806 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1807 goto tr_valid; 1808 1809 tr_handle_set_address: 1810 if (value & 0xFF00) { 1811 goto tr_stalled; 1812 } 1813 sc->sc_rt_addr = value; 1814 goto tr_valid; 1815 1816 tr_handle_set_config: 1817 if (value >= 2) { 1818 goto tr_stalled; 1819 } 1820 sc->sc_conf = value; 1821 goto tr_valid; 1822 1823 tr_handle_get_interface: 1824 len = 1; 1825 sc->sc_hub_temp.wValue[0] = 0; 1826 goto tr_valid; 1827 1828 tr_handle_get_tt_state: 1829 tr_handle_get_class_status: 1830 tr_handle_get_iface_status: 1831 tr_handle_get_ep_status: 1832 len = 2; 1833 USETW(sc->sc_hub_temp.wValue, 0); 1834 goto tr_valid; 1835 1836 tr_handle_set_halt: 1837 tr_handle_set_interface: 1838 tr_handle_set_wakeup: 1839 tr_handle_clear_wakeup: 1840 tr_handle_clear_halt: 1841 goto tr_valid; 1842 1843 tr_handle_clear_port_feature: 1844 if (index != 1) { 1845 goto tr_stalled; 1846 } 1847 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1848 1849 switch (value) { 1850 case UHF_PORT_SUSPEND: 1851 atmegadci_wakeup_peer(sc); 1852 break; 1853 1854 case UHF_PORT_ENABLE: 1855 sc->sc_flags.port_enabled = 0; 1856 break; 1857 1858 case UHF_PORT_TEST: 1859 case UHF_PORT_INDICATOR: 1860 case UHF_C_PORT_ENABLE: 1861 case UHF_C_PORT_OVER_CURRENT: 1862 case UHF_C_PORT_RESET: 1863 /* nops */ 1864 break; 1865 case UHF_PORT_POWER: 1866 sc->sc_flags.port_powered = 0; 1867 atmegadci_pull_down(sc); 1868 atmegadci_clocks_off(sc); 1869 break; 1870 case UHF_C_PORT_CONNECTION: 1871 /* clear connect change flag */ 1872 sc->sc_flags.change_connect = 0; 1873 1874 if (!sc->sc_flags.status_bus_reset) { 1875 /* we are not connected */ 1876 break; 1877 } 1878 1879 /* configure the control endpoint */ 1880 1881 /* select endpoint number */ 1882 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0); 1883 1884 /* set endpoint reset */ 1885 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0)); 1886 1887 /* clear endpoint reset */ 1888 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1889 1890 /* enable and stall endpoint */ 1891 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1892 ATMEGA_UECONX_EPEN | 1893 ATMEGA_UECONX_STALLRQ); 1894 1895 /* one bank, 64-bytes wMaxPacket */ 1896 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1897 ATMEGA_UECFG0X_EPTYPE0); 1898 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1899 ATMEGA_UECFG1X_ALLOC | 1900 ATMEGA_UECFG1X_EPBK0 | 1901 ATMEGA_UECFG1X_EPSIZE(3)); 1902 1903 /* check valid config */ 1904 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1905 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1906 device_printf(sc->sc_bus.bdev, 1907 "Chip rejected EP0 configuration\n"); 1908 } 1909 break; 1910 case UHF_C_PORT_SUSPEND: 1911 sc->sc_flags.change_suspend = 0; 1912 break; 1913 default: 1914 err = USB_ERR_IOERROR; 1915 goto done; 1916 } 1917 goto tr_valid; 1918 1919 tr_handle_set_port_feature: 1920 if (index != 1) { 1921 goto tr_stalled; 1922 } 1923 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1924 1925 switch (value) { 1926 case UHF_PORT_ENABLE: 1927 sc->sc_flags.port_enabled = 1; 1928 break; 1929 case UHF_PORT_SUSPEND: 1930 case UHF_PORT_RESET: 1931 case UHF_PORT_TEST: 1932 case UHF_PORT_INDICATOR: 1933 /* nops */ 1934 break; 1935 case UHF_PORT_POWER: 1936 sc->sc_flags.port_powered = 1; 1937 break; 1938 default: 1939 err = USB_ERR_IOERROR; 1940 goto done; 1941 } 1942 goto tr_valid; 1943 1944 tr_handle_get_port_status: 1945 1946 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 1947 1948 if (index != 1) { 1949 goto tr_stalled; 1950 } 1951 if (sc->sc_flags.status_vbus) { 1952 atmegadci_clocks_on(sc); 1953 atmegadci_pull_up(sc); 1954 } else { 1955 atmegadci_pull_down(sc); 1956 atmegadci_clocks_off(sc); 1957 } 1958 1959 /* Select FULL-speed and Device Side Mode */ 1960 1961 value = UPS_PORT_MODE_DEVICE; 1962 1963 if (sc->sc_flags.port_powered) { 1964 value |= UPS_PORT_POWER; 1965 } 1966 if (sc->sc_flags.port_enabled) { 1967 value |= UPS_PORT_ENABLED; 1968 } 1969 if (sc->sc_flags.status_vbus && 1970 sc->sc_flags.status_bus_reset) { 1971 value |= UPS_CURRENT_CONNECT_STATUS; 1972 } 1973 if (sc->sc_flags.status_suspend) { 1974 value |= UPS_SUSPEND; 1975 } 1976 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 1977 1978 value = 0; 1979 1980 if (sc->sc_flags.change_connect) { 1981 value |= UPS_C_CONNECT_STATUS; 1982 } 1983 if (sc->sc_flags.change_suspend) { 1984 value |= UPS_C_SUSPEND; 1985 } 1986 USETW(sc->sc_hub_temp.ps.wPortChange, value); 1987 len = sizeof(sc->sc_hub_temp.ps); 1988 goto tr_valid; 1989 1990 tr_handle_get_class_descriptor: 1991 if (value & 0xFF) { 1992 goto tr_stalled; 1993 } 1994 ptr = (const void *)&atmegadci_hubd; 1995 len = sizeof(atmegadci_hubd); 1996 goto tr_valid; 1997 1998 tr_stalled: 1999 err = USB_ERR_STALLED; 2000 tr_valid: 2001 done: 2002 *plength = len; 2003 *pptr = ptr; 2004 return (err); 2005 } 2006 2007 static void 2008 atmegadci_xfer_setup(struct usb_setup_params *parm) 2009 { 2010 const struct usb_hw_ep_profile *pf; 2011 struct atmegadci_softc *sc; 2012 struct usb_xfer *xfer; 2013 void *last_obj; 2014 uint32_t ntd; 2015 uint32_t n; 2016 uint8_t ep_no; 2017 2018 sc = ATMEGA_BUS2SC(parm->udev->bus); 2019 xfer = parm->curr_xfer; 2020 2021 /* 2022 * NOTE: This driver does not use any of the parameters that 2023 * are computed from the following values. Just set some 2024 * reasonable dummies: 2025 */ 2026 parm->hc_max_packet_size = 0x500; 2027 parm->hc_max_packet_count = 1; 2028 parm->hc_max_frame_size = 0x500; 2029 2030 usbd_transfer_setup_sub(parm); 2031 2032 /* 2033 * compute maximum number of TDs 2034 */ 2035 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2036 2037 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2038 + 1 /* SYNC 2 */ ; 2039 } else { 2040 2041 ntd = xfer->nframes + 1 /* SYNC */ ; 2042 } 2043 2044 /* 2045 * check if "usbd_transfer_setup_sub" set an error 2046 */ 2047 if (parm->err) 2048 return; 2049 2050 /* 2051 * allocate transfer descriptors 2052 */ 2053 last_obj = NULL; 2054 2055 /* 2056 * get profile stuff 2057 */ 2058 ep_no = xfer->endpointno & UE_ADDR; 2059 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2060 2061 if (pf == NULL) { 2062 /* should not happen */ 2063 parm->err = USB_ERR_INVAL; 2064 return; 2065 } 2066 2067 /* align data */ 2068 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2069 2070 for (n = 0; n != ntd; n++) { 2071 2072 struct atmegadci_td *td; 2073 2074 if (parm->buf) { 2075 2076 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2077 2078 /* init TD */ 2079 td->max_packet_size = xfer->max_packet_size; 2080 td->ep_no = ep_no; 2081 if (pf->support_multi_buffer) { 2082 td->support_multi_buffer = 1; 2083 } 2084 td->obj_next = last_obj; 2085 2086 last_obj = td; 2087 } 2088 parm->size[0] += sizeof(*td); 2089 } 2090 2091 xfer->td_start[0] = last_obj; 2092 } 2093 2094 static void 2095 atmegadci_xfer_unsetup(struct usb_xfer *xfer) 2096 { 2097 return; 2098 } 2099 2100 static void 2101 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2102 struct usb_endpoint *ep) 2103 { 2104 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2105 2106 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2107 ep, udev->address, 2108 edesc->bEndpointAddress, udev->flags.usb_mode, 2109 sc->sc_rt_addr, udev->device_index); 2110 2111 if (udev->device_index != sc->sc_rt_addr) { 2112 2113 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2114 /* not supported */ 2115 return; 2116 } 2117 if (udev->speed != USB_SPEED_FULL) { 2118 /* not supported */ 2119 return; 2120 } 2121 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2122 ep->methods = &atmegadci_device_isoc_fs_methods; 2123 else 2124 ep->methods = &atmegadci_device_non_isoc_methods; 2125 } 2126 } 2127 2128 struct usb_bus_methods atmegadci_bus_methods = 2129 { 2130 .endpoint_init = &atmegadci_ep_init, 2131 .xfer_setup = &atmegadci_xfer_setup, 2132 .xfer_unsetup = &atmegadci_xfer_unsetup, 2133 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2134 .set_stall = &atmegadci_set_stall, 2135 .clear_stall = &atmegadci_clear_stall, 2136 .roothub_exec = &atmegadci_roothub_exec, 2137 .xfer_poll = &atmegadci_do_poll, 2138 }; 2139