1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 #include <dev/usb/usb_defs.h> 43 44 #define USB_DEBUG_VAR atmegadci_debug 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_debug.h> 48 #include <dev/usb/usb_busdma.h> 49 #include <dev/usb/usb_process.h> 50 #include <dev/usb/usb_sw_transfer.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/atmegadci.h> 59 60 #define ATMEGA_BUS2SC(bus) \ 61 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 62 USB_P2U(&(((struct atmegadci_softc *)0)->sc_bus)))) 63 64 #define ATMEGA_PC2SC(pc) \ 65 ATMEGA_BUS2SC((pc)->tag_parent->info->bus) 66 67 #if USB_DEBUG 68 static int atmegadci_debug = 0; 69 70 SYSCTL_NODE(_hw_usb2, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 71 SYSCTL_INT(_hw_usb2_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 72 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 73 #endif 74 75 #define ATMEGA_INTR_ENDPT 1 76 77 /* prototypes */ 78 79 struct usb2_bus_methods atmegadci_bus_methods; 80 struct usb2_pipe_methods atmegadci_device_bulk_methods; 81 struct usb2_pipe_methods atmegadci_device_ctrl_methods; 82 struct usb2_pipe_methods atmegadci_device_intr_methods; 83 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods; 84 struct usb2_pipe_methods atmegadci_root_ctrl_methods; 85 struct usb2_pipe_methods atmegadci_root_intr_methods; 86 87 static atmegadci_cmd_t atmegadci_setup_rx; 88 static atmegadci_cmd_t atmegadci_data_rx; 89 static atmegadci_cmd_t atmegadci_data_tx; 90 static atmegadci_cmd_t atmegadci_data_tx_sync; 91 static void atmegadci_device_done(struct usb2_xfer *, usb2_error_t); 92 static void atmegadci_do_poll(struct usb2_bus *); 93 static void atmegadci_root_ctrl_poll(struct atmegadci_softc *); 94 static void atmegadci_standard_done(struct usb2_xfer *); 95 96 static usb2_sw_transfer_func_t atmegadci_root_intr_done; 97 static usb2_sw_transfer_func_t atmegadci_root_ctrl_done; 98 99 /* 100 * Here is a list of what the chip supports: 101 */ 102 static const struct usb2_hw_ep_profile 103 atmegadci_ep_profile[2] = { 104 105 [0] = { 106 .max_in_frame_size = 64, 107 .max_out_frame_size = 64, 108 .is_simplex = 1, 109 .support_control = 1, 110 }, 111 [1] = { 112 .max_in_frame_size = 64, 113 .max_out_frame_size = 64, 114 .is_simplex = 1, 115 .support_multi_buffer = 1, 116 .support_bulk = 1, 117 .support_interrupt = 1, 118 .support_isochronous = 1, 119 .support_in = 1, 120 .support_out = 1, 121 }, 122 }; 123 124 static void 125 atmegadci_get_hw_ep_profile(struct usb2_device *udev, 126 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 127 { 128 if (ep_addr == 0) 129 *ppf = atmegadci_ep_profile; 130 else if (ep_addr < ATMEGA_EP_MAX) 131 *ppf = atmegadci_ep_profile + 1; 132 else 133 *ppf = NULL; 134 } 135 136 static void 137 atmegadci_clocks_on(struct atmegadci_softc *sc) 138 { 139 if (sc->sc_flags.clocks_off && 140 sc->sc_flags.port_powered) { 141 142 DPRINTFN(5, "\n"); 143 144 /* turn on clocks */ 145 (sc->sc_clocks_on) (&sc->sc_bus); 146 147 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 148 ATMEGA_USBCON_USBE | 149 ATMEGA_USBCON_OTGPADE | 150 ATMEGA_USBCON_VBUSTE); 151 152 sc->sc_flags.clocks_off = 0; 153 154 /* enable transceiver ? */ 155 } 156 } 157 158 static void 159 atmegadci_clocks_off(struct atmegadci_softc *sc) 160 { 161 if (!sc->sc_flags.clocks_off) { 162 163 DPRINTFN(5, "\n"); 164 165 /* disable Transceiver ? */ 166 167 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 168 ATMEGA_USBCON_USBE | 169 ATMEGA_USBCON_OTGPADE | 170 ATMEGA_USBCON_FRZCLK | 171 ATMEGA_USBCON_VBUSTE); 172 173 /* turn clocks off */ 174 (sc->sc_clocks_off) (&sc->sc_bus); 175 176 sc->sc_flags.clocks_off = 1; 177 } 178 } 179 180 static void 181 atmegadci_pull_up(struct atmegadci_softc *sc) 182 { 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 189 } 190 } 191 192 static void 193 atmegadci_pull_down(struct atmegadci_softc *sc) 194 { 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 200 } 201 } 202 203 static void 204 atmegadci_wakeup_peer(struct usb2_xfer *xfer) 205 { 206 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 207 uint8_t use_polling; 208 uint8_t temp; 209 210 if (!sc->sc_flags.status_suspend) { 211 return; 212 } 213 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 214 215 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 216 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 217 218 /* wait 8 milliseconds */ 219 if (use_polling) { 220 /* polling */ 221 DELAY(8000); 222 } else { 223 /* Wait for reset to complete. */ 224 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 225 } 226 227 /* hardware should have cleared RMWKUP bit */ 228 } 229 230 static void 231 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 232 { 233 DPRINTFN(5, "addr=%d\n", addr); 234 235 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 236 237 addr |= ATMEGA_UDADDR_ADDEN; 238 239 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 240 } 241 242 static uint8_t 243 atmegadci_setup_rx(struct atmegadci_td *td) 244 { 245 struct atmegadci_softc *sc; 246 struct usb2_device_request req; 247 uint16_t count; 248 uint8_t temp; 249 250 /* get pointer to softc */ 251 sc = ATMEGA_PC2SC(td->pc); 252 253 /* select endpoint number */ 254 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 255 256 /* check endpoint status */ 257 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 258 259 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 260 261 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 262 /* abort any ongoing transfer */ 263 if (!td->did_stall) { 264 DPRINTFN(5, "stalling\n"); 265 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 266 ATMEGA_UECONX_EPEN | 267 ATMEGA_UECONX_STALLRQ); 268 td->did_stall = 1; 269 } 270 goto not_complete; 271 } 272 /* get the packet byte count */ 273 count = 274 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 275 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 276 277 /* mask away undefined bits */ 278 count &= 0x7FF; 279 280 /* verify data length */ 281 if (count != td->remainder) { 282 DPRINTFN(0, "Invalid SETUP packet " 283 "length, %d bytes\n", count); 284 goto not_complete; 285 } 286 if (count != sizeof(req)) { 287 DPRINTFN(0, "Unsupported SETUP packet " 288 "length, %d bytes\n", count); 289 goto not_complete; 290 } 291 /* receive data */ 292 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 293 (void *)&req, sizeof(req)); 294 295 /* copy data into real buffer */ 296 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 297 298 td->offset = sizeof(req); 299 td->remainder = 0; 300 301 /* sneak peek the set address */ 302 if ((req.bmRequestType == UT_WRITE_DEVICE) && 303 (req.bRequest == UR_SET_ADDRESS)) { 304 sc->sc_dv_addr = req.wValue[0] & 0x7F; 305 } else { 306 sc->sc_dv_addr = 0xFF; 307 } 308 309 /* clear SETUP packet interrupt */ 310 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 311 return (0); /* complete */ 312 313 not_complete: 314 /* we only want to know if there is a SETUP packet */ 315 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 316 return (1); /* not complete */ 317 } 318 319 static uint8_t 320 atmegadci_data_rx(struct atmegadci_td *td) 321 { 322 struct atmegadci_softc *sc; 323 struct usb2_page_search buf_res; 324 uint16_t count; 325 uint8_t temp; 326 uint8_t to; 327 uint8_t got_short; 328 329 to = 3; /* don't loop forever! */ 330 got_short = 0; 331 332 /* get pointer to softc */ 333 sc = ATMEGA_PC2SC(td->pc); 334 335 /* select endpoint number */ 336 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 337 338 repeat: 339 /* check if any of the FIFO banks have data */ 340 /* check endpoint status */ 341 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 342 343 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 344 345 if (temp & ATMEGA_UEINTX_RXSTPI) { 346 if (td->remainder == 0) { 347 /* 348 * We are actually complete and have 349 * received the next SETUP 350 */ 351 DPRINTFN(5, "faking complete\n"); 352 return (0); /* complete */ 353 } 354 /* 355 * USB Host Aborted the transfer. 356 */ 357 td->error = 1; 358 return (0); /* complete */ 359 } 360 /* check status */ 361 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 362 ATMEGA_UEINTX_RXOUTI))) { 363 /* no data */ 364 goto not_complete; 365 } 366 /* get the packet byte count */ 367 count = 368 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 369 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 370 371 /* mask away undefined bits */ 372 count &= 0x7FF; 373 374 /* verify the packet byte count */ 375 if (count != td->max_packet_size) { 376 if (count < td->max_packet_size) { 377 /* we have a short packet */ 378 td->short_pkt = 1; 379 got_short = 1; 380 } else { 381 /* invalid USB packet */ 382 td->error = 1; 383 return (0); /* we are complete */ 384 } 385 } 386 /* verify the packet byte count */ 387 if (count > td->remainder) { 388 /* invalid USB packet */ 389 td->error = 1; 390 return (0); /* we are complete */ 391 } 392 while (count > 0) { 393 usb2_get_page(td->pc, td->offset, &buf_res); 394 395 /* get correct length */ 396 if (buf_res.length > count) { 397 buf_res.length = count; 398 } 399 /* receive data */ 400 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 401 buf_res.buffer, buf_res.length); 402 403 /* update counters */ 404 count -= buf_res.length; 405 td->offset += buf_res.length; 406 td->remainder -= buf_res.length; 407 } 408 409 /* clear OUT packet interrupt */ 410 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 411 412 /* release FIFO bank */ 413 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 414 415 /* check if we are complete */ 416 if ((td->remainder == 0) || got_short) { 417 if (td->short_pkt) { 418 /* we are complete */ 419 return (0); 420 } 421 /* else need to receive a zero length packet */ 422 } 423 if (--to) { 424 goto repeat; 425 } 426 not_complete: 427 /* we only want to know if there is a SETUP packet or OUT packet */ 428 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 429 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 430 return (1); /* not complete */ 431 } 432 433 static uint8_t 434 atmegadci_data_tx(struct atmegadci_td *td) 435 { 436 struct atmegadci_softc *sc; 437 struct usb2_page_search buf_res; 438 uint16_t count; 439 uint8_t to; 440 uint8_t temp; 441 442 to = 3; /* don't loop forever! */ 443 444 /* get pointer to softc */ 445 sc = ATMEGA_PC2SC(td->pc); 446 447 /* select endpoint number */ 448 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 449 450 repeat: 451 452 /* check endpoint status */ 453 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 454 455 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 456 457 if (temp & ATMEGA_UEINTX_RXSTPI) { 458 /* 459 * The current transfer was aborted 460 * by the USB Host 461 */ 462 td->error = 1; 463 return (0); /* complete */ 464 } 465 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 466 ATMEGA_UEINTX_TXINI))) { 467 /* cannot write any data */ 468 goto not_complete; 469 } 470 count = td->max_packet_size; 471 if (td->remainder < count) { 472 /* we have a short packet */ 473 td->short_pkt = 1; 474 count = td->remainder; 475 } 476 while (count > 0) { 477 478 usb2_get_page(td->pc, td->offset, &buf_res); 479 480 /* get correct length */ 481 if (buf_res.length > count) { 482 buf_res.length = count; 483 } 484 /* transmit data */ 485 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 486 buf_res.buffer, buf_res.length); 487 488 /* update counters */ 489 count -= buf_res.length; 490 td->offset += buf_res.length; 491 td->remainder -= buf_res.length; 492 } 493 494 /* clear IN packet interrupt */ 495 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 496 497 /* allocate FIFO bank */ 498 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 499 500 /* check remainder */ 501 if (td->remainder == 0) { 502 if (td->short_pkt) { 503 return (0); /* complete */ 504 } 505 /* else we need to transmit a short packet */ 506 } 507 if (--to) { 508 goto repeat; 509 } 510 not_complete: 511 /* we only want to know if there is a SETUP packet or free IN packet */ 512 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 513 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 514 return (1); /* not complete */ 515 } 516 517 static uint8_t 518 atmegadci_data_tx_sync(struct atmegadci_td *td) 519 { 520 struct atmegadci_softc *sc; 521 uint8_t temp; 522 523 /* get pointer to softc */ 524 sc = ATMEGA_PC2SC(td->pc); 525 526 /* select endpoint number */ 527 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 528 529 /* check endpoint status */ 530 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 531 532 DPRINTFN(5, "temp=0x%02x\n", temp); 533 534 if (temp & ATMEGA_UEINTX_RXSTPI) { 535 DPRINTFN(5, "faking complete\n"); 536 /* Race condition */ 537 return (0); /* complete */ 538 } 539 /* 540 * The control endpoint has only got one bank, so if that bank 541 * is free the packet has been transferred! 542 */ 543 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 544 ATMEGA_UEINTX_TXINI))) { 545 /* cannot write any data */ 546 goto not_complete; 547 } 548 if (sc->sc_dv_addr != 0xFF) { 549 /* set new address */ 550 atmegadci_set_address(sc, sc->sc_dv_addr); 551 } 552 return (0); /* complete */ 553 554 not_complete: 555 /* we only want to know if there is a SETUP packet or free IN packet */ 556 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 557 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 558 return (1); /* not complete */ 559 } 560 561 static uint8_t 562 atmegadci_xfer_do_fifo(struct usb2_xfer *xfer) 563 { 564 struct atmegadci_td *td; 565 566 DPRINTFN(9, "\n"); 567 568 td = xfer->td_transfer_cache; 569 while (1) { 570 if ((td->func) (td)) { 571 /* operation in progress */ 572 break; 573 } 574 if (((void *)td) == xfer->td_transfer_last) { 575 goto done; 576 } 577 if (td->error) { 578 goto done; 579 } else if (td->remainder > 0) { 580 /* 581 * We had a short transfer. If there is no alternate 582 * next, stop processing ! 583 */ 584 if (!td->alt_next) { 585 goto done; 586 } 587 } 588 /* 589 * Fetch the next transfer descriptor and transfer 590 * some flags to the next transfer descriptor 591 */ 592 td = td->obj_next; 593 xfer->td_transfer_cache = td; 594 } 595 return (1); /* not complete */ 596 597 done: 598 /* compute all actual lengths */ 599 600 atmegadci_standard_done(xfer); 601 return (0); /* complete */ 602 } 603 604 static void 605 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 606 { 607 struct usb2_xfer *xfer; 608 609 repeat: 610 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 611 if (!atmegadci_xfer_do_fifo(xfer)) { 612 /* queue has been modified */ 613 goto repeat; 614 } 615 } 616 } 617 618 static void 619 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 620 { 621 DPRINTFN(5, "vbus = %u\n", is_on); 622 623 if (is_on) { 624 if (!sc->sc_flags.status_vbus) { 625 sc->sc_flags.status_vbus = 1; 626 627 /* complete root HUB interrupt endpoint */ 628 629 usb2_sw_transfer(&sc->sc_root_intr, 630 &atmegadci_root_intr_done); 631 } 632 } else { 633 if (sc->sc_flags.status_vbus) { 634 sc->sc_flags.status_vbus = 0; 635 sc->sc_flags.status_bus_reset = 0; 636 sc->sc_flags.status_suspend = 0; 637 sc->sc_flags.change_suspend = 0; 638 sc->sc_flags.change_connect = 1; 639 640 /* complete root HUB interrupt endpoint */ 641 642 usb2_sw_transfer(&sc->sc_root_intr, 643 &atmegadci_root_intr_done); 644 } 645 } 646 } 647 648 void 649 atmegadci_interrupt(struct atmegadci_softc *sc) 650 { 651 uint8_t status; 652 653 USB_BUS_LOCK(&sc->sc_bus); 654 655 /* read interrupt status */ 656 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 657 658 /* clear all set interrupts */ 659 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, ~status); 660 661 /* check for any bus state change interrupts */ 662 if (status & ATMEGA_UDINT_EORSTI) { 663 664 DPRINTFN(5, "end of reset\n"); 665 666 /* set correct state */ 667 sc->sc_flags.status_bus_reset = 1; 668 sc->sc_flags.status_suspend = 0; 669 sc->sc_flags.change_suspend = 0; 670 sc->sc_flags.change_connect = 1; 671 672 /* disable resume interrupt */ 673 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 674 ATMEGA_UDINT_SUSPE | 675 ATMEGA_UDINT_EORSTE); 676 677 /* complete root HUB interrupt endpoint */ 678 usb2_sw_transfer(&sc->sc_root_intr, 679 &atmegadci_root_intr_done); 680 } 681 /* 682 * If resume and suspend is set at the same time we interpret 683 * that like RESUME. Resume is set when there is at least 3 684 * milliseconds of inactivity on the USB BUS. 685 */ 686 if (status & ATMEGA_UDINT_EORSMI) { 687 688 DPRINTFN(5, "resume interrupt\n"); 689 690 if (sc->sc_flags.status_suspend) { 691 /* update status bits */ 692 sc->sc_flags.status_suspend = 0; 693 sc->sc_flags.change_suspend = 1; 694 695 /* disable resume interrupt */ 696 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 697 ATMEGA_UDINT_SUSPE | 698 ATMEGA_UDINT_EORSTE); 699 700 /* complete root HUB interrupt endpoint */ 701 usb2_sw_transfer(&sc->sc_root_intr, 702 &atmegadci_root_intr_done); 703 } 704 } else if (status & ATMEGA_UDINT_SUSPI) { 705 706 DPRINTFN(5, "suspend interrupt\n"); 707 708 if (!sc->sc_flags.status_suspend) { 709 /* update status bits */ 710 sc->sc_flags.status_suspend = 1; 711 sc->sc_flags.change_suspend = 1; 712 713 /* disable suspend interrupt */ 714 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 715 ATMEGA_UDINT_EORSMI | 716 ATMEGA_UDINT_EORSTE); 717 718 /* complete root HUB interrupt endpoint */ 719 usb2_sw_transfer(&sc->sc_root_intr, 720 &atmegadci_root_intr_done); 721 } 722 } 723 /* check VBUS */ 724 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 725 726 /* clear all set interrupts */ 727 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, ~status); 728 729 if (status & ATMEGA_USBINT_VBUSTI) { 730 uint8_t temp; 731 732 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 733 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 734 } 735 /* check for any endpoint interrupts */ 736 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 737 738 /* clear all set interrupts */ 739 ATMEGA_WRITE_1(sc, ATMEGA_UEINT, ~status); 740 741 if (status) { 742 743 DPRINTFN(5, "real endpoint interrupt 0x%02x\n", status); 744 745 atmegadci_interrupt_poll(sc); 746 } 747 USB_BUS_UNLOCK(&sc->sc_bus); 748 } 749 750 static void 751 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 752 { 753 struct atmegadci_td *td; 754 755 /* get current Transfer Descriptor */ 756 td = temp->td_next; 757 temp->td = td; 758 759 /* prepare for next TD */ 760 temp->td_next = td->obj_next; 761 762 /* fill out the Transfer Descriptor */ 763 td->func = temp->func; 764 td->pc = temp->pc; 765 td->offset = temp->offset; 766 td->remainder = temp->len; 767 td->error = 0; 768 td->did_stall = 0; 769 td->short_pkt = temp->short_pkt; 770 td->alt_next = temp->setup_alt_next; 771 } 772 773 static void 774 atmegadci_setup_standard_chain(struct usb2_xfer *xfer) 775 { 776 struct atmegadci_std_temp temp; 777 struct atmegadci_softc *sc; 778 struct atmegadci_td *td; 779 uint32_t x; 780 uint8_t ep_no; 781 uint8_t need_sync; 782 783 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 784 xfer->address, UE_GET_ADDR(xfer->endpoint), 785 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 786 787 temp.max_frame_size = xfer->max_frame_size; 788 789 td = xfer->td_start[0]; 790 xfer->td_transfer_first = td; 791 xfer->td_transfer_cache = td; 792 793 /* setup temp */ 794 795 temp.td = NULL; 796 temp.td_next = xfer->td_start[0]; 797 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 798 temp.offset = 0; 799 800 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 801 ep_no = (xfer->endpoint & UE_ADDR); 802 803 /* check if we should prepend a setup message */ 804 805 if (xfer->flags_int.control_xfr) { 806 if (xfer->flags_int.control_hdr) { 807 808 temp.func = &atmegadci_setup_rx; 809 temp.len = xfer->frlengths[0]; 810 temp.pc = xfer->frbuffers + 0; 811 temp.short_pkt = temp.len ? 1 : 0; 812 813 atmegadci_setup_standard_chain_sub(&temp); 814 } 815 x = 1; 816 } else { 817 x = 0; 818 } 819 820 if (x != xfer->nframes) { 821 if (xfer->endpoint & UE_DIR_IN) { 822 temp.func = &atmegadci_data_tx; 823 need_sync = 1; 824 } else { 825 temp.func = &atmegadci_data_rx; 826 need_sync = 0; 827 } 828 829 /* setup "pc" pointer */ 830 temp.pc = xfer->frbuffers + x; 831 } else { 832 need_sync = 0; 833 } 834 while (x != xfer->nframes) { 835 836 /* DATA0 / DATA1 message */ 837 838 temp.len = xfer->frlengths[x]; 839 840 x++; 841 842 if (x == xfer->nframes) { 843 temp.setup_alt_next = 0; 844 } 845 if (temp.len == 0) { 846 847 /* make sure that we send an USB packet */ 848 849 temp.short_pkt = 0; 850 851 } else { 852 853 /* regular data transfer */ 854 855 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 856 } 857 858 atmegadci_setup_standard_chain_sub(&temp); 859 860 if (xfer->flags_int.isochronous_xfr) { 861 temp.offset += temp.len; 862 } else { 863 /* get next Page Cache pointer */ 864 temp.pc = xfer->frbuffers + x; 865 } 866 } 867 868 /* always setup a valid "pc" pointer for status and sync */ 869 temp.pc = xfer->frbuffers + 0; 870 871 /* check if we need to sync */ 872 if (need_sync && xfer->flags_int.control_xfr) { 873 874 /* we need a SYNC point after TX */ 875 temp.func = &atmegadci_data_tx_sync; 876 temp.len = 0; 877 temp.short_pkt = 0; 878 879 atmegadci_setup_standard_chain_sub(&temp); 880 } 881 /* check if we should append a status stage */ 882 if (xfer->flags_int.control_xfr && 883 !xfer->flags_int.control_act) { 884 885 /* 886 * Send a DATA1 message and invert the current 887 * endpoint direction. 888 */ 889 if (xfer->endpoint & UE_DIR_IN) { 890 temp.func = &atmegadci_data_rx; 891 need_sync = 0; 892 } else { 893 temp.func = &atmegadci_data_tx; 894 need_sync = 1; 895 } 896 temp.len = 0; 897 temp.short_pkt = 0; 898 899 atmegadci_setup_standard_chain_sub(&temp); 900 if (need_sync) { 901 /* we need a SYNC point after TX */ 902 temp.func = &atmegadci_data_tx_sync; 903 temp.len = 0; 904 temp.short_pkt = 0; 905 906 atmegadci_setup_standard_chain_sub(&temp); 907 } 908 } 909 /* must have at least one frame! */ 910 td = temp.td; 911 xfer->td_transfer_last = td; 912 } 913 914 static void 915 atmegadci_timeout(void *arg) 916 { 917 struct usb2_xfer *xfer = arg; 918 919 DPRINTF("xfer=%p\n", xfer); 920 921 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 922 923 /* transfer is transferred */ 924 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 925 } 926 927 static void 928 atmegadci_start_standard_chain(struct usb2_xfer *xfer) 929 { 930 DPRINTFN(9, "\n"); 931 932 /* poll one time - will turn on interrupts */ 933 if (atmegadci_xfer_do_fifo(xfer)) { 934 935 /* put transfer on interrupt queue */ 936 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 937 938 /* start timeout, if any */ 939 if (xfer->timeout != 0) { 940 usb2_transfer_timeout_ms(xfer, 941 &atmegadci_timeout, xfer->timeout); 942 } 943 } 944 } 945 946 static void 947 atmegadci_root_intr_done(struct usb2_xfer *xfer, 948 struct usb2_sw_transfer *std) 949 { 950 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 951 952 DPRINTFN(9, "\n"); 953 954 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 955 956 if (std->state != USB_SW_TR_PRE_DATA) { 957 if (std->state == USB_SW_TR_PRE_CALLBACK) { 958 /* transfer transferred */ 959 atmegadci_device_done(xfer, std->err); 960 } 961 goto done; 962 } 963 /* setup buffer */ 964 std->ptr = sc->sc_hub_idata; 965 std->len = sizeof(sc->sc_hub_idata); 966 967 /* set port bit */ 968 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 969 970 done: 971 return; 972 } 973 974 static usb2_error_t 975 atmegadci_standard_done_sub(struct usb2_xfer *xfer) 976 { 977 struct atmegadci_td *td; 978 uint32_t len; 979 uint8_t error; 980 981 DPRINTFN(9, "\n"); 982 983 td = xfer->td_transfer_cache; 984 985 do { 986 len = td->remainder; 987 988 if (xfer->aframes != xfer->nframes) { 989 /* 990 * Verify the length and subtract 991 * the remainder from "frlengths[]": 992 */ 993 if (len > xfer->frlengths[xfer->aframes]) { 994 td->error = 1; 995 } else { 996 xfer->frlengths[xfer->aframes] -= len; 997 } 998 } 999 /* Check for transfer error */ 1000 if (td->error) { 1001 /* the transfer is finished */ 1002 error = 1; 1003 td = NULL; 1004 break; 1005 } 1006 /* Check for short transfer */ 1007 if (len > 0) { 1008 if (xfer->flags_int.short_frames_ok) { 1009 /* follow alt next */ 1010 if (td->alt_next) { 1011 td = td->obj_next; 1012 } else { 1013 td = NULL; 1014 } 1015 } else { 1016 /* the transfer is finished */ 1017 td = NULL; 1018 } 1019 error = 0; 1020 break; 1021 } 1022 td = td->obj_next; 1023 1024 /* this USB frame is complete */ 1025 error = 0; 1026 break; 1027 1028 } while (0); 1029 1030 /* update transfer cache */ 1031 1032 xfer->td_transfer_cache = td; 1033 1034 return (error ? 1035 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1036 } 1037 1038 static void 1039 atmegadci_standard_done(struct usb2_xfer *xfer) 1040 { 1041 usb2_error_t err = 0; 1042 1043 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1044 xfer, xfer->pipe); 1045 1046 /* reset scanner */ 1047 1048 xfer->td_transfer_cache = xfer->td_transfer_first; 1049 1050 if (xfer->flags_int.control_xfr) { 1051 1052 if (xfer->flags_int.control_hdr) { 1053 1054 err = atmegadci_standard_done_sub(xfer); 1055 } 1056 xfer->aframes = 1; 1057 1058 if (xfer->td_transfer_cache == NULL) { 1059 goto done; 1060 } 1061 } 1062 while (xfer->aframes != xfer->nframes) { 1063 1064 err = atmegadci_standard_done_sub(xfer); 1065 xfer->aframes++; 1066 1067 if (xfer->td_transfer_cache == NULL) { 1068 goto done; 1069 } 1070 } 1071 1072 if (xfer->flags_int.control_xfr && 1073 !xfer->flags_int.control_act) { 1074 1075 err = atmegadci_standard_done_sub(xfer); 1076 } 1077 done: 1078 atmegadci_device_done(xfer, err); 1079 } 1080 1081 /*------------------------------------------------------------------------* 1082 * atmegadci_device_done 1083 * 1084 * NOTE: this function can be called more than one time on the 1085 * same USB transfer! 1086 *------------------------------------------------------------------------*/ 1087 static void 1088 atmegadci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1089 { 1090 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1091 uint8_t ep_no; 1092 1093 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1094 1095 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1096 xfer, xfer->pipe, error); 1097 1098 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1099 ep_no = (xfer->endpoint & UE_ADDR); 1100 1101 /* select endpoint number */ 1102 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1103 1104 /* disable endpoint interrupt */ 1105 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1106 1107 DPRINTFN(15, "disabled interrupts!\n"); 1108 } 1109 /* dequeue transfer and start next transfer */ 1110 usb2_transfer_done(xfer, error); 1111 } 1112 1113 static void 1114 atmegadci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1115 struct usb2_pipe *pipe) 1116 { 1117 struct atmegadci_softc *sc; 1118 uint8_t ep_no; 1119 1120 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1121 1122 DPRINTFN(5, "pipe=%p\n", pipe); 1123 1124 if (xfer) { 1125 /* cancel any ongoing transfers */ 1126 atmegadci_device_done(xfer, USB_ERR_STALLED); 1127 } 1128 sc = ATMEGA_BUS2SC(udev->bus); 1129 /* get endpoint number */ 1130 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1131 /* select endpoint number */ 1132 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1133 /* set stall */ 1134 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1135 ATMEGA_UECONX_EPEN | 1136 ATMEGA_UECONX_STALLRQ); 1137 } 1138 1139 static void 1140 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1141 uint8_t ep_type, uint8_t ep_dir) 1142 { 1143 uint8_t temp; 1144 1145 if (ep_type == UE_CONTROL) { 1146 /* clearing stall is not needed */ 1147 return; 1148 } 1149 /* select endpoint number */ 1150 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1151 1152 /* set endpoint reset */ 1153 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1154 1155 /* clear endpoint reset */ 1156 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1157 1158 /* set stall */ 1159 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1160 ATMEGA_UECONX_EPEN | 1161 ATMEGA_UECONX_STALLRQ); 1162 1163 /* reset data toggle */ 1164 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1165 ATMEGA_UECONX_EPEN | 1166 ATMEGA_UECONX_RSTDT); 1167 1168 /* clear stall */ 1169 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1170 ATMEGA_UECONX_EPEN | 1171 ATMEGA_UECONX_STALLRQC); 1172 1173 if (ep_type == UE_CONTROL) { 1174 /* one bank, 64-bytes wMaxPacket */ 1175 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1176 ATMEGA_UECFG0X_EPTYPE0); 1177 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1178 ATMEGA_UECFG1X_ALLOC | 1179 ATMEGA_UECFG1X_EPBK0 | 1180 ATMEGA_UECFG1X_EPSIZE(7)); 1181 } else { 1182 temp = 0; 1183 if (ep_type == UE_BULK) { 1184 temp |= ATMEGA_UECFG0X_EPTYPE2; 1185 } else if (ep_type == UE_INTERRUPT) { 1186 temp |= ATMEGA_UECFG0X_EPTYPE3; 1187 } else { 1188 temp |= ATMEGA_UECFG0X_EPTYPE1; 1189 } 1190 if (ep_dir & UE_DIR_IN) { 1191 temp |= ATMEGA_UECFG0X_EPDIR; 1192 } 1193 /* two banks, 64-bytes wMaxPacket */ 1194 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1195 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1196 ATMEGA_UECFG1X_ALLOC | 1197 ATMEGA_UECFG1X_EPBK1 | 1198 ATMEGA_UECFG1X_EPSIZE(7)); 1199 1200 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1201 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1202 DPRINTFN(0, "Chip rejected configuration\n"); 1203 } 1204 } 1205 } 1206 1207 static void 1208 atmegadci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1209 { 1210 struct atmegadci_softc *sc; 1211 struct usb2_endpoint_descriptor *ed; 1212 1213 DPRINTFN(5, "pipe=%p\n", pipe); 1214 1215 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1216 1217 /* check mode */ 1218 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1219 /* not supported */ 1220 return; 1221 } 1222 /* get softc */ 1223 sc = ATMEGA_BUS2SC(udev->bus); 1224 1225 /* get endpoint descriptor */ 1226 ed = pipe->edesc; 1227 1228 /* reset endpoint */ 1229 atmegadci_clear_stall_sub(sc, 1230 (ed->bEndpointAddress & UE_ADDR), 1231 (ed->bmAttributes & UE_XFERTYPE), 1232 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1233 } 1234 1235 usb2_error_t 1236 atmegadci_init(struct atmegadci_softc *sc) 1237 { 1238 uint8_t n; 1239 1240 DPRINTF("start\n"); 1241 1242 /* set up the bus structure */ 1243 sc->sc_bus.usbrev = USB_REV_1_1; 1244 sc->sc_bus.methods = &atmegadci_bus_methods; 1245 1246 USB_BUS_LOCK(&sc->sc_bus); 1247 1248 /* enable USB PAD regulator */ 1249 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1250 ATMEGA_UHWCON_UVREGE); 1251 1252 /* turn on clocks */ 1253 (sc->sc_clocks_on) (&sc->sc_bus); 1254 1255 /* wait a little for things to stabilise */ 1256 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1257 1258 /* enable interrupts */ 1259 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1260 ATMEGA_UDINT_SUSPE | 1261 ATMEGA_UDINT_EORSTE); 1262 1263 /* reset all endpoints */ 1264 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1265 (1 << ATMEGA_EP_MAX) - 1); 1266 1267 /* disable reset */ 1268 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1269 1270 /* disable all endpoints */ 1271 for (n = 1; n != ATMEGA_EP_MAX; n++) { 1272 1273 /* select endpoint */ 1274 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1275 1276 /* disable endpoint interrupt */ 1277 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1278 1279 /* disable endpoint */ 1280 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1281 } 1282 1283 /* turn off clocks */ 1284 1285 atmegadci_clocks_off(sc); 1286 1287 USB_BUS_UNLOCK(&sc->sc_bus); 1288 1289 /* catch any lost interrupts */ 1290 1291 atmegadci_do_poll(&sc->sc_bus); 1292 1293 return (0); /* success */ 1294 } 1295 1296 void 1297 atmegadci_uninit(struct atmegadci_softc *sc) 1298 { 1299 USB_BUS_LOCK(&sc->sc_bus); 1300 1301 /* turn on clocks */ 1302 (sc->sc_clocks_on) (&sc->sc_bus); 1303 1304 /* disable interrupts */ 1305 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1306 1307 /* reset all endpoints */ 1308 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1309 (1 << ATMEGA_EP_MAX) - 1); 1310 1311 /* disable reset */ 1312 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1313 1314 sc->sc_flags.port_powered = 0; 1315 sc->sc_flags.status_vbus = 0; 1316 sc->sc_flags.status_bus_reset = 0; 1317 sc->sc_flags.status_suspend = 0; 1318 sc->sc_flags.change_suspend = 0; 1319 sc->sc_flags.change_connect = 1; 1320 1321 atmegadci_pull_down(sc); 1322 atmegadci_clocks_off(sc); 1323 1324 /* disable USB PAD regulator */ 1325 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1326 1327 USB_BUS_UNLOCK(&sc->sc_bus); 1328 } 1329 1330 void 1331 atmegadci_suspend(struct atmegadci_softc *sc) 1332 { 1333 return; 1334 } 1335 1336 void 1337 atmegadci_resume(struct atmegadci_softc *sc) 1338 { 1339 return; 1340 } 1341 1342 static void 1343 atmegadci_do_poll(struct usb2_bus *bus) 1344 { 1345 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1346 1347 USB_BUS_LOCK(&sc->sc_bus); 1348 atmegadci_interrupt_poll(sc); 1349 atmegadci_root_ctrl_poll(sc); 1350 USB_BUS_UNLOCK(&sc->sc_bus); 1351 } 1352 1353 /*------------------------------------------------------------------------* 1354 * at91dci bulk support 1355 *------------------------------------------------------------------------*/ 1356 static void 1357 atmegadci_device_bulk_open(struct usb2_xfer *xfer) 1358 { 1359 return; 1360 } 1361 1362 static void 1363 atmegadci_device_bulk_close(struct usb2_xfer *xfer) 1364 { 1365 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1366 } 1367 1368 static void 1369 atmegadci_device_bulk_enter(struct usb2_xfer *xfer) 1370 { 1371 return; 1372 } 1373 1374 static void 1375 atmegadci_device_bulk_start(struct usb2_xfer *xfer) 1376 { 1377 /* setup TDs */ 1378 atmegadci_setup_standard_chain(xfer); 1379 atmegadci_start_standard_chain(xfer); 1380 } 1381 1382 struct usb2_pipe_methods atmegadci_device_bulk_methods = 1383 { 1384 .open = atmegadci_device_bulk_open, 1385 .close = atmegadci_device_bulk_close, 1386 .enter = atmegadci_device_bulk_enter, 1387 .start = atmegadci_device_bulk_start, 1388 .enter_is_cancelable = 1, 1389 .start_is_cancelable = 1, 1390 }; 1391 1392 /*------------------------------------------------------------------------* 1393 * at91dci control support 1394 *------------------------------------------------------------------------*/ 1395 static void 1396 atmegadci_device_ctrl_open(struct usb2_xfer *xfer) 1397 { 1398 return; 1399 } 1400 1401 static void 1402 atmegadci_device_ctrl_close(struct usb2_xfer *xfer) 1403 { 1404 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1405 } 1406 1407 static void 1408 atmegadci_device_ctrl_enter(struct usb2_xfer *xfer) 1409 { 1410 return; 1411 } 1412 1413 static void 1414 atmegadci_device_ctrl_start(struct usb2_xfer *xfer) 1415 { 1416 /* setup TDs */ 1417 atmegadci_setup_standard_chain(xfer); 1418 atmegadci_start_standard_chain(xfer); 1419 } 1420 1421 struct usb2_pipe_methods atmegadci_device_ctrl_methods = 1422 { 1423 .open = atmegadci_device_ctrl_open, 1424 .close = atmegadci_device_ctrl_close, 1425 .enter = atmegadci_device_ctrl_enter, 1426 .start = atmegadci_device_ctrl_start, 1427 .enter_is_cancelable = 1, 1428 .start_is_cancelable = 1, 1429 }; 1430 1431 /*------------------------------------------------------------------------* 1432 * at91dci interrupt support 1433 *------------------------------------------------------------------------*/ 1434 static void 1435 atmegadci_device_intr_open(struct usb2_xfer *xfer) 1436 { 1437 return; 1438 } 1439 1440 static void 1441 atmegadci_device_intr_close(struct usb2_xfer *xfer) 1442 { 1443 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1444 } 1445 1446 static void 1447 atmegadci_device_intr_enter(struct usb2_xfer *xfer) 1448 { 1449 return; 1450 } 1451 1452 static void 1453 atmegadci_device_intr_start(struct usb2_xfer *xfer) 1454 { 1455 /* setup TDs */ 1456 atmegadci_setup_standard_chain(xfer); 1457 atmegadci_start_standard_chain(xfer); 1458 } 1459 1460 struct usb2_pipe_methods atmegadci_device_intr_methods = 1461 { 1462 .open = atmegadci_device_intr_open, 1463 .close = atmegadci_device_intr_close, 1464 .enter = atmegadci_device_intr_enter, 1465 .start = atmegadci_device_intr_start, 1466 .enter_is_cancelable = 1, 1467 .start_is_cancelable = 1, 1468 }; 1469 1470 /*------------------------------------------------------------------------* 1471 * at91dci full speed isochronous support 1472 *------------------------------------------------------------------------*/ 1473 static void 1474 atmegadci_device_isoc_fs_open(struct usb2_xfer *xfer) 1475 { 1476 return; 1477 } 1478 1479 static void 1480 atmegadci_device_isoc_fs_close(struct usb2_xfer *xfer) 1481 { 1482 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1483 } 1484 1485 static void 1486 atmegadci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1487 { 1488 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1489 uint32_t temp; 1490 uint32_t nframes; 1491 1492 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1493 xfer, xfer->pipe->isoc_next, xfer->nframes); 1494 1495 /* get the current frame index */ 1496 1497 nframes = 1498 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1499 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1500 1501 nframes &= ATMEGA_FRAME_MASK; 1502 1503 /* 1504 * check if the frame index is within the window where the frames 1505 * will be inserted 1506 */ 1507 temp = (nframes - xfer->pipe->isoc_next) & ATMEGA_FRAME_MASK; 1508 1509 if ((xfer->pipe->is_synced == 0) || 1510 (temp < xfer->nframes)) { 1511 /* 1512 * If there is data underflow or the pipe queue is 1513 * empty we schedule the transfer a few frames ahead 1514 * of the current frame position. Else two isochronous 1515 * transfers might overlap. 1516 */ 1517 xfer->pipe->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1518 xfer->pipe->is_synced = 1; 1519 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1520 } 1521 /* 1522 * compute how many milliseconds the insertion is ahead of the 1523 * current frame position: 1524 */ 1525 temp = (xfer->pipe->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1526 1527 /* 1528 * pre-compute when the isochronous transfer will be finished: 1529 */ 1530 xfer->isoc_time_complete = 1531 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1532 xfer->nframes; 1533 1534 /* compute frame number for next insertion */ 1535 xfer->pipe->isoc_next += xfer->nframes; 1536 1537 /* setup TDs */ 1538 atmegadci_setup_standard_chain(xfer); 1539 } 1540 1541 static void 1542 atmegadci_device_isoc_fs_start(struct usb2_xfer *xfer) 1543 { 1544 /* start TD chain */ 1545 atmegadci_start_standard_chain(xfer); 1546 } 1547 1548 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods = 1549 { 1550 .open = atmegadci_device_isoc_fs_open, 1551 .close = atmegadci_device_isoc_fs_close, 1552 .enter = atmegadci_device_isoc_fs_enter, 1553 .start = atmegadci_device_isoc_fs_start, 1554 .enter_is_cancelable = 1, 1555 .start_is_cancelable = 1, 1556 }; 1557 1558 /*------------------------------------------------------------------------* 1559 * at91dci root control support 1560 *------------------------------------------------------------------------* 1561 * simulate a hardware HUB by handling 1562 * all the necessary requests 1563 *------------------------------------------------------------------------*/ 1564 1565 static void 1566 atmegadci_root_ctrl_open(struct usb2_xfer *xfer) 1567 { 1568 return; 1569 } 1570 1571 static void 1572 atmegadci_root_ctrl_close(struct usb2_xfer *xfer) 1573 { 1574 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1575 1576 if (sc->sc_root_ctrl.xfer == xfer) { 1577 sc->sc_root_ctrl.xfer = NULL; 1578 } 1579 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1580 } 1581 1582 /* 1583 * USB descriptors for the virtual Root HUB: 1584 */ 1585 1586 static const struct usb2_device_descriptor atmegadci_devd = { 1587 .bLength = sizeof(struct usb2_device_descriptor), 1588 .bDescriptorType = UDESC_DEVICE, 1589 .bcdUSB = {0x00, 0x02}, 1590 .bDeviceClass = UDCLASS_HUB, 1591 .bDeviceSubClass = UDSUBCLASS_HUB, 1592 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1593 .bMaxPacketSize = 64, 1594 .bcdDevice = {0x00, 0x01}, 1595 .iManufacturer = 1, 1596 .iProduct = 2, 1597 .bNumConfigurations = 1, 1598 }; 1599 1600 static const struct usb2_device_qualifier atmegadci_odevd = { 1601 .bLength = sizeof(struct usb2_device_qualifier), 1602 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1603 .bcdUSB = {0x00, 0x02}, 1604 .bDeviceClass = UDCLASS_HUB, 1605 .bDeviceSubClass = UDSUBCLASS_HUB, 1606 .bDeviceProtocol = UDPROTO_FSHUB, 1607 .bMaxPacketSize0 = 0, 1608 .bNumConfigurations = 0, 1609 }; 1610 1611 static const struct atmegadci_config_desc atmegadci_confd = { 1612 .confd = { 1613 .bLength = sizeof(struct usb2_config_descriptor), 1614 .bDescriptorType = UDESC_CONFIG, 1615 .wTotalLength[0] = sizeof(atmegadci_confd), 1616 .bNumInterface = 1, 1617 .bConfigurationValue = 1, 1618 .iConfiguration = 0, 1619 .bmAttributes = UC_SELF_POWERED, 1620 .bMaxPower = 0, 1621 }, 1622 .ifcd = { 1623 .bLength = sizeof(struct usb2_interface_descriptor), 1624 .bDescriptorType = UDESC_INTERFACE, 1625 .bNumEndpoints = 1, 1626 .bInterfaceClass = UICLASS_HUB, 1627 .bInterfaceSubClass = UISUBCLASS_HUB, 1628 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1629 }, 1630 1631 .endpd = { 1632 .bLength = sizeof(struct usb2_endpoint_descriptor), 1633 .bDescriptorType = UDESC_ENDPOINT, 1634 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1635 .bmAttributes = UE_INTERRUPT, 1636 .wMaxPacketSize[0] = 8, 1637 .bInterval = 255, 1638 }, 1639 }; 1640 1641 static const struct usb2_hub_descriptor_min atmegadci_hubd = { 1642 .bDescLength = sizeof(atmegadci_hubd), 1643 .bDescriptorType = UDESC_HUB, 1644 .bNbrPorts = 1, 1645 .wHubCharacteristics[0] = 1646 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1647 .wHubCharacteristics[1] = 1648 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1649 .bPwrOn2PwrGood = 50, 1650 .bHubContrCurrent = 0, 1651 .DeviceRemovable = {0}, /* port is removable */ 1652 }; 1653 1654 #define STRING_LANG \ 1655 0x09, 0x04, /* American English */ 1656 1657 #define STRING_VENDOR \ 1658 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1659 1660 #define STRING_PRODUCT \ 1661 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1662 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1663 'U', 0, 'B', 0, 1664 1665 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1666 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1667 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1668 1669 static void 1670 atmegadci_root_ctrl_enter(struct usb2_xfer *xfer) 1671 { 1672 return; 1673 } 1674 1675 static void 1676 atmegadci_root_ctrl_start(struct usb2_xfer *xfer) 1677 { 1678 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1679 1680 sc->sc_root_ctrl.xfer = xfer; 1681 1682 usb2_bus_roothub_exec(xfer->xroot->bus); 1683 } 1684 1685 static void 1686 atmegadci_root_ctrl_task(struct usb2_bus *bus) 1687 { 1688 atmegadci_root_ctrl_poll(ATMEGA_BUS2SC(bus)); 1689 } 1690 1691 static void 1692 atmegadci_root_ctrl_done(struct usb2_xfer *xfer, 1693 struct usb2_sw_transfer *std) 1694 { 1695 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1696 uint16_t value; 1697 uint16_t index; 1698 uint8_t use_polling; 1699 1700 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1701 1702 if (std->state != USB_SW_TR_SETUP) { 1703 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1704 /* transfer transferred */ 1705 atmegadci_device_done(xfer, std->err); 1706 } 1707 goto done; 1708 } 1709 /* buffer reset */ 1710 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1711 std->len = 0; 1712 1713 value = UGETW(std->req.wValue); 1714 index = UGETW(std->req.wIndex); 1715 1716 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 1717 1718 /* demultiplex the control request */ 1719 1720 switch (std->req.bmRequestType) { 1721 case UT_READ_DEVICE: 1722 switch (std->req.bRequest) { 1723 case UR_GET_DESCRIPTOR: 1724 goto tr_handle_get_descriptor; 1725 case UR_GET_CONFIG: 1726 goto tr_handle_get_config; 1727 case UR_GET_STATUS: 1728 goto tr_handle_get_status; 1729 default: 1730 goto tr_stalled; 1731 } 1732 break; 1733 1734 case UT_WRITE_DEVICE: 1735 switch (std->req.bRequest) { 1736 case UR_SET_ADDRESS: 1737 goto tr_handle_set_address; 1738 case UR_SET_CONFIG: 1739 goto tr_handle_set_config; 1740 case UR_CLEAR_FEATURE: 1741 goto tr_valid; /* nop */ 1742 case UR_SET_DESCRIPTOR: 1743 goto tr_valid; /* nop */ 1744 case UR_SET_FEATURE: 1745 default: 1746 goto tr_stalled; 1747 } 1748 break; 1749 1750 case UT_WRITE_ENDPOINT: 1751 switch (std->req.bRequest) { 1752 case UR_CLEAR_FEATURE: 1753 switch (UGETW(std->req.wValue)) { 1754 case UF_ENDPOINT_HALT: 1755 goto tr_handle_clear_halt; 1756 case UF_DEVICE_REMOTE_WAKEUP: 1757 goto tr_handle_clear_wakeup; 1758 default: 1759 goto tr_stalled; 1760 } 1761 break; 1762 case UR_SET_FEATURE: 1763 switch (UGETW(std->req.wValue)) { 1764 case UF_ENDPOINT_HALT: 1765 goto tr_handle_set_halt; 1766 case UF_DEVICE_REMOTE_WAKEUP: 1767 goto tr_handle_set_wakeup; 1768 default: 1769 goto tr_stalled; 1770 } 1771 break; 1772 case UR_SYNCH_FRAME: 1773 goto tr_valid; /* nop */ 1774 default: 1775 goto tr_stalled; 1776 } 1777 break; 1778 1779 case UT_READ_ENDPOINT: 1780 switch (std->req.bRequest) { 1781 case UR_GET_STATUS: 1782 goto tr_handle_get_ep_status; 1783 default: 1784 goto tr_stalled; 1785 } 1786 break; 1787 1788 case UT_WRITE_INTERFACE: 1789 switch (std->req.bRequest) { 1790 case UR_SET_INTERFACE: 1791 goto tr_handle_set_interface; 1792 case UR_CLEAR_FEATURE: 1793 goto tr_valid; /* nop */ 1794 case UR_SET_FEATURE: 1795 default: 1796 goto tr_stalled; 1797 } 1798 break; 1799 1800 case UT_READ_INTERFACE: 1801 switch (std->req.bRequest) { 1802 case UR_GET_INTERFACE: 1803 goto tr_handle_get_interface; 1804 case UR_GET_STATUS: 1805 goto tr_handle_get_iface_status; 1806 default: 1807 goto tr_stalled; 1808 } 1809 break; 1810 1811 case UT_WRITE_CLASS_INTERFACE: 1812 case UT_WRITE_VENDOR_INTERFACE: 1813 /* XXX forward */ 1814 break; 1815 1816 case UT_READ_CLASS_INTERFACE: 1817 case UT_READ_VENDOR_INTERFACE: 1818 /* XXX forward */ 1819 break; 1820 1821 case UT_WRITE_CLASS_DEVICE: 1822 switch (std->req.bRequest) { 1823 case UR_CLEAR_FEATURE: 1824 goto tr_valid; 1825 case UR_SET_DESCRIPTOR: 1826 case UR_SET_FEATURE: 1827 break; 1828 default: 1829 goto tr_stalled; 1830 } 1831 break; 1832 1833 case UT_WRITE_CLASS_OTHER: 1834 switch (std->req.bRequest) { 1835 case UR_CLEAR_FEATURE: 1836 goto tr_handle_clear_port_feature; 1837 case UR_SET_FEATURE: 1838 goto tr_handle_set_port_feature; 1839 case UR_CLEAR_TT_BUFFER: 1840 case UR_RESET_TT: 1841 case UR_STOP_TT: 1842 goto tr_valid; 1843 1844 default: 1845 goto tr_stalled; 1846 } 1847 break; 1848 1849 case UT_READ_CLASS_OTHER: 1850 switch (std->req.bRequest) { 1851 case UR_GET_TT_STATE: 1852 goto tr_handle_get_tt_state; 1853 case UR_GET_STATUS: 1854 goto tr_handle_get_port_status; 1855 default: 1856 goto tr_stalled; 1857 } 1858 break; 1859 1860 case UT_READ_CLASS_DEVICE: 1861 switch (std->req.bRequest) { 1862 case UR_GET_DESCRIPTOR: 1863 goto tr_handle_get_class_descriptor; 1864 case UR_GET_STATUS: 1865 goto tr_handle_get_class_status; 1866 1867 default: 1868 goto tr_stalled; 1869 } 1870 break; 1871 default: 1872 goto tr_stalled; 1873 } 1874 goto tr_valid; 1875 1876 tr_handle_get_descriptor: 1877 switch (value >> 8) { 1878 case UDESC_DEVICE: 1879 if (value & 0xff) { 1880 goto tr_stalled; 1881 } 1882 std->len = sizeof(atmegadci_devd); 1883 std->ptr = USB_ADD_BYTES(&atmegadci_devd, 0); 1884 goto tr_valid; 1885 case UDESC_CONFIG: 1886 if (value & 0xff) { 1887 goto tr_stalled; 1888 } 1889 std->len = sizeof(atmegadci_confd); 1890 std->ptr = USB_ADD_BYTES(&atmegadci_confd, 0); 1891 goto tr_valid; 1892 case UDESC_STRING: 1893 switch (value & 0xff) { 1894 case 0: /* Language table */ 1895 std->len = sizeof(atmegadci_langtab); 1896 std->ptr = USB_ADD_BYTES(&atmegadci_langtab, 0); 1897 goto tr_valid; 1898 1899 case 1: /* Vendor */ 1900 std->len = sizeof(atmegadci_vendor); 1901 std->ptr = USB_ADD_BYTES(&atmegadci_vendor, 0); 1902 goto tr_valid; 1903 1904 case 2: /* Product */ 1905 std->len = sizeof(atmegadci_product); 1906 std->ptr = USB_ADD_BYTES(&atmegadci_product, 0); 1907 goto tr_valid; 1908 default: 1909 break; 1910 } 1911 break; 1912 default: 1913 goto tr_stalled; 1914 } 1915 goto tr_stalled; 1916 1917 tr_handle_get_config: 1918 std->len = 1; 1919 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1920 goto tr_valid; 1921 1922 tr_handle_get_status: 1923 std->len = 2; 1924 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1925 goto tr_valid; 1926 1927 tr_handle_set_address: 1928 if (value & 0xFF00) { 1929 goto tr_stalled; 1930 } 1931 sc->sc_rt_addr = value; 1932 goto tr_valid; 1933 1934 tr_handle_set_config: 1935 if (value >= 2) { 1936 goto tr_stalled; 1937 } 1938 sc->sc_conf = value; 1939 goto tr_valid; 1940 1941 tr_handle_get_interface: 1942 std->len = 1; 1943 sc->sc_hub_temp.wValue[0] = 0; 1944 goto tr_valid; 1945 1946 tr_handle_get_tt_state: 1947 tr_handle_get_class_status: 1948 tr_handle_get_iface_status: 1949 tr_handle_get_ep_status: 1950 std->len = 2; 1951 USETW(sc->sc_hub_temp.wValue, 0); 1952 goto tr_valid; 1953 1954 tr_handle_set_halt: 1955 tr_handle_set_interface: 1956 tr_handle_set_wakeup: 1957 tr_handle_clear_wakeup: 1958 tr_handle_clear_halt: 1959 goto tr_valid; 1960 1961 tr_handle_clear_port_feature: 1962 if (index != 1) { 1963 goto tr_stalled; 1964 } 1965 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1966 1967 switch (value) { 1968 case UHF_PORT_SUSPEND: 1969 atmegadci_wakeup_peer(xfer); 1970 break; 1971 1972 case UHF_PORT_ENABLE: 1973 sc->sc_flags.port_enabled = 0; 1974 break; 1975 1976 case UHF_PORT_TEST: 1977 case UHF_PORT_INDICATOR: 1978 case UHF_C_PORT_ENABLE: 1979 case UHF_C_PORT_OVER_CURRENT: 1980 case UHF_C_PORT_RESET: 1981 /* nops */ 1982 break; 1983 case UHF_PORT_POWER: 1984 sc->sc_flags.port_powered = 0; 1985 atmegadci_pull_down(sc); 1986 atmegadci_clocks_off(sc); 1987 break; 1988 case UHF_C_PORT_CONNECTION: 1989 sc->sc_flags.change_connect = 0; 1990 break; 1991 case UHF_C_PORT_SUSPEND: 1992 sc->sc_flags.change_suspend = 0; 1993 break; 1994 default: 1995 std->err = USB_ERR_IOERROR; 1996 goto done; 1997 } 1998 goto tr_valid; 1999 2000 tr_handle_set_port_feature: 2001 if (index != 1) { 2002 goto tr_stalled; 2003 } 2004 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2005 2006 switch (value) { 2007 case UHF_PORT_ENABLE: 2008 sc->sc_flags.port_enabled = 1; 2009 break; 2010 case UHF_PORT_SUSPEND: 2011 case UHF_PORT_RESET: 2012 case UHF_PORT_TEST: 2013 case UHF_PORT_INDICATOR: 2014 /* nops */ 2015 break; 2016 case UHF_PORT_POWER: 2017 sc->sc_flags.port_powered = 1; 2018 break; 2019 default: 2020 std->err = USB_ERR_IOERROR; 2021 goto done; 2022 } 2023 goto tr_valid; 2024 2025 tr_handle_get_port_status: 2026 2027 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2028 2029 if (index != 1) { 2030 goto tr_stalled; 2031 } 2032 if (sc->sc_flags.status_vbus) { 2033 atmegadci_clocks_on(sc); 2034 atmegadci_pull_up(sc); 2035 } else { 2036 atmegadci_pull_down(sc); 2037 atmegadci_clocks_off(sc); 2038 } 2039 2040 /* Select FULL-speed and Device Side Mode */ 2041 2042 value = UPS_PORT_MODE_DEVICE; 2043 2044 if (sc->sc_flags.port_powered) { 2045 value |= UPS_PORT_POWER; 2046 } 2047 if (sc->sc_flags.port_enabled) { 2048 value |= UPS_PORT_ENABLED; 2049 } 2050 if (sc->sc_flags.status_vbus && 2051 sc->sc_flags.status_bus_reset) { 2052 value |= UPS_CURRENT_CONNECT_STATUS; 2053 } 2054 if (sc->sc_flags.status_suspend) { 2055 value |= UPS_SUSPEND; 2056 } 2057 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2058 2059 value = 0; 2060 2061 if (sc->sc_flags.change_connect) { 2062 value |= UPS_C_CONNECT_STATUS; 2063 } 2064 if (sc->sc_flags.change_suspend) { 2065 value |= UPS_C_SUSPEND; 2066 } 2067 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2068 std->len = sizeof(sc->sc_hub_temp.ps); 2069 goto tr_valid; 2070 2071 tr_handle_get_class_descriptor: 2072 if (value & 0xFF) { 2073 goto tr_stalled; 2074 } 2075 std->ptr = USB_ADD_BYTES(&atmegadci_hubd, 0); 2076 std->len = sizeof(atmegadci_hubd); 2077 goto tr_valid; 2078 2079 tr_stalled: 2080 std->err = USB_ERR_STALLED; 2081 tr_valid: 2082 done: 2083 return; 2084 } 2085 2086 static void 2087 atmegadci_root_ctrl_poll(struct atmegadci_softc *sc) 2088 { 2089 usb2_sw_transfer(&sc->sc_root_ctrl, 2090 &atmegadci_root_ctrl_done); 2091 } 2092 2093 struct usb2_pipe_methods atmegadci_root_ctrl_methods = 2094 { 2095 .open = atmegadci_root_ctrl_open, 2096 .close = atmegadci_root_ctrl_close, 2097 .enter = atmegadci_root_ctrl_enter, 2098 .start = atmegadci_root_ctrl_start, 2099 .enter_is_cancelable = 1, 2100 .start_is_cancelable = 0, 2101 }; 2102 2103 /*------------------------------------------------------------------------* 2104 * at91dci root interrupt support 2105 *------------------------------------------------------------------------*/ 2106 static void 2107 atmegadci_root_intr_open(struct usb2_xfer *xfer) 2108 { 2109 return; 2110 } 2111 2112 static void 2113 atmegadci_root_intr_close(struct usb2_xfer *xfer) 2114 { 2115 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2116 2117 if (sc->sc_root_intr.xfer == xfer) { 2118 sc->sc_root_intr.xfer = NULL; 2119 } 2120 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 2121 } 2122 2123 static void 2124 atmegadci_root_intr_enter(struct usb2_xfer *xfer) 2125 { 2126 return; 2127 } 2128 2129 static void 2130 atmegadci_root_intr_start(struct usb2_xfer *xfer) 2131 { 2132 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2133 2134 sc->sc_root_intr.xfer = xfer; 2135 } 2136 2137 struct usb2_pipe_methods atmegadci_root_intr_methods = 2138 { 2139 .open = atmegadci_root_intr_open, 2140 .close = atmegadci_root_intr_close, 2141 .enter = atmegadci_root_intr_enter, 2142 .start = atmegadci_root_intr_start, 2143 .enter_is_cancelable = 1, 2144 .start_is_cancelable = 1, 2145 }; 2146 2147 static void 2148 atmegadci_xfer_setup(struct usb2_setup_params *parm) 2149 { 2150 const struct usb2_hw_ep_profile *pf; 2151 struct atmegadci_softc *sc; 2152 struct usb2_xfer *xfer; 2153 void *last_obj; 2154 uint32_t ntd; 2155 uint32_t n; 2156 uint8_t ep_no; 2157 2158 sc = ATMEGA_BUS2SC(parm->udev->bus); 2159 xfer = parm->curr_xfer; 2160 2161 /* 2162 * NOTE: This driver does not use any of the parameters that 2163 * are computed from the following values. Just set some 2164 * reasonable dummies: 2165 */ 2166 parm->hc_max_packet_size = 0x500; 2167 parm->hc_max_packet_count = 1; 2168 parm->hc_max_frame_size = 0x500; 2169 2170 usb2_transfer_setup_sub(parm); 2171 2172 /* 2173 * compute maximum number of TDs 2174 */ 2175 if (parm->methods == &atmegadci_device_ctrl_methods) { 2176 2177 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2178 + 1 /* SYNC 2 */ ; 2179 2180 } else if (parm->methods == &atmegadci_device_bulk_methods) { 2181 2182 ntd = xfer->nframes + 1 /* SYNC */ ; 2183 2184 } else if (parm->methods == &atmegadci_device_intr_methods) { 2185 2186 ntd = xfer->nframes + 1 /* SYNC */ ; 2187 2188 } else if (parm->methods == &atmegadci_device_isoc_fs_methods) { 2189 2190 ntd = xfer->nframes + 1 /* SYNC */ ; 2191 2192 } else { 2193 2194 ntd = 0; 2195 } 2196 2197 /* 2198 * check if "usb2_transfer_setup_sub" set an error 2199 */ 2200 if (parm->err) { 2201 return; 2202 } 2203 /* 2204 * allocate transfer descriptors 2205 */ 2206 last_obj = NULL; 2207 2208 /* 2209 * get profile stuff 2210 */ 2211 if (ntd) { 2212 2213 ep_no = xfer->endpoint & UE_ADDR; 2214 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2215 2216 if (pf == NULL) { 2217 /* should not happen */ 2218 parm->err = USB_ERR_INVAL; 2219 return; 2220 } 2221 } else { 2222 ep_no = 0; 2223 pf = NULL; 2224 } 2225 2226 /* align data */ 2227 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2228 2229 for (n = 0; n != ntd; n++) { 2230 2231 struct atmegadci_td *td; 2232 2233 if (parm->buf) { 2234 2235 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2236 2237 /* init TD */ 2238 td->max_packet_size = xfer->max_packet_size; 2239 td->ep_no = ep_no; 2240 if (pf->support_multi_buffer) { 2241 td->support_multi_buffer = 1; 2242 } 2243 td->obj_next = last_obj; 2244 2245 last_obj = td; 2246 } 2247 parm->size[0] += sizeof(*td); 2248 } 2249 2250 xfer->td_start[0] = last_obj; 2251 } 2252 2253 static void 2254 atmegadci_xfer_unsetup(struct usb2_xfer *xfer) 2255 { 2256 return; 2257 } 2258 2259 static void 2260 atmegadci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2261 struct usb2_pipe *pipe) 2262 { 2263 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2264 2265 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2266 pipe, udev->address, 2267 edesc->bEndpointAddress, udev->flags.usb2_mode, 2268 sc->sc_rt_addr); 2269 2270 if (udev->device_index == sc->sc_rt_addr) { 2271 2272 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2273 /* not supported */ 2274 return; 2275 } 2276 switch (edesc->bEndpointAddress) { 2277 case USB_CONTROL_ENDPOINT: 2278 pipe->methods = &atmegadci_root_ctrl_methods; 2279 break; 2280 case UE_DIR_IN | ATMEGA_INTR_ENDPT: 2281 pipe->methods = &atmegadci_root_intr_methods; 2282 break; 2283 default: 2284 /* do nothing */ 2285 break; 2286 } 2287 } else { 2288 2289 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2290 /* not supported */ 2291 return; 2292 } 2293 if (udev->speed != USB_SPEED_FULL) { 2294 /* not supported */ 2295 return; 2296 } 2297 switch (edesc->bmAttributes & UE_XFERTYPE) { 2298 case UE_CONTROL: 2299 pipe->methods = &atmegadci_device_ctrl_methods; 2300 break; 2301 case UE_INTERRUPT: 2302 pipe->methods = &atmegadci_device_intr_methods; 2303 break; 2304 case UE_ISOCHRONOUS: 2305 pipe->methods = &atmegadci_device_isoc_fs_methods; 2306 break; 2307 case UE_BULK: 2308 pipe->methods = &atmegadci_device_bulk_methods; 2309 break; 2310 default: 2311 /* do nothing */ 2312 break; 2313 } 2314 } 2315 } 2316 2317 struct usb2_bus_methods atmegadci_bus_methods = 2318 { 2319 .pipe_init = &atmegadci_pipe_init, 2320 .xfer_setup = &atmegadci_xfer_setup, 2321 .xfer_unsetup = &atmegadci_xfer_unsetup, 2322 .do_poll = &atmegadci_do_poll, 2323 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2324 .set_stall = &atmegadci_set_stall, 2325 .clear_stall = &atmegadci_clear_stall, 2326 .roothub_exec = &atmegadci_root_ctrl_task, 2327 }; 2328