1 #include <sys/cdefs.h> 2 __FBSDID("$FreeBSD$"); 3 4 /*- 5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This file contains the driver for the ATMEGA series USB Device 31 * Controller 32 */ 33 34 /* 35 * NOTE: When the chip detects BUS-reset it will also reset the 36 * endpoints, Function-address and more. 37 */ 38 39 #include <dev/usb/usb.h> 40 #include <dev/usb/usb_mfunc.h> 41 #include <dev/usb/usb_error.h> 42 #include <dev/usb/usb_defs.h> 43 44 #define USB_DEBUG_VAR atmegadci_debug 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_debug.h> 48 #include <dev/usb/usb_busdma.h> 49 #include <dev/usb/usb_process.h> 50 #include <dev/usb/usb_sw_transfer.h> 51 #include <dev/usb/usb_transfer.h> 52 #include <dev/usb/usb_device.h> 53 #include <dev/usb/usb_hub.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/controller/atmegadci.h> 59 60 #define ATMEGA_BUS2SC(bus) \ 61 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \ 62 USB_P2U(&(((struct atmegadci_softc *)0)->sc_bus)))) 63 64 #define ATMEGA_PC2SC(pc) \ 65 ATMEGA_BUS2SC((pc)->tag_parent->info->bus) 66 67 #if USB_DEBUG 68 static int atmegadci_debug = 0; 69 70 SYSCTL_NODE(_hw_usb2, OID_AUTO, atmegadci, CTLFLAG_RW, 0, "USB ATMEGA DCI"); 71 SYSCTL_INT(_hw_usb2_atmegadci, OID_AUTO, debug, CTLFLAG_RW, 72 &atmegadci_debug, 0, "ATMEGA DCI debug level"); 73 #endif 74 75 #define ATMEGA_INTR_ENDPT 1 76 77 /* prototypes */ 78 79 struct usb2_bus_methods atmegadci_bus_methods; 80 struct usb2_pipe_methods atmegadci_device_bulk_methods; 81 struct usb2_pipe_methods atmegadci_device_ctrl_methods; 82 struct usb2_pipe_methods atmegadci_device_intr_methods; 83 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods; 84 struct usb2_pipe_methods atmegadci_root_ctrl_methods; 85 struct usb2_pipe_methods atmegadci_root_intr_methods; 86 87 static atmegadci_cmd_t atmegadci_setup_rx; 88 static atmegadci_cmd_t atmegadci_data_rx; 89 static atmegadci_cmd_t atmegadci_data_tx; 90 static atmegadci_cmd_t atmegadci_data_tx_sync; 91 static void atmegadci_device_done(struct usb2_xfer *, usb2_error_t); 92 static void atmegadci_do_poll(struct usb2_bus *); 93 static void atmegadci_root_ctrl_poll(struct atmegadci_softc *); 94 static void atmegadci_standard_done(struct usb2_xfer *); 95 96 static usb2_sw_transfer_func_t atmegadci_root_intr_done; 97 static usb2_sw_transfer_func_t atmegadci_root_ctrl_done; 98 99 /* 100 * Here is a list of what the chip supports: 101 */ 102 static const struct usb2_hw_ep_profile 103 atmegadci_ep_profile[2] = { 104 105 [0] = { 106 .max_in_frame_size = 64, 107 .max_out_frame_size = 64, 108 .is_simplex = 1, 109 .support_control = 1, 110 }, 111 [1] = { 112 .max_in_frame_size = 64, 113 .max_out_frame_size = 64, 114 .is_simplex = 1, 115 .support_multi_buffer = 1, 116 .support_bulk = 1, 117 .support_interrupt = 1, 118 .support_isochronous = 1, 119 .support_in = 1, 120 .support_out = 1, 121 }, 122 }; 123 124 static void 125 atmegadci_get_hw_ep_profile(struct usb2_device *udev, 126 const struct usb2_hw_ep_profile **ppf, uint8_t ep_addr) 127 { 128 if (ep_addr == 0) 129 *ppf = atmegadci_ep_profile; 130 else if (ep_addr < ATMEGA_EP_MAX) 131 *ppf = atmegadci_ep_profile + 1; 132 else 133 *ppf = NULL; 134 } 135 136 static void 137 atmegadci_clocks_on(struct atmegadci_softc *sc) 138 { 139 if (sc->sc_flags.clocks_off && 140 sc->sc_flags.port_powered) { 141 142 DPRINTFN(5, "\n"); 143 144 /* turn on clocks */ 145 (sc->sc_clocks_on) (&sc->sc_bus); 146 147 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 148 ATMEGA_USBCON_USBE | 149 ATMEGA_USBCON_OTGPADE | 150 ATMEGA_USBCON_VBUSTE); 151 152 sc->sc_flags.clocks_off = 0; 153 154 /* enable transceiver ? */ 155 } 156 } 157 158 static void 159 atmegadci_clocks_off(struct atmegadci_softc *sc) 160 { 161 if (!sc->sc_flags.clocks_off) { 162 163 DPRINTFN(5, "\n"); 164 165 /* disable Transceiver ? */ 166 167 ATMEGA_WRITE_1(sc, ATMEGA_USBCON, 168 ATMEGA_USBCON_USBE | 169 ATMEGA_USBCON_OTGPADE | 170 ATMEGA_USBCON_FRZCLK | 171 ATMEGA_USBCON_VBUSTE); 172 173 /* turn clocks off */ 174 (sc->sc_clocks_off) (&sc->sc_bus); 175 176 sc->sc_flags.clocks_off = 1; 177 } 178 } 179 180 static void 181 atmegadci_pull_up(struct atmegadci_softc *sc) 182 { 183 /* pullup D+, if possible */ 184 185 if (!sc->sc_flags.d_pulled_up && 186 sc->sc_flags.port_powered) { 187 sc->sc_flags.d_pulled_up = 1; 188 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0); 189 } 190 } 191 192 static void 193 atmegadci_pull_down(struct atmegadci_softc *sc) 194 { 195 /* pulldown D+, if possible */ 196 197 if (sc->sc_flags.d_pulled_up) { 198 sc->sc_flags.d_pulled_up = 0; 199 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH); 200 } 201 } 202 203 static void 204 atmegadci_wakeup_peer(struct usb2_xfer *xfer) 205 { 206 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 207 uint8_t temp; 208 209 if (!sc->sc_flags.status_suspend) { 210 return; 211 } 212 213 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON); 214 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP); 215 216 /* wait 8 milliseconds */ 217 /* Wait for reset to complete. */ 218 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 219 220 /* hardware should have cleared RMWKUP bit */ 221 } 222 223 static void 224 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr) 225 { 226 DPRINTFN(5, "addr=%d\n", addr); 227 228 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 229 230 addr |= ATMEGA_UDADDR_ADDEN; 231 232 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr); 233 } 234 235 static uint8_t 236 atmegadci_setup_rx(struct atmegadci_td *td) 237 { 238 struct atmegadci_softc *sc; 239 struct usb2_device_request req; 240 uint16_t count; 241 uint8_t temp; 242 243 /* get pointer to softc */ 244 sc = ATMEGA_PC2SC(td->pc); 245 246 /* select endpoint number */ 247 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 248 249 /* check endpoint status */ 250 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 251 252 DPRINTFN(5, "UEINTX=0x%02x\n", temp); 253 254 if (!(temp & ATMEGA_UEINTX_RXSTPI)) { 255 /* abort any ongoing transfer */ 256 if (!td->did_stall) { 257 DPRINTFN(5, "stalling\n"); 258 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 259 ATMEGA_UECONX_EPEN | 260 ATMEGA_UECONX_STALLRQ); 261 td->did_stall = 1; 262 } 263 goto not_complete; 264 } 265 /* get the packet byte count */ 266 count = 267 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 268 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 269 270 /* mask away undefined bits */ 271 count &= 0x7FF; 272 273 /* verify data length */ 274 if (count != td->remainder) { 275 DPRINTFN(0, "Invalid SETUP packet " 276 "length, %d bytes\n", count); 277 goto not_complete; 278 } 279 if (count != sizeof(req)) { 280 DPRINTFN(0, "Unsupported SETUP packet " 281 "length, %d bytes\n", count); 282 goto not_complete; 283 } 284 /* receive data */ 285 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 286 (void *)&req, sizeof(req)); 287 288 /* copy data into real buffer */ 289 usb2_copy_in(td->pc, 0, &req, sizeof(req)); 290 291 td->offset = sizeof(req); 292 td->remainder = 0; 293 294 /* sneak peek the set address */ 295 if ((req.bmRequestType == UT_WRITE_DEVICE) && 296 (req.bRequest == UR_SET_ADDRESS)) { 297 sc->sc_dv_addr = req.wValue[0] & 0x7F; 298 } else { 299 sc->sc_dv_addr = 0xFF; 300 } 301 302 /* clear SETUP packet interrupt */ 303 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI); 304 return (0); /* complete */ 305 306 not_complete: 307 /* we only want to know if there is a SETUP packet */ 308 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE); 309 return (1); /* not complete */ 310 } 311 312 static uint8_t 313 atmegadci_data_rx(struct atmegadci_td *td) 314 { 315 struct atmegadci_softc *sc; 316 struct usb2_page_search buf_res; 317 uint16_t count; 318 uint8_t temp; 319 uint8_t to; 320 uint8_t got_short; 321 322 to = 3; /* don't loop forever! */ 323 got_short = 0; 324 325 /* get pointer to softc */ 326 sc = ATMEGA_PC2SC(td->pc); 327 328 /* select endpoint number */ 329 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 330 331 repeat: 332 /* check if any of the FIFO banks have data */ 333 /* check endpoint status */ 334 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 335 336 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 337 338 if (temp & ATMEGA_UEINTX_RXSTPI) { 339 if (td->remainder == 0) { 340 /* 341 * We are actually complete and have 342 * received the next SETUP 343 */ 344 DPRINTFN(5, "faking complete\n"); 345 return (0); /* complete */ 346 } 347 /* 348 * USB Host Aborted the transfer. 349 */ 350 td->error = 1; 351 return (0); /* complete */ 352 } 353 /* check status */ 354 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 355 ATMEGA_UEINTX_RXOUTI))) { 356 /* no data */ 357 goto not_complete; 358 } 359 /* get the packet byte count */ 360 count = 361 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) | 362 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX)); 363 364 /* mask away undefined bits */ 365 count &= 0x7FF; 366 367 /* verify the packet byte count */ 368 if (count != td->max_packet_size) { 369 if (count < td->max_packet_size) { 370 /* we have a short packet */ 371 td->short_pkt = 1; 372 got_short = 1; 373 } else { 374 /* invalid USB packet */ 375 td->error = 1; 376 return (0); /* we are complete */ 377 } 378 } 379 /* verify the packet byte count */ 380 if (count > td->remainder) { 381 /* invalid USB packet */ 382 td->error = 1; 383 return (0); /* we are complete */ 384 } 385 while (count > 0) { 386 usb2_get_page(td->pc, td->offset, &buf_res); 387 388 /* get correct length */ 389 if (buf_res.length > count) { 390 buf_res.length = count; 391 } 392 /* receive data */ 393 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX, 394 buf_res.buffer, buf_res.length); 395 396 /* update counters */ 397 count -= buf_res.length; 398 td->offset += buf_res.length; 399 td->remainder -= buf_res.length; 400 } 401 402 /* clear OUT packet interrupt */ 403 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF); 404 405 /* release FIFO bank */ 406 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF); 407 408 /* check if we are complete */ 409 if ((td->remainder == 0) || got_short) { 410 if (td->short_pkt) { 411 /* we are complete */ 412 return (0); 413 } 414 /* else need to receive a zero length packet */ 415 } 416 if (--to) { 417 goto repeat; 418 } 419 not_complete: 420 /* we only want to know if there is a SETUP packet or OUT packet */ 421 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 422 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE); 423 return (1); /* not complete */ 424 } 425 426 static uint8_t 427 atmegadci_data_tx(struct atmegadci_td *td) 428 { 429 struct atmegadci_softc *sc; 430 struct usb2_page_search buf_res; 431 uint16_t count; 432 uint8_t to; 433 uint8_t temp; 434 435 to = 3; /* don't loop forever! */ 436 437 /* get pointer to softc */ 438 sc = ATMEGA_PC2SC(td->pc); 439 440 /* select endpoint number */ 441 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 442 443 repeat: 444 445 /* check endpoint status */ 446 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 447 448 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder); 449 450 if (temp & ATMEGA_UEINTX_RXSTPI) { 451 /* 452 * The current transfer was aborted 453 * by the USB Host 454 */ 455 td->error = 1; 456 return (0); /* complete */ 457 } 458 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 459 ATMEGA_UEINTX_TXINI))) { 460 /* cannot write any data */ 461 goto not_complete; 462 } 463 count = td->max_packet_size; 464 if (td->remainder < count) { 465 /* we have a short packet */ 466 td->short_pkt = 1; 467 count = td->remainder; 468 } 469 while (count > 0) { 470 471 usb2_get_page(td->pc, td->offset, &buf_res); 472 473 /* get correct length */ 474 if (buf_res.length > count) { 475 buf_res.length = count; 476 } 477 /* transmit data */ 478 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX, 479 buf_res.buffer, buf_res.length); 480 481 /* update counters */ 482 count -= buf_res.length; 483 td->offset += buf_res.length; 484 td->remainder -= buf_res.length; 485 } 486 487 /* clear IN packet interrupt */ 488 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI); 489 490 /* allocate FIFO bank */ 491 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON); 492 493 /* check remainder */ 494 if (td->remainder == 0) { 495 if (td->short_pkt) { 496 return (0); /* complete */ 497 } 498 /* else we need to transmit a short packet */ 499 } 500 if (--to) { 501 goto repeat; 502 } 503 not_complete: 504 /* we only want to know if there is a SETUP packet or free IN packet */ 505 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 506 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 507 return (1); /* not complete */ 508 } 509 510 static uint8_t 511 atmegadci_data_tx_sync(struct atmegadci_td *td) 512 { 513 struct atmegadci_softc *sc; 514 uint8_t temp; 515 516 /* get pointer to softc */ 517 sc = ATMEGA_PC2SC(td->pc); 518 519 /* select endpoint number */ 520 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no); 521 522 /* check endpoint status */ 523 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX); 524 525 DPRINTFN(5, "temp=0x%02x\n", temp); 526 527 if (temp & ATMEGA_UEINTX_RXSTPI) { 528 DPRINTFN(5, "faking complete\n"); 529 /* Race condition */ 530 return (0); /* complete */ 531 } 532 /* 533 * The control endpoint has only got one bank, so if that bank 534 * is free the packet has been transferred! 535 */ 536 if (!(temp & (ATMEGA_UEINTX_FIFOCON | 537 ATMEGA_UEINTX_TXINI))) { 538 /* cannot write any data */ 539 goto not_complete; 540 } 541 if (sc->sc_dv_addr != 0xFF) { 542 /* set new address */ 543 atmegadci_set_address(sc, sc->sc_dv_addr); 544 } 545 return (0); /* complete */ 546 547 not_complete: 548 /* we only want to know if there is a SETUP packet or free IN packet */ 549 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 550 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE); 551 return (1); /* not complete */ 552 } 553 554 static uint8_t 555 atmegadci_xfer_do_fifo(struct usb2_xfer *xfer) 556 { 557 struct atmegadci_td *td; 558 559 DPRINTFN(9, "\n"); 560 561 td = xfer->td_transfer_cache; 562 while (1) { 563 if ((td->func) (td)) { 564 /* operation in progress */ 565 break; 566 } 567 if (((void *)td) == xfer->td_transfer_last) { 568 goto done; 569 } 570 if (td->error) { 571 goto done; 572 } else if (td->remainder > 0) { 573 /* 574 * We had a short transfer. If there is no alternate 575 * next, stop processing ! 576 */ 577 if (!td->alt_next) { 578 goto done; 579 } 580 } 581 /* 582 * Fetch the next transfer descriptor and transfer 583 * some flags to the next transfer descriptor 584 */ 585 td = td->obj_next; 586 xfer->td_transfer_cache = td; 587 } 588 return (1); /* not complete */ 589 590 done: 591 /* compute all actual lengths */ 592 593 atmegadci_standard_done(xfer); 594 return (0); /* complete */ 595 } 596 597 static void 598 atmegadci_interrupt_poll(struct atmegadci_softc *sc) 599 { 600 struct usb2_xfer *xfer; 601 602 repeat: 603 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 604 if (!atmegadci_xfer_do_fifo(xfer)) { 605 /* queue has been modified */ 606 goto repeat; 607 } 608 } 609 } 610 611 static void 612 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on) 613 { 614 DPRINTFN(5, "vbus = %u\n", is_on); 615 616 if (is_on) { 617 if (!sc->sc_flags.status_vbus) { 618 sc->sc_flags.status_vbus = 1; 619 620 /* complete root HUB interrupt endpoint */ 621 622 usb2_sw_transfer(&sc->sc_root_intr, 623 &atmegadci_root_intr_done); 624 } 625 } else { 626 if (sc->sc_flags.status_vbus) { 627 sc->sc_flags.status_vbus = 0; 628 sc->sc_flags.status_bus_reset = 0; 629 sc->sc_flags.status_suspend = 0; 630 sc->sc_flags.change_suspend = 0; 631 sc->sc_flags.change_connect = 1; 632 633 /* complete root HUB interrupt endpoint */ 634 635 usb2_sw_transfer(&sc->sc_root_intr, 636 &atmegadci_root_intr_done); 637 } 638 } 639 } 640 641 void 642 atmegadci_interrupt(struct atmegadci_softc *sc) 643 { 644 uint8_t status; 645 646 USB_BUS_LOCK(&sc->sc_bus); 647 648 /* read interrupt status */ 649 status = ATMEGA_READ_1(sc, ATMEGA_UDINT); 650 651 /* clear all set interrupts */ 652 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, ~status); 653 654 /* check for any bus state change interrupts */ 655 if (status & ATMEGA_UDINT_EORSTI) { 656 657 DPRINTFN(5, "end of reset\n"); 658 659 /* set correct state */ 660 sc->sc_flags.status_bus_reset = 1; 661 sc->sc_flags.status_suspend = 0; 662 sc->sc_flags.change_suspend = 0; 663 sc->sc_flags.change_connect = 1; 664 665 /* disable resume interrupt */ 666 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 667 ATMEGA_UDINT_SUSPE | 668 ATMEGA_UDINT_EORSTE); 669 670 /* complete root HUB interrupt endpoint */ 671 usb2_sw_transfer(&sc->sc_root_intr, 672 &atmegadci_root_intr_done); 673 } 674 /* 675 * If resume and suspend is set at the same time we interpret 676 * that like RESUME. Resume is set when there is at least 3 677 * milliseconds of inactivity on the USB BUS. 678 */ 679 if (status & ATMEGA_UDINT_EORSMI) { 680 681 DPRINTFN(5, "resume interrupt\n"); 682 683 if (sc->sc_flags.status_suspend) { 684 /* update status bits */ 685 sc->sc_flags.status_suspend = 0; 686 sc->sc_flags.change_suspend = 1; 687 688 /* disable resume interrupt */ 689 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 690 ATMEGA_UDINT_SUSPE | 691 ATMEGA_UDINT_EORSTE); 692 693 /* complete root HUB interrupt endpoint */ 694 usb2_sw_transfer(&sc->sc_root_intr, 695 &atmegadci_root_intr_done); 696 } 697 } else if (status & ATMEGA_UDINT_SUSPI) { 698 699 DPRINTFN(5, "suspend interrupt\n"); 700 701 if (!sc->sc_flags.status_suspend) { 702 /* update status bits */ 703 sc->sc_flags.status_suspend = 1; 704 sc->sc_flags.change_suspend = 1; 705 706 /* disable suspend interrupt */ 707 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 708 ATMEGA_UDINT_EORSMI | 709 ATMEGA_UDINT_EORSTE); 710 711 /* complete root HUB interrupt endpoint */ 712 usb2_sw_transfer(&sc->sc_root_intr, 713 &atmegadci_root_intr_done); 714 } 715 } 716 /* check VBUS */ 717 status = ATMEGA_READ_1(sc, ATMEGA_USBINT); 718 719 /* clear all set interrupts */ 720 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, ~status); 721 722 if (status & ATMEGA_USBINT_VBUSTI) { 723 uint8_t temp; 724 725 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA); 726 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS); 727 } 728 /* check for any endpoint interrupts */ 729 status = ATMEGA_READ_1(sc, ATMEGA_UEINT); 730 731 /* clear all set interrupts */ 732 ATMEGA_WRITE_1(sc, ATMEGA_UEINT, ~status); 733 734 if (status) { 735 736 DPRINTFN(5, "real endpoint interrupt 0x%02x\n", status); 737 738 atmegadci_interrupt_poll(sc); 739 } 740 USB_BUS_UNLOCK(&sc->sc_bus); 741 } 742 743 static void 744 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp) 745 { 746 struct atmegadci_td *td; 747 748 /* get current Transfer Descriptor */ 749 td = temp->td_next; 750 temp->td = td; 751 752 /* prepare for next TD */ 753 temp->td_next = td->obj_next; 754 755 /* fill out the Transfer Descriptor */ 756 td->func = temp->func; 757 td->pc = temp->pc; 758 td->offset = temp->offset; 759 td->remainder = temp->len; 760 td->error = 0; 761 td->did_stall = 0; 762 td->short_pkt = temp->short_pkt; 763 td->alt_next = temp->setup_alt_next; 764 } 765 766 static void 767 atmegadci_setup_standard_chain(struct usb2_xfer *xfer) 768 { 769 struct atmegadci_std_temp temp; 770 struct atmegadci_softc *sc; 771 struct atmegadci_td *td; 772 uint32_t x; 773 uint8_t ep_no; 774 uint8_t need_sync; 775 776 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 777 xfer->address, UE_GET_ADDR(xfer->endpoint), 778 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 779 780 temp.max_frame_size = xfer->max_frame_size; 781 782 td = xfer->td_start[0]; 783 xfer->td_transfer_first = td; 784 xfer->td_transfer_cache = td; 785 786 /* setup temp */ 787 788 temp.td = NULL; 789 temp.td_next = xfer->td_start[0]; 790 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 791 temp.offset = 0; 792 793 sc = ATMEGA_BUS2SC(xfer->xroot->bus); 794 ep_no = (xfer->endpoint & UE_ADDR); 795 796 /* check if we should prepend a setup message */ 797 798 if (xfer->flags_int.control_xfr) { 799 if (xfer->flags_int.control_hdr) { 800 801 temp.func = &atmegadci_setup_rx; 802 temp.len = xfer->frlengths[0]; 803 temp.pc = xfer->frbuffers + 0; 804 temp.short_pkt = temp.len ? 1 : 0; 805 806 atmegadci_setup_standard_chain_sub(&temp); 807 } 808 x = 1; 809 } else { 810 x = 0; 811 } 812 813 if (x != xfer->nframes) { 814 if (xfer->endpoint & UE_DIR_IN) { 815 temp.func = &atmegadci_data_tx; 816 need_sync = 1; 817 } else { 818 temp.func = &atmegadci_data_rx; 819 need_sync = 0; 820 } 821 822 /* setup "pc" pointer */ 823 temp.pc = xfer->frbuffers + x; 824 } else { 825 need_sync = 0; 826 } 827 while (x != xfer->nframes) { 828 829 /* DATA0 / DATA1 message */ 830 831 temp.len = xfer->frlengths[x]; 832 833 x++; 834 835 if (x == xfer->nframes) { 836 temp.setup_alt_next = 0; 837 } 838 if (temp.len == 0) { 839 840 /* make sure that we send an USB packet */ 841 842 temp.short_pkt = 0; 843 844 } else { 845 846 /* regular data transfer */ 847 848 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1; 849 } 850 851 atmegadci_setup_standard_chain_sub(&temp); 852 853 if (xfer->flags_int.isochronous_xfr) { 854 temp.offset += temp.len; 855 } else { 856 /* get next Page Cache pointer */ 857 temp.pc = xfer->frbuffers + x; 858 } 859 } 860 861 /* always setup a valid "pc" pointer for status and sync */ 862 temp.pc = xfer->frbuffers + 0; 863 864 /* check if we need to sync */ 865 if (need_sync && xfer->flags_int.control_xfr) { 866 867 /* we need a SYNC point after TX */ 868 temp.func = &atmegadci_data_tx_sync; 869 temp.len = 0; 870 temp.short_pkt = 0; 871 872 atmegadci_setup_standard_chain_sub(&temp); 873 } 874 /* check if we should append a status stage */ 875 if (xfer->flags_int.control_xfr && 876 !xfer->flags_int.control_act) { 877 878 /* 879 * Send a DATA1 message and invert the current 880 * endpoint direction. 881 */ 882 if (xfer->endpoint & UE_DIR_IN) { 883 temp.func = &atmegadci_data_rx; 884 need_sync = 0; 885 } else { 886 temp.func = &atmegadci_data_tx; 887 need_sync = 1; 888 } 889 temp.len = 0; 890 temp.short_pkt = 0; 891 892 atmegadci_setup_standard_chain_sub(&temp); 893 if (need_sync) { 894 /* we need a SYNC point after TX */ 895 temp.func = &atmegadci_data_tx_sync; 896 temp.len = 0; 897 temp.short_pkt = 0; 898 899 atmegadci_setup_standard_chain_sub(&temp); 900 } 901 } 902 /* must have at least one frame! */ 903 td = temp.td; 904 xfer->td_transfer_last = td; 905 } 906 907 static void 908 atmegadci_timeout(void *arg) 909 { 910 struct usb2_xfer *xfer = arg; 911 912 DPRINTF("xfer=%p\n", xfer); 913 914 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 915 916 /* transfer is transferred */ 917 atmegadci_device_done(xfer, USB_ERR_TIMEOUT); 918 } 919 920 static void 921 atmegadci_start_standard_chain(struct usb2_xfer *xfer) 922 { 923 DPRINTFN(9, "\n"); 924 925 /* poll one time - will turn on interrupts */ 926 if (atmegadci_xfer_do_fifo(xfer)) { 927 928 /* put transfer on interrupt queue */ 929 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 930 931 /* start timeout, if any */ 932 if (xfer->timeout != 0) { 933 usb2_transfer_timeout_ms(xfer, 934 &atmegadci_timeout, xfer->timeout); 935 } 936 } 937 } 938 939 static void 940 atmegadci_root_intr_done(struct usb2_xfer *xfer, 941 struct usb2_sw_transfer *std) 942 { 943 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 944 945 DPRINTFN(9, "\n"); 946 947 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 948 949 if (std->state != USB_SW_TR_PRE_DATA) { 950 if (std->state == USB_SW_TR_PRE_CALLBACK) { 951 /* transfer transferred */ 952 atmegadci_device_done(xfer, std->err); 953 } 954 goto done; 955 } 956 /* setup buffer */ 957 std->ptr = sc->sc_hub_idata; 958 std->len = sizeof(sc->sc_hub_idata); 959 960 /* set port bit */ 961 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 962 963 done: 964 return; 965 } 966 967 static usb2_error_t 968 atmegadci_standard_done_sub(struct usb2_xfer *xfer) 969 { 970 struct atmegadci_td *td; 971 uint32_t len; 972 uint8_t error; 973 974 DPRINTFN(9, "\n"); 975 976 td = xfer->td_transfer_cache; 977 978 do { 979 len = td->remainder; 980 981 if (xfer->aframes != xfer->nframes) { 982 /* 983 * Verify the length and subtract 984 * the remainder from "frlengths[]": 985 */ 986 if (len > xfer->frlengths[xfer->aframes]) { 987 td->error = 1; 988 } else { 989 xfer->frlengths[xfer->aframes] -= len; 990 } 991 } 992 /* Check for transfer error */ 993 if (td->error) { 994 /* the transfer is finished */ 995 error = 1; 996 td = NULL; 997 break; 998 } 999 /* Check for short transfer */ 1000 if (len > 0) { 1001 if (xfer->flags_int.short_frames_ok) { 1002 /* follow alt next */ 1003 if (td->alt_next) { 1004 td = td->obj_next; 1005 } else { 1006 td = NULL; 1007 } 1008 } else { 1009 /* the transfer is finished */ 1010 td = NULL; 1011 } 1012 error = 0; 1013 break; 1014 } 1015 td = td->obj_next; 1016 1017 /* this USB frame is complete */ 1018 error = 0; 1019 break; 1020 1021 } while (0); 1022 1023 /* update transfer cache */ 1024 1025 xfer->td_transfer_cache = td; 1026 1027 return (error ? 1028 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1029 } 1030 1031 static void 1032 atmegadci_standard_done(struct usb2_xfer *xfer) 1033 { 1034 usb2_error_t err = 0; 1035 1036 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1037 xfer, xfer->pipe); 1038 1039 /* reset scanner */ 1040 1041 xfer->td_transfer_cache = xfer->td_transfer_first; 1042 1043 if (xfer->flags_int.control_xfr) { 1044 1045 if (xfer->flags_int.control_hdr) { 1046 1047 err = atmegadci_standard_done_sub(xfer); 1048 } 1049 xfer->aframes = 1; 1050 1051 if (xfer->td_transfer_cache == NULL) { 1052 goto done; 1053 } 1054 } 1055 while (xfer->aframes != xfer->nframes) { 1056 1057 err = atmegadci_standard_done_sub(xfer); 1058 xfer->aframes++; 1059 1060 if (xfer->td_transfer_cache == NULL) { 1061 goto done; 1062 } 1063 } 1064 1065 if (xfer->flags_int.control_xfr && 1066 !xfer->flags_int.control_act) { 1067 1068 err = atmegadci_standard_done_sub(xfer); 1069 } 1070 done: 1071 atmegadci_device_done(xfer, err); 1072 } 1073 1074 /*------------------------------------------------------------------------* 1075 * atmegadci_device_done 1076 * 1077 * NOTE: this function can be called more than one time on the 1078 * same USB transfer! 1079 *------------------------------------------------------------------------*/ 1080 static void 1081 atmegadci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 1082 { 1083 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1084 uint8_t ep_no; 1085 1086 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1087 1088 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 1089 xfer, xfer->pipe, error); 1090 1091 if (xfer->flags_int.usb2_mode == USB_MODE_DEVICE) { 1092 ep_no = (xfer->endpoint & UE_ADDR); 1093 1094 /* select endpoint number */ 1095 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1096 1097 /* disable endpoint interrupt */ 1098 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1099 1100 DPRINTFN(15, "disabled interrupts!\n"); 1101 } 1102 /* dequeue transfer and start next transfer */ 1103 usb2_transfer_done(xfer, error); 1104 } 1105 1106 static void 1107 atmegadci_set_stall(struct usb2_device *udev, struct usb2_xfer *xfer, 1108 struct usb2_pipe *pipe) 1109 { 1110 struct atmegadci_softc *sc; 1111 uint8_t ep_no; 1112 1113 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1114 1115 DPRINTFN(5, "pipe=%p\n", pipe); 1116 1117 if (xfer) { 1118 /* cancel any ongoing transfers */ 1119 atmegadci_device_done(xfer, USB_ERR_STALLED); 1120 } 1121 sc = ATMEGA_BUS2SC(udev->bus); 1122 /* get endpoint number */ 1123 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR); 1124 /* select endpoint number */ 1125 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1126 /* set stall */ 1127 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1128 ATMEGA_UECONX_EPEN | 1129 ATMEGA_UECONX_STALLRQ); 1130 } 1131 1132 static void 1133 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no, 1134 uint8_t ep_type, uint8_t ep_dir) 1135 { 1136 uint8_t temp; 1137 1138 if (ep_type == UE_CONTROL) { 1139 /* clearing stall is not needed */ 1140 return; 1141 } 1142 /* select endpoint number */ 1143 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no); 1144 1145 /* set endpoint reset */ 1146 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no)); 1147 1148 /* clear endpoint reset */ 1149 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1150 1151 /* set stall */ 1152 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1153 ATMEGA_UECONX_EPEN | 1154 ATMEGA_UECONX_STALLRQ); 1155 1156 /* reset data toggle */ 1157 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1158 ATMEGA_UECONX_EPEN | 1159 ATMEGA_UECONX_RSTDT); 1160 1161 /* clear stall */ 1162 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 1163 ATMEGA_UECONX_EPEN | 1164 ATMEGA_UECONX_STALLRQC); 1165 1166 if (ep_type == UE_CONTROL) { 1167 /* one bank, 64-bytes wMaxPacket */ 1168 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, 1169 ATMEGA_UECFG0X_EPTYPE0); 1170 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1171 ATMEGA_UECFG1X_ALLOC | 1172 ATMEGA_UECFG1X_EPBK0 | 1173 ATMEGA_UECFG1X_EPSIZE(7)); 1174 } else { 1175 temp = 0; 1176 if (ep_type == UE_BULK) { 1177 temp |= ATMEGA_UECFG0X_EPTYPE2; 1178 } else if (ep_type == UE_INTERRUPT) { 1179 temp |= ATMEGA_UECFG0X_EPTYPE3; 1180 } else { 1181 temp |= ATMEGA_UECFG0X_EPTYPE1; 1182 } 1183 if (ep_dir & UE_DIR_IN) { 1184 temp |= ATMEGA_UECFG0X_EPDIR; 1185 } 1186 /* two banks, 64-bytes wMaxPacket */ 1187 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp); 1188 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X, 1189 ATMEGA_UECFG1X_ALLOC | 1190 ATMEGA_UECFG1X_EPBK1 | 1191 ATMEGA_UECFG1X_EPSIZE(7)); 1192 1193 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X); 1194 if (!(temp & ATMEGA_UESTA0X_CFGOK)) { 1195 DPRINTFN(0, "Chip rejected configuration\n"); 1196 } 1197 } 1198 } 1199 1200 static void 1201 atmegadci_clear_stall(struct usb2_device *udev, struct usb2_pipe *pipe) 1202 { 1203 struct atmegadci_softc *sc; 1204 struct usb2_endpoint_descriptor *ed; 1205 1206 DPRINTFN(5, "pipe=%p\n", pipe); 1207 1208 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1209 1210 /* check mode */ 1211 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 1212 /* not supported */ 1213 return; 1214 } 1215 /* get softc */ 1216 sc = ATMEGA_BUS2SC(udev->bus); 1217 1218 /* get endpoint descriptor */ 1219 ed = pipe->edesc; 1220 1221 /* reset endpoint */ 1222 atmegadci_clear_stall_sub(sc, 1223 (ed->bEndpointAddress & UE_ADDR), 1224 (ed->bmAttributes & UE_XFERTYPE), 1225 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1226 } 1227 1228 usb2_error_t 1229 atmegadci_init(struct atmegadci_softc *sc) 1230 { 1231 uint8_t n; 1232 1233 DPRINTF("start\n"); 1234 1235 /* set up the bus structure */ 1236 sc->sc_bus.usbrev = USB_REV_1_1; 1237 sc->sc_bus.methods = &atmegadci_bus_methods; 1238 1239 USB_BUS_LOCK(&sc->sc_bus); 1240 1241 /* enable USB PAD regulator */ 1242 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 1243 ATMEGA_UHWCON_UVREGE); 1244 1245 /* turn on clocks */ 1246 (sc->sc_clocks_on) (&sc->sc_bus); 1247 1248 /* wait a little for things to stabilise */ 1249 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 1250 1251 /* enable interrupts */ 1252 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 1253 ATMEGA_UDINT_SUSPE | 1254 ATMEGA_UDINT_EORSTE); 1255 1256 /* reset all endpoints */ 1257 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1258 (1 << ATMEGA_EP_MAX) - 1); 1259 1260 /* disable reset */ 1261 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1262 1263 /* disable all endpoints */ 1264 for (n = 1; n != ATMEGA_EP_MAX; n++) { 1265 1266 /* select endpoint */ 1267 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n); 1268 1269 /* disable endpoint interrupt */ 1270 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0); 1271 1272 /* disable endpoint */ 1273 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0); 1274 } 1275 1276 /* turn off clocks */ 1277 1278 atmegadci_clocks_off(sc); 1279 1280 USB_BUS_UNLOCK(&sc->sc_bus); 1281 1282 /* catch any lost interrupts */ 1283 1284 atmegadci_do_poll(&sc->sc_bus); 1285 1286 return (0); /* success */ 1287 } 1288 1289 void 1290 atmegadci_uninit(struct atmegadci_softc *sc) 1291 { 1292 USB_BUS_LOCK(&sc->sc_bus); 1293 1294 /* turn on clocks */ 1295 (sc->sc_clocks_on) (&sc->sc_bus); 1296 1297 /* disable interrupts */ 1298 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0); 1299 1300 /* reset all endpoints */ 1301 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 1302 (1 << ATMEGA_EP_MAX) - 1); 1303 1304 /* disable reset */ 1305 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0); 1306 1307 sc->sc_flags.port_powered = 0; 1308 sc->sc_flags.status_vbus = 0; 1309 sc->sc_flags.status_bus_reset = 0; 1310 sc->sc_flags.status_suspend = 0; 1311 sc->sc_flags.change_suspend = 0; 1312 sc->sc_flags.change_connect = 1; 1313 1314 atmegadci_pull_down(sc); 1315 atmegadci_clocks_off(sc); 1316 1317 /* disable USB PAD regulator */ 1318 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0); 1319 1320 USB_BUS_UNLOCK(&sc->sc_bus); 1321 } 1322 1323 void 1324 atmegadci_suspend(struct atmegadci_softc *sc) 1325 { 1326 return; 1327 } 1328 1329 void 1330 atmegadci_resume(struct atmegadci_softc *sc) 1331 { 1332 return; 1333 } 1334 1335 static void 1336 atmegadci_do_poll(struct usb2_bus *bus) 1337 { 1338 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus); 1339 1340 USB_BUS_LOCK(&sc->sc_bus); 1341 atmegadci_interrupt_poll(sc); 1342 atmegadci_root_ctrl_poll(sc); 1343 USB_BUS_UNLOCK(&sc->sc_bus); 1344 } 1345 1346 /*------------------------------------------------------------------------* 1347 * at91dci bulk support 1348 *------------------------------------------------------------------------*/ 1349 static void 1350 atmegadci_device_bulk_open(struct usb2_xfer *xfer) 1351 { 1352 return; 1353 } 1354 1355 static void 1356 atmegadci_device_bulk_close(struct usb2_xfer *xfer) 1357 { 1358 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1359 } 1360 1361 static void 1362 atmegadci_device_bulk_enter(struct usb2_xfer *xfer) 1363 { 1364 return; 1365 } 1366 1367 static void 1368 atmegadci_device_bulk_start(struct usb2_xfer *xfer) 1369 { 1370 /* setup TDs */ 1371 atmegadci_setup_standard_chain(xfer); 1372 atmegadci_start_standard_chain(xfer); 1373 } 1374 1375 struct usb2_pipe_methods atmegadci_device_bulk_methods = 1376 { 1377 .open = atmegadci_device_bulk_open, 1378 .close = atmegadci_device_bulk_close, 1379 .enter = atmegadci_device_bulk_enter, 1380 .start = atmegadci_device_bulk_start, 1381 .enter_is_cancelable = 1, 1382 .start_is_cancelable = 1, 1383 }; 1384 1385 /*------------------------------------------------------------------------* 1386 * at91dci control support 1387 *------------------------------------------------------------------------*/ 1388 static void 1389 atmegadci_device_ctrl_open(struct usb2_xfer *xfer) 1390 { 1391 return; 1392 } 1393 1394 static void 1395 atmegadci_device_ctrl_close(struct usb2_xfer *xfer) 1396 { 1397 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1398 } 1399 1400 static void 1401 atmegadci_device_ctrl_enter(struct usb2_xfer *xfer) 1402 { 1403 return; 1404 } 1405 1406 static void 1407 atmegadci_device_ctrl_start(struct usb2_xfer *xfer) 1408 { 1409 /* setup TDs */ 1410 atmegadci_setup_standard_chain(xfer); 1411 atmegadci_start_standard_chain(xfer); 1412 } 1413 1414 struct usb2_pipe_methods atmegadci_device_ctrl_methods = 1415 { 1416 .open = atmegadci_device_ctrl_open, 1417 .close = atmegadci_device_ctrl_close, 1418 .enter = atmegadci_device_ctrl_enter, 1419 .start = atmegadci_device_ctrl_start, 1420 .enter_is_cancelable = 1, 1421 .start_is_cancelable = 1, 1422 }; 1423 1424 /*------------------------------------------------------------------------* 1425 * at91dci interrupt support 1426 *------------------------------------------------------------------------*/ 1427 static void 1428 atmegadci_device_intr_open(struct usb2_xfer *xfer) 1429 { 1430 return; 1431 } 1432 1433 static void 1434 atmegadci_device_intr_close(struct usb2_xfer *xfer) 1435 { 1436 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1437 } 1438 1439 static void 1440 atmegadci_device_intr_enter(struct usb2_xfer *xfer) 1441 { 1442 return; 1443 } 1444 1445 static void 1446 atmegadci_device_intr_start(struct usb2_xfer *xfer) 1447 { 1448 /* setup TDs */ 1449 atmegadci_setup_standard_chain(xfer); 1450 atmegadci_start_standard_chain(xfer); 1451 } 1452 1453 struct usb2_pipe_methods atmegadci_device_intr_methods = 1454 { 1455 .open = atmegadci_device_intr_open, 1456 .close = atmegadci_device_intr_close, 1457 .enter = atmegadci_device_intr_enter, 1458 .start = atmegadci_device_intr_start, 1459 .enter_is_cancelable = 1, 1460 .start_is_cancelable = 1, 1461 }; 1462 1463 /*------------------------------------------------------------------------* 1464 * at91dci full speed isochronous support 1465 *------------------------------------------------------------------------*/ 1466 static void 1467 atmegadci_device_isoc_fs_open(struct usb2_xfer *xfer) 1468 { 1469 return; 1470 } 1471 1472 static void 1473 atmegadci_device_isoc_fs_close(struct usb2_xfer *xfer) 1474 { 1475 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1476 } 1477 1478 static void 1479 atmegadci_device_isoc_fs_enter(struct usb2_xfer *xfer) 1480 { 1481 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1482 uint32_t temp; 1483 uint32_t nframes; 1484 1485 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1486 xfer, xfer->pipe->isoc_next, xfer->nframes); 1487 1488 /* get the current frame index */ 1489 1490 nframes = 1491 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) | 1492 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML)); 1493 1494 nframes &= ATMEGA_FRAME_MASK; 1495 1496 /* 1497 * check if the frame index is within the window where the frames 1498 * will be inserted 1499 */ 1500 temp = (nframes - xfer->pipe->isoc_next) & ATMEGA_FRAME_MASK; 1501 1502 if ((xfer->pipe->is_synced == 0) || 1503 (temp < xfer->nframes)) { 1504 /* 1505 * If there is data underflow or the pipe queue is 1506 * empty we schedule the transfer a few frames ahead 1507 * of the current frame position. Else two isochronous 1508 * transfers might overlap. 1509 */ 1510 xfer->pipe->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK; 1511 xfer->pipe->is_synced = 1; 1512 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 1513 } 1514 /* 1515 * compute how many milliseconds the insertion is ahead of the 1516 * current frame position: 1517 */ 1518 temp = (xfer->pipe->isoc_next - nframes) & ATMEGA_FRAME_MASK; 1519 1520 /* 1521 * pre-compute when the isochronous transfer will be finished: 1522 */ 1523 xfer->isoc_time_complete = 1524 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1525 xfer->nframes; 1526 1527 /* compute frame number for next insertion */ 1528 xfer->pipe->isoc_next += xfer->nframes; 1529 1530 /* setup TDs */ 1531 atmegadci_setup_standard_chain(xfer); 1532 } 1533 1534 static void 1535 atmegadci_device_isoc_fs_start(struct usb2_xfer *xfer) 1536 { 1537 /* start TD chain */ 1538 atmegadci_start_standard_chain(xfer); 1539 } 1540 1541 struct usb2_pipe_methods atmegadci_device_isoc_fs_methods = 1542 { 1543 .open = atmegadci_device_isoc_fs_open, 1544 .close = atmegadci_device_isoc_fs_close, 1545 .enter = atmegadci_device_isoc_fs_enter, 1546 .start = atmegadci_device_isoc_fs_start, 1547 .enter_is_cancelable = 1, 1548 .start_is_cancelable = 1, 1549 }; 1550 1551 /*------------------------------------------------------------------------* 1552 * at91dci root control support 1553 *------------------------------------------------------------------------* 1554 * simulate a hardware HUB by handling 1555 * all the necessary requests 1556 *------------------------------------------------------------------------*/ 1557 1558 static void 1559 atmegadci_root_ctrl_open(struct usb2_xfer *xfer) 1560 { 1561 return; 1562 } 1563 1564 static void 1565 atmegadci_root_ctrl_close(struct usb2_xfer *xfer) 1566 { 1567 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1568 1569 if (sc->sc_root_ctrl.xfer == xfer) { 1570 sc->sc_root_ctrl.xfer = NULL; 1571 } 1572 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 1573 } 1574 1575 /* 1576 * USB descriptors for the virtual Root HUB: 1577 */ 1578 1579 static const struct usb2_device_descriptor atmegadci_devd = { 1580 .bLength = sizeof(struct usb2_device_descriptor), 1581 .bDescriptorType = UDESC_DEVICE, 1582 .bcdUSB = {0x00, 0x02}, 1583 .bDeviceClass = UDCLASS_HUB, 1584 .bDeviceSubClass = UDSUBCLASS_HUB, 1585 .bDeviceProtocol = UDPROTO_HSHUBSTT, 1586 .bMaxPacketSize = 64, 1587 .bcdDevice = {0x00, 0x01}, 1588 .iManufacturer = 1, 1589 .iProduct = 2, 1590 .bNumConfigurations = 1, 1591 }; 1592 1593 static const struct usb2_device_qualifier atmegadci_odevd = { 1594 .bLength = sizeof(struct usb2_device_qualifier), 1595 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 1596 .bcdUSB = {0x00, 0x02}, 1597 .bDeviceClass = UDCLASS_HUB, 1598 .bDeviceSubClass = UDSUBCLASS_HUB, 1599 .bDeviceProtocol = UDPROTO_FSHUB, 1600 .bMaxPacketSize0 = 0, 1601 .bNumConfigurations = 0, 1602 }; 1603 1604 static const struct atmegadci_config_desc atmegadci_confd = { 1605 .confd = { 1606 .bLength = sizeof(struct usb2_config_descriptor), 1607 .bDescriptorType = UDESC_CONFIG, 1608 .wTotalLength[0] = sizeof(atmegadci_confd), 1609 .bNumInterface = 1, 1610 .bConfigurationValue = 1, 1611 .iConfiguration = 0, 1612 .bmAttributes = UC_SELF_POWERED, 1613 .bMaxPower = 0, 1614 }, 1615 .ifcd = { 1616 .bLength = sizeof(struct usb2_interface_descriptor), 1617 .bDescriptorType = UDESC_INTERFACE, 1618 .bNumEndpoints = 1, 1619 .bInterfaceClass = UICLASS_HUB, 1620 .bInterfaceSubClass = UISUBCLASS_HUB, 1621 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 1622 }, 1623 1624 .endpd = { 1625 .bLength = sizeof(struct usb2_endpoint_descriptor), 1626 .bDescriptorType = UDESC_ENDPOINT, 1627 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT), 1628 .bmAttributes = UE_INTERRUPT, 1629 .wMaxPacketSize[0] = 8, 1630 .bInterval = 255, 1631 }, 1632 }; 1633 1634 static const struct usb2_hub_descriptor_min atmegadci_hubd = { 1635 .bDescLength = sizeof(atmegadci_hubd), 1636 .bDescriptorType = UDESC_HUB, 1637 .bNbrPorts = 1, 1638 .wHubCharacteristics[0] = 1639 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF, 1640 .wHubCharacteristics[1] = 1641 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 8, 1642 .bPwrOn2PwrGood = 50, 1643 .bHubContrCurrent = 0, 1644 .DeviceRemovable = {0}, /* port is removable */ 1645 }; 1646 1647 #define STRING_LANG \ 1648 0x09, 0x04, /* American English */ 1649 1650 #define STRING_VENDOR \ 1651 'A', 0, 'T', 0, 'M', 0, 'E', 0, 'G', 0, 'A', 0 1652 1653 #define STRING_PRODUCT \ 1654 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 1655 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 1656 'U', 0, 'B', 0, 1657 1658 USB_MAKE_STRING_DESC(STRING_LANG, atmegadci_langtab); 1659 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor); 1660 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product); 1661 1662 static void 1663 atmegadci_root_ctrl_enter(struct usb2_xfer *xfer) 1664 { 1665 return; 1666 } 1667 1668 static void 1669 atmegadci_root_ctrl_start(struct usb2_xfer *xfer) 1670 { 1671 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1672 1673 sc->sc_root_ctrl.xfer = xfer; 1674 1675 usb2_bus_roothub_exec(xfer->xroot->bus); 1676 } 1677 1678 static void 1679 atmegadci_root_ctrl_task(struct usb2_bus *bus) 1680 { 1681 atmegadci_root_ctrl_poll(ATMEGA_BUS2SC(bus)); 1682 } 1683 1684 static void 1685 atmegadci_root_ctrl_done(struct usb2_xfer *xfer, 1686 struct usb2_sw_transfer *std) 1687 { 1688 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 1689 uint16_t value; 1690 uint16_t index; 1691 1692 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1693 1694 if (std->state != USB_SW_TR_SETUP) { 1695 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1696 /* transfer transferred */ 1697 atmegadci_device_done(xfer, std->err); 1698 } 1699 goto done; 1700 } 1701 /* buffer reset */ 1702 std->ptr = USB_ADD_BYTES(&sc->sc_hub_temp, 0); 1703 std->len = 0; 1704 1705 value = UGETW(std->req.wValue); 1706 index = UGETW(std->req.wIndex); 1707 1708 /* demultiplex the control request */ 1709 1710 switch (std->req.bmRequestType) { 1711 case UT_READ_DEVICE: 1712 switch (std->req.bRequest) { 1713 case UR_GET_DESCRIPTOR: 1714 goto tr_handle_get_descriptor; 1715 case UR_GET_CONFIG: 1716 goto tr_handle_get_config; 1717 case UR_GET_STATUS: 1718 goto tr_handle_get_status; 1719 default: 1720 goto tr_stalled; 1721 } 1722 break; 1723 1724 case UT_WRITE_DEVICE: 1725 switch (std->req.bRequest) { 1726 case UR_SET_ADDRESS: 1727 goto tr_handle_set_address; 1728 case UR_SET_CONFIG: 1729 goto tr_handle_set_config; 1730 case UR_CLEAR_FEATURE: 1731 goto tr_valid; /* nop */ 1732 case UR_SET_DESCRIPTOR: 1733 goto tr_valid; /* nop */ 1734 case UR_SET_FEATURE: 1735 default: 1736 goto tr_stalled; 1737 } 1738 break; 1739 1740 case UT_WRITE_ENDPOINT: 1741 switch (std->req.bRequest) { 1742 case UR_CLEAR_FEATURE: 1743 switch (UGETW(std->req.wValue)) { 1744 case UF_ENDPOINT_HALT: 1745 goto tr_handle_clear_halt; 1746 case UF_DEVICE_REMOTE_WAKEUP: 1747 goto tr_handle_clear_wakeup; 1748 default: 1749 goto tr_stalled; 1750 } 1751 break; 1752 case UR_SET_FEATURE: 1753 switch (UGETW(std->req.wValue)) { 1754 case UF_ENDPOINT_HALT: 1755 goto tr_handle_set_halt; 1756 case UF_DEVICE_REMOTE_WAKEUP: 1757 goto tr_handle_set_wakeup; 1758 default: 1759 goto tr_stalled; 1760 } 1761 break; 1762 case UR_SYNCH_FRAME: 1763 goto tr_valid; /* nop */ 1764 default: 1765 goto tr_stalled; 1766 } 1767 break; 1768 1769 case UT_READ_ENDPOINT: 1770 switch (std->req.bRequest) { 1771 case UR_GET_STATUS: 1772 goto tr_handle_get_ep_status; 1773 default: 1774 goto tr_stalled; 1775 } 1776 break; 1777 1778 case UT_WRITE_INTERFACE: 1779 switch (std->req.bRequest) { 1780 case UR_SET_INTERFACE: 1781 goto tr_handle_set_interface; 1782 case UR_CLEAR_FEATURE: 1783 goto tr_valid; /* nop */ 1784 case UR_SET_FEATURE: 1785 default: 1786 goto tr_stalled; 1787 } 1788 break; 1789 1790 case UT_READ_INTERFACE: 1791 switch (std->req.bRequest) { 1792 case UR_GET_INTERFACE: 1793 goto tr_handle_get_interface; 1794 case UR_GET_STATUS: 1795 goto tr_handle_get_iface_status; 1796 default: 1797 goto tr_stalled; 1798 } 1799 break; 1800 1801 case UT_WRITE_CLASS_INTERFACE: 1802 case UT_WRITE_VENDOR_INTERFACE: 1803 /* XXX forward */ 1804 break; 1805 1806 case UT_READ_CLASS_INTERFACE: 1807 case UT_READ_VENDOR_INTERFACE: 1808 /* XXX forward */ 1809 break; 1810 1811 case UT_WRITE_CLASS_DEVICE: 1812 switch (std->req.bRequest) { 1813 case UR_CLEAR_FEATURE: 1814 goto tr_valid; 1815 case UR_SET_DESCRIPTOR: 1816 case UR_SET_FEATURE: 1817 break; 1818 default: 1819 goto tr_stalled; 1820 } 1821 break; 1822 1823 case UT_WRITE_CLASS_OTHER: 1824 switch (std->req.bRequest) { 1825 case UR_CLEAR_FEATURE: 1826 goto tr_handle_clear_port_feature; 1827 case UR_SET_FEATURE: 1828 goto tr_handle_set_port_feature; 1829 case UR_CLEAR_TT_BUFFER: 1830 case UR_RESET_TT: 1831 case UR_STOP_TT: 1832 goto tr_valid; 1833 1834 default: 1835 goto tr_stalled; 1836 } 1837 break; 1838 1839 case UT_READ_CLASS_OTHER: 1840 switch (std->req.bRequest) { 1841 case UR_GET_TT_STATE: 1842 goto tr_handle_get_tt_state; 1843 case UR_GET_STATUS: 1844 goto tr_handle_get_port_status; 1845 default: 1846 goto tr_stalled; 1847 } 1848 break; 1849 1850 case UT_READ_CLASS_DEVICE: 1851 switch (std->req.bRequest) { 1852 case UR_GET_DESCRIPTOR: 1853 goto tr_handle_get_class_descriptor; 1854 case UR_GET_STATUS: 1855 goto tr_handle_get_class_status; 1856 1857 default: 1858 goto tr_stalled; 1859 } 1860 break; 1861 default: 1862 goto tr_stalled; 1863 } 1864 goto tr_valid; 1865 1866 tr_handle_get_descriptor: 1867 switch (value >> 8) { 1868 case UDESC_DEVICE: 1869 if (value & 0xff) { 1870 goto tr_stalled; 1871 } 1872 std->len = sizeof(atmegadci_devd); 1873 std->ptr = USB_ADD_BYTES(&atmegadci_devd, 0); 1874 goto tr_valid; 1875 case UDESC_CONFIG: 1876 if (value & 0xff) { 1877 goto tr_stalled; 1878 } 1879 std->len = sizeof(atmegadci_confd); 1880 std->ptr = USB_ADD_BYTES(&atmegadci_confd, 0); 1881 goto tr_valid; 1882 case UDESC_STRING: 1883 switch (value & 0xff) { 1884 case 0: /* Language table */ 1885 std->len = sizeof(atmegadci_langtab); 1886 std->ptr = USB_ADD_BYTES(&atmegadci_langtab, 0); 1887 goto tr_valid; 1888 1889 case 1: /* Vendor */ 1890 std->len = sizeof(atmegadci_vendor); 1891 std->ptr = USB_ADD_BYTES(&atmegadci_vendor, 0); 1892 goto tr_valid; 1893 1894 case 2: /* Product */ 1895 std->len = sizeof(atmegadci_product); 1896 std->ptr = USB_ADD_BYTES(&atmegadci_product, 0); 1897 goto tr_valid; 1898 default: 1899 break; 1900 } 1901 break; 1902 default: 1903 goto tr_stalled; 1904 } 1905 goto tr_stalled; 1906 1907 tr_handle_get_config: 1908 std->len = 1; 1909 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 1910 goto tr_valid; 1911 1912 tr_handle_get_status: 1913 std->len = 2; 1914 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 1915 goto tr_valid; 1916 1917 tr_handle_set_address: 1918 if (value & 0xFF00) { 1919 goto tr_stalled; 1920 } 1921 sc->sc_rt_addr = value; 1922 goto tr_valid; 1923 1924 tr_handle_set_config: 1925 if (value >= 2) { 1926 goto tr_stalled; 1927 } 1928 sc->sc_conf = value; 1929 goto tr_valid; 1930 1931 tr_handle_get_interface: 1932 std->len = 1; 1933 sc->sc_hub_temp.wValue[0] = 0; 1934 goto tr_valid; 1935 1936 tr_handle_get_tt_state: 1937 tr_handle_get_class_status: 1938 tr_handle_get_iface_status: 1939 tr_handle_get_ep_status: 1940 std->len = 2; 1941 USETW(sc->sc_hub_temp.wValue, 0); 1942 goto tr_valid; 1943 1944 tr_handle_set_halt: 1945 tr_handle_set_interface: 1946 tr_handle_set_wakeup: 1947 tr_handle_clear_wakeup: 1948 tr_handle_clear_halt: 1949 goto tr_valid; 1950 1951 tr_handle_clear_port_feature: 1952 if (index != 1) { 1953 goto tr_stalled; 1954 } 1955 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 1956 1957 switch (value) { 1958 case UHF_PORT_SUSPEND: 1959 atmegadci_wakeup_peer(xfer); 1960 break; 1961 1962 case UHF_PORT_ENABLE: 1963 sc->sc_flags.port_enabled = 0; 1964 break; 1965 1966 case UHF_PORT_TEST: 1967 case UHF_PORT_INDICATOR: 1968 case UHF_C_PORT_ENABLE: 1969 case UHF_C_PORT_OVER_CURRENT: 1970 case UHF_C_PORT_RESET: 1971 /* nops */ 1972 break; 1973 case UHF_PORT_POWER: 1974 sc->sc_flags.port_powered = 0; 1975 atmegadci_pull_down(sc); 1976 atmegadci_clocks_off(sc); 1977 break; 1978 case UHF_C_PORT_CONNECTION: 1979 sc->sc_flags.change_connect = 0; 1980 break; 1981 case UHF_C_PORT_SUSPEND: 1982 sc->sc_flags.change_suspend = 0; 1983 break; 1984 default: 1985 std->err = USB_ERR_IOERROR; 1986 goto done; 1987 } 1988 goto tr_valid; 1989 1990 tr_handle_set_port_feature: 1991 if (index != 1) { 1992 goto tr_stalled; 1993 } 1994 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 1995 1996 switch (value) { 1997 case UHF_PORT_ENABLE: 1998 sc->sc_flags.port_enabled = 1; 1999 break; 2000 case UHF_PORT_SUSPEND: 2001 case UHF_PORT_RESET: 2002 case UHF_PORT_TEST: 2003 case UHF_PORT_INDICATOR: 2004 /* nops */ 2005 break; 2006 case UHF_PORT_POWER: 2007 sc->sc_flags.port_powered = 1; 2008 break; 2009 default: 2010 std->err = USB_ERR_IOERROR; 2011 goto done; 2012 } 2013 goto tr_valid; 2014 2015 tr_handle_get_port_status: 2016 2017 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2018 2019 if (index != 1) { 2020 goto tr_stalled; 2021 } 2022 if (sc->sc_flags.status_vbus) { 2023 atmegadci_clocks_on(sc); 2024 atmegadci_pull_up(sc); 2025 } else { 2026 atmegadci_pull_down(sc); 2027 atmegadci_clocks_off(sc); 2028 } 2029 2030 /* Select FULL-speed and Device Side Mode */ 2031 2032 value = UPS_PORT_MODE_DEVICE; 2033 2034 if (sc->sc_flags.port_powered) { 2035 value |= UPS_PORT_POWER; 2036 } 2037 if (sc->sc_flags.port_enabled) { 2038 value |= UPS_PORT_ENABLED; 2039 } 2040 if (sc->sc_flags.status_vbus && 2041 sc->sc_flags.status_bus_reset) { 2042 value |= UPS_CURRENT_CONNECT_STATUS; 2043 } 2044 if (sc->sc_flags.status_suspend) { 2045 value |= UPS_SUSPEND; 2046 } 2047 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2048 2049 value = 0; 2050 2051 if (sc->sc_flags.change_connect) { 2052 value |= UPS_C_CONNECT_STATUS; 2053 } 2054 if (sc->sc_flags.change_suspend) { 2055 value |= UPS_C_SUSPEND; 2056 } 2057 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2058 std->len = sizeof(sc->sc_hub_temp.ps); 2059 goto tr_valid; 2060 2061 tr_handle_get_class_descriptor: 2062 if (value & 0xFF) { 2063 goto tr_stalled; 2064 } 2065 std->ptr = USB_ADD_BYTES(&atmegadci_hubd, 0); 2066 std->len = sizeof(atmegadci_hubd); 2067 goto tr_valid; 2068 2069 tr_stalled: 2070 std->err = USB_ERR_STALLED; 2071 tr_valid: 2072 done: 2073 return; 2074 } 2075 2076 static void 2077 atmegadci_root_ctrl_poll(struct atmegadci_softc *sc) 2078 { 2079 usb2_sw_transfer(&sc->sc_root_ctrl, 2080 &atmegadci_root_ctrl_done); 2081 } 2082 2083 struct usb2_pipe_methods atmegadci_root_ctrl_methods = 2084 { 2085 .open = atmegadci_root_ctrl_open, 2086 .close = atmegadci_root_ctrl_close, 2087 .enter = atmegadci_root_ctrl_enter, 2088 .start = atmegadci_root_ctrl_start, 2089 .enter_is_cancelable = 1, 2090 .start_is_cancelable = 0, 2091 }; 2092 2093 /*------------------------------------------------------------------------* 2094 * at91dci root interrupt support 2095 *------------------------------------------------------------------------*/ 2096 static void 2097 atmegadci_root_intr_open(struct usb2_xfer *xfer) 2098 { 2099 return; 2100 } 2101 2102 static void 2103 atmegadci_root_intr_close(struct usb2_xfer *xfer) 2104 { 2105 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2106 2107 if (sc->sc_root_intr.xfer == xfer) { 2108 sc->sc_root_intr.xfer = NULL; 2109 } 2110 atmegadci_device_done(xfer, USB_ERR_CANCELLED); 2111 } 2112 2113 static void 2114 atmegadci_root_intr_enter(struct usb2_xfer *xfer) 2115 { 2116 return; 2117 } 2118 2119 static void 2120 atmegadci_root_intr_start(struct usb2_xfer *xfer) 2121 { 2122 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus); 2123 2124 sc->sc_root_intr.xfer = xfer; 2125 } 2126 2127 struct usb2_pipe_methods atmegadci_root_intr_methods = 2128 { 2129 .open = atmegadci_root_intr_open, 2130 .close = atmegadci_root_intr_close, 2131 .enter = atmegadci_root_intr_enter, 2132 .start = atmegadci_root_intr_start, 2133 .enter_is_cancelable = 1, 2134 .start_is_cancelable = 1, 2135 }; 2136 2137 static void 2138 atmegadci_xfer_setup(struct usb2_setup_params *parm) 2139 { 2140 const struct usb2_hw_ep_profile *pf; 2141 struct atmegadci_softc *sc; 2142 struct usb2_xfer *xfer; 2143 void *last_obj; 2144 uint32_t ntd; 2145 uint32_t n; 2146 uint8_t ep_no; 2147 2148 sc = ATMEGA_BUS2SC(parm->udev->bus); 2149 xfer = parm->curr_xfer; 2150 2151 /* 2152 * NOTE: This driver does not use any of the parameters that 2153 * are computed from the following values. Just set some 2154 * reasonable dummies: 2155 */ 2156 parm->hc_max_packet_size = 0x500; 2157 parm->hc_max_packet_count = 1; 2158 parm->hc_max_frame_size = 0x500; 2159 2160 usb2_transfer_setup_sub(parm); 2161 2162 /* 2163 * compute maximum number of TDs 2164 */ 2165 if (parm->methods == &atmegadci_device_ctrl_methods) { 2166 2167 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2168 + 1 /* SYNC 2 */ ; 2169 2170 } else if (parm->methods == &atmegadci_device_bulk_methods) { 2171 2172 ntd = xfer->nframes + 1 /* SYNC */ ; 2173 2174 } else if (parm->methods == &atmegadci_device_intr_methods) { 2175 2176 ntd = xfer->nframes + 1 /* SYNC */ ; 2177 2178 } else if (parm->methods == &atmegadci_device_isoc_fs_methods) { 2179 2180 ntd = xfer->nframes + 1 /* SYNC */ ; 2181 2182 } else { 2183 2184 ntd = 0; 2185 } 2186 2187 /* 2188 * check if "usb2_transfer_setup_sub" set an error 2189 */ 2190 if (parm->err) { 2191 return; 2192 } 2193 /* 2194 * allocate transfer descriptors 2195 */ 2196 last_obj = NULL; 2197 2198 /* 2199 * get profile stuff 2200 */ 2201 if (ntd) { 2202 2203 ep_no = xfer->endpoint & UE_ADDR; 2204 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no); 2205 2206 if (pf == NULL) { 2207 /* should not happen */ 2208 parm->err = USB_ERR_INVAL; 2209 return; 2210 } 2211 } else { 2212 ep_no = 0; 2213 pf = NULL; 2214 } 2215 2216 /* align data */ 2217 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2218 2219 for (n = 0; n != ntd; n++) { 2220 2221 struct atmegadci_td *td; 2222 2223 if (parm->buf) { 2224 2225 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2226 2227 /* init TD */ 2228 td->max_packet_size = xfer->max_packet_size; 2229 td->ep_no = ep_no; 2230 if (pf->support_multi_buffer) { 2231 td->support_multi_buffer = 1; 2232 } 2233 td->obj_next = last_obj; 2234 2235 last_obj = td; 2236 } 2237 parm->size[0] += sizeof(*td); 2238 } 2239 2240 xfer->td_start[0] = last_obj; 2241 } 2242 2243 static void 2244 atmegadci_xfer_unsetup(struct usb2_xfer *xfer) 2245 { 2246 return; 2247 } 2248 2249 static void 2250 atmegadci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 2251 struct usb2_pipe *pipe) 2252 { 2253 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus); 2254 2255 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 2256 pipe, udev->address, 2257 edesc->bEndpointAddress, udev->flags.usb2_mode, 2258 sc->sc_rt_addr); 2259 2260 if (udev->device_index == sc->sc_rt_addr) { 2261 2262 if (udev->flags.usb2_mode != USB_MODE_HOST) { 2263 /* not supported */ 2264 return; 2265 } 2266 switch (edesc->bEndpointAddress) { 2267 case USB_CONTROL_ENDPOINT: 2268 pipe->methods = &atmegadci_root_ctrl_methods; 2269 break; 2270 case UE_DIR_IN | ATMEGA_INTR_ENDPT: 2271 pipe->methods = &atmegadci_root_intr_methods; 2272 break; 2273 default: 2274 /* do nothing */ 2275 break; 2276 } 2277 } else { 2278 2279 if (udev->flags.usb2_mode != USB_MODE_DEVICE) { 2280 /* not supported */ 2281 return; 2282 } 2283 if (udev->speed != USB_SPEED_FULL) { 2284 /* not supported */ 2285 return; 2286 } 2287 switch (edesc->bmAttributes & UE_XFERTYPE) { 2288 case UE_CONTROL: 2289 pipe->methods = &atmegadci_device_ctrl_methods; 2290 break; 2291 case UE_INTERRUPT: 2292 pipe->methods = &atmegadci_device_intr_methods; 2293 break; 2294 case UE_ISOCHRONOUS: 2295 pipe->methods = &atmegadci_device_isoc_fs_methods; 2296 break; 2297 case UE_BULK: 2298 pipe->methods = &atmegadci_device_bulk_methods; 2299 break; 2300 default: 2301 /* do nothing */ 2302 break; 2303 } 2304 } 2305 } 2306 2307 struct usb2_bus_methods atmegadci_bus_methods = 2308 { 2309 .pipe_init = &atmegadci_pipe_init, 2310 .xfer_setup = &atmegadci_xfer_setup, 2311 .xfer_unsetup = &atmegadci_xfer_unsetup, 2312 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile, 2313 .set_stall = &atmegadci_set_stall, 2314 .clear_stall = &atmegadci_clear_stall, 2315 .roothub_exec = &atmegadci_root_ctrl_task, 2316 }; 2317