1 /* 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 #include <dev/uart/uart_dev_z8530.h> 40 41 #include "uart_if.h" 42 43 #define DEFAULT_RCLK 307200 44 45 /* Multiplexed I/O. */ 46 static __inline void 47 uart_setmreg(struct uart_bas *bas, int reg, int val) 48 { 49 50 uart_setreg(bas, REG_CTRL, reg); 51 uart_barrier(bas); 52 uart_setreg(bas, REG_CTRL, val); 53 } 54 55 static __inline uint8_t 56 uart_getmreg(struct uart_bas *bas, int reg) 57 { 58 59 uart_setreg(bas, REG_CTRL, reg); 60 uart_barrier(bas); 61 return (uart_getreg(bas, REG_CTRL)); 62 } 63 64 static int 65 z8530_divisor(int rclk, int baudrate) 66 { 67 int act_baud, divisor, error; 68 69 if (baudrate == 0) 70 return (0); 71 72 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 73 if (divisor >= 65536) 74 return (0); 75 act_baud = rclk / 2 / (divisor + 2); 76 77 /* 10 times error in percent: */ 78 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 79 80 /* 3.0% maximum error tolerance: */ 81 if (error < -30 || error > 30) 82 return (0); 83 84 return (divisor); 85 } 86 87 static int 88 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 89 int parity, uint8_t *tpcp) 90 { 91 int divisor; 92 uint8_t mpm, rpc, tpc; 93 94 rpc = RPC_RXE; 95 mpm = MPM_CM16; 96 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 97 98 if (databits >= 8) { 99 rpc |= RPC_RB8; 100 tpc |= TPC_TB8; 101 } else if (databits == 7) { 102 rpc |= RPC_RB7; 103 tpc |= TPC_TB7; 104 } else if (databits == 6) { 105 rpc |= RPC_RB6; 106 tpc |= TPC_TB6; 107 } else { 108 rpc |= RPC_RB5; 109 tpc |= TPC_TB5; 110 } 111 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 112 switch (parity) { 113 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 114 case UART_PARITY_NONE: break; 115 case UART_PARITY_ODD: mpm |= MPM_PE; break; 116 default: return (EINVAL); 117 } 118 119 /* Set baudrate. */ 120 if (baudrate > 0) { 121 divisor = z8530_divisor(bas->rclk, baudrate); 122 if (divisor == 0) 123 return (EINVAL); 124 uart_setmreg(bas, WR_TCL, divisor & 0xff); 125 uart_barrier(bas); 126 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 127 uart_barrier(bas); 128 } 129 130 uart_setmreg(bas, WR_RPC, rpc); 131 uart_barrier(bas); 132 uart_setmreg(bas, WR_MPM, mpm); 133 uart_barrier(bas); 134 uart_setmreg(bas, WR_TPC, tpc); 135 uart_barrier(bas); 136 *tpcp = tpc; 137 return (0); 138 } 139 140 static int 141 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 142 int parity) 143 { 144 uint8_t mic, tpc; 145 146 if (bas->rclk == 0) 147 bas->rclk = DEFAULT_RCLK; 148 149 /* Assume we don't need to perform a full hardware reset. */ 150 mic = MIC_MIE | MIC_NV; 151 switch (bas->chan) { 152 case 1: 153 mic |= MIC_CRA; 154 break; 155 case 2: 156 mic |= MIC_CRB; 157 break; 158 } 159 uart_setmreg(bas, WR_MIC, mic); 160 uart_barrier(bas); 161 /* Set clock sources and enable BRG. */ 162 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 163 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 164 uart_barrier(bas); 165 /* Set data encoding. */ 166 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 167 uart_barrier(bas); 168 169 tpc = TPC_DTR | TPC_RTS; 170 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 171 return (int)tpc; 172 } 173 174 /* 175 * Low-level UART interface. 176 */ 177 static int z8530_probe(struct uart_bas *bas); 178 static void z8530_init(struct uart_bas *bas, int, int, int, int); 179 static void z8530_term(struct uart_bas *bas); 180 static void z8530_putc(struct uart_bas *bas, int); 181 static int z8530_poll(struct uart_bas *bas); 182 static int z8530_getc(struct uart_bas *bas); 183 184 struct uart_ops uart_z8530_ops = { 185 .probe = z8530_probe, 186 .init = z8530_init, 187 .term = z8530_term, 188 .putc = z8530_putc, 189 .poll = z8530_poll, 190 .getc = z8530_getc, 191 }; 192 193 static int 194 z8530_probe(struct uart_bas *bas) 195 { 196 197 return (0); 198 } 199 200 static void 201 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 202 int parity) 203 { 204 205 z8530_setup(bas, baudrate, databits, stopbits, parity); 206 } 207 208 static void 209 z8530_term(struct uart_bas *bas) 210 { 211 } 212 213 static void 214 z8530_putc(struct uart_bas *bas, int c) 215 { 216 217 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 218 ; 219 uart_setreg(bas, REG_DATA, c); 220 uart_barrier(bas); 221 } 222 223 static int 224 z8530_poll(struct uart_bas *bas) 225 { 226 227 if (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 228 return (-1); 229 return (uart_getreg(bas, REG_DATA)); 230 } 231 232 static int 233 z8530_getc(struct uart_bas *bas) 234 { 235 236 while (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 237 ; 238 return (uart_getreg(bas, REG_DATA)); 239 } 240 241 /* 242 * High-level UART interface. 243 */ 244 struct z8530_softc { 245 struct uart_softc base; 246 uint8_t tpc; 247 }; 248 249 static int z8530_bus_attach(struct uart_softc *); 250 static int z8530_bus_detach(struct uart_softc *); 251 static int z8530_bus_flush(struct uart_softc *, int); 252 static int z8530_bus_getsig(struct uart_softc *); 253 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 254 static int z8530_bus_ipend(struct uart_softc *); 255 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 256 static int z8530_bus_probe(struct uart_softc *); 257 static int z8530_bus_receive(struct uart_softc *); 258 static int z8530_bus_setsig(struct uart_softc *, int); 259 static int z8530_bus_transmit(struct uart_softc *); 260 261 static kobj_method_t z8530_methods[] = { 262 KOBJMETHOD(uart_attach, z8530_bus_attach), 263 KOBJMETHOD(uart_detach, z8530_bus_detach), 264 KOBJMETHOD(uart_flush, z8530_bus_flush), 265 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 266 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 267 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 268 KOBJMETHOD(uart_param, z8530_bus_param), 269 KOBJMETHOD(uart_probe, z8530_bus_probe), 270 KOBJMETHOD(uart_receive, z8530_bus_receive), 271 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 272 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 273 { 0, 0 } 274 }; 275 276 struct uart_class uart_z8530_class = { 277 "z8530 class", 278 z8530_methods, 279 sizeof(struct z8530_softc), 280 .uc_range = 2, 281 .uc_rclk = DEFAULT_RCLK 282 }; 283 284 #define SIGCHG(c, i, s, d) \ 285 if (c) { \ 286 i |= (i & s) ? s : s | d; \ 287 } else { \ 288 i = (i & s) ? (i & ~s) | d : i; \ 289 } 290 291 static int 292 z8530_bus_attach(struct uart_softc *sc) 293 { 294 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 295 struct uart_bas *bas; 296 struct uart_devinfo *di; 297 298 bas = &sc->sc_bas; 299 if (sc->sc_sysdev != NULL) { 300 di = sc->sc_sysdev; 301 z8530->tpc = TPC_DTR|TPC_RTS; 302 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 303 di->parity, &z8530->tpc); 304 } else { 305 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 306 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 307 } 308 309 sc->sc_rxfifosz = 3; 310 sc->sc_txfifosz = 1; 311 312 (void)z8530_bus_getsig(sc); 313 314 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 315 uart_barrier(bas); 316 uart_setmreg(bas, WR_IDT, IDT_TIE | IDT_RIA); 317 uart_barrier(bas); 318 uart_setmreg(bas, WR_IV, 0); 319 uart_barrier(bas); 320 uart_setmreg(bas, WR_TPC, z8530->tpc); 321 uart_barrier(bas); 322 return (0); 323 } 324 325 static int 326 z8530_bus_detach(struct uart_softc *sc) 327 { 328 329 return (0); 330 } 331 332 static int 333 z8530_bus_flush(struct uart_softc *sc, int what) 334 { 335 336 return (0); 337 } 338 339 static int 340 z8530_bus_getsig(struct uart_softc *sc) 341 { 342 uint32_t new, old, sig; 343 uint8_t bes; 344 345 do { 346 old = sc->sc_hwsig; 347 sig = old; 348 mtx_lock_spin(&sc->sc_hwmtx); 349 bes = uart_getmreg(&sc->sc_bas, RR_BES); 350 mtx_unlock_spin(&sc->sc_hwmtx); 351 SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS); 352 SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD); 353 new = sig & ~UART_SIGMASK_DELTA; 354 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 355 return (sig); 356 } 357 358 static int 359 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 360 { 361 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 362 struct uart_bas *bas; 363 int error; 364 365 bas = &sc->sc_bas; 366 error = 0; 367 mtx_lock_spin(&sc->sc_hwmtx); 368 switch (request) { 369 case UART_IOCTL_BREAK: 370 if (data) 371 z8530->tpc |= TPC_BRK; 372 else 373 z8530->tpc &= ~TPC_BRK; 374 uart_setmreg(bas, WR_TPC, z8530->tpc); 375 uart_barrier(bas); 376 break; 377 default: 378 error = EINVAL; 379 break; 380 } 381 mtx_unlock_spin(&sc->sc_hwmtx); 382 return (error); 383 } 384 385 static int 386 z8530_bus_ipend(struct uart_softc *sc) 387 { 388 struct uart_bas *bas; 389 int ipend; 390 uint32_t sig; 391 uint8_t bes, src; 392 393 bas = &sc->sc_bas; 394 ipend = 0; 395 mtx_lock_spin(&sc->sc_hwmtx); 396 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 397 uart_barrier(bas); 398 bes = uart_getmreg(bas, RR_BES); 399 if (bes & BES_BRK) { 400 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 401 ipend |= UART_IPEND_BREAK; 402 } 403 if (bes & BES_TXE) { 404 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 405 ipend |= UART_IPEND_TXIDLE; 406 } 407 if (bes & BES_RXA) 408 ipend |= UART_IPEND_RXREADY; 409 sig = sc->sc_hwsig; 410 SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS); 411 SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD); 412 if (sig & UART_SIGMASK_DELTA) 413 ipend |= UART_IPEND_SIGCHG; 414 src = uart_getmreg(bas, RR_SRC); 415 if (src & SRC_OVR) { 416 uart_setreg(bas, REG_CTRL, CR_RSTERR); 417 ipend |= UART_IPEND_OVERRUN; 418 } 419 mtx_unlock_spin(&sc->sc_hwmtx); 420 return (ipend); 421 } 422 423 static int 424 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 425 int stopbits, int parity) 426 { 427 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 428 int error; 429 430 mtx_lock_spin(&sc->sc_hwmtx); 431 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 432 &z8530->tpc); 433 mtx_unlock_spin(&sc->sc_hwmtx); 434 return (error); 435 } 436 437 static int 438 z8530_bus_probe(struct uart_softc *sc) 439 { 440 char buf[80]; 441 int error; 442 char ch; 443 444 error = z8530_probe(&sc->sc_bas); 445 if (error) 446 return (error); 447 448 ch = sc->sc_bas.chan - 1 + 'A'; 449 450 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 451 device_set_desc_copy(sc->sc_dev, buf); 452 return (0); 453 } 454 455 static int 456 z8530_bus_receive(struct uart_softc *sc) 457 { 458 struct uart_bas *bas; 459 int xc; 460 uint8_t bes, src; 461 462 bas = &sc->sc_bas; 463 mtx_lock_spin(&sc->sc_hwmtx); 464 bes = uart_getmreg(bas, RR_BES); 465 while (bes & BES_RXA) { 466 if (uart_rx_full(sc)) { 467 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 468 break; 469 } 470 src = uart_getmreg(bas, RR_SRC); 471 xc = uart_getreg(bas, REG_DATA); 472 if (src & SRC_FE) 473 xc |= UART_STAT_FRAMERR; 474 if (src & SRC_PE) 475 xc |= UART_STAT_PARERR; 476 uart_rx_put(sc, xc); 477 if (src & (SRC_FE | SRC_PE)) { 478 uart_setreg(bas, REG_CTRL, CR_RSTERR); 479 uart_barrier(bas); 480 } 481 bes = uart_getmreg(bas, RR_BES); 482 } 483 /* Discard everything left in the Rx FIFO. */ 484 while (bes & BES_RXA) { 485 src = uart_getmreg(bas, RR_SRC); 486 (void)uart_getreg(bas, REG_DATA); 487 if (src & (SRC_FE | SRC_PE)) { 488 uart_setreg(bas, REG_CTRL, CR_RSTERR); 489 uart_barrier(bas); 490 } 491 bes = uart_getmreg(bas, RR_BES); 492 } 493 mtx_unlock_spin(&sc->sc_hwmtx); 494 return (0); 495 } 496 497 static int 498 z8530_bus_setsig(struct uart_softc *sc, int sig) 499 { 500 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 501 struct uart_bas *bas; 502 uint32_t new, old; 503 504 bas = &sc->sc_bas; 505 do { 506 old = sc->sc_hwsig; 507 new = old; 508 if (sig & UART_SIG_DDTR) { 509 SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR, 510 UART_SIG_DDTR); 511 } 512 if (sig & UART_SIG_DRTS) { 513 SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS, 514 UART_SIG_DRTS); 515 } 516 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 517 518 mtx_lock_spin(&sc->sc_hwmtx); 519 if (new & UART_SIG_DTR) 520 z8530->tpc |= TPC_DTR; 521 else 522 z8530->tpc &= ~TPC_DTR; 523 if (new & UART_SIG_RTS) 524 z8530->tpc |= TPC_RTS; 525 else 526 z8530->tpc &= ~TPC_RTS; 527 uart_setmreg(bas, WR_TPC, z8530->tpc); 528 uart_barrier(bas); 529 mtx_unlock_spin(&sc->sc_hwmtx); 530 return (0); 531 } 532 533 static int 534 z8530_bus_transmit(struct uart_softc *sc) 535 { 536 struct uart_bas *bas; 537 538 bas = &sc->sc_bas; 539 mtx_lock_spin(&sc->sc_hwmtx); 540 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 541 ; 542 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 543 uart_barrier(bas); 544 sc->sc_txbusy = 1; 545 mtx_unlock_spin(&sc->sc_hwmtx); 546 return (0); 547 } 548