1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/z8530.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 307200 45 46 /* Multiplexed I/O. */ 47 static __inline void 48 uart_setmreg(struct uart_bas *bas, int reg, int val) 49 { 50 51 uart_setreg(bas, REG_CTRL, reg); 52 uart_barrier(bas); 53 uart_setreg(bas, REG_CTRL, val); 54 } 55 56 static __inline uint8_t 57 uart_getmreg(struct uart_bas *bas, int reg) 58 { 59 60 uart_setreg(bas, REG_CTRL, reg); 61 uart_barrier(bas); 62 return (uart_getreg(bas, REG_CTRL)); 63 } 64 65 static int 66 z8530_divisor(int rclk, int baudrate) 67 { 68 int act_baud, divisor, error; 69 70 if (baudrate == 0) 71 return (-1); 72 73 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 74 if (divisor < 0 || divisor >= 65536) 75 return (-1); 76 act_baud = rclk / 2 / (divisor + 2); 77 78 /* 10 times error in percent: */ 79 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 80 81 /* 3.0% maximum error tolerance: */ 82 if (error < -30 || error > 30) 83 return (-1); 84 85 return (divisor); 86 } 87 88 static int 89 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 90 int parity, uint8_t *tpcp) 91 { 92 int divisor; 93 uint8_t mpm, rpc, tpc; 94 95 rpc = RPC_RXE; 96 mpm = MPM_CM16; 97 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 98 99 if (databits >= 8) { 100 rpc |= RPC_RB8; 101 tpc |= TPC_TB8; 102 } else if (databits == 7) { 103 rpc |= RPC_RB7; 104 tpc |= TPC_TB7; 105 } else if (databits == 6) { 106 rpc |= RPC_RB6; 107 tpc |= TPC_TB6; 108 } else { 109 rpc |= RPC_RB5; 110 tpc |= TPC_TB5; 111 } 112 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 113 switch (parity) { 114 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 115 case UART_PARITY_NONE: break; 116 case UART_PARITY_ODD: mpm |= MPM_PE; break; 117 default: return (EINVAL); 118 } 119 120 if (baudrate > 0) { 121 divisor = z8530_divisor(bas->rclk, baudrate); 122 if (divisor == -1) 123 return (EINVAL); 124 } else 125 divisor = -1; 126 127 uart_setmreg(bas, WR_MCB2, MCB2_PCLK); 128 uart_barrier(bas); 129 130 if (divisor >= 0) { 131 uart_setmreg(bas, WR_TCL, divisor & 0xff); 132 uart_barrier(bas); 133 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 134 uart_barrier(bas); 135 } 136 137 uart_setmreg(bas, WR_RPC, rpc); 138 uart_barrier(bas); 139 uart_setmreg(bas, WR_MPM, mpm); 140 uart_barrier(bas); 141 uart_setmreg(bas, WR_TPC, tpc); 142 uart_barrier(bas); 143 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 144 uart_barrier(bas); 145 *tpcp = tpc; 146 return (0); 147 } 148 149 static int 150 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 151 int parity) 152 { 153 uint8_t tpc; 154 155 if (bas->rclk == 0) 156 bas->rclk = DEFAULT_RCLK; 157 158 /* Assume we don't need to perform a full hardware reset. */ 159 switch (bas->chan) { 160 case 1: 161 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); 162 break; 163 case 2: 164 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); 165 break; 166 } 167 uart_barrier(bas); 168 /* Set clock sources. */ 169 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 170 uart_setmreg(bas, WR_MCB2, MCB2_PCLK); 171 uart_barrier(bas); 172 /* Set data encoding. */ 173 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 174 uart_barrier(bas); 175 176 tpc = TPC_DTR | TPC_RTS; 177 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 178 return (int)tpc; 179 } 180 181 /* 182 * Low-level UART interface. 183 */ 184 static int z8530_probe(struct uart_bas *bas); 185 static void z8530_init(struct uart_bas *bas, int, int, int, int); 186 static void z8530_term(struct uart_bas *bas); 187 static void z8530_putc(struct uart_bas *bas, int); 188 static int z8530_poll(struct uart_bas *bas); 189 static int z8530_getc(struct uart_bas *bas, struct mtx *); 190 191 struct uart_ops uart_z8530_ops = { 192 .probe = z8530_probe, 193 .init = z8530_init, 194 .term = z8530_term, 195 .putc = z8530_putc, 196 .poll = z8530_poll, 197 .getc = z8530_getc, 198 }; 199 200 static int 201 z8530_probe(struct uart_bas *bas) 202 { 203 204 return (0); 205 } 206 207 static void 208 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 209 int parity) 210 { 211 212 z8530_setup(bas, baudrate, databits, stopbits, parity); 213 } 214 215 static void 216 z8530_term(struct uart_bas *bas) 217 { 218 } 219 220 static void 221 z8530_putc(struct uart_bas *bas, int c) 222 { 223 224 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) 225 ; 226 uart_setreg(bas, REG_DATA, c); 227 uart_barrier(bas); 228 } 229 230 static int 231 z8530_poll(struct uart_bas *bas) 232 { 233 234 if (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) 235 return (-1); 236 return (uart_getreg(bas, REG_DATA)); 237 } 238 239 static int 240 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx) 241 { 242 int c; 243 244 uart_lock(hwmtx); 245 246 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { 247 uart_unlock(hwmtx); 248 DELAY(10); 249 uart_lock(hwmtx); 250 } 251 252 c = uart_getreg(bas, REG_DATA); 253 254 uart_unlock(hwmtx); 255 256 return (c); 257 } 258 259 /* 260 * High-level UART interface. 261 */ 262 struct z8530_softc { 263 struct uart_softc base; 264 uint8_t tpc; 265 uint8_t txidle; 266 }; 267 268 static int z8530_bus_attach(struct uart_softc *); 269 static int z8530_bus_detach(struct uart_softc *); 270 static int z8530_bus_flush(struct uart_softc *, int); 271 static int z8530_bus_getsig(struct uart_softc *); 272 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 273 static int z8530_bus_ipend(struct uart_softc *); 274 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 275 static int z8530_bus_probe(struct uart_softc *); 276 static int z8530_bus_receive(struct uart_softc *); 277 static int z8530_bus_setsig(struct uart_softc *, int); 278 static int z8530_bus_transmit(struct uart_softc *); 279 280 static kobj_method_t z8530_methods[] = { 281 KOBJMETHOD(uart_attach, z8530_bus_attach), 282 KOBJMETHOD(uart_detach, z8530_bus_detach), 283 KOBJMETHOD(uart_flush, z8530_bus_flush), 284 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 285 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 286 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 287 KOBJMETHOD(uart_param, z8530_bus_param), 288 KOBJMETHOD(uart_probe, z8530_bus_probe), 289 KOBJMETHOD(uart_receive, z8530_bus_receive), 290 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 291 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 292 { 0, 0 } 293 }; 294 295 struct uart_class uart_z8530_class = { 296 "z8530 class", 297 z8530_methods, 298 sizeof(struct z8530_softc), 299 .uc_range = 2, 300 .uc_rclk = DEFAULT_RCLK 301 }; 302 303 #define SIGCHG(c, i, s, d) \ 304 if (c) { \ 305 i |= (i & s) ? s : s | d; \ 306 } else { \ 307 i = (i & s) ? (i & ~s) | d : i; \ 308 } 309 310 static int 311 z8530_bus_attach(struct uart_softc *sc) 312 { 313 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 314 struct uart_bas *bas; 315 struct uart_devinfo *di; 316 317 bas = &sc->sc_bas; 318 if (sc->sc_sysdev != NULL) { 319 di = sc->sc_sysdev; 320 z8530->tpc = TPC_DTR|TPC_RTS; 321 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 322 di->parity, &z8530->tpc); 323 } else { 324 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 325 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 326 } 327 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */ 328 329 sc->sc_rxfifosz = 3; 330 sc->sc_txfifosz = 1; 331 332 (void)z8530_bus_getsig(sc); 333 334 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 335 uart_barrier(bas); 336 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 337 uart_barrier(bas); 338 uart_setmreg(bas, WR_IV, 0); 339 uart_barrier(bas); 340 uart_setmreg(bas, WR_TPC, z8530->tpc); 341 uart_barrier(bas); 342 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); 343 uart_barrier(bas); 344 return (0); 345 } 346 347 static int 348 z8530_bus_detach(struct uart_softc *sc) 349 { 350 351 return (0); 352 } 353 354 static int 355 z8530_bus_flush(struct uart_softc *sc, int what) 356 { 357 358 return (0); 359 } 360 361 static int 362 z8530_bus_getsig(struct uart_softc *sc) 363 { 364 uint32_t new, old, sig; 365 uint8_t bes; 366 367 do { 368 old = sc->sc_hwsig; 369 sig = old; 370 uart_lock(sc->sc_hwmtx); 371 bes = uart_getmreg(&sc->sc_bas, RR_BES); 372 uart_unlock(sc->sc_hwmtx); 373 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 374 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 375 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 376 new = sig & ~SER_MASK_DELTA; 377 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 378 return (sig); 379 } 380 381 static int 382 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 383 { 384 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 385 struct uart_bas *bas; 386 int error; 387 388 bas = &sc->sc_bas; 389 error = 0; 390 uart_lock(sc->sc_hwmtx); 391 switch (request) { 392 case UART_IOCTL_BREAK: 393 if (data) 394 z8530->tpc |= TPC_BRK; 395 else 396 z8530->tpc &= ~TPC_BRK; 397 uart_setmreg(bas, WR_TPC, z8530->tpc); 398 uart_barrier(bas); 399 break; 400 default: 401 error = EINVAL; 402 break; 403 } 404 uart_unlock(sc->sc_hwmtx); 405 return (error); 406 } 407 408 static int 409 z8530_bus_ipend(struct uart_softc *sc) 410 { 411 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 412 struct uart_bas *bas; 413 int ipend; 414 uint32_t sig; 415 uint8_t bes, ip, iv, src; 416 417 bas = &sc->sc_bas; 418 ipend = 0; 419 420 uart_lock(sc->sc_hwmtx); 421 switch (bas->chan) { 422 case 1: 423 ip = uart_getmreg(bas, RR_IP); 424 break; 425 case 2: /* XXX hack!!! */ 426 iv = uart_getmreg(bas, RR_IV) & 0x0E; 427 switch (iv) { 428 case IV_TEB: ip = IP_TIA; break; 429 case IV_XSB: ip = IP_SIA; break; 430 case IV_RAB: ip = IP_RIA; break; 431 default: ip = 0; break; 432 } 433 break; 434 default: 435 ip = 0; 436 break; 437 } 438 439 if (ip & IP_RIA) 440 ipend |= SER_INT_RXREADY; 441 442 if (ip & IP_TIA) { 443 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 444 uart_barrier(bas); 445 if (z8530->txidle) { 446 ipend |= SER_INT_TXIDLE; 447 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */ 448 } 449 } 450 451 if (ip & IP_SIA) { 452 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 453 uart_barrier(bas); 454 bes = uart_getmreg(bas, RR_BES); 455 if (bes & BES_BRK) 456 ipend |= SER_INT_BREAK; 457 sig = sc->sc_hwsig; 458 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 459 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 460 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 461 if (sig & SER_MASK_DELTA) 462 ipend |= SER_INT_SIGCHG; 463 src = uart_getmreg(bas, RR_SRC); 464 if (src & SRC_OVR) { 465 uart_setreg(bas, REG_CTRL, CR_RSTERR); 466 uart_barrier(bas); 467 ipend |= SER_INT_OVERRUN; 468 } 469 } 470 471 if (ipend) { 472 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 473 uart_barrier(bas); 474 } 475 476 uart_unlock(sc->sc_hwmtx); 477 478 return (ipend); 479 } 480 481 static int 482 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 483 int stopbits, int parity) 484 { 485 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 486 int error; 487 488 uart_lock(sc->sc_hwmtx); 489 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 490 &z8530->tpc); 491 uart_unlock(sc->sc_hwmtx); 492 return (error); 493 } 494 495 static int 496 z8530_bus_probe(struct uart_softc *sc) 497 { 498 char buf[80]; 499 int error; 500 char ch; 501 502 error = z8530_probe(&sc->sc_bas); 503 if (error) 504 return (error); 505 506 ch = sc->sc_bas.chan - 1 + 'A'; 507 508 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 509 device_set_desc_copy(sc->sc_dev, buf); 510 return (0); 511 } 512 513 static int 514 z8530_bus_receive(struct uart_softc *sc) 515 { 516 struct uart_bas *bas; 517 int xc; 518 uint8_t bes, src; 519 520 bas = &sc->sc_bas; 521 uart_lock(sc->sc_hwmtx); 522 bes = uart_getmreg(bas, RR_BES); 523 while (bes & BES_RXA) { 524 if (uart_rx_full(sc)) { 525 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 526 break; 527 } 528 xc = uart_getreg(bas, REG_DATA); 529 uart_barrier(bas); 530 src = uart_getmreg(bas, RR_SRC); 531 if (src & SRC_FE) 532 xc |= UART_STAT_FRAMERR; 533 if (src & SRC_PE) 534 xc |= UART_STAT_PARERR; 535 if (src & SRC_OVR) 536 xc |= UART_STAT_OVERRUN; 537 uart_rx_put(sc, xc); 538 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 539 uart_setreg(bas, REG_CTRL, CR_RSTERR); 540 uart_barrier(bas); 541 } 542 bes = uart_getmreg(bas, RR_BES); 543 } 544 /* Discard everything left in the Rx FIFO. */ 545 while (bes & BES_RXA) { 546 (void)uart_getreg(bas, REG_DATA); 547 uart_barrier(bas); 548 src = uart_getmreg(bas, RR_SRC); 549 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 550 uart_setreg(bas, REG_CTRL, CR_RSTERR); 551 uart_barrier(bas); 552 } 553 bes = uart_getmreg(bas, RR_BES); 554 } 555 uart_unlock(sc->sc_hwmtx); 556 return (0); 557 } 558 559 static int 560 z8530_bus_setsig(struct uart_softc *sc, int sig) 561 { 562 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 563 struct uart_bas *bas; 564 uint32_t new, old; 565 566 bas = &sc->sc_bas; 567 do { 568 old = sc->sc_hwsig; 569 new = old; 570 if (sig & SER_DDTR) { 571 SIGCHG(sig & SER_DTR, new, SER_DTR, 572 SER_DDTR); 573 } 574 if (sig & SER_DRTS) { 575 SIGCHG(sig & SER_RTS, new, SER_RTS, 576 SER_DRTS); 577 } 578 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 579 580 uart_lock(sc->sc_hwmtx); 581 if (new & SER_DTR) 582 z8530->tpc |= TPC_DTR; 583 else 584 z8530->tpc &= ~TPC_DTR; 585 if (new & SER_RTS) 586 z8530->tpc |= TPC_RTS; 587 else 588 z8530->tpc &= ~TPC_RTS; 589 uart_setmreg(bas, WR_TPC, z8530->tpc); 590 uart_barrier(bas); 591 uart_unlock(sc->sc_hwmtx); 592 return (0); 593 } 594 595 static int 596 z8530_bus_transmit(struct uart_softc *sc) 597 { 598 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 599 struct uart_bas *bas; 600 601 bas = &sc->sc_bas; 602 uart_lock(sc->sc_hwmtx); 603 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 604 ; 605 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 606 uart_barrier(bas); 607 sc->sc_txbusy = 1; 608 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ 609 uart_unlock(sc->sc_hwmtx); 610 return (0); 611 } 612