1 /* 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 #include <dev/uart/uart_dev_z8530.h> 40 41 #include "uart_if.h" 42 43 #define DEFAULT_RCLK 307200 44 45 /* Multiplexed I/O. */ 46 static __inline void 47 uart_setmreg(struct uart_bas *bas, int reg, int val) 48 { 49 50 uart_setreg(bas, REG_CTRL, reg); 51 uart_barrier(bas); 52 uart_setreg(bas, REG_CTRL, val); 53 } 54 55 static __inline uint8_t 56 uart_getmreg(struct uart_bas *bas, int reg) 57 { 58 59 uart_setreg(bas, REG_CTRL, reg); 60 uart_barrier(bas); 61 return (uart_getreg(bas, REG_CTRL)); 62 } 63 64 static int 65 z8530_divisor(int rclk, int baudrate) 66 { 67 int act_baud, divisor, error; 68 69 if (baudrate == 0) 70 return (0); 71 72 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 73 if (divisor >= 65536) 74 return (0); 75 act_baud = rclk / 2 / (divisor + 2); 76 77 /* 10 times error in percent: */ 78 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 79 80 /* 3.0% maximum error tolerance: */ 81 if (error < -30 || error > 30) 82 return (0); 83 84 return (divisor); 85 } 86 87 static int 88 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 89 int parity, uint8_t *tpcp) 90 { 91 int divisor; 92 uint8_t mpm, rpc, tpc; 93 94 rpc = RPC_RXE; 95 mpm = MPM_CM16; 96 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 97 98 if (databits >= 8) { 99 rpc |= RPC_RB8; 100 tpc |= TPC_TB8; 101 } else if (databits == 7) { 102 rpc |= RPC_RB7; 103 tpc |= TPC_TB7; 104 } else if (databits == 6) { 105 rpc |= RPC_RB6; 106 tpc |= TPC_TB6; 107 } else { 108 rpc |= RPC_RB5; 109 tpc |= TPC_TB5; 110 } 111 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 112 switch (parity) { 113 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 114 case UART_PARITY_NONE: break; 115 case UART_PARITY_ODD: mpm |= MPM_PE; break; 116 default: return (EINVAL); 117 } 118 119 /* Set baudrate. */ 120 if (baudrate > 0) { 121 divisor = z8530_divisor(bas->rclk, baudrate); 122 if (divisor == 0) 123 return (EINVAL); 124 uart_setmreg(bas, WR_TCL, divisor & 0xff); 125 uart_barrier(bas); 126 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 127 uart_barrier(bas); 128 } 129 130 uart_setmreg(bas, WR_RPC, rpc); 131 uart_barrier(bas); 132 uart_setmreg(bas, WR_MPM, mpm); 133 uart_barrier(bas); 134 uart_setmreg(bas, WR_TPC, tpc); 135 uart_barrier(bas); 136 *tpcp = tpc; 137 return (0); 138 } 139 140 static int 141 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 142 int parity) 143 { 144 uint8_t mic, tpc; 145 146 if (bas->rclk == 0) 147 bas->rclk = DEFAULT_RCLK; 148 149 /* Assume we don't need to perform a full hardware reset. */ 150 mic = MIC_MIE | MIC_NV; 151 switch (bas->chan) { 152 case 1: 153 mic |= MIC_CRA; 154 break; 155 case 2: 156 mic |= MIC_CRB; 157 break; 158 } 159 uart_setmreg(bas, WR_MIC, mic); 160 uart_barrier(bas); 161 /* Set clock sources and enable BRG. */ 162 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 163 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 164 uart_barrier(bas); 165 /* Set data encoding. */ 166 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 167 uart_barrier(bas); 168 169 tpc = TPC_DTR | TPC_RTS; 170 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 171 return (int)tpc; 172 } 173 174 /* 175 * Low-level UART interface. 176 */ 177 static int z8530_probe(struct uart_bas *bas); 178 static void z8530_init(struct uart_bas *bas, int, int, int, int); 179 static void z8530_term(struct uart_bas *bas); 180 static void z8530_putc(struct uart_bas *bas, int); 181 static int z8530_poll(struct uart_bas *bas); 182 static int z8530_getc(struct uart_bas *bas); 183 184 struct uart_ops uart_z8530_ops = { 185 .probe = z8530_probe, 186 .init = z8530_init, 187 .term = z8530_term, 188 .putc = z8530_putc, 189 .poll = z8530_poll, 190 .getc = z8530_getc, 191 }; 192 193 static int 194 z8530_probe(struct uart_bas *bas) 195 { 196 197 return (0); 198 } 199 200 static void 201 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 202 int parity) 203 { 204 205 z8530_setup(bas, baudrate, databits, stopbits, parity); 206 } 207 208 static void 209 z8530_term(struct uart_bas *bas) 210 { 211 } 212 213 static void 214 z8530_putc(struct uart_bas *bas, int c) 215 { 216 217 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 218 ; 219 uart_setreg(bas, REG_DATA, c); 220 uart_barrier(bas); 221 } 222 223 static int 224 z8530_poll(struct uart_bas *bas) 225 { 226 227 if (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 228 return (-1); 229 return (uart_getreg(bas, REG_DATA)); 230 } 231 232 static int 233 z8530_getc(struct uart_bas *bas) 234 { 235 236 while (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 237 ; 238 return (uart_getreg(bas, REG_DATA)); 239 } 240 241 /* 242 * High-level UART interface. 243 */ 244 struct z8530_softc { 245 struct uart_softc base; 246 uint8_t tpc; 247 uint8_t txidle; 248 }; 249 250 static int z8530_bus_attach(struct uart_softc *); 251 static int z8530_bus_detach(struct uart_softc *); 252 static int z8530_bus_flush(struct uart_softc *, int); 253 static int z8530_bus_getsig(struct uart_softc *); 254 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 255 static int z8530_bus_ipend(struct uart_softc *); 256 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 257 static int z8530_bus_probe(struct uart_softc *); 258 static int z8530_bus_receive(struct uart_softc *); 259 static int z8530_bus_setsig(struct uart_softc *, int); 260 static int z8530_bus_transmit(struct uart_softc *); 261 262 static kobj_method_t z8530_methods[] = { 263 KOBJMETHOD(uart_attach, z8530_bus_attach), 264 KOBJMETHOD(uart_detach, z8530_bus_detach), 265 KOBJMETHOD(uart_flush, z8530_bus_flush), 266 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 267 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 268 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 269 KOBJMETHOD(uart_param, z8530_bus_param), 270 KOBJMETHOD(uart_probe, z8530_bus_probe), 271 KOBJMETHOD(uart_receive, z8530_bus_receive), 272 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 273 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 274 { 0, 0 } 275 }; 276 277 struct uart_class uart_z8530_class = { 278 "z8530 class", 279 z8530_methods, 280 sizeof(struct z8530_softc), 281 .uc_range = 2, 282 .uc_rclk = DEFAULT_RCLK 283 }; 284 285 #define SIGCHG(c, i, s, d) \ 286 if (c) { \ 287 i |= (i & s) ? s : s | d; \ 288 } else { \ 289 i = (i & s) ? (i & ~s) | d : i; \ 290 } 291 292 static int 293 z8530_bus_attach(struct uart_softc *sc) 294 { 295 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 296 struct uart_bas *bas; 297 struct uart_devinfo *di; 298 299 bas = &sc->sc_bas; 300 if (sc->sc_sysdev != NULL) { 301 di = sc->sc_sysdev; 302 z8530->tpc = TPC_DTR|TPC_RTS; 303 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 304 di->parity, &z8530->tpc); 305 } else { 306 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 307 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 308 } 309 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE. */ 310 311 sc->sc_rxfifosz = 3; 312 sc->sc_txfifosz = 1; 313 314 (void)z8530_bus_getsig(sc); 315 316 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 317 uart_barrier(bas); 318 uart_setmreg(bas, WR_IDT, IDT_TIE | IDT_RIA); 319 uart_barrier(bas); 320 uart_setmreg(bas, WR_IV, 0); 321 uart_barrier(bas); 322 uart_setmreg(bas, WR_TPC, z8530->tpc); 323 uart_barrier(bas); 324 return (0); 325 } 326 327 static int 328 z8530_bus_detach(struct uart_softc *sc) 329 { 330 331 return (0); 332 } 333 334 static int 335 z8530_bus_flush(struct uart_softc *sc, int what) 336 { 337 338 return (0); 339 } 340 341 static int 342 z8530_bus_getsig(struct uart_softc *sc) 343 { 344 uint32_t new, old, sig; 345 uint8_t bes; 346 347 do { 348 old = sc->sc_hwsig; 349 sig = old; 350 mtx_lock_spin(&sc->sc_hwmtx); 351 bes = uart_getmreg(&sc->sc_bas, RR_BES); 352 mtx_unlock_spin(&sc->sc_hwmtx); 353 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 354 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 355 new = sig & ~UART_SIGMASK_DELTA; 356 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 357 return (sig); 358 } 359 360 static int 361 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 362 { 363 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 364 struct uart_bas *bas; 365 int error; 366 367 bas = &sc->sc_bas; 368 error = 0; 369 mtx_lock_spin(&sc->sc_hwmtx); 370 switch (request) { 371 case UART_IOCTL_BREAK: 372 if (data) 373 z8530->tpc |= TPC_BRK; 374 else 375 z8530->tpc &= ~TPC_BRK; 376 uart_setmreg(bas, WR_TPC, z8530->tpc); 377 uart_barrier(bas); 378 break; 379 default: 380 error = EINVAL; 381 break; 382 } 383 mtx_unlock_spin(&sc->sc_hwmtx); 384 return (error); 385 } 386 387 static int 388 z8530_bus_ipend(struct uart_softc *sc) 389 { 390 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 391 struct uart_bas *bas; 392 int ipend; 393 uint32_t sig; 394 uint8_t bes, src; 395 396 bas = &sc->sc_bas; 397 ipend = 0; 398 mtx_lock_spin(&sc->sc_hwmtx); 399 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 400 uart_barrier(bas); 401 bes = uart_getmreg(bas, RR_BES); 402 if (bes & BES_BRK) { 403 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 404 ipend |= UART_IPEND_BREAK; 405 } 406 if (bes & BES_TXE && z8530->txidle) { 407 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 408 ipend |= UART_IPEND_TXIDLE; 409 z8530->txidle = 0; /* Suppress UART_IPEND_TXIDLE. */ 410 } 411 if (bes & BES_RXA) 412 ipend |= UART_IPEND_RXREADY; 413 sig = sc->sc_hwsig; 414 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 415 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 416 if (sig & UART_SIGMASK_DELTA) 417 ipend |= UART_IPEND_SIGCHG; 418 src = uart_getmreg(bas, RR_SRC); 419 if (src & SRC_OVR) { 420 uart_setreg(bas, REG_CTRL, CR_RSTERR); 421 ipend |= UART_IPEND_OVERRUN; 422 } 423 mtx_unlock_spin(&sc->sc_hwmtx); 424 return (ipend); 425 } 426 427 static int 428 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 429 int stopbits, int parity) 430 { 431 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 432 int error; 433 434 mtx_lock_spin(&sc->sc_hwmtx); 435 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 436 &z8530->tpc); 437 mtx_unlock_spin(&sc->sc_hwmtx); 438 return (error); 439 } 440 441 static int 442 z8530_bus_probe(struct uart_softc *sc) 443 { 444 char buf[80]; 445 int error; 446 char ch; 447 448 error = z8530_probe(&sc->sc_bas); 449 if (error) 450 return (error); 451 452 ch = sc->sc_bas.chan - 1 + 'A'; 453 454 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 455 device_set_desc_copy(sc->sc_dev, buf); 456 return (0); 457 } 458 459 static int 460 z8530_bus_receive(struct uart_softc *sc) 461 { 462 struct uart_bas *bas; 463 int xc; 464 uint8_t bes, src; 465 466 bas = &sc->sc_bas; 467 mtx_lock_spin(&sc->sc_hwmtx); 468 bes = uart_getmreg(bas, RR_BES); 469 while (bes & BES_RXA) { 470 if (uart_rx_full(sc)) { 471 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 472 break; 473 } 474 src = uart_getmreg(bas, RR_SRC); 475 xc = uart_getreg(bas, REG_DATA); 476 if (src & SRC_FE) 477 xc |= UART_STAT_FRAMERR; 478 if (src & SRC_PE) 479 xc |= UART_STAT_PARERR; 480 uart_rx_put(sc, xc); 481 if (src & (SRC_FE | SRC_PE)) { 482 uart_setreg(bas, REG_CTRL, CR_RSTERR); 483 uart_barrier(bas); 484 } 485 bes = uart_getmreg(bas, RR_BES); 486 } 487 /* Discard everything left in the Rx FIFO. */ 488 while (bes & BES_RXA) { 489 src = uart_getmreg(bas, RR_SRC); 490 (void)uart_getreg(bas, REG_DATA); 491 if (src & (SRC_FE | SRC_PE)) { 492 uart_setreg(bas, REG_CTRL, CR_RSTERR); 493 uart_barrier(bas); 494 } 495 bes = uart_getmreg(bas, RR_BES); 496 } 497 mtx_unlock_spin(&sc->sc_hwmtx); 498 return (0); 499 } 500 501 static int 502 z8530_bus_setsig(struct uart_softc *sc, int sig) 503 { 504 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 505 struct uart_bas *bas; 506 uint32_t new, old; 507 508 bas = &sc->sc_bas; 509 do { 510 old = sc->sc_hwsig; 511 new = old; 512 if (sig & SER_DDTR) { 513 SIGCHG(sig & SER_DTR, new, SER_DTR, 514 SER_DDTR); 515 } 516 if (sig & SER_DRTS) { 517 SIGCHG(sig & SER_RTS, new, SER_RTS, 518 SER_DRTS); 519 } 520 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 521 522 mtx_lock_spin(&sc->sc_hwmtx); 523 if (new & SER_DTR) 524 z8530->tpc |= TPC_DTR; 525 else 526 z8530->tpc &= ~TPC_DTR; 527 if (new & SER_RTS) 528 z8530->tpc |= TPC_RTS; 529 else 530 z8530->tpc &= ~TPC_RTS; 531 uart_setmreg(bas, WR_TPC, z8530->tpc); 532 uart_barrier(bas); 533 mtx_unlock_spin(&sc->sc_hwmtx); 534 return (0); 535 } 536 537 static int 538 z8530_bus_transmit(struct uart_softc *sc) 539 { 540 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 541 struct uart_bas *bas; 542 543 bas = &sc->sc_bas; 544 mtx_lock_spin(&sc->sc_hwmtx); 545 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 546 ; 547 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 548 uart_barrier(bas); 549 sc->sc_txbusy = 1; 550 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE again. */ 551 mtx_unlock_spin(&sc->sc_hwmtx); 552 return (0); 553 } 554