1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/z8530.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 307200 45 46 /* Multiplexed I/O. */ 47 static __inline void 48 uart_setmreg(struct uart_bas *bas, int reg, int val) 49 { 50 51 uart_setreg(bas, REG_CTRL, reg); 52 uart_barrier(bas); 53 uart_setreg(bas, REG_CTRL, val); 54 } 55 56 static __inline uint8_t 57 uart_getmreg(struct uart_bas *bas, int reg) 58 { 59 60 uart_setreg(bas, REG_CTRL, reg); 61 uart_barrier(bas); 62 return (uart_getreg(bas, REG_CTRL)); 63 } 64 65 static int 66 z8530_divisor(int rclk, int baudrate) 67 { 68 int act_baud, divisor, error; 69 70 if (baudrate == 0) 71 return (0); 72 73 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 74 if (divisor >= 65536) 75 return (0); 76 act_baud = rclk / 2 / (divisor + 2); 77 78 /* 10 times error in percent: */ 79 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 80 81 /* 3.0% maximum error tolerance: */ 82 if (error < -30 || error > 30) 83 return (0); 84 85 return (divisor); 86 } 87 88 static int 89 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 90 int parity, uint8_t *tpcp) 91 { 92 int divisor; 93 uint8_t mpm, rpc, tpc; 94 95 rpc = RPC_RXE; 96 mpm = MPM_CM16; 97 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 98 99 if (databits >= 8) { 100 rpc |= RPC_RB8; 101 tpc |= TPC_TB8; 102 } else if (databits == 7) { 103 rpc |= RPC_RB7; 104 tpc |= TPC_TB7; 105 } else if (databits == 6) { 106 rpc |= RPC_RB6; 107 tpc |= TPC_TB6; 108 } else { 109 rpc |= RPC_RB5; 110 tpc |= TPC_TB5; 111 } 112 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 113 switch (parity) { 114 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 115 case UART_PARITY_NONE: break; 116 case UART_PARITY_ODD: mpm |= MPM_PE; break; 117 default: return (EINVAL); 118 } 119 120 /* Set baudrate. */ 121 if (baudrate > 0) { 122 divisor = z8530_divisor(bas->rclk, baudrate); 123 if (divisor == 0) 124 return (EINVAL); 125 uart_setmreg(bas, WR_TCL, divisor & 0xff); 126 uart_barrier(bas); 127 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 128 uart_barrier(bas); 129 } 130 131 uart_setmreg(bas, WR_RPC, rpc); 132 uart_barrier(bas); 133 uart_setmreg(bas, WR_MPM, mpm); 134 uart_barrier(bas); 135 uart_setmreg(bas, WR_TPC, tpc); 136 uart_barrier(bas); 137 *tpcp = tpc; 138 return (0); 139 } 140 141 static int 142 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 143 int parity) 144 { 145 uint8_t tpc; 146 147 if (bas->rclk == 0) 148 bas->rclk = DEFAULT_RCLK; 149 150 /* Assume we don't need to perform a full hardware reset. */ 151 switch (bas->chan) { 152 case 1: 153 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); 154 break; 155 case 2: 156 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); 157 break; 158 } 159 uart_barrier(bas); 160 /* Set clock sources and enable BRG. */ 161 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 162 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 163 uart_barrier(bas); 164 /* Set data encoding. */ 165 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 166 uart_barrier(bas); 167 168 tpc = TPC_DTR | TPC_RTS; 169 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 170 return (int)tpc; 171 } 172 173 /* 174 * Low-level UART interface. 175 */ 176 static int z8530_probe(struct uart_bas *bas); 177 static void z8530_init(struct uart_bas *bas, int, int, int, int); 178 static void z8530_term(struct uart_bas *bas); 179 static void z8530_putc(struct uart_bas *bas, int); 180 static int z8530_poll(struct uart_bas *bas); 181 static int z8530_getc(struct uart_bas *bas); 182 183 struct uart_ops uart_z8530_ops = { 184 .probe = z8530_probe, 185 .init = z8530_init, 186 .term = z8530_term, 187 .putc = z8530_putc, 188 .poll = z8530_poll, 189 .getc = z8530_getc, 190 }; 191 192 static int 193 z8530_probe(struct uart_bas *bas) 194 { 195 196 return (0); 197 } 198 199 static void 200 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 201 int parity) 202 { 203 204 z8530_setup(bas, baudrate, databits, stopbits, parity); 205 } 206 207 static void 208 z8530_term(struct uart_bas *bas) 209 { 210 } 211 212 static void 213 z8530_putc(struct uart_bas *bas, int c) 214 { 215 216 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 217 ; 218 uart_setreg(bas, REG_DATA, c); 219 uart_barrier(bas); 220 } 221 222 static int 223 z8530_poll(struct uart_bas *bas) 224 { 225 226 if (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 227 return (-1); 228 return (uart_getreg(bas, REG_DATA)); 229 } 230 231 static int 232 z8530_getc(struct uart_bas *bas) 233 { 234 235 while (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 236 ; 237 return (uart_getreg(bas, REG_DATA)); 238 } 239 240 /* 241 * High-level UART interface. 242 */ 243 struct z8530_softc { 244 struct uart_softc base; 245 uint8_t tpc; 246 uint8_t txidle; 247 }; 248 249 static int z8530_bus_attach(struct uart_softc *); 250 static int z8530_bus_detach(struct uart_softc *); 251 static int z8530_bus_flush(struct uart_softc *, int); 252 static int z8530_bus_getsig(struct uart_softc *); 253 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 254 static int z8530_bus_ipend(struct uart_softc *); 255 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 256 static int z8530_bus_probe(struct uart_softc *); 257 static int z8530_bus_receive(struct uart_softc *); 258 static int z8530_bus_setsig(struct uart_softc *, int); 259 static int z8530_bus_transmit(struct uart_softc *); 260 261 static kobj_method_t z8530_methods[] = { 262 KOBJMETHOD(uart_attach, z8530_bus_attach), 263 KOBJMETHOD(uart_detach, z8530_bus_detach), 264 KOBJMETHOD(uart_flush, z8530_bus_flush), 265 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 266 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 267 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 268 KOBJMETHOD(uart_param, z8530_bus_param), 269 KOBJMETHOD(uart_probe, z8530_bus_probe), 270 KOBJMETHOD(uart_receive, z8530_bus_receive), 271 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 272 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 273 { 0, 0 } 274 }; 275 276 struct uart_class uart_z8530_class = { 277 "z8530 class", 278 z8530_methods, 279 sizeof(struct z8530_softc), 280 .uc_range = 2, 281 .uc_rclk = DEFAULT_RCLK 282 }; 283 284 #define SIGCHG(c, i, s, d) \ 285 if (c) { \ 286 i |= (i & s) ? s : s | d; \ 287 } else { \ 288 i = (i & s) ? (i & ~s) | d : i; \ 289 } 290 291 static int 292 z8530_bus_attach(struct uart_softc *sc) 293 { 294 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 295 struct uart_bas *bas; 296 struct uart_devinfo *di; 297 298 bas = &sc->sc_bas; 299 if (sc->sc_sysdev != NULL) { 300 di = sc->sc_sysdev; 301 z8530->tpc = TPC_DTR|TPC_RTS; 302 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 303 di->parity, &z8530->tpc); 304 } else { 305 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 306 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 307 } 308 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE. */ 309 310 sc->sc_rxfifosz = 3; 311 sc->sc_txfifosz = 1; 312 313 (void)z8530_bus_getsig(sc); 314 315 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 316 uart_barrier(bas); 317 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 318 uart_barrier(bas); 319 uart_setmreg(bas, WR_IV, 0); 320 uart_barrier(bas); 321 uart_setmreg(bas, WR_TPC, z8530->tpc); 322 uart_barrier(bas); 323 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); 324 uart_barrier(bas); 325 return (0); 326 } 327 328 static int 329 z8530_bus_detach(struct uart_softc *sc) 330 { 331 332 return (0); 333 } 334 335 static int 336 z8530_bus_flush(struct uart_softc *sc, int what) 337 { 338 339 return (0); 340 } 341 342 static int 343 z8530_bus_getsig(struct uart_softc *sc) 344 { 345 uint32_t new, old, sig; 346 uint8_t bes; 347 348 do { 349 old = sc->sc_hwsig; 350 sig = old; 351 mtx_lock_spin(&sc->sc_hwmtx); 352 bes = uart_getmreg(&sc->sc_bas, RR_BES); 353 mtx_unlock_spin(&sc->sc_hwmtx); 354 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 355 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 356 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 357 new = sig & ~UART_SIGMASK_DELTA; 358 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 359 return (sig); 360 } 361 362 static int 363 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 364 { 365 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 366 struct uart_bas *bas; 367 int error; 368 369 bas = &sc->sc_bas; 370 error = 0; 371 mtx_lock_spin(&sc->sc_hwmtx); 372 switch (request) { 373 case UART_IOCTL_BREAK: 374 if (data) 375 z8530->tpc |= TPC_BRK; 376 else 377 z8530->tpc &= ~TPC_BRK; 378 uart_setmreg(bas, WR_TPC, z8530->tpc); 379 uart_barrier(bas); 380 break; 381 default: 382 error = EINVAL; 383 break; 384 } 385 mtx_unlock_spin(&sc->sc_hwmtx); 386 return (error); 387 } 388 389 static int 390 z8530_bus_ipend(struct uart_softc *sc) 391 { 392 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 393 struct uart_bas *bas; 394 int ipend; 395 uint32_t sig; 396 uint8_t bes, ip, iv, src; 397 398 bas = &sc->sc_bas; 399 ipend = 0; 400 401 mtx_lock_spin(&sc->sc_hwmtx); 402 switch (bas->chan) { 403 case 1: 404 ip = uart_getmreg(bas, RR_IP); 405 break; 406 case 2: /* XXX hack!!! */ 407 iv = uart_getmreg(bas, RR_IV) & 0x0E; 408 switch (iv) { 409 case IV_TEB: ip = IP_TIA; break; 410 case IV_XSB: ip = IP_SIA; break; 411 case IV_RAB: ip = IP_RIA; break; 412 default: ip = 0; break; 413 } 414 break; 415 default: 416 ip = 0; 417 break; 418 } 419 420 if (ip & IP_RIA) 421 ipend |= UART_IPEND_RXREADY; 422 423 if (ip & IP_TIA) { 424 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 425 uart_barrier(bas); 426 if (z8530->txidle) { 427 ipend |= UART_IPEND_TXIDLE; 428 z8530->txidle = 0; /* Mask UART_IPEND_TXIDLE. */ 429 } 430 } 431 432 if (ip & IP_SIA) { 433 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 434 uart_barrier(bas); 435 bes = uart_getmreg(bas, RR_BES); 436 if (bes & BES_BRK) 437 ipend |= UART_IPEND_BREAK; 438 sig = sc->sc_hwsig; 439 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 440 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 441 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 442 if (sig & UART_SIGMASK_DELTA) 443 ipend |= UART_IPEND_SIGCHG; 444 src = uart_getmreg(bas, RR_SRC); 445 if (src & SRC_OVR) { 446 uart_setreg(bas, REG_CTRL, CR_RSTERR); 447 uart_barrier(bas); 448 ipend |= UART_IPEND_OVERRUN; 449 } 450 } 451 452 if (ipend) { 453 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 454 uart_barrier(bas); 455 } 456 457 mtx_unlock_spin(&sc->sc_hwmtx); 458 459 return (ipend); 460 } 461 462 static int 463 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 464 int stopbits, int parity) 465 { 466 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 467 int error; 468 469 mtx_lock_spin(&sc->sc_hwmtx); 470 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 471 &z8530->tpc); 472 mtx_unlock_spin(&sc->sc_hwmtx); 473 return (error); 474 } 475 476 static int 477 z8530_bus_probe(struct uart_softc *sc) 478 { 479 char buf[80]; 480 int error; 481 char ch; 482 483 error = z8530_probe(&sc->sc_bas); 484 if (error) 485 return (error); 486 487 ch = sc->sc_bas.chan - 1 + 'A'; 488 489 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 490 device_set_desc_copy(sc->sc_dev, buf); 491 return (0); 492 } 493 494 static int 495 z8530_bus_receive(struct uart_softc *sc) 496 { 497 struct uart_bas *bas; 498 int xc; 499 uint8_t bes, src; 500 501 bas = &sc->sc_bas; 502 mtx_lock_spin(&sc->sc_hwmtx); 503 bes = uart_getmreg(bas, RR_BES); 504 while (bes & BES_RXA) { 505 if (uart_rx_full(sc)) { 506 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 507 break; 508 } 509 xc = uart_getreg(bas, REG_DATA); 510 uart_barrier(bas); 511 src = uart_getmreg(bas, RR_SRC); 512 if (src & SRC_FE) 513 xc |= UART_STAT_FRAMERR; 514 if (src & SRC_PE) 515 xc |= UART_STAT_PARERR; 516 if (src & SRC_OVR) 517 xc |= UART_STAT_OVERRUN; 518 uart_rx_put(sc, xc); 519 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 520 uart_setreg(bas, REG_CTRL, CR_RSTERR); 521 uart_barrier(bas); 522 } 523 bes = uart_getmreg(bas, RR_BES); 524 } 525 /* Discard everything left in the Rx FIFO. */ 526 while (bes & BES_RXA) { 527 (void)uart_getreg(bas, REG_DATA); 528 uart_barrier(bas); 529 src = uart_getmreg(bas, RR_SRC); 530 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 531 uart_setreg(bas, REG_CTRL, CR_RSTERR); 532 uart_barrier(bas); 533 } 534 bes = uart_getmreg(bas, RR_BES); 535 } 536 mtx_unlock_spin(&sc->sc_hwmtx); 537 return (0); 538 } 539 540 static int 541 z8530_bus_setsig(struct uart_softc *sc, int sig) 542 { 543 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 544 struct uart_bas *bas; 545 uint32_t new, old; 546 547 bas = &sc->sc_bas; 548 do { 549 old = sc->sc_hwsig; 550 new = old; 551 if (sig & SER_DDTR) { 552 SIGCHG(sig & SER_DTR, new, SER_DTR, 553 SER_DDTR); 554 } 555 if (sig & SER_DRTS) { 556 SIGCHG(sig & SER_RTS, new, SER_RTS, 557 SER_DRTS); 558 } 559 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 560 561 mtx_lock_spin(&sc->sc_hwmtx); 562 if (new & SER_DTR) 563 z8530->tpc |= TPC_DTR; 564 else 565 z8530->tpc &= ~TPC_DTR; 566 if (new & SER_RTS) 567 z8530->tpc |= TPC_RTS; 568 else 569 z8530->tpc &= ~TPC_RTS; 570 uart_setmreg(bas, WR_TPC, z8530->tpc); 571 uart_barrier(bas); 572 mtx_unlock_spin(&sc->sc_hwmtx); 573 return (0); 574 } 575 576 static int 577 z8530_bus_transmit(struct uart_softc *sc) 578 { 579 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 580 struct uart_bas *bas; 581 582 bas = &sc->sc_bas; 583 mtx_lock_spin(&sc->sc_hwmtx); 584 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 585 ; 586 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 587 uart_barrier(bas); 588 sc->sc_txbusy = 1; 589 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE again. */ 590 mtx_unlock_spin(&sc->sc_hwmtx); 591 return (0); 592 } 593