1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/z8530.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 307200 45 46 /* Hack! */ 47 #ifdef __powerpc__ 48 #define UART_PCLK 0 49 #else 50 #define UART_PCLK MCB2_PCLK 51 #endif 52 53 /* Multiplexed I/O. */ 54 static __inline void 55 uart_setmreg(struct uart_bas *bas, int reg, int val) 56 { 57 58 uart_setreg(bas, REG_CTRL, reg); 59 uart_barrier(bas); 60 uart_setreg(bas, REG_CTRL, val); 61 } 62 63 static __inline uint8_t 64 uart_getmreg(struct uart_bas *bas, int reg) 65 { 66 67 uart_setreg(bas, REG_CTRL, reg); 68 uart_barrier(bas); 69 return (uart_getreg(bas, REG_CTRL)); 70 } 71 72 static int 73 z8530_divisor(int rclk, int baudrate) 74 { 75 int act_baud, divisor, error; 76 77 if (baudrate == 0) 78 return (-1); 79 80 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 81 if (divisor < 0 || divisor >= 65536) 82 return (-1); 83 act_baud = rclk / 2 / (divisor + 2); 84 85 /* 10 times error in percent: */ 86 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 87 88 /* 3.0% maximum error tolerance: */ 89 if (error < -30 || error > 30) 90 return (-1); 91 92 return (divisor); 93 } 94 95 static int 96 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 97 int parity, uint8_t *tpcp) 98 { 99 int divisor; 100 uint8_t mpm, rpc, tpc; 101 102 rpc = RPC_RXE; 103 mpm = MPM_CM16; 104 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 105 106 if (databits >= 8) { 107 rpc |= RPC_RB8; 108 tpc |= TPC_TB8; 109 } else if (databits == 7) { 110 rpc |= RPC_RB7; 111 tpc |= TPC_TB7; 112 } else if (databits == 6) { 113 rpc |= RPC_RB6; 114 tpc |= TPC_TB6; 115 } else { 116 rpc |= RPC_RB5; 117 tpc |= TPC_TB5; 118 } 119 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 120 switch (parity) { 121 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 122 case UART_PARITY_NONE: break; 123 case UART_PARITY_ODD: mpm |= MPM_PE; break; 124 default: return (EINVAL); 125 } 126 127 if (baudrate > 0) { 128 divisor = z8530_divisor(bas->rclk, baudrate); 129 if (divisor == -1) 130 return (EINVAL); 131 } else 132 divisor = -1; 133 134 uart_setmreg(bas, WR_MCB2, UART_PCLK); 135 uart_barrier(bas); 136 137 if (divisor >= 0) { 138 uart_setmreg(bas, WR_TCL, divisor & 0xff); 139 uart_barrier(bas); 140 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 141 uart_barrier(bas); 142 } 143 144 uart_setmreg(bas, WR_RPC, rpc); 145 uart_barrier(bas); 146 uart_setmreg(bas, WR_MPM, mpm); 147 uart_barrier(bas); 148 uart_setmreg(bas, WR_TPC, tpc); 149 uart_barrier(bas); 150 uart_setmreg(bas, WR_MCB2, UART_PCLK | MCB2_BRGE); 151 uart_barrier(bas); 152 *tpcp = tpc; 153 return (0); 154 } 155 156 static int 157 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 158 int parity) 159 { 160 uint8_t tpc; 161 162 if (bas->rclk == 0) 163 bas->rclk = DEFAULT_RCLK; 164 165 /* Assume we don't need to perform a full hardware reset. */ 166 switch (bas->chan) { 167 case 1: 168 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); 169 break; 170 case 2: 171 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); 172 break; 173 } 174 uart_barrier(bas); 175 /* Set clock sources. */ 176 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 177 uart_setmreg(bas, WR_MCB2, UART_PCLK); 178 uart_barrier(bas); 179 /* Set data encoding. */ 180 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 181 uart_barrier(bas); 182 183 tpc = TPC_DTR | TPC_RTS; 184 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 185 return (int)tpc; 186 } 187 188 /* 189 * Low-level UART interface. 190 */ 191 static int z8530_probe(struct uart_bas *bas); 192 static void z8530_init(struct uart_bas *bas, int, int, int, int); 193 static void z8530_term(struct uart_bas *bas); 194 static void z8530_putc(struct uart_bas *bas, int); 195 static int z8530_rxready(struct uart_bas *bas); 196 static int z8530_getc(struct uart_bas *bas, struct mtx *); 197 198 static struct uart_ops uart_z8530_ops = { 199 .probe = z8530_probe, 200 .init = z8530_init, 201 .term = z8530_term, 202 .putc = z8530_putc, 203 .rxready = z8530_rxready, 204 .getc = z8530_getc, 205 }; 206 207 static int 208 z8530_probe(struct uart_bas *bas) 209 { 210 211 return (0); 212 } 213 214 static void 215 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 216 int parity) 217 { 218 219 z8530_setup(bas, baudrate, databits, stopbits, parity); 220 } 221 222 static void 223 z8530_term(struct uart_bas *bas) 224 { 225 } 226 227 static void 228 z8530_putc(struct uart_bas *bas, int c) 229 { 230 231 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) 232 ; 233 uart_setreg(bas, REG_DATA, c); 234 uart_barrier(bas); 235 } 236 237 static int 238 z8530_rxready(struct uart_bas *bas) 239 { 240 241 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0); 242 } 243 244 static int 245 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx) 246 { 247 int c; 248 249 uart_lock(hwmtx); 250 251 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { 252 uart_unlock(hwmtx); 253 DELAY(10); 254 uart_lock(hwmtx); 255 } 256 257 c = uart_getreg(bas, REG_DATA); 258 259 uart_unlock(hwmtx); 260 261 return (c); 262 } 263 264 /* 265 * High-level UART interface. 266 */ 267 struct z8530_softc { 268 struct uart_softc base; 269 uint8_t tpc; 270 uint8_t txidle; 271 }; 272 273 static int z8530_bus_attach(struct uart_softc *); 274 static int z8530_bus_detach(struct uart_softc *); 275 static int z8530_bus_flush(struct uart_softc *, int); 276 static int z8530_bus_getsig(struct uart_softc *); 277 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 278 static int z8530_bus_ipend(struct uart_softc *); 279 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 280 static int z8530_bus_probe(struct uart_softc *); 281 static int z8530_bus_receive(struct uart_softc *); 282 static int z8530_bus_setsig(struct uart_softc *, int); 283 static int z8530_bus_transmit(struct uart_softc *); 284 static void z8530_bus_grab(struct uart_softc *); 285 static void z8530_bus_ungrab(struct uart_softc *); 286 287 static kobj_method_t z8530_methods[] = { 288 KOBJMETHOD(uart_attach, z8530_bus_attach), 289 KOBJMETHOD(uart_detach, z8530_bus_detach), 290 KOBJMETHOD(uart_flush, z8530_bus_flush), 291 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 292 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 293 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 294 KOBJMETHOD(uart_param, z8530_bus_param), 295 KOBJMETHOD(uart_probe, z8530_bus_probe), 296 KOBJMETHOD(uart_receive, z8530_bus_receive), 297 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 298 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 299 KOBJMETHOD(uart_grab, z8530_bus_grab), 300 KOBJMETHOD(uart_ungrab, z8530_bus_ungrab), 301 { 0, 0 } 302 }; 303 304 struct uart_class uart_z8530_class = { 305 "z8530", 306 z8530_methods, 307 sizeof(struct z8530_softc), 308 .uc_ops = &uart_z8530_ops, 309 .uc_range = 2, 310 .uc_rclk = DEFAULT_RCLK 311 }; 312 313 #define SIGCHG(c, i, s, d) \ 314 if (c) { \ 315 i |= (i & s) ? s : s | d; \ 316 } else { \ 317 i = (i & s) ? (i & ~s) | d : i; \ 318 } 319 320 static int 321 z8530_bus_attach(struct uart_softc *sc) 322 { 323 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 324 struct uart_bas *bas; 325 struct uart_devinfo *di; 326 327 bas = &sc->sc_bas; 328 if (sc->sc_sysdev != NULL) { 329 di = sc->sc_sysdev; 330 z8530->tpc = TPC_DTR|TPC_RTS; 331 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 332 di->parity, &z8530->tpc); 333 } else { 334 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 335 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 336 } 337 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */ 338 339 (void)z8530_bus_getsig(sc); 340 341 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 342 uart_barrier(bas); 343 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 344 uart_barrier(bas); 345 uart_setmreg(bas, WR_IV, 0); 346 uart_barrier(bas); 347 uart_setmreg(bas, WR_TPC, z8530->tpc); 348 uart_barrier(bas); 349 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); 350 uart_barrier(bas); 351 return (0); 352 } 353 354 static int 355 z8530_bus_detach(struct uart_softc *sc) 356 { 357 358 return (0); 359 } 360 361 static int 362 z8530_bus_flush(struct uart_softc *sc, int what) 363 { 364 365 return (0); 366 } 367 368 static int 369 z8530_bus_getsig(struct uart_softc *sc) 370 { 371 uint32_t new, old, sig; 372 uint8_t bes; 373 374 do { 375 old = sc->sc_hwsig; 376 sig = old; 377 uart_lock(sc->sc_hwmtx); 378 bes = uart_getmreg(&sc->sc_bas, RR_BES); 379 uart_unlock(sc->sc_hwmtx); 380 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 381 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 382 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 383 new = sig & ~SER_MASK_DELTA; 384 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 385 return (sig); 386 } 387 388 static int 389 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 390 { 391 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 392 struct uart_bas *bas; 393 int baudrate, divisor, error; 394 395 bas = &sc->sc_bas; 396 error = 0; 397 uart_lock(sc->sc_hwmtx); 398 switch (request) { 399 case UART_IOCTL_BREAK: 400 if (data) 401 z8530->tpc |= TPC_BRK; 402 else 403 z8530->tpc &= ~TPC_BRK; 404 uart_setmreg(bas, WR_TPC, z8530->tpc); 405 uart_barrier(bas); 406 break; 407 case UART_IOCTL_BAUD: 408 divisor = uart_getmreg(bas, RR_TCH); 409 divisor = (divisor << 8) | uart_getmreg(bas, RR_TCL); 410 baudrate = bas->rclk / 2 / (divisor + 2); 411 *(int*)data = baudrate; 412 break; 413 default: 414 error = EINVAL; 415 break; 416 } 417 uart_unlock(sc->sc_hwmtx); 418 return (error); 419 } 420 421 static int 422 z8530_bus_ipend(struct uart_softc *sc) 423 { 424 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 425 struct uart_bas *bas; 426 int ipend; 427 uint32_t sig; 428 uint8_t bes, ip, iv, src; 429 430 bas = &sc->sc_bas; 431 ipend = 0; 432 433 uart_lock(sc->sc_hwmtx); 434 switch (bas->chan) { 435 case 1: 436 ip = uart_getmreg(bas, RR_IP); 437 break; 438 case 2: /* XXX hack!!! */ 439 iv = uart_getmreg(bas, RR_IV) & 0x0E; 440 switch (iv) { 441 case IV_TEB: ip = IP_TIA; break; 442 case IV_XSB: ip = IP_SIA; break; 443 case IV_RAB: ip = IP_RIA; break; 444 default: ip = 0; break; 445 } 446 break; 447 default: 448 ip = 0; 449 break; 450 } 451 452 if (ip & IP_RIA) 453 ipend |= SER_INT_RXREADY; 454 455 if (ip & IP_TIA) { 456 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 457 uart_barrier(bas); 458 if (z8530->txidle) { 459 ipend |= SER_INT_TXIDLE; 460 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */ 461 } 462 } 463 464 if (ip & IP_SIA) { 465 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 466 uart_barrier(bas); 467 bes = uart_getmreg(bas, RR_BES); 468 if (bes & BES_BRK) 469 ipend |= SER_INT_BREAK; 470 sig = sc->sc_hwsig; 471 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 472 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 473 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 474 if (sig & SER_MASK_DELTA) 475 ipend |= SER_INT_SIGCHG; 476 src = uart_getmreg(bas, RR_SRC); 477 if (src & SRC_OVR) { 478 uart_setreg(bas, REG_CTRL, CR_RSTERR); 479 uart_barrier(bas); 480 ipend |= SER_INT_OVERRUN; 481 } 482 } 483 484 if (ipend) { 485 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 486 uart_barrier(bas); 487 } 488 489 uart_unlock(sc->sc_hwmtx); 490 491 return (ipend); 492 } 493 494 static int 495 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 496 int stopbits, int parity) 497 { 498 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 499 int error; 500 501 uart_lock(sc->sc_hwmtx); 502 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 503 &z8530->tpc); 504 uart_unlock(sc->sc_hwmtx); 505 return (error); 506 } 507 508 static int 509 z8530_bus_probe(struct uart_softc *sc) 510 { 511 char buf[80]; 512 int error; 513 char ch; 514 515 error = z8530_probe(&sc->sc_bas); 516 if (error) 517 return (error); 518 519 sc->sc_rxfifosz = 3; 520 sc->sc_txfifosz = 1; 521 522 ch = sc->sc_bas.chan - 1 + 'A'; 523 524 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 525 device_set_desc_copy(sc->sc_dev, buf); 526 return (0); 527 } 528 529 static int 530 z8530_bus_receive(struct uart_softc *sc) 531 { 532 struct uart_bas *bas; 533 int xc; 534 uint8_t bes, src; 535 536 bas = &sc->sc_bas; 537 uart_lock(sc->sc_hwmtx); 538 bes = uart_getmreg(bas, RR_BES); 539 while (bes & BES_RXA) { 540 if (uart_rx_full(sc)) { 541 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 542 break; 543 } 544 xc = uart_getreg(bas, REG_DATA); 545 uart_barrier(bas); 546 src = uart_getmreg(bas, RR_SRC); 547 if (src & SRC_FE) 548 xc |= UART_STAT_FRAMERR; 549 if (src & SRC_PE) 550 xc |= UART_STAT_PARERR; 551 if (src & SRC_OVR) 552 xc |= UART_STAT_OVERRUN; 553 uart_rx_put(sc, xc); 554 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 555 uart_setreg(bas, REG_CTRL, CR_RSTERR); 556 uart_barrier(bas); 557 } 558 bes = uart_getmreg(bas, RR_BES); 559 } 560 /* Discard everything left in the Rx FIFO. */ 561 while (bes & BES_RXA) { 562 (void)uart_getreg(bas, REG_DATA); 563 uart_barrier(bas); 564 src = uart_getmreg(bas, RR_SRC); 565 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 566 uart_setreg(bas, REG_CTRL, CR_RSTERR); 567 uart_barrier(bas); 568 } 569 bes = uart_getmreg(bas, RR_BES); 570 } 571 uart_unlock(sc->sc_hwmtx); 572 return (0); 573 } 574 575 static int 576 z8530_bus_setsig(struct uart_softc *sc, int sig) 577 { 578 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 579 struct uart_bas *bas; 580 uint32_t new, old; 581 582 bas = &sc->sc_bas; 583 do { 584 old = sc->sc_hwsig; 585 new = old; 586 if (sig & SER_DDTR) { 587 SIGCHG(sig & SER_DTR, new, SER_DTR, 588 SER_DDTR); 589 } 590 if (sig & SER_DRTS) { 591 SIGCHG(sig & SER_RTS, new, SER_RTS, 592 SER_DRTS); 593 } 594 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 595 596 uart_lock(sc->sc_hwmtx); 597 if (new & SER_DTR) 598 z8530->tpc |= TPC_DTR; 599 else 600 z8530->tpc &= ~TPC_DTR; 601 if (new & SER_RTS) 602 z8530->tpc |= TPC_RTS; 603 else 604 z8530->tpc &= ~TPC_RTS; 605 uart_setmreg(bas, WR_TPC, z8530->tpc); 606 uart_barrier(bas); 607 uart_unlock(sc->sc_hwmtx); 608 return (0); 609 } 610 611 static int 612 z8530_bus_transmit(struct uart_softc *sc) 613 { 614 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 615 struct uart_bas *bas; 616 617 bas = &sc->sc_bas; 618 uart_lock(sc->sc_hwmtx); 619 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 620 ; 621 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 622 uart_barrier(bas); 623 sc->sc_txbusy = 1; 624 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ 625 uart_unlock(sc->sc_hwmtx); 626 return (0); 627 } 628 629 static void 630 z8530_bus_grab(struct uart_softc *sc) 631 { 632 struct uart_bas *bas; 633 634 bas = &sc->sc_bas; 635 uart_lock(sc->sc_hwmtx); 636 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE); 637 uart_barrier(bas); 638 uart_unlock(sc->sc_hwmtx); 639 } 640 641 static void 642 z8530_bus_ungrab(struct uart_softc *sc) 643 { 644 struct uart_bas *bas; 645 646 bas = &sc->sc_bas; 647 uart_lock(sc->sc_hwmtx); 648 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 649 uart_barrier(bas); 650 uart_unlock(sc->sc_hwmtx); 651 } 652