1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/z8530.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 307200 45 46 /* Multiplexed I/O. */ 47 static __inline void 48 uart_setmreg(struct uart_bas *bas, int reg, int val) 49 { 50 51 uart_setreg(bas, REG_CTRL, reg); 52 uart_barrier(bas); 53 uart_setreg(bas, REG_CTRL, val); 54 } 55 56 static __inline uint8_t 57 uart_getmreg(struct uart_bas *bas, int reg) 58 { 59 60 uart_setreg(bas, REG_CTRL, reg); 61 uart_barrier(bas); 62 return (uart_getreg(bas, REG_CTRL)); 63 } 64 65 static int 66 z8530_divisor(int rclk, int baudrate) 67 { 68 int act_baud, divisor, error; 69 70 if (baudrate == 0) 71 return (0); 72 73 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 74 if (divisor < 0 || divisor >= 65536) 75 return (0); 76 act_baud = rclk / 2 / (divisor + 2); 77 78 /* 10 times error in percent: */ 79 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 80 81 /* 3.0% maximum error tolerance: */ 82 if (error < -30 || error > 30) 83 return (0); 84 85 return (divisor); 86 } 87 88 static int 89 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 90 int parity, uint8_t *tpcp) 91 { 92 int divisor; 93 uint8_t mpm, rpc, tpc; 94 95 rpc = RPC_RXE; 96 mpm = MPM_CM16; 97 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 98 99 if (databits >= 8) { 100 rpc |= RPC_RB8; 101 tpc |= TPC_TB8; 102 } else if (databits == 7) { 103 rpc |= RPC_RB7; 104 tpc |= TPC_TB7; 105 } else if (databits == 6) { 106 rpc |= RPC_RB6; 107 tpc |= TPC_TB6; 108 } else { 109 rpc |= RPC_RB5; 110 tpc |= TPC_TB5; 111 } 112 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 113 switch (parity) { 114 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 115 case UART_PARITY_NONE: break; 116 case UART_PARITY_ODD: mpm |= MPM_PE; break; 117 default: return (EINVAL); 118 } 119 120 /* Set baudrate. */ 121 if (baudrate > 0) { 122 divisor = z8530_divisor(bas->rclk, baudrate); 123 if (divisor == 0) 124 return (EINVAL); 125 uart_setmreg(bas, WR_TCL, divisor & 0xff); 126 uart_barrier(bas); 127 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 128 uart_barrier(bas); 129 } 130 131 uart_setmreg(bas, WR_RPC, rpc); 132 uart_barrier(bas); 133 uart_setmreg(bas, WR_MPM, mpm); 134 uart_barrier(bas); 135 uart_setmreg(bas, WR_TPC, tpc); 136 uart_barrier(bas); 137 *tpcp = tpc; 138 return (0); 139 } 140 141 static int 142 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 143 int parity) 144 { 145 uint8_t tpc; 146 147 if (bas->rclk == 0) 148 bas->rclk = DEFAULT_RCLK; 149 150 /* Assume we don't need to perform a full hardware reset. */ 151 switch (bas->chan) { 152 case 1: 153 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRA); 154 break; 155 case 2: 156 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_CRB); 157 break; 158 } 159 uart_barrier(bas); 160 /* Set clock sources and enable BRG. */ 161 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 162 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 163 uart_barrier(bas); 164 /* Set data encoding. */ 165 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 166 uart_barrier(bas); 167 168 tpc = TPC_DTR | TPC_RTS; 169 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 170 return (int)tpc; 171 } 172 173 /* 174 * Low-level UART interface. 175 */ 176 static int z8530_probe(struct uart_bas *bas); 177 static void z8530_init(struct uart_bas *bas, int, int, int, int); 178 static void z8530_term(struct uart_bas *bas); 179 static void z8530_putc(struct uart_bas *bas, int); 180 static int z8530_poll(struct uart_bas *bas); 181 static int z8530_getc(struct uart_bas *bas, struct mtx *); 182 183 struct uart_ops uart_z8530_ops = { 184 .probe = z8530_probe, 185 .init = z8530_init, 186 .term = z8530_term, 187 .putc = z8530_putc, 188 .poll = z8530_poll, 189 .getc = z8530_getc, 190 }; 191 192 static int 193 z8530_probe(struct uart_bas *bas) 194 { 195 196 return (0); 197 } 198 199 static void 200 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 201 int parity) 202 { 203 204 z8530_setup(bas, baudrate, databits, stopbits, parity); 205 } 206 207 static void 208 z8530_term(struct uart_bas *bas) 209 { 210 } 211 212 static void 213 z8530_putc(struct uart_bas *bas, int c) 214 { 215 216 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) 217 ; 218 uart_setreg(bas, REG_DATA, c); 219 uart_barrier(bas); 220 } 221 222 static int 223 z8530_poll(struct uart_bas *bas) 224 { 225 226 if (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) 227 return (-1); 228 return (uart_getreg(bas, REG_DATA)); 229 } 230 231 static int 232 z8530_getc(struct uart_bas *bas, struct mtx *hwmtx) 233 { 234 int c; 235 236 uart_lock(hwmtx); 237 238 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { 239 uart_unlock(hwmtx); 240 DELAY(10); 241 uart_lock(hwmtx); 242 } 243 244 c = uart_getreg(bas, REG_DATA); 245 246 uart_unlock(hwmtx); 247 248 return (c); 249 } 250 251 /* 252 * High-level UART interface. 253 */ 254 struct z8530_softc { 255 struct uart_softc base; 256 uint8_t tpc; 257 uint8_t txidle; 258 }; 259 260 static int z8530_bus_attach(struct uart_softc *); 261 static int z8530_bus_detach(struct uart_softc *); 262 static int z8530_bus_flush(struct uart_softc *, int); 263 static int z8530_bus_getsig(struct uart_softc *); 264 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 265 static int z8530_bus_ipend(struct uart_softc *); 266 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 267 static int z8530_bus_probe(struct uart_softc *); 268 static int z8530_bus_receive(struct uart_softc *); 269 static int z8530_bus_setsig(struct uart_softc *, int); 270 static int z8530_bus_transmit(struct uart_softc *); 271 272 static kobj_method_t z8530_methods[] = { 273 KOBJMETHOD(uart_attach, z8530_bus_attach), 274 KOBJMETHOD(uart_detach, z8530_bus_detach), 275 KOBJMETHOD(uart_flush, z8530_bus_flush), 276 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 277 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 278 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 279 KOBJMETHOD(uart_param, z8530_bus_param), 280 KOBJMETHOD(uart_probe, z8530_bus_probe), 281 KOBJMETHOD(uart_receive, z8530_bus_receive), 282 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 283 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 284 { 0, 0 } 285 }; 286 287 struct uart_class uart_z8530_class = { 288 "z8530 class", 289 z8530_methods, 290 sizeof(struct z8530_softc), 291 .uc_range = 2, 292 .uc_rclk = DEFAULT_RCLK 293 }; 294 295 #define SIGCHG(c, i, s, d) \ 296 if (c) { \ 297 i |= (i & s) ? s : s | d; \ 298 } else { \ 299 i = (i & s) ? (i & ~s) | d : i; \ 300 } 301 302 static int 303 z8530_bus_attach(struct uart_softc *sc) 304 { 305 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 306 struct uart_bas *bas; 307 struct uart_devinfo *di; 308 309 bas = &sc->sc_bas; 310 if (sc->sc_sysdev != NULL) { 311 di = sc->sc_sysdev; 312 z8530->tpc = TPC_DTR|TPC_RTS; 313 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 314 di->parity, &z8530->tpc); 315 } else { 316 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 317 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 318 } 319 z8530->txidle = 1; /* Report SER_INT_TXIDLE. */ 320 321 sc->sc_rxfifosz = 3; 322 sc->sc_txfifosz = 1; 323 324 (void)z8530_bus_getsig(sc); 325 326 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 327 uart_barrier(bas); 328 uart_setmreg(bas, WR_IDT, IDT_XIE | IDT_TIE | IDT_RIA); 329 uart_barrier(bas); 330 uart_setmreg(bas, WR_IV, 0); 331 uart_barrier(bas); 332 uart_setmreg(bas, WR_TPC, z8530->tpc); 333 uart_barrier(bas); 334 uart_setmreg(bas, WR_MIC, MIC_NV | MIC_MIE); 335 uart_barrier(bas); 336 return (0); 337 } 338 339 static int 340 z8530_bus_detach(struct uart_softc *sc) 341 { 342 343 return (0); 344 } 345 346 static int 347 z8530_bus_flush(struct uart_softc *sc, int what) 348 { 349 350 return (0); 351 } 352 353 static int 354 z8530_bus_getsig(struct uart_softc *sc) 355 { 356 uint32_t new, old, sig; 357 uint8_t bes; 358 359 do { 360 old = sc->sc_hwsig; 361 sig = old; 362 uart_lock(sc->sc_hwmtx); 363 bes = uart_getmreg(&sc->sc_bas, RR_BES); 364 uart_unlock(sc->sc_hwmtx); 365 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 366 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 367 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 368 new = sig & ~SER_MASK_DELTA; 369 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 370 return (sig); 371 } 372 373 static int 374 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 375 { 376 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 377 struct uart_bas *bas; 378 int error; 379 380 bas = &sc->sc_bas; 381 error = 0; 382 uart_lock(sc->sc_hwmtx); 383 switch (request) { 384 case UART_IOCTL_BREAK: 385 if (data) 386 z8530->tpc |= TPC_BRK; 387 else 388 z8530->tpc &= ~TPC_BRK; 389 uart_setmreg(bas, WR_TPC, z8530->tpc); 390 uart_barrier(bas); 391 break; 392 default: 393 error = EINVAL; 394 break; 395 } 396 uart_unlock(sc->sc_hwmtx); 397 return (error); 398 } 399 400 static int 401 z8530_bus_ipend(struct uart_softc *sc) 402 { 403 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 404 struct uart_bas *bas; 405 int ipend; 406 uint32_t sig; 407 uint8_t bes, ip, iv, src; 408 409 bas = &sc->sc_bas; 410 ipend = 0; 411 412 uart_lock(sc->sc_hwmtx); 413 switch (bas->chan) { 414 case 1: 415 ip = uart_getmreg(bas, RR_IP); 416 break; 417 case 2: /* XXX hack!!! */ 418 iv = uart_getmreg(bas, RR_IV) & 0x0E; 419 switch (iv) { 420 case IV_TEB: ip = IP_TIA; break; 421 case IV_XSB: ip = IP_SIA; break; 422 case IV_RAB: ip = IP_RIA; break; 423 default: ip = 0; break; 424 } 425 break; 426 default: 427 ip = 0; 428 break; 429 } 430 431 if (ip & IP_RIA) 432 ipend |= SER_INT_RXREADY; 433 434 if (ip & IP_TIA) { 435 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 436 uart_barrier(bas); 437 if (z8530->txidle) { 438 ipend |= SER_INT_TXIDLE; 439 z8530->txidle = 0; /* Mask SER_INT_TXIDLE. */ 440 } 441 } 442 443 if (ip & IP_SIA) { 444 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 445 uart_barrier(bas); 446 bes = uart_getmreg(bas, RR_BES); 447 if (bes & BES_BRK) 448 ipend |= SER_INT_BREAK; 449 sig = sc->sc_hwsig; 450 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 451 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 452 SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); 453 if (sig & SER_MASK_DELTA) 454 ipend |= SER_INT_SIGCHG; 455 src = uart_getmreg(bas, RR_SRC); 456 if (src & SRC_OVR) { 457 uart_setreg(bas, REG_CTRL, CR_RSTERR); 458 uart_barrier(bas); 459 ipend |= SER_INT_OVERRUN; 460 } 461 } 462 463 if (ipend) { 464 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 465 uart_barrier(bas); 466 } 467 468 uart_unlock(sc->sc_hwmtx); 469 470 return (ipend); 471 } 472 473 static int 474 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 475 int stopbits, int parity) 476 { 477 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 478 int error; 479 480 uart_lock(sc->sc_hwmtx); 481 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 482 &z8530->tpc); 483 uart_unlock(sc->sc_hwmtx); 484 return (error); 485 } 486 487 static int 488 z8530_bus_probe(struct uart_softc *sc) 489 { 490 char buf[80]; 491 int error; 492 char ch; 493 494 error = z8530_probe(&sc->sc_bas); 495 if (error) 496 return (error); 497 498 ch = sc->sc_bas.chan - 1 + 'A'; 499 500 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 501 device_set_desc_copy(sc->sc_dev, buf); 502 return (0); 503 } 504 505 static int 506 z8530_bus_receive(struct uart_softc *sc) 507 { 508 struct uart_bas *bas; 509 int xc; 510 uint8_t bes, src; 511 512 bas = &sc->sc_bas; 513 uart_lock(sc->sc_hwmtx); 514 bes = uart_getmreg(bas, RR_BES); 515 while (bes & BES_RXA) { 516 if (uart_rx_full(sc)) { 517 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 518 break; 519 } 520 xc = uart_getreg(bas, REG_DATA); 521 uart_barrier(bas); 522 src = uart_getmreg(bas, RR_SRC); 523 if (src & SRC_FE) 524 xc |= UART_STAT_FRAMERR; 525 if (src & SRC_PE) 526 xc |= UART_STAT_PARERR; 527 if (src & SRC_OVR) 528 xc |= UART_STAT_OVERRUN; 529 uart_rx_put(sc, xc); 530 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 531 uart_setreg(bas, REG_CTRL, CR_RSTERR); 532 uart_barrier(bas); 533 } 534 bes = uart_getmreg(bas, RR_BES); 535 } 536 /* Discard everything left in the Rx FIFO. */ 537 while (bes & BES_RXA) { 538 (void)uart_getreg(bas, REG_DATA); 539 uart_barrier(bas); 540 src = uart_getmreg(bas, RR_SRC); 541 if (src & (SRC_FE | SRC_PE | SRC_OVR)) { 542 uart_setreg(bas, REG_CTRL, CR_RSTERR); 543 uart_barrier(bas); 544 } 545 bes = uart_getmreg(bas, RR_BES); 546 } 547 uart_unlock(sc->sc_hwmtx); 548 return (0); 549 } 550 551 static int 552 z8530_bus_setsig(struct uart_softc *sc, int sig) 553 { 554 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 555 struct uart_bas *bas; 556 uint32_t new, old; 557 558 bas = &sc->sc_bas; 559 do { 560 old = sc->sc_hwsig; 561 new = old; 562 if (sig & SER_DDTR) { 563 SIGCHG(sig & SER_DTR, new, SER_DTR, 564 SER_DDTR); 565 } 566 if (sig & SER_DRTS) { 567 SIGCHG(sig & SER_RTS, new, SER_RTS, 568 SER_DRTS); 569 } 570 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 571 572 uart_lock(sc->sc_hwmtx); 573 if (new & SER_DTR) 574 z8530->tpc |= TPC_DTR; 575 else 576 z8530->tpc &= ~TPC_DTR; 577 if (new & SER_RTS) 578 z8530->tpc |= TPC_RTS; 579 else 580 z8530->tpc &= ~TPC_RTS; 581 uart_setmreg(bas, WR_TPC, z8530->tpc); 582 uart_barrier(bas); 583 uart_unlock(sc->sc_hwmtx); 584 return (0); 585 } 586 587 static int 588 z8530_bus_transmit(struct uart_softc *sc) 589 { 590 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 591 struct uart_bas *bas; 592 593 bas = &sc->sc_bas; 594 uart_lock(sc->sc_hwmtx); 595 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 596 ; 597 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 598 uart_barrier(bas); 599 sc->sc_txbusy = 1; 600 z8530->txidle = 1; /* Report SER_INT_TXIDLE again. */ 601 uart_unlock(sc->sc_hwmtx); 602 return (0); 603 } 604