1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <machine/bus.h> 35 36 #include <dev/uart/uart.h> 37 #include <dev/uart/uart_cpu.h> 38 #include <dev/uart/uart_bus.h> 39 40 #include <dev/ic/z8530.h> 41 42 #include "uart_if.h" 43 44 #define DEFAULT_RCLK 307200 45 46 /* Multiplexed I/O. */ 47 static __inline void 48 uart_setmreg(struct uart_bas *bas, int reg, int val) 49 { 50 51 uart_setreg(bas, REG_CTRL, reg); 52 uart_barrier(bas); 53 uart_setreg(bas, REG_CTRL, val); 54 } 55 56 static __inline uint8_t 57 uart_getmreg(struct uart_bas *bas, int reg) 58 { 59 60 uart_setreg(bas, REG_CTRL, reg); 61 uart_barrier(bas); 62 return (uart_getreg(bas, REG_CTRL)); 63 } 64 65 static int 66 z8530_divisor(int rclk, int baudrate) 67 { 68 int act_baud, divisor, error; 69 70 if (baudrate == 0) 71 return (0); 72 73 divisor = (rclk + baudrate) / (baudrate << 1) - 2; 74 if (divisor >= 65536) 75 return (0); 76 act_baud = rclk / 2 / (divisor + 2); 77 78 /* 10 times error in percent: */ 79 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 80 81 /* 3.0% maximum error tolerance: */ 82 if (error < -30 || error > 30) 83 return (0); 84 85 return (divisor); 86 } 87 88 static int 89 z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 90 int parity, uint8_t *tpcp) 91 { 92 int divisor; 93 uint8_t mpm, rpc, tpc; 94 95 rpc = RPC_RXE; 96 mpm = MPM_CM16; 97 tpc = TPC_TXE | (*tpcp & (TPC_DTR | TPC_RTS)); 98 99 if (databits >= 8) { 100 rpc |= RPC_RB8; 101 tpc |= TPC_TB8; 102 } else if (databits == 7) { 103 rpc |= RPC_RB7; 104 tpc |= TPC_TB7; 105 } else if (databits == 6) { 106 rpc |= RPC_RB6; 107 tpc |= TPC_TB6; 108 } else { 109 rpc |= RPC_RB5; 110 tpc |= TPC_TB5; 111 } 112 mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1; 113 switch (parity) { 114 case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break; 115 case UART_PARITY_NONE: break; 116 case UART_PARITY_ODD: mpm |= MPM_PE; break; 117 default: return (EINVAL); 118 } 119 120 /* Set baudrate. */ 121 if (baudrate > 0) { 122 divisor = z8530_divisor(bas->rclk, baudrate); 123 if (divisor == 0) 124 return (EINVAL); 125 uart_setmreg(bas, WR_TCL, divisor & 0xff); 126 uart_barrier(bas); 127 uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff); 128 uart_barrier(bas); 129 } 130 131 uart_setmreg(bas, WR_RPC, rpc); 132 uart_barrier(bas); 133 uart_setmreg(bas, WR_MPM, mpm); 134 uart_barrier(bas); 135 uart_setmreg(bas, WR_TPC, tpc); 136 uart_barrier(bas); 137 *tpcp = tpc; 138 return (0); 139 } 140 141 static int 142 z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 143 int parity) 144 { 145 uint8_t mic, tpc; 146 147 if (bas->rclk == 0) 148 bas->rclk = DEFAULT_RCLK; 149 150 /* Assume we don't need to perform a full hardware reset. */ 151 mic = MIC_MIE | MIC_NV; 152 switch (bas->chan) { 153 case 1: 154 mic |= MIC_CRA; 155 break; 156 case 2: 157 mic |= MIC_CRB; 158 break; 159 } 160 uart_setmreg(bas, WR_MIC, mic); 161 uart_barrier(bas); 162 /* Set clock sources and enable BRG. */ 163 uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG); 164 uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE); 165 uart_barrier(bas); 166 /* Set data encoding. */ 167 uart_setmreg(bas, WR_MCB1, MCB1_NRZ); 168 uart_barrier(bas); 169 170 tpc = TPC_DTR | TPC_RTS; 171 z8530_param(bas, baudrate, databits, stopbits, parity, &tpc); 172 return (int)tpc; 173 } 174 175 /* 176 * Low-level UART interface. 177 */ 178 static int z8530_probe(struct uart_bas *bas); 179 static void z8530_init(struct uart_bas *bas, int, int, int, int); 180 static void z8530_term(struct uart_bas *bas); 181 static void z8530_putc(struct uart_bas *bas, int); 182 static int z8530_poll(struct uart_bas *bas); 183 static int z8530_getc(struct uart_bas *bas); 184 185 struct uart_ops uart_z8530_ops = { 186 .probe = z8530_probe, 187 .init = z8530_init, 188 .term = z8530_term, 189 .putc = z8530_putc, 190 .poll = z8530_poll, 191 .getc = z8530_getc, 192 }; 193 194 static int 195 z8530_probe(struct uart_bas *bas) 196 { 197 198 return (0); 199 } 200 201 static void 202 z8530_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 203 int parity) 204 { 205 206 z8530_setup(bas, baudrate, databits, stopbits, parity); 207 } 208 209 static void 210 z8530_term(struct uart_bas *bas) 211 { 212 } 213 214 static void 215 z8530_putc(struct uart_bas *bas, int c) 216 { 217 218 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 219 ; 220 uart_setreg(bas, REG_DATA, c); 221 uart_barrier(bas); 222 } 223 224 static int 225 z8530_poll(struct uart_bas *bas) 226 { 227 228 if (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 229 return (-1); 230 return (uart_getreg(bas, REG_DATA)); 231 } 232 233 static int 234 z8530_getc(struct uart_bas *bas) 235 { 236 237 while (!(uart_getmreg(bas, RR_BES) & BES_RXA)) 238 ; 239 return (uart_getreg(bas, REG_DATA)); 240 } 241 242 /* 243 * High-level UART interface. 244 */ 245 struct z8530_softc { 246 struct uart_softc base; 247 uint8_t tpc; 248 uint8_t txidle; 249 }; 250 251 static int z8530_bus_attach(struct uart_softc *); 252 static int z8530_bus_detach(struct uart_softc *); 253 static int z8530_bus_flush(struct uart_softc *, int); 254 static int z8530_bus_getsig(struct uart_softc *); 255 static int z8530_bus_ioctl(struct uart_softc *, int, intptr_t); 256 static int z8530_bus_ipend(struct uart_softc *); 257 static int z8530_bus_param(struct uart_softc *, int, int, int, int); 258 static int z8530_bus_probe(struct uart_softc *); 259 static int z8530_bus_receive(struct uart_softc *); 260 static int z8530_bus_setsig(struct uart_softc *, int); 261 static int z8530_bus_transmit(struct uart_softc *); 262 263 static kobj_method_t z8530_methods[] = { 264 KOBJMETHOD(uart_attach, z8530_bus_attach), 265 KOBJMETHOD(uart_detach, z8530_bus_detach), 266 KOBJMETHOD(uart_flush, z8530_bus_flush), 267 KOBJMETHOD(uart_getsig, z8530_bus_getsig), 268 KOBJMETHOD(uart_ioctl, z8530_bus_ioctl), 269 KOBJMETHOD(uart_ipend, z8530_bus_ipend), 270 KOBJMETHOD(uart_param, z8530_bus_param), 271 KOBJMETHOD(uart_probe, z8530_bus_probe), 272 KOBJMETHOD(uart_receive, z8530_bus_receive), 273 KOBJMETHOD(uart_setsig, z8530_bus_setsig), 274 KOBJMETHOD(uart_transmit, z8530_bus_transmit), 275 { 0, 0 } 276 }; 277 278 struct uart_class uart_z8530_class = { 279 "z8530 class", 280 z8530_methods, 281 sizeof(struct z8530_softc), 282 .uc_range = 2, 283 .uc_rclk = DEFAULT_RCLK 284 }; 285 286 #define SIGCHG(c, i, s, d) \ 287 if (c) { \ 288 i |= (i & s) ? s : s | d; \ 289 } else { \ 290 i = (i & s) ? (i & ~s) | d : i; \ 291 } 292 293 static int 294 z8530_bus_attach(struct uart_softc *sc) 295 { 296 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 297 struct uart_bas *bas; 298 struct uart_devinfo *di; 299 300 bas = &sc->sc_bas; 301 if (sc->sc_sysdev != NULL) { 302 di = sc->sc_sysdev; 303 z8530->tpc = TPC_DTR|TPC_RTS; 304 z8530_param(bas, di->baudrate, di->databits, di->stopbits, 305 di->parity, &z8530->tpc); 306 } else { 307 z8530->tpc = z8530_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 308 z8530->tpc &= ~(TPC_DTR|TPC_RTS); 309 } 310 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE. */ 311 312 sc->sc_rxfifosz = 3; 313 sc->sc_txfifosz = 1; 314 315 (void)z8530_bus_getsig(sc); 316 317 uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD); 318 uart_barrier(bas); 319 uart_setmreg(bas, WR_IDT, IDT_TIE | IDT_RIA); 320 uart_barrier(bas); 321 uart_setmreg(bas, WR_IV, 0); 322 uart_barrier(bas); 323 uart_setmreg(bas, WR_TPC, z8530->tpc); 324 uart_barrier(bas); 325 return (0); 326 } 327 328 static int 329 z8530_bus_detach(struct uart_softc *sc) 330 { 331 332 return (0); 333 } 334 335 static int 336 z8530_bus_flush(struct uart_softc *sc, int what) 337 { 338 339 return (0); 340 } 341 342 static int 343 z8530_bus_getsig(struct uart_softc *sc) 344 { 345 uint32_t new, old, sig; 346 uint8_t bes; 347 348 do { 349 old = sc->sc_hwsig; 350 sig = old; 351 mtx_lock_spin(&sc->sc_hwmtx); 352 bes = uart_getmreg(&sc->sc_bas, RR_BES); 353 mtx_unlock_spin(&sc->sc_hwmtx); 354 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 355 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 356 new = sig & ~UART_SIGMASK_DELTA; 357 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 358 return (sig); 359 } 360 361 static int 362 z8530_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 363 { 364 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 365 struct uart_bas *bas; 366 int error; 367 368 bas = &sc->sc_bas; 369 error = 0; 370 mtx_lock_spin(&sc->sc_hwmtx); 371 switch (request) { 372 case UART_IOCTL_BREAK: 373 if (data) 374 z8530->tpc |= TPC_BRK; 375 else 376 z8530->tpc &= ~TPC_BRK; 377 uart_setmreg(bas, WR_TPC, z8530->tpc); 378 uart_barrier(bas); 379 break; 380 default: 381 error = EINVAL; 382 break; 383 } 384 mtx_unlock_spin(&sc->sc_hwmtx); 385 return (error); 386 } 387 388 static int 389 z8530_bus_ipend(struct uart_softc *sc) 390 { 391 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 392 struct uart_bas *bas; 393 int ipend; 394 uint32_t sig; 395 uint8_t bes, src; 396 397 bas = &sc->sc_bas; 398 ipend = 0; 399 mtx_lock_spin(&sc->sc_hwmtx); 400 uart_setreg(bas, REG_CTRL, CR_RSTIUS); 401 uart_barrier(bas); 402 bes = uart_getmreg(bas, RR_BES); 403 if (bes & BES_BRK) { 404 uart_setreg(bas, REG_CTRL, CR_RSTXSI); 405 ipend |= UART_IPEND_BREAK; 406 } 407 if (bes & BES_TXE && z8530->txidle) { 408 uart_setreg(bas, REG_CTRL, CR_RSTTXI); 409 ipend |= UART_IPEND_TXIDLE; 410 z8530->txidle = 0; /* Suppress UART_IPEND_TXIDLE. */ 411 } 412 if (bes & BES_RXA) 413 ipend |= UART_IPEND_RXREADY; 414 sig = sc->sc_hwsig; 415 SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); 416 SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); 417 if (sig & UART_SIGMASK_DELTA) 418 ipend |= UART_IPEND_SIGCHG; 419 src = uart_getmreg(bas, RR_SRC); 420 if (src & SRC_OVR) { 421 uart_setreg(bas, REG_CTRL, CR_RSTERR); 422 ipend |= UART_IPEND_OVERRUN; 423 } 424 mtx_unlock_spin(&sc->sc_hwmtx); 425 return (ipend); 426 } 427 428 static int 429 z8530_bus_param(struct uart_softc *sc, int baudrate, int databits, 430 int stopbits, int parity) 431 { 432 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 433 int error; 434 435 mtx_lock_spin(&sc->sc_hwmtx); 436 error = z8530_param(&sc->sc_bas, baudrate, databits, stopbits, parity, 437 &z8530->tpc); 438 mtx_unlock_spin(&sc->sc_hwmtx); 439 return (error); 440 } 441 442 static int 443 z8530_bus_probe(struct uart_softc *sc) 444 { 445 char buf[80]; 446 int error; 447 char ch; 448 449 error = z8530_probe(&sc->sc_bas); 450 if (error) 451 return (error); 452 453 ch = sc->sc_bas.chan - 1 + 'A'; 454 455 snprintf(buf, sizeof(buf), "z8530, channel %c", ch); 456 device_set_desc_copy(sc->sc_dev, buf); 457 return (0); 458 } 459 460 static int 461 z8530_bus_receive(struct uart_softc *sc) 462 { 463 struct uart_bas *bas; 464 int xc; 465 uint8_t bes, src; 466 467 bas = &sc->sc_bas; 468 mtx_lock_spin(&sc->sc_hwmtx); 469 bes = uart_getmreg(bas, RR_BES); 470 while (bes & BES_RXA) { 471 if (uart_rx_full(sc)) { 472 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 473 break; 474 } 475 src = uart_getmreg(bas, RR_SRC); 476 xc = uart_getreg(bas, REG_DATA); 477 if (src & SRC_FE) 478 xc |= UART_STAT_FRAMERR; 479 if (src & SRC_PE) 480 xc |= UART_STAT_PARERR; 481 uart_rx_put(sc, xc); 482 if (src & (SRC_FE | SRC_PE)) { 483 uart_setreg(bas, REG_CTRL, CR_RSTERR); 484 uart_barrier(bas); 485 } 486 bes = uart_getmreg(bas, RR_BES); 487 } 488 /* Discard everything left in the Rx FIFO. */ 489 while (bes & BES_RXA) { 490 src = uart_getmreg(bas, RR_SRC); 491 (void)uart_getreg(bas, REG_DATA); 492 if (src & (SRC_FE | SRC_PE)) { 493 uart_setreg(bas, REG_CTRL, CR_RSTERR); 494 uart_barrier(bas); 495 } 496 bes = uart_getmreg(bas, RR_BES); 497 } 498 mtx_unlock_spin(&sc->sc_hwmtx); 499 return (0); 500 } 501 502 static int 503 z8530_bus_setsig(struct uart_softc *sc, int sig) 504 { 505 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 506 struct uart_bas *bas; 507 uint32_t new, old; 508 509 bas = &sc->sc_bas; 510 do { 511 old = sc->sc_hwsig; 512 new = old; 513 if (sig & SER_DDTR) { 514 SIGCHG(sig & SER_DTR, new, SER_DTR, 515 SER_DDTR); 516 } 517 if (sig & SER_DRTS) { 518 SIGCHG(sig & SER_RTS, new, SER_RTS, 519 SER_DRTS); 520 } 521 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 522 523 mtx_lock_spin(&sc->sc_hwmtx); 524 if (new & SER_DTR) 525 z8530->tpc |= TPC_DTR; 526 else 527 z8530->tpc &= ~TPC_DTR; 528 if (new & SER_RTS) 529 z8530->tpc |= TPC_RTS; 530 else 531 z8530->tpc &= ~TPC_RTS; 532 uart_setmreg(bas, WR_TPC, z8530->tpc); 533 uart_barrier(bas); 534 mtx_unlock_spin(&sc->sc_hwmtx); 535 return (0); 536 } 537 538 static int 539 z8530_bus_transmit(struct uart_softc *sc) 540 { 541 struct z8530_softc *z8530 = (struct z8530_softc*)sc; 542 struct uart_bas *bas; 543 544 bas = &sc->sc_bas; 545 mtx_lock_spin(&sc->sc_hwmtx); 546 while (!(uart_getmreg(bas, RR_BES) & BES_TXE)) 547 ; 548 uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]); 549 uart_barrier(bas); 550 sc->sc_txbusy = 1; 551 z8530->txidle = 1; /* Report UART_IPEND_TXIDLE again. */ 552 mtx_unlock_spin(&sc->sc_hwmtx); 553 return (0); 554 } 555