1 /*- 2 * Copyright (c) 2006 Juniper Networks 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/endian.h> 35 #include <machine/bus.h> 36 37 #include <dev/ic/quicc.h> 38 39 #include <dev/uart/uart.h> 40 #include <dev/uart/uart_cpu.h> 41 #include <dev/uart/uart_bus.h> 42 43 #include "uart_if.h" 44 45 #define DEFAULT_RCLK ((266000000 * 2) / 16) 46 47 #define quicc_read2(bas, reg) \ 48 bus_space_read_2((bas)->bst, (bas)->bsh, reg) 49 #define quicc_read4(bas, reg) \ 50 bus_space_read_4((bas)->bst, (bas)->bsh, reg) 51 52 #define quicc_write2(bas, reg, val) \ 53 bus_space_write_2((bas)->bst, (bas)->bsh, reg, val) 54 #define quicc_write4(bas, reg, val) \ 55 bus_space_write_4((bas)->bst, (bas)->bsh, reg, val) 56 57 static int 58 quicc_divisor(int rclk, int baudrate) 59 { 60 int act_baud, divisor, error; 61 62 if (baudrate == 0) 63 return (-1); 64 65 divisor = rclk / baudrate / 16; 66 if (divisor > 4096) 67 divisor = ((divisor >> 3) - 2) | 1; 68 else if (divisor >= 0) 69 divisor = (divisor - 1) << 1; 70 if (divisor < 0 || divisor >= 8192) 71 return (-1); 72 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4)); 73 74 /* 10 times error in percent: */ 75 error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1; 76 77 /* 3.0% maximum error tolerance: */ 78 if (error < -30 || error > 30) 79 return (-1); 80 81 return (divisor); 82 } 83 84 static int 85 quicc_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 86 int parity) 87 { 88 int divisor; 89 uint16_t psmr; 90 91 if (baudrate > 0) { 92 divisor = quicc_divisor(bas->rclk, baudrate); 93 if (divisor == -1) 94 return (EINVAL); 95 quicc_write4(bas, QUICC_REG_BRG(bas->chan - 1), 96 divisor | 0x10000); 97 } 98 99 psmr = 0; 100 switch (databits) { 101 case 5: psmr |= 0x0000; break; 102 case 6: psmr |= 0x1000; break; 103 case 7: psmr |= 0x2000; break; 104 case 8: psmr |= 0x3000; break; 105 default: return (EINVAL); 106 } 107 switch (stopbits) { 108 case 1: psmr |= 0x0000; break; 109 case 2: psmr |= 0x4000; break; 110 default: return (EINVAL); 111 } 112 switch (parity) { 113 case UART_PARITY_EVEN: psmr |= 0x1a; break; 114 case UART_PARITY_MARK: psmr |= 0x1f; break; 115 case UART_PARITY_NONE: psmr |= 0x00; break; 116 case UART_PARITY_ODD: psmr |= 0x10; break; 117 case UART_PARITY_SPACE: psmr |= 0x15; break; 118 default: return (EINVAL); 119 } 120 quicc_write2(bas, QUICC_REG_SCC_PSMR(bas->chan - 1), psmr); 121 return (0); 122 } 123 124 static void 125 quicc_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits, 126 int parity) 127 { 128 129 if (bas->rclk == 0) 130 bas->rclk = DEFAULT_RCLK; 131 132 /* 133 * GSMR_L = 0x00028034 134 * GSMR_H = 0x00000020 135 */ 136 quicc_param(bas, baudrate, databits, stopbits, parity); 137 138 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); 139 quicc_write2(bas, QUICC_REG_SCC_SCCM(bas->chan - 1), 0x0027); 140 } 141 142 /* 143 * Low-level UART interface. 144 */ 145 static int quicc_probe(struct uart_bas *bas); 146 static void quicc_init(struct uart_bas *bas, int, int, int, int); 147 static void quicc_term(struct uart_bas *bas); 148 static void quicc_putc(struct uart_bas *bas, int); 149 static int quicc_rxready(struct uart_bas *bas); 150 static int quicc_getc(struct uart_bas *bas, struct mtx *); 151 152 static struct uart_ops uart_quicc_ops = { 153 .probe = quicc_probe, 154 .init = quicc_init, 155 .term = quicc_term, 156 .putc = quicc_putc, 157 .rxready = quicc_rxready, 158 .getc = quicc_getc, 159 }; 160 161 static int 162 quicc_probe(struct uart_bas *bas) 163 { 164 165 return (0); 166 } 167 168 static void 169 quicc_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 170 int parity) 171 { 172 173 quicc_setup(bas, baudrate, databits, stopbits, parity); 174 } 175 176 static void 177 quicc_term(struct uart_bas *bas) 178 { 179 } 180 181 static void 182 quicc_putc(struct uart_bas *bas, int c) 183 { 184 int unit; 185 uint16_t toseq; 186 187 unit = bas->chan - 1; 188 while (quicc_read2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit)) & 0x2000) 189 DELAY(10); 190 191 toseq = 0x2000 | (c & 0xff); 192 quicc_write2(bas, QUICC_PRAM_SCC_UART_TOSEQ(unit), toseq); 193 } 194 195 static int 196 quicc_rxready(struct uart_bas *bas) 197 { 198 uint16_t rb; 199 200 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 201 return ((quicc_read2(bas, rb) & 0x8000) ? 0 : 1); 202 } 203 204 static int 205 quicc_getc(struct uart_bas *bas, struct mtx *hwmtx) 206 { 207 volatile char *buf; 208 int c; 209 uint16_t rb, sc; 210 211 uart_lock(hwmtx); 212 213 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 214 215 while ((sc = quicc_read2(bas, rb)) & 0x8000) { 216 uart_unlock(hwmtx); 217 DELAY(4); 218 uart_lock(hwmtx); 219 } 220 221 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); 222 c = *buf; 223 quicc_write2(bas, rb, sc | 0x8000); 224 225 uart_unlock(hwmtx); 226 227 return (c); 228 } 229 230 /* 231 * High-level UART interface. 232 */ 233 struct quicc_softc { 234 struct uart_softc base; 235 }; 236 237 static int quicc_bus_attach(struct uart_softc *); 238 static int quicc_bus_detach(struct uart_softc *); 239 static int quicc_bus_flush(struct uart_softc *, int); 240 static int quicc_bus_getsig(struct uart_softc *); 241 static int quicc_bus_ioctl(struct uart_softc *, int, intptr_t); 242 static int quicc_bus_ipend(struct uart_softc *); 243 static int quicc_bus_param(struct uart_softc *, int, int, int, int); 244 static int quicc_bus_probe(struct uart_softc *); 245 static int quicc_bus_receive(struct uart_softc *); 246 static int quicc_bus_setsig(struct uart_softc *, int); 247 static int quicc_bus_transmit(struct uart_softc *); 248 static void quicc_bus_grab(struct uart_softc *); 249 static void quicc_bus_ungrab(struct uart_softc *); 250 251 static kobj_method_t quicc_methods[] = { 252 KOBJMETHOD(uart_attach, quicc_bus_attach), 253 KOBJMETHOD(uart_detach, quicc_bus_detach), 254 KOBJMETHOD(uart_flush, quicc_bus_flush), 255 KOBJMETHOD(uart_getsig, quicc_bus_getsig), 256 KOBJMETHOD(uart_ioctl, quicc_bus_ioctl), 257 KOBJMETHOD(uart_ipend, quicc_bus_ipend), 258 KOBJMETHOD(uart_param, quicc_bus_param), 259 KOBJMETHOD(uart_probe, quicc_bus_probe), 260 KOBJMETHOD(uart_receive, quicc_bus_receive), 261 KOBJMETHOD(uart_setsig, quicc_bus_setsig), 262 KOBJMETHOD(uart_transmit, quicc_bus_transmit), 263 KOBJMETHOD(uart_grab, quicc_bus_grab), 264 KOBJMETHOD(uart_ungrab, quicc_bus_ungrab), 265 { 0, 0 } 266 }; 267 268 struct uart_class uart_quicc_class = { 269 "quicc", 270 quicc_methods, 271 sizeof(struct quicc_softc), 272 .uc_ops = &uart_quicc_ops, 273 .uc_range = 2, 274 .uc_rclk = DEFAULT_RCLK 275 }; 276 277 #define SIGCHG(c, i, s, d) \ 278 if (c) { \ 279 i |= (i & s) ? s : s | d; \ 280 } else { \ 281 i = (i & s) ? (i & ~s) | d : i; \ 282 } 283 284 static int 285 quicc_bus_attach(struct uart_softc *sc) 286 { 287 struct uart_bas *bas; 288 struct uart_devinfo *di; 289 uint16_t st, rb; 290 291 bas = &sc->sc_bas; 292 if (sc->sc_sysdev != NULL) { 293 di = sc->sc_sysdev; 294 quicc_param(bas, di->baudrate, di->databits, di->stopbits, 295 di->parity); 296 } else { 297 quicc_setup(bas, 9600, 8, 1, UART_PARITY_NONE); 298 } 299 300 /* Enable interrupts on the receive buffer. */ 301 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 302 st = quicc_read2(bas, rb); 303 quicc_write2(bas, rb, st | 0x9000); 304 305 (void)quicc_bus_getsig(sc); 306 307 return (0); 308 } 309 310 static int 311 quicc_bus_detach(struct uart_softc *sc) 312 { 313 314 return (0); 315 } 316 317 static int 318 quicc_bus_flush(struct uart_softc *sc, int what) 319 { 320 321 return (0); 322 } 323 324 static int 325 quicc_bus_getsig(struct uart_softc *sc) 326 { 327 uint32_t new, old, sig; 328 uint32_t dummy; 329 330 do { 331 old = sc->sc_hwsig; 332 sig = old; 333 uart_lock(sc->sc_hwmtx); 334 /* XXX SIGNALS */ 335 dummy = 0; 336 uart_unlock(sc->sc_hwmtx); 337 SIGCHG(dummy, sig, SER_CTS, SER_DCTS); 338 SIGCHG(dummy, sig, SER_DCD, SER_DDCD); 339 SIGCHG(dummy, sig, SER_DSR, SER_DDSR); 340 new = sig & ~SER_MASK_DELTA; 341 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 342 return (sig); 343 } 344 345 static int 346 quicc_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 347 { 348 struct uart_bas *bas; 349 uint32_t brg; 350 int baudrate, error; 351 352 bas = &sc->sc_bas; 353 error = 0; 354 uart_lock(sc->sc_hwmtx); 355 switch (request) { 356 case UART_IOCTL_BREAK: 357 break; 358 case UART_IOCTL_BAUD: 359 brg = quicc_read4(bas, QUICC_REG_BRG(bas->chan - 1)) & 0x1fff; 360 brg = (brg & 1) ? (brg + 1) << 3 : (brg + 2) >> 1; 361 baudrate = bas->rclk / (brg * 16); 362 *(int*)data = baudrate; 363 break; 364 default: 365 error = EINVAL; 366 break; 367 } 368 uart_unlock(sc->sc_hwmtx); 369 return (error); 370 } 371 372 static int 373 quicc_bus_ipend(struct uart_softc *sc) 374 { 375 struct uart_bas *bas; 376 int ipend; 377 uint16_t scce; 378 379 bas = &sc->sc_bas; 380 ipend = 0; 381 382 uart_lock(sc->sc_hwmtx); 383 scce = quicc_read2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1)); 384 quicc_write2(bas, QUICC_REG_SCC_SCCE(bas->chan - 1), ~0); 385 uart_unlock(sc->sc_hwmtx); 386 if (scce & 0x0001) 387 ipend |= SER_INT_RXREADY; 388 if (scce & 0x0002) 389 ipend |= SER_INT_TXIDLE; 390 if (scce & 0x0004) 391 ipend |= SER_INT_OVERRUN; 392 if (scce & 0x0020) 393 ipend |= SER_INT_BREAK; 394 /* XXX SIGNALS */ 395 return (ipend); 396 } 397 398 static int 399 quicc_bus_param(struct uart_softc *sc, int baudrate, int databits, 400 int stopbits, int parity) 401 { 402 int error; 403 404 uart_lock(sc->sc_hwmtx); 405 error = quicc_param(&sc->sc_bas, baudrate, databits, stopbits, 406 parity); 407 uart_unlock(sc->sc_hwmtx); 408 return (error); 409 } 410 411 static int 412 quicc_bus_probe(struct uart_softc *sc) 413 { 414 char buf[80]; 415 int error; 416 417 error = quicc_probe(&sc->sc_bas); 418 if (error) 419 return (error); 420 421 sc->sc_rxfifosz = 1; 422 sc->sc_txfifosz = 1; 423 424 snprintf(buf, sizeof(buf), "quicc, channel %d", sc->sc_bas.chan); 425 device_set_desc_copy(sc->sc_dev, buf); 426 return (0); 427 } 428 429 static int 430 quicc_bus_receive(struct uart_softc *sc) 431 { 432 struct uart_bas *bas; 433 volatile char *buf; 434 uint16_t st, rb; 435 436 bas = &sc->sc_bas; 437 uart_lock(sc->sc_hwmtx); 438 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 439 st = quicc_read2(bas, rb); 440 buf = (void *)(uintptr_t)quicc_read4(bas, rb + 4); 441 uart_rx_put(sc, *buf); 442 quicc_write2(bas, rb, st | 0x9000); 443 uart_unlock(sc->sc_hwmtx); 444 return (0); 445 } 446 447 static int 448 quicc_bus_setsig(struct uart_softc *sc, int sig) 449 { 450 struct uart_bas *bas; 451 uint32_t new, old; 452 453 bas = &sc->sc_bas; 454 do { 455 old = sc->sc_hwsig; 456 new = old; 457 if (sig & SER_DDTR) { 458 SIGCHG(sig & SER_DTR, new, SER_DTR, 459 SER_DDTR); 460 } 461 if (sig & SER_DRTS) { 462 SIGCHG(sig & SER_RTS, new, SER_RTS, 463 SER_DRTS); 464 } 465 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 466 467 uart_lock(sc->sc_hwmtx); 468 /* XXX SIGNALS */ 469 uart_unlock(sc->sc_hwmtx); 470 return (0); 471 } 472 473 static int 474 quicc_bus_transmit(struct uart_softc *sc) 475 { 476 volatile char *buf; 477 struct uart_bas *bas; 478 uint16_t st, tb; 479 480 bas = &sc->sc_bas; 481 uart_lock(sc->sc_hwmtx); 482 tb = quicc_read2(bas, QUICC_PRAM_SCC_TBASE(bas->chan - 1)); 483 st = quicc_read2(bas, tb); 484 buf = (void *)(uintptr_t)quicc_read4(bas, tb + 4); 485 *buf = sc->sc_txbuf[0]; 486 quicc_write2(bas, tb + 2, 1); 487 quicc_write2(bas, tb, st | 0x9000); 488 sc->sc_txbusy = 1; 489 uart_unlock(sc->sc_hwmtx); 490 return (0); 491 } 492 493 static void 494 quicc_bus_grab(struct uart_softc *sc) 495 { 496 struct uart_bas *bas; 497 uint16_t st, rb; 498 499 /* Disable interrupts on the receive buffer. */ 500 bas = &sc->sc_bas; 501 uart_lock(sc->sc_hwmtx); 502 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 503 st = quicc_read2(bas, rb); 504 quicc_write2(bas, rb, st & ~0x9000); 505 uart_unlock(sc->sc_hwmtx); 506 } 507 508 static void 509 quicc_bus_ungrab(struct uart_softc *sc) 510 { 511 struct uart_bas *bas; 512 uint16_t st, rb; 513 514 /* Enable interrupts on the receive buffer. */ 515 bas = &sc->sc_bas; 516 uart_lock(sc->sc_hwmtx); 517 rb = quicc_read2(bas, QUICC_PRAM_SCC_RBASE(bas->chan - 1)); 518 st = quicc_read2(bas, rb); 519 quicc_write2(bas, rb, st | 0x9000); 520 uart_unlock(sc->sc_hwmtx); 521 } 522 523