1 /* 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_UART_DEV_NS8250_H_ 30 #define _DEV_UART_DEV_NS8250_H_ 31 32 /* Enhanced Feature Register. */ 33 #define EFR_CTS 0x80 34 #define EFR_RTS 0x40 35 #define EFR_SCD 0x20 /* Special Character Detect. */ 36 #define EFR_EFC 0x10 /* Enhanced Function Control. */ 37 #define EFR_SFC_MASK 0x0f /* Software Flow Control. */ 38 #define EFR_SFC_TX12 0x0c /* BIT: Transmit XON1+2/XOFF1+2. */ 39 #define EFR_SFC_TX1 0x08 /* BIT: Transmit XON1/XOFF1. */ 40 #define EFR_SFC_TX2 0x04 /* BIT: Transmit XON2/XOFF2. */ 41 #define EFR_SFC_RX1 0x02 /* BIT: Receive XON1/XOFF1. */ 42 #define EFR_SFC_RX2 0x01 /* BIT: Receive XON2/XOFF2. */ 43 #define EFR_SFC_T12R12 0x0f /* VAL: TX 1+2, RX 1+2. */ 44 #define EFR_SFC_T1R12 0x0b /* VAL: TX 1, RX 1+2. */ 45 #define EFR_SFC_T2R12 0x07 /* VAL: TX 2, RX 1+2. */ 46 47 /* FIFO Control Register. */ 48 #define FCR_RX_HIGH 0xc0 49 #define FCR_RX_MEDH 0x80 50 #define FCR_RX_MEDL 0x40 51 #define FCR_RX_LOW 0x00 52 #define FCR_TX_HIGH 0x30 53 #define FCR_TX_MEDH 0x20 54 #define FCR_TX_LOW 0x10 55 #define FCR_TX_MEDL 0x00 56 #define FCR_DMA 0x08 57 #define FCR_XMT_RST 0x04 58 #define FCR_RCV_RST 0x02 59 #define FCR_ENABLE 0x01 60 61 /* Interrupt Enable Register. */ 62 #define IER_CTS 0x80 63 #define IER_RTS 0x40 64 #define IER_XOFF 0x20 65 #define IER_SLEEP 0x10 66 #define IER_EMSC 0x08 67 #define IER_ERLS 0x04 68 #define IER_ETXRDY 0x02 69 #define IER_ERXRDY 0x01 70 71 /* Interrupt Identification Register. */ 72 #define IIR_FIFO_MASK 0xc0 73 #define IIR_RTSCTS 0x20 74 #define IIR_XOFF 0x10 75 #define IIR_IMASK 0x0f 76 #define IIR_RXTOUT 0x0c 77 #define IIR_RLS 0x06 78 #define IIR_RXRDY 0x04 79 #define IIR_TXRDY 0x02 80 #define IIR_MLSC 0x00 81 #define IIR_NOPEND 0x01 82 83 /* Line Control Register. */ 84 #define LCR_DLAB 0x80 85 #define LCR_SBREAK 0x40 86 #define LCR_PZERO 0x30 87 #define LCR_PONE 0x20 88 #define LCR_PEVEN 0x10 89 #define LCR_PODD 0x00 90 #define LCR_PENAB 0x08 91 #define LCR_STOPB 0x04 92 #define LCR_8BITS 0x03 93 #define LCR_7BITS 0x02 94 #define LCR_6BITS 0x01 95 #define LCR_5BITS 0x00 96 97 /* Line Status Register. */ 98 #define LSR_DERR 0x80 99 #define LSR_TEMT 0x40 /* Transmitter Empty. */ 100 #define LSR_THRE 0x20 /* Transmitter Holding Register Empty. */ 101 #define LSR_BI 0x10 102 #define LSR_FE 0x08 103 #define LSR_PE 0x04 104 #define LSR_OE 0x02 105 #define LSR_RXRDY 0x01 106 107 /* Modem Control Register. */ 108 #define MCR_CS 0x80 109 #define MCR_IRE 0x40 110 #define MCR_ISEL 0x20 111 #define MCR_LOOPBACK 0x10 112 #define MCR_IE 0x08 113 #define MCR_LBDCD MCR_IE 114 #define MCR_LBRI 0x04 115 #define MCR_RTS 0x02 116 #define MCR_DTR 0x01 117 118 /* Modem Status Register. */ 119 #define MSR_DCD 0x80 120 #define MSR_RI 0x40 121 #define MSR_DSR 0x20 122 #define MSR_CTS 0x10 123 #define MSR_DDCD 0x08 124 #define MSR_TERI 0x04 125 #define MSR_DDSR 0x02 126 #define MSR_DCTS 0x01 127 128 /* General registers. */ 129 #define REG_DATA 0 /* Data Register. */ 130 #define REG_RBR REG_DATA /* Receiver Buffer Register (R). */ 131 #define REG_THR REG_DATA /* Transmitter Holding Register (W). */ 132 #define REG_IER 1 /* Interrupt Enable Register */ 133 #define REG_IIR 2 /* Interrupt Ident. Register (R). */ 134 #define REG_FCR 2 /* FIFO Control Register (W). */ 135 #define REG_LCR 3 /* Line Control Register. */ 136 #define REG_MCR 4 /* Modem Control Register. */ 137 #define REG_LSR 5 /* Line Status Register. */ 138 #define REG_MSR 6 /* Modem Status Register. */ 139 #define REG_SPR 7 /* Scratch Pad Register. */ 140 141 /* Baudrate registers (LCR[7] = 1). */ 142 #define REG_DLBL 0 /* Divisor Latch (LSB). */ 143 #define REG_DLBH 1 /* Divisor Latch (MSB). */ 144 #define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */ 145 146 /* Enhanced registers (LCR = 0xBF). */ 147 #define REG_EFR 2 /* Enhanced Feature Register. */ 148 #define REG_XON1 4 /* XON character 1. */ 149 #define REG_XON2 5 /* XON character 2. */ 150 #define REG_XOFF1 6 /* XOFF character 1. */ 151 #define REG_XOFF2 7 /* XOFF character 2. */ 152 153 #endif /* _DEV_UART_DEV_NS8250_H_ */ 154