1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 #include "opt_uart.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 56 #include <dev/ic/ns16550.h> 57 58 #include "uart_if.h" 59 60 #define DEFAULT_RCLK 1843200 61 62 /* 63 * Set the default baudrate tolerance to 3.0%. 64 * 65 * Some embedded boards have odd reference clocks (eg 25MHz) 66 * and we need to handle higher variances in the target baud rate. 67 */ 68 #ifndef UART_DEV_TOLERANCE_PCT 69 #define UART_DEV_TOLERANCE_PCT 30 70 #endif /* UART_DEV_TOLERANCE_PCT */ 71 72 static int broken_txfifo = 0; 73 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75 76 /* 77 * Clear pending interrupts. THRE is cleared by reading IIR. Data 78 * that may have been received gets lost here. 79 */ 80 static void 81 ns8250_clrint(struct uart_bas *bas) 82 { 83 uint8_t iir, lsr; 84 85 iir = uart_getreg(bas, REG_IIR); 86 while ((iir & IIR_NOPEND) == 0) { 87 iir &= IIR_IMASK; 88 if (iir == IIR_RLS) { 89 lsr = uart_getreg(bas, REG_LSR); 90 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91 (void)uart_getreg(bas, REG_DATA); 92 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 93 (void)uart_getreg(bas, REG_DATA); 94 else if (iir == IIR_MLSC) 95 (void)uart_getreg(bas, REG_MSR); 96 uart_barrier(bas); 97 iir = uart_getreg(bas, REG_IIR); 98 } 99 } 100 101 static int 102 ns8250_delay(struct uart_bas *bas) 103 { 104 int divisor; 105 u_char lcr; 106 107 lcr = uart_getreg(bas, REG_LCR); 108 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 109 uart_barrier(bas); 110 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 111 uart_barrier(bas); 112 uart_setreg(bas, REG_LCR, lcr); 113 uart_barrier(bas); 114 115 /* 1/10th the time to transmit 1 character (estimate). */ 116 if (divisor <= 134) 117 return (16000000 * divisor / bas->rclk); 118 return (16000 * divisor / (bas->rclk / 1000)); 119 } 120 121 static int 122 ns8250_divisor(int rclk, int baudrate) 123 { 124 int actual_baud, divisor; 125 int error; 126 127 if (baudrate == 0) 128 return (0); 129 130 divisor = (rclk / (baudrate << 3) + 1) >> 1; 131 if (divisor == 0 || divisor >= 65536) 132 return (0); 133 actual_baud = rclk / (divisor << 4); 134 135 /* 10 times error in percent: */ 136 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 137 138 /* enforce maximum error tolerance: */ 139 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 140 return (0); 141 142 return (divisor); 143 } 144 145 static int 146 ns8250_drain(struct uart_bas *bas, int what) 147 { 148 int delay, limit; 149 150 delay = ns8250_delay(bas); 151 152 if (what & UART_DRAIN_TRANSMITTER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs. 157 */ 158 limit = 10*1024; 159 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 160 DELAY(delay); 161 if (limit == 0) { 162 /* printf("ns8250: transmitter appears stuck... "); */ 163 return (EIO); 164 } 165 } 166 167 if (what & UART_DRAIN_RECEIVER) { 168 /* 169 * Pick an arbitrary high limit to avoid getting stuck in 170 * an infinite loop when the hardware is broken. Make the 171 * limit high enough to handle large FIFOs and integrated 172 * UARTs. The HP rx2600 for example has 3 UARTs on the 173 * management board that tend to get a lot of data send 174 * to it when the UART is first activated. 175 */ 176 limit=10*4096; 177 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 178 (void)uart_getreg(bas, REG_DATA); 179 uart_barrier(bas); 180 DELAY(delay << 2); 181 } 182 if (limit == 0) { 183 /* printf("ns8250: receiver appears broken... "); */ 184 return (EIO); 185 } 186 } 187 188 return (0); 189 } 190 191 /* 192 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 193 * drained. WARNING: this function clobbers the FIFO setting! 194 */ 195 static void 196 ns8250_flush(struct uart_bas *bas, int what) 197 { 198 uint8_t fcr; 199 200 fcr = FCR_ENABLE; 201 if (what & UART_FLUSH_TRANSMITTER) 202 fcr |= FCR_XMT_RST; 203 if (what & UART_FLUSH_RECEIVER) 204 fcr |= FCR_RCV_RST; 205 uart_setreg(bas, REG_FCR, fcr); 206 uart_barrier(bas); 207 } 208 209 static int 210 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 211 int parity) 212 { 213 int divisor; 214 uint8_t lcr; 215 216 lcr = 0; 217 if (databits >= 8) 218 lcr |= LCR_8BITS; 219 else if (databits == 7) 220 lcr |= LCR_7BITS; 221 else if (databits == 6) 222 lcr |= LCR_6BITS; 223 else 224 lcr |= LCR_5BITS; 225 if (stopbits > 1) 226 lcr |= LCR_STOPB; 227 lcr |= parity << 3; 228 229 /* Set baudrate. */ 230 if (baudrate > 0) { 231 divisor = ns8250_divisor(bas->rclk, baudrate); 232 if (divisor == 0) 233 return (EINVAL); 234 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 235 uart_barrier(bas); 236 uart_setreg(bas, REG_DLL, divisor & 0xff); 237 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 238 uart_barrier(bas); 239 } 240 241 /* Set LCR and clear DLAB. */ 242 uart_setreg(bas, REG_LCR, lcr); 243 uart_barrier(bas); 244 return (0); 245 } 246 247 /* 248 * Low-level UART interface. 249 */ 250 static int ns8250_probe(struct uart_bas *bas); 251 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 252 static void ns8250_term(struct uart_bas *bas); 253 static void ns8250_putc(struct uart_bas *bas, int); 254 static int ns8250_rxready(struct uart_bas *bas); 255 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 256 257 struct uart_ops uart_ns8250_ops = { 258 .probe = ns8250_probe, 259 .init = ns8250_init, 260 .term = ns8250_term, 261 .putc = ns8250_putc, 262 .rxready = ns8250_rxready, 263 .getc = ns8250_getc, 264 }; 265 266 static int 267 ns8250_probe(struct uart_bas *bas) 268 { 269 u_char val; 270 271 /* Check known 0 bits that don't depend on DLAB. */ 272 val = uart_getreg(bas, REG_IIR); 273 if (val & 0x30) 274 return (ENXIO); 275 /* 276 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 277 * chip, but otherwise doesn't seem to have a function. In 278 * other words, uart(4) works regardless. Ignore that bit so 279 * the probe succeeds. 280 */ 281 val = uart_getreg(bas, REG_MCR); 282 if (val & 0xa0) 283 return (ENXIO); 284 285 return (0); 286 } 287 288 static void 289 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 290 int parity) 291 { 292 u_char ier; 293 294 if (bas->rclk == 0) 295 bas->rclk = DEFAULT_RCLK; 296 ns8250_param(bas, baudrate, databits, stopbits, parity); 297 298 /* Disable all interrupt sources. */ 299 /* 300 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 301 * UARTs split the receive time-out interrupt bit out separately as 302 * 0x10. This gets handled by ier_mask and ier_rxbits below. 303 */ 304 ier = uart_getreg(bas, REG_IER) & 0xe0; 305 uart_setreg(bas, REG_IER, ier); 306 uart_barrier(bas); 307 308 /* Disable the FIFO (if present). */ 309 uart_setreg(bas, REG_FCR, 0); 310 uart_barrier(bas); 311 312 /* Set RTS & DTR. */ 313 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 314 uart_barrier(bas); 315 316 ns8250_clrint(bas); 317 } 318 319 static void 320 ns8250_term(struct uart_bas *bas) 321 { 322 323 /* Clear RTS & DTR. */ 324 uart_setreg(bas, REG_MCR, MCR_IE); 325 uart_barrier(bas); 326 } 327 328 static void 329 ns8250_putc(struct uart_bas *bas, int c) 330 { 331 int limit; 332 333 limit = 250000; 334 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 335 DELAY(4); 336 uart_setreg(bas, REG_DATA, c); 337 uart_barrier(bas); 338 limit = 250000; 339 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 340 DELAY(4); 341 } 342 343 static int 344 ns8250_rxready(struct uart_bas *bas) 345 { 346 347 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 348 } 349 350 static int 351 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 352 { 353 int c; 354 355 uart_lock(hwmtx); 356 357 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 358 uart_unlock(hwmtx); 359 DELAY(4); 360 uart_lock(hwmtx); 361 } 362 363 c = uart_getreg(bas, REG_DATA); 364 365 uart_unlock(hwmtx); 366 367 return (c); 368 } 369 370 static kobj_method_t ns8250_methods[] = { 371 KOBJMETHOD(uart_attach, ns8250_bus_attach), 372 KOBJMETHOD(uart_detach, ns8250_bus_detach), 373 KOBJMETHOD(uart_flush, ns8250_bus_flush), 374 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 375 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 376 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 377 KOBJMETHOD(uart_param, ns8250_bus_param), 378 KOBJMETHOD(uart_probe, ns8250_bus_probe), 379 KOBJMETHOD(uart_receive, ns8250_bus_receive), 380 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 381 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 382 KOBJMETHOD(uart_grab, ns8250_bus_grab), 383 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 384 { 0, 0 } 385 }; 386 387 struct uart_class uart_ns8250_class = { 388 "ns8250", 389 ns8250_methods, 390 sizeof(struct ns8250_softc), 391 .uc_ops = &uart_ns8250_ops, 392 .uc_range = 8, 393 .uc_rclk = DEFAULT_RCLK, 394 .uc_rshift = 0 395 }; 396 397 #ifdef FDT 398 static struct ofw_compat_data compat_data[] = { 399 {"ns16550", (uintptr_t)&uart_ns8250_class}, 400 {NULL, (uintptr_t)NULL}, 401 }; 402 UART_FDT_CLASS_AND_DEVICE(compat_data); 403 #endif 404 405 /* Use token-pasting to form SER_ and MSR_ named constants. */ 406 #define SER(sig) SER_##sig 407 #define SERD(sig) SER_D##sig 408 #define MSR(sig) MSR_##sig 409 #define MSRD(sig) MSR_D##sig 410 411 /* 412 * Detect signal changes using software delta detection. The previous state of 413 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 414 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 415 * new state of both the signal and the delta bits. 416 */ 417 #define SIGCHGSW(var, msr, sig) \ 418 if ((msr) & MSR(sig)) { \ 419 if ((var & SER(sig)) == 0) \ 420 var |= SERD(sig) | SER(sig); \ 421 } else { \ 422 if ((var & SER(sig)) != 0) \ 423 var = SERD(sig) | (var & ~SER(sig)); \ 424 } 425 426 /* 427 * Detect signal changes using the hardware msr delta bits. This is currently 428 * used only when PPS timing information is being captured using the "narrow 429 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 430 * by time the interrupt handler is invoked. The hardware will latch the fact 431 * that it changed in the delta bits. 432 */ 433 #define SIGCHGHW(var, msr, sig) \ 434 if ((msr) & MSRD(sig)) { \ 435 if (((msr) & MSR(sig)) != 0) \ 436 var |= SERD(sig) | SER(sig); \ 437 else \ 438 var = SERD(sig) | (var & ~SER(sig)); \ 439 } 440 441 int 442 ns8250_bus_attach(struct uart_softc *sc) 443 { 444 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 445 struct uart_bas *bas; 446 unsigned int ivar; 447 #ifdef FDT 448 phandle_t node; 449 pcell_t cell; 450 #endif 451 452 ns8250->busy_detect = 0; 453 454 #ifdef FDT 455 /* 456 * Check whether uart requires to read USR reg when IIR_BUSY and 457 * has broken txfifo. 458 */ 459 node = ofw_bus_get_node(sc->sc_dev); 460 if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 461 ns8250->busy_detect = cell ? 1 : 0; 462 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 463 broken_txfifo = cell ? 1 : 0; 464 #endif 465 466 bas = &sc->sc_bas; 467 468 ns8250->mcr = uart_getreg(bas, REG_MCR); 469 ns8250->fcr = FCR_ENABLE; 470 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 471 &ivar)) { 472 if (UART_FLAGS_FCR_RX_LOW(ivar)) 473 ns8250->fcr |= FCR_RX_LOW; 474 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 475 ns8250->fcr |= FCR_RX_MEDL; 476 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 477 ns8250->fcr |= FCR_RX_HIGH; 478 else 479 ns8250->fcr |= FCR_RX_MEDH; 480 } else 481 ns8250->fcr |= FCR_RX_MEDH; 482 483 /* Get IER mask */ 484 ivar = 0xf0; 485 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 486 &ivar); 487 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 488 489 /* Get IER RX interrupt bits */ 490 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 491 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 492 &ivar); 493 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 494 495 uart_setreg(bas, REG_FCR, ns8250->fcr); 496 uart_barrier(bas); 497 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 498 499 if (ns8250->mcr & MCR_DTR) 500 sc->sc_hwsig |= SER_DTR; 501 if (ns8250->mcr & MCR_RTS) 502 sc->sc_hwsig |= SER_RTS; 503 ns8250_bus_getsig(sc); 504 505 ns8250_clrint(bas); 506 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 507 ns8250->ier |= ns8250->ier_rxbits; 508 uart_setreg(bas, REG_IER, ns8250->ier); 509 uart_barrier(bas); 510 511 /* 512 * Timing of the H/W access was changed with r253161 of uart_core.c 513 * It has been observed that an ITE IT8513E would signal a break 514 * condition with pretty much every character it received, unless 515 * it had enough time to settle between ns8250_bus_attach() and 516 * ns8250_bus_ipend() -- which it accidentally had before r253161. 517 * It's not understood why the UART chip behaves this way and it 518 * could very well be that the DELAY make the H/W work in the same 519 * accidental manner as before. More analysis is warranted, but 520 * at least now we fixed a known regression. 521 */ 522 DELAY(200); 523 return (0); 524 } 525 526 int 527 ns8250_bus_detach(struct uart_softc *sc) 528 { 529 struct ns8250_softc *ns8250; 530 struct uart_bas *bas; 531 u_char ier; 532 533 ns8250 = (struct ns8250_softc *)sc; 534 bas = &sc->sc_bas; 535 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 536 uart_setreg(bas, REG_IER, ier); 537 uart_barrier(bas); 538 ns8250_clrint(bas); 539 return (0); 540 } 541 542 int 543 ns8250_bus_flush(struct uart_softc *sc, int what) 544 { 545 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 546 struct uart_bas *bas; 547 int error; 548 549 bas = &sc->sc_bas; 550 uart_lock(sc->sc_hwmtx); 551 if (sc->sc_rxfifosz > 1) { 552 ns8250_flush(bas, what); 553 uart_setreg(bas, REG_FCR, ns8250->fcr); 554 uart_barrier(bas); 555 error = 0; 556 } else 557 error = ns8250_drain(bas, what); 558 uart_unlock(sc->sc_hwmtx); 559 return (error); 560 } 561 562 int 563 ns8250_bus_getsig(struct uart_softc *sc) 564 { 565 uint32_t old, sig; 566 uint8_t msr; 567 568 /* 569 * The delta bits are reputed to be broken on some hardware, so use 570 * software delta detection by default. Use the hardware delta bits 571 * when capturing PPS pulses which are too narrow for software detection 572 * to see the edges. Hardware delta for RI doesn't work like the 573 * others, so always use software for it. Other threads may be changing 574 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully 575 * update without other changes happening. Note that the SIGCHGxx() 576 * macros carefully preserve the delta bits when we have to loop several 577 * times and a signal transitions between iterations. 578 */ 579 do { 580 old = sc->sc_hwsig; 581 sig = old; 582 uart_lock(sc->sc_hwmtx); 583 msr = uart_getreg(&sc->sc_bas, REG_MSR); 584 uart_unlock(sc->sc_hwmtx); 585 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 586 SIGCHGHW(sig, msr, DSR); 587 SIGCHGHW(sig, msr, CTS); 588 SIGCHGHW(sig, msr, DCD); 589 } else { 590 SIGCHGSW(sig, msr, DSR); 591 SIGCHGSW(sig, msr, CTS); 592 SIGCHGSW(sig, msr, DCD); 593 } 594 SIGCHGSW(sig, msr, RI); 595 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 596 return (sig); 597 } 598 599 int 600 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 601 { 602 struct uart_bas *bas; 603 int baudrate, divisor, error; 604 uint8_t efr, lcr; 605 606 bas = &sc->sc_bas; 607 error = 0; 608 uart_lock(sc->sc_hwmtx); 609 switch (request) { 610 case UART_IOCTL_BREAK: 611 lcr = uart_getreg(bas, REG_LCR); 612 if (data) 613 lcr |= LCR_SBREAK; 614 else 615 lcr &= ~LCR_SBREAK; 616 uart_setreg(bas, REG_LCR, lcr); 617 uart_barrier(bas); 618 break; 619 case UART_IOCTL_IFLOW: 620 lcr = uart_getreg(bas, REG_LCR); 621 uart_barrier(bas); 622 uart_setreg(bas, REG_LCR, 0xbf); 623 uart_barrier(bas); 624 efr = uart_getreg(bas, REG_EFR); 625 if (data) 626 efr |= EFR_RTS; 627 else 628 efr &= ~EFR_RTS; 629 uart_setreg(bas, REG_EFR, efr); 630 uart_barrier(bas); 631 uart_setreg(bas, REG_LCR, lcr); 632 uart_barrier(bas); 633 break; 634 case UART_IOCTL_OFLOW: 635 lcr = uart_getreg(bas, REG_LCR); 636 uart_barrier(bas); 637 uart_setreg(bas, REG_LCR, 0xbf); 638 uart_barrier(bas); 639 efr = uart_getreg(bas, REG_EFR); 640 if (data) 641 efr |= EFR_CTS; 642 else 643 efr &= ~EFR_CTS; 644 uart_setreg(bas, REG_EFR, efr); 645 uart_barrier(bas); 646 uart_setreg(bas, REG_LCR, lcr); 647 uart_barrier(bas); 648 break; 649 case UART_IOCTL_BAUD: 650 lcr = uart_getreg(bas, REG_LCR); 651 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 652 uart_barrier(bas); 653 divisor = uart_getreg(bas, REG_DLL) | 654 (uart_getreg(bas, REG_DLH) << 8); 655 uart_barrier(bas); 656 uart_setreg(bas, REG_LCR, lcr); 657 uart_barrier(bas); 658 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 659 if (baudrate > 0) 660 *(int*)data = baudrate; 661 else 662 error = ENXIO; 663 break; 664 default: 665 error = EINVAL; 666 break; 667 } 668 uart_unlock(sc->sc_hwmtx); 669 return (error); 670 } 671 672 int 673 ns8250_bus_ipend(struct uart_softc *sc) 674 { 675 struct uart_bas *bas; 676 struct ns8250_softc *ns8250; 677 int ipend; 678 uint8_t iir, lsr; 679 680 ns8250 = (struct ns8250_softc *)sc; 681 bas = &sc->sc_bas; 682 uart_lock(sc->sc_hwmtx); 683 iir = uart_getreg(bas, REG_IIR); 684 685 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 686 (void)uart_getreg(bas, DW_REG_USR); 687 uart_unlock(sc->sc_hwmtx); 688 return (0); 689 } 690 if (iir & IIR_NOPEND) { 691 uart_unlock(sc->sc_hwmtx); 692 return (0); 693 } 694 ipend = 0; 695 if (iir & IIR_RXRDY) { 696 lsr = uart_getreg(bas, REG_LSR); 697 if (lsr & LSR_OE) 698 ipend |= SER_INT_OVERRUN; 699 if (lsr & LSR_BI) 700 ipend |= SER_INT_BREAK; 701 if (lsr & LSR_RXRDY) 702 ipend |= SER_INT_RXREADY; 703 } else { 704 if (iir & IIR_TXRDY) { 705 ipend |= SER_INT_TXIDLE; 706 uart_setreg(bas, REG_IER, ns8250->ier); 707 } else 708 ipend |= SER_INT_SIGCHG; 709 } 710 if (ipend == 0) 711 ns8250_clrint(bas); 712 uart_unlock(sc->sc_hwmtx); 713 return (ipend); 714 } 715 716 int 717 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 718 int stopbits, int parity) 719 { 720 struct ns8250_softc *ns8250; 721 struct uart_bas *bas; 722 int error, limit; 723 724 ns8250 = (struct ns8250_softc*)sc; 725 bas = &sc->sc_bas; 726 uart_lock(sc->sc_hwmtx); 727 /* 728 * When using DW UART with BUSY detection it is necessary to wait 729 * until all serial transfers are finished before manipulating the 730 * line control. LCR will not be affected when UART is busy. 731 */ 732 if (ns8250->busy_detect != 0) { 733 /* 734 * Pick an arbitrary high limit to avoid getting stuck in 735 * an infinite loop in case when the hardware is broken. 736 */ 737 limit = 10 * 1024; 738 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 739 --limit) 740 DELAY(4); 741 742 if (limit <= 0) { 743 /* UART appears to be stuck */ 744 uart_unlock(sc->sc_hwmtx); 745 return (EIO); 746 } 747 } 748 749 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 750 uart_unlock(sc->sc_hwmtx); 751 return (error); 752 } 753 754 int 755 ns8250_bus_probe(struct uart_softc *sc) 756 { 757 struct ns8250_softc *ns8250; 758 struct uart_bas *bas; 759 int count, delay, error, limit; 760 uint8_t lsr, mcr, ier; 761 762 ns8250 = (struct ns8250_softc *)sc; 763 bas = &sc->sc_bas; 764 765 error = ns8250_probe(bas); 766 if (error) 767 return (error); 768 769 mcr = MCR_IE; 770 if (sc->sc_sysdev == NULL) { 771 /* By using ns8250_init() we also set DTR and RTS. */ 772 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 773 } else 774 mcr |= MCR_DTR | MCR_RTS; 775 776 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 777 if (error) 778 return (error); 779 780 /* 781 * Set loopback mode. This avoids having garbage on the wire and 782 * also allows us send and receive data. We set DTR and RTS to 783 * avoid the possibility that automatic flow-control prevents 784 * any data from being sent. 785 */ 786 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 787 uart_barrier(bas); 788 789 /* 790 * Enable FIFOs. And check that the UART has them. If not, we're 791 * done. Since this is the first time we enable the FIFOs, we reset 792 * them. 793 */ 794 uart_setreg(bas, REG_FCR, FCR_ENABLE); 795 uart_barrier(bas); 796 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 797 /* 798 * NS16450 or INS8250. We don't bother to differentiate 799 * between them. They're too old to be interesting. 800 */ 801 uart_setreg(bas, REG_MCR, mcr); 802 uart_barrier(bas); 803 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 804 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 805 return (0); 806 } 807 808 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 809 uart_barrier(bas); 810 811 count = 0; 812 delay = ns8250_delay(bas); 813 814 /* We have FIFOs. Drain the transmitter and receiver. */ 815 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 816 if (error) { 817 uart_setreg(bas, REG_MCR, mcr); 818 uart_setreg(bas, REG_FCR, 0); 819 uart_barrier(bas); 820 goto describe; 821 } 822 823 /* 824 * We should have a sufficiently clean "pipe" to determine the 825 * size of the FIFOs. We send as much characters as is reasonable 826 * and wait for the overflow bit in the LSR register to be 827 * asserted, counting the characters as we send them. Based on 828 * that count we know the FIFO size. 829 */ 830 do { 831 uart_setreg(bas, REG_DATA, 0); 832 uart_barrier(bas); 833 count++; 834 835 limit = 30; 836 lsr = 0; 837 /* 838 * LSR bits are cleared upon read, so we must accumulate 839 * them to be able to test LSR_OE below. 840 */ 841 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 842 --limit) 843 DELAY(delay); 844 if (limit == 0) { 845 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 846 uart_setreg(bas, REG_IER, ier); 847 uart_setreg(bas, REG_MCR, mcr); 848 uart_setreg(bas, REG_FCR, 0); 849 uart_barrier(bas); 850 count = 0; 851 goto describe; 852 } 853 } while ((lsr & LSR_OE) == 0 && count < 130); 854 count--; 855 856 uart_setreg(bas, REG_MCR, mcr); 857 858 /* Reset FIFOs. */ 859 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 860 861 describe: 862 if (count >= 14 && count <= 16) { 863 sc->sc_rxfifosz = 16; 864 device_set_desc(sc->sc_dev, "16550 or compatible"); 865 } else if (count >= 28 && count <= 32) { 866 sc->sc_rxfifosz = 32; 867 device_set_desc(sc->sc_dev, "16650 or compatible"); 868 } else if (count >= 56 && count <= 64) { 869 sc->sc_rxfifosz = 64; 870 device_set_desc(sc->sc_dev, "16750 or compatible"); 871 } else if (count >= 112 && count <= 128) { 872 sc->sc_rxfifosz = 128; 873 device_set_desc(sc->sc_dev, "16950 or compatible"); 874 } else { 875 sc->sc_rxfifosz = 16; 876 device_set_desc(sc->sc_dev, 877 "Non-standard ns8250 class UART with FIFOs"); 878 } 879 880 /* 881 * Force the Tx FIFO size to 16 bytes for now. We don't program the 882 * Tx trigger. Also, we assume that all data has been sent when the 883 * interrupt happens. 884 */ 885 sc->sc_txfifosz = 16; 886 887 #if 0 888 /* 889 * XXX there are some issues related to hardware flow control and 890 * it's likely that uart(4) is the cause. This basicly needs more 891 * investigation, but we avoid using for hardware flow control 892 * until then. 893 */ 894 /* 16650s or higher have automatic flow control. */ 895 if (sc->sc_rxfifosz > 16) { 896 sc->sc_hwiflow = 1; 897 sc->sc_hwoflow = 1; 898 } 899 #endif 900 901 return (0); 902 } 903 904 int 905 ns8250_bus_receive(struct uart_softc *sc) 906 { 907 struct uart_bas *bas; 908 int xc; 909 uint8_t lsr; 910 911 bas = &sc->sc_bas; 912 uart_lock(sc->sc_hwmtx); 913 lsr = uart_getreg(bas, REG_LSR); 914 while (lsr & LSR_RXRDY) { 915 if (uart_rx_full(sc)) { 916 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 917 break; 918 } 919 xc = uart_getreg(bas, REG_DATA); 920 if (lsr & LSR_FE) 921 xc |= UART_STAT_FRAMERR; 922 if (lsr & LSR_PE) 923 xc |= UART_STAT_PARERR; 924 uart_rx_put(sc, xc); 925 lsr = uart_getreg(bas, REG_LSR); 926 } 927 /* Discard everything left in the Rx FIFO. */ 928 while (lsr & LSR_RXRDY) { 929 (void)uart_getreg(bas, REG_DATA); 930 uart_barrier(bas); 931 lsr = uart_getreg(bas, REG_LSR); 932 } 933 uart_unlock(sc->sc_hwmtx); 934 return (0); 935 } 936 937 int 938 ns8250_bus_setsig(struct uart_softc *sc, int sig) 939 { 940 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 941 struct uart_bas *bas; 942 uint32_t new, old; 943 944 bas = &sc->sc_bas; 945 do { 946 old = sc->sc_hwsig; 947 new = old; 948 if (sig & SER_DDTR) { 949 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 950 } 951 if (sig & SER_DRTS) { 952 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 953 } 954 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 955 uart_lock(sc->sc_hwmtx); 956 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 957 if (new & SER_DTR) 958 ns8250->mcr |= MCR_DTR; 959 if (new & SER_RTS) 960 ns8250->mcr |= MCR_RTS; 961 uart_setreg(bas, REG_MCR, ns8250->mcr); 962 uart_barrier(bas); 963 uart_unlock(sc->sc_hwmtx); 964 return (0); 965 } 966 967 int 968 ns8250_bus_transmit(struct uart_softc *sc) 969 { 970 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 971 struct uart_bas *bas; 972 int i; 973 974 bas = &sc->sc_bas; 975 uart_lock(sc->sc_hwmtx); 976 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 977 ; 978 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 979 uart_barrier(bas); 980 for (i = 0; i < sc->sc_txdatasz; i++) { 981 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 982 uart_barrier(bas); 983 } 984 if (broken_txfifo) 985 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 986 else 987 sc->sc_txbusy = 1; 988 uart_unlock(sc->sc_hwmtx); 989 if (broken_txfifo) 990 uart_sched_softih(sc, SER_INT_TXIDLE); 991 return (0); 992 } 993 994 void 995 ns8250_bus_grab(struct uart_softc *sc) 996 { 997 struct uart_bas *bas = &sc->sc_bas; 998 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 999 u_char ier; 1000 1001 /* 1002 * turn off all interrupts to enter polling mode. Leave the 1003 * saved mask alone. We'll restore whatever it was in ungrab. 1004 * All pending interupt signals are reset when IER is set to 0. 1005 */ 1006 uart_lock(sc->sc_hwmtx); 1007 ier = uart_getreg(bas, REG_IER); 1008 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1009 uart_barrier(bas); 1010 uart_unlock(sc->sc_hwmtx); 1011 } 1012 1013 void 1014 ns8250_bus_ungrab(struct uart_softc *sc) 1015 { 1016 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1017 struct uart_bas *bas = &sc->sc_bas; 1018 1019 /* 1020 * Restore previous interrupt mask 1021 */ 1022 uart_lock(sc->sc_hwmtx); 1023 uart_setreg(bas, REG_IER, ns8250->ier); 1024 uart_barrier(bas); 1025 uart_unlock(sc->sc_hwmtx); 1026 } 1027