1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/sysctl.h> 38 #include <machine/bus.h> 39 40 #ifdef FDT 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #endif 45 46 #include <dev/uart/uart.h> 47 #include <dev/uart/uart_cpu.h> 48 #ifdef FDT 49 #include <dev/uart/uart_cpu_fdt.h> 50 #endif 51 #include <dev/uart/uart_bus.h> 52 #include <dev/uart/uart_dev_ns8250.h> 53 54 #include <dev/ic/ns16550.h> 55 56 #include "uart_if.h" 57 58 #define DEFAULT_RCLK 1843200 59 60 static int broken_txfifo = 0; 61 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 62 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 63 64 /* 65 * Clear pending interrupts. THRE is cleared by reading IIR. Data 66 * that may have been received gets lost here. 67 */ 68 static void 69 ns8250_clrint(struct uart_bas *bas) 70 { 71 uint8_t iir, lsr; 72 73 iir = uart_getreg(bas, REG_IIR); 74 while ((iir & IIR_NOPEND) == 0) { 75 iir &= IIR_IMASK; 76 if (iir == IIR_RLS) { 77 lsr = uart_getreg(bas, REG_LSR); 78 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 79 (void)uart_getreg(bas, REG_DATA); 80 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 81 (void)uart_getreg(bas, REG_DATA); 82 else if (iir == IIR_MLSC) 83 (void)uart_getreg(bas, REG_MSR); 84 uart_barrier(bas); 85 iir = uart_getreg(bas, REG_IIR); 86 } 87 } 88 89 static int 90 ns8250_delay(struct uart_bas *bas) 91 { 92 int divisor; 93 u_char lcr; 94 95 lcr = uart_getreg(bas, REG_LCR); 96 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 97 uart_barrier(bas); 98 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 99 uart_barrier(bas); 100 uart_setreg(bas, REG_LCR, lcr); 101 uart_barrier(bas); 102 103 /* 1/10th the time to transmit 1 character (estimate). */ 104 if (divisor <= 134) 105 return (16000000 * divisor / bas->rclk); 106 return (16000 * divisor / (bas->rclk / 1000)); 107 } 108 109 static int 110 ns8250_divisor(int rclk, int baudrate) 111 { 112 int actual_baud, divisor; 113 int error; 114 115 if (baudrate == 0) 116 return (0); 117 118 divisor = (rclk / (baudrate << 3) + 1) >> 1; 119 if (divisor == 0 || divisor >= 65536) 120 return (0); 121 actual_baud = rclk / (divisor << 4); 122 123 /* 10 times error in percent: */ 124 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 125 126 /* 3.0% maximum error tolerance: */ 127 if (error < -30 || error > 30) 128 return (0); 129 130 return (divisor); 131 } 132 133 static int 134 ns8250_drain(struct uart_bas *bas, int what) 135 { 136 int delay, limit; 137 138 delay = ns8250_delay(bas); 139 140 if (what & UART_DRAIN_TRANSMITTER) { 141 /* 142 * Pick an arbitrary high limit to avoid getting stuck in 143 * an infinite loop when the hardware is broken. Make the 144 * limit high enough to handle large FIFOs. 145 */ 146 limit = 10*1024; 147 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 148 DELAY(delay); 149 if (limit == 0) { 150 /* printf("ns8250: transmitter appears stuck... "); */ 151 return (EIO); 152 } 153 } 154 155 if (what & UART_DRAIN_RECEIVER) { 156 /* 157 * Pick an arbitrary high limit to avoid getting stuck in 158 * an infinite loop when the hardware is broken. Make the 159 * limit high enough to handle large FIFOs and integrated 160 * UARTs. The HP rx2600 for example has 3 UARTs on the 161 * management board that tend to get a lot of data send 162 * to it when the UART is first activated. 163 */ 164 limit=10*4096; 165 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 166 (void)uart_getreg(bas, REG_DATA); 167 uart_barrier(bas); 168 DELAY(delay << 2); 169 } 170 if (limit == 0) { 171 /* printf("ns8250: receiver appears broken... "); */ 172 return (EIO); 173 } 174 } 175 176 return (0); 177 } 178 179 /* 180 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 181 * drained. WARNING: this function clobbers the FIFO setting! 182 */ 183 static void 184 ns8250_flush(struct uart_bas *bas, int what) 185 { 186 uint8_t fcr; 187 188 fcr = FCR_ENABLE; 189 if (what & UART_FLUSH_TRANSMITTER) 190 fcr |= FCR_XMT_RST; 191 if (what & UART_FLUSH_RECEIVER) 192 fcr |= FCR_RCV_RST; 193 uart_setreg(bas, REG_FCR, fcr); 194 uart_barrier(bas); 195 } 196 197 static int 198 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 199 int parity) 200 { 201 int divisor; 202 uint8_t lcr; 203 204 lcr = 0; 205 if (databits >= 8) 206 lcr |= LCR_8BITS; 207 else if (databits == 7) 208 lcr |= LCR_7BITS; 209 else if (databits == 6) 210 lcr |= LCR_6BITS; 211 else 212 lcr |= LCR_5BITS; 213 if (stopbits > 1) 214 lcr |= LCR_STOPB; 215 lcr |= parity << 3; 216 217 /* Set baudrate. */ 218 if (baudrate > 0) { 219 divisor = ns8250_divisor(bas->rclk, baudrate); 220 if (divisor == 0) 221 return (EINVAL); 222 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 223 uart_barrier(bas); 224 uart_setreg(bas, REG_DLL, divisor & 0xff); 225 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 226 uart_barrier(bas); 227 } 228 229 /* Set LCR and clear DLAB. */ 230 uart_setreg(bas, REG_LCR, lcr); 231 uart_barrier(bas); 232 return (0); 233 } 234 235 /* 236 * Low-level UART interface. 237 */ 238 static int ns8250_probe(struct uart_bas *bas); 239 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 240 static void ns8250_term(struct uart_bas *bas); 241 static void ns8250_putc(struct uart_bas *bas, int); 242 static int ns8250_rxready(struct uart_bas *bas); 243 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 244 245 struct uart_ops uart_ns8250_ops = { 246 .probe = ns8250_probe, 247 .init = ns8250_init, 248 .term = ns8250_term, 249 .putc = ns8250_putc, 250 .rxready = ns8250_rxready, 251 .getc = ns8250_getc, 252 }; 253 254 static int 255 ns8250_probe(struct uart_bas *bas) 256 { 257 u_char val; 258 259 /* Check known 0 bits that don't depend on DLAB. */ 260 val = uart_getreg(bas, REG_IIR); 261 if (val & 0x30) 262 return (ENXIO); 263 /* 264 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 265 * chip, but otherwise doesn't seem to have a function. In 266 * other words, uart(4) works regardless. Ignore that bit so 267 * the probe succeeds. 268 */ 269 val = uart_getreg(bas, REG_MCR); 270 if (val & 0xa0) 271 return (ENXIO); 272 273 return (0); 274 } 275 276 static void 277 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 278 int parity) 279 { 280 u_char ier; 281 282 if (bas->rclk == 0) 283 bas->rclk = DEFAULT_RCLK; 284 ns8250_param(bas, baudrate, databits, stopbits, parity); 285 286 /* Disable all interrupt sources. */ 287 /* 288 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 289 * UARTs split the receive time-out interrupt bit out separately as 290 * 0x10. This gets handled by ier_mask and ier_rxbits below. 291 */ 292 ier = uart_getreg(bas, REG_IER) & 0xe0; 293 uart_setreg(bas, REG_IER, ier); 294 uart_barrier(bas); 295 296 /* Disable the FIFO (if present). */ 297 uart_setreg(bas, REG_FCR, 0); 298 uart_barrier(bas); 299 300 /* Set RTS & DTR. */ 301 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 302 uart_barrier(bas); 303 304 ns8250_clrint(bas); 305 } 306 307 static void 308 ns8250_term(struct uart_bas *bas) 309 { 310 311 /* Clear RTS & DTR. */ 312 uart_setreg(bas, REG_MCR, MCR_IE); 313 uart_barrier(bas); 314 } 315 316 static void 317 ns8250_putc(struct uart_bas *bas, int c) 318 { 319 int limit; 320 321 limit = 250000; 322 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 323 DELAY(4); 324 uart_setreg(bas, REG_DATA, c); 325 uart_barrier(bas); 326 limit = 250000; 327 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 328 DELAY(4); 329 } 330 331 static int 332 ns8250_rxready(struct uart_bas *bas) 333 { 334 335 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 336 } 337 338 static int 339 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 340 { 341 int c; 342 343 uart_lock(hwmtx); 344 345 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 346 uart_unlock(hwmtx); 347 DELAY(4); 348 uart_lock(hwmtx); 349 } 350 351 c = uart_getreg(bas, REG_DATA); 352 353 uart_unlock(hwmtx); 354 355 return (c); 356 } 357 358 static kobj_method_t ns8250_methods[] = { 359 KOBJMETHOD(uart_attach, ns8250_bus_attach), 360 KOBJMETHOD(uart_detach, ns8250_bus_detach), 361 KOBJMETHOD(uart_flush, ns8250_bus_flush), 362 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 363 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 364 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 365 KOBJMETHOD(uart_param, ns8250_bus_param), 366 KOBJMETHOD(uart_probe, ns8250_bus_probe), 367 KOBJMETHOD(uart_receive, ns8250_bus_receive), 368 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 369 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 370 KOBJMETHOD(uart_grab, ns8250_bus_grab), 371 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 372 { 0, 0 } 373 }; 374 375 struct uart_class uart_ns8250_class = { 376 "ns8250", 377 ns8250_methods, 378 sizeof(struct ns8250_softc), 379 .uc_ops = &uart_ns8250_ops, 380 .uc_range = 8, 381 .uc_rclk = DEFAULT_RCLK 382 }; 383 384 #ifdef FDT 385 static struct ofw_compat_data compat_data[] = { 386 {"ns16550", (uintptr_t)&uart_ns8250_class}, 387 {NULL, (uintptr_t)NULL}, 388 }; 389 UART_FDT_CLASS_AND_DEVICE(compat_data); 390 #endif 391 392 #define SIGCHG(c, i, s, d) \ 393 if (c) { \ 394 i |= (i & s) ? s : s | d; \ 395 } else { \ 396 i = (i & s) ? (i & ~s) | d : i; \ 397 } 398 399 int 400 ns8250_bus_attach(struct uart_softc *sc) 401 { 402 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 403 struct uart_bas *bas; 404 unsigned int ivar; 405 #ifdef FDT 406 phandle_t node; 407 pcell_t cell; 408 #endif 409 410 ns8250->busy_detect = 0; 411 412 #ifdef FDT 413 /* 414 * Check whether uart requires to read USR reg when IIR_BUSY and 415 * has broken txfifo. 416 */ 417 node = ofw_bus_get_node(sc->sc_dev); 418 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 419 ns8250->busy_detect = 1; 420 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 421 broken_txfifo = 1; 422 #endif 423 424 bas = &sc->sc_bas; 425 426 ns8250->mcr = uart_getreg(bas, REG_MCR); 427 ns8250->fcr = FCR_ENABLE; 428 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 429 &ivar)) { 430 if (UART_FLAGS_FCR_RX_LOW(ivar)) 431 ns8250->fcr |= FCR_RX_LOW; 432 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 433 ns8250->fcr |= FCR_RX_MEDL; 434 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 435 ns8250->fcr |= FCR_RX_HIGH; 436 else 437 ns8250->fcr |= FCR_RX_MEDH; 438 } else 439 ns8250->fcr |= FCR_RX_MEDH; 440 441 /* Get IER mask */ 442 ivar = 0xf0; 443 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 444 &ivar); 445 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 446 447 /* Get IER RX interrupt bits */ 448 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 449 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 450 &ivar); 451 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 452 453 uart_setreg(bas, REG_FCR, ns8250->fcr); 454 uart_barrier(bas); 455 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 456 457 if (ns8250->mcr & MCR_DTR) 458 sc->sc_hwsig |= SER_DTR; 459 if (ns8250->mcr & MCR_RTS) 460 sc->sc_hwsig |= SER_RTS; 461 ns8250_bus_getsig(sc); 462 463 ns8250_clrint(bas); 464 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 465 ns8250->ier |= ns8250->ier_rxbits; 466 uart_setreg(bas, REG_IER, ns8250->ier); 467 uart_barrier(bas); 468 469 /* 470 * Timing of the H/W access was changed with r253161 of uart_core.c 471 * It has been observed that an ITE IT8513E would signal a break 472 * condition with pretty much every character it received, unless 473 * it had enough time to settle between ns8250_bus_attach() and 474 * ns8250_bus_ipend() -- which it accidentally had before r253161. 475 * It's not understood why the UART chip behaves this way and it 476 * could very well be that the DELAY make the H/W work in the same 477 * accidental manner as before. More analysis is warranted, but 478 * at least now we fixed a known regression. 479 */ 480 DELAY(200); 481 return (0); 482 } 483 484 int 485 ns8250_bus_detach(struct uart_softc *sc) 486 { 487 struct ns8250_softc *ns8250; 488 struct uart_bas *bas; 489 u_char ier; 490 491 ns8250 = (struct ns8250_softc *)sc; 492 bas = &sc->sc_bas; 493 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 494 uart_setreg(bas, REG_IER, ier); 495 uart_barrier(bas); 496 ns8250_clrint(bas); 497 return (0); 498 } 499 500 int 501 ns8250_bus_flush(struct uart_softc *sc, int what) 502 { 503 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 504 struct uart_bas *bas; 505 int error; 506 507 bas = &sc->sc_bas; 508 uart_lock(sc->sc_hwmtx); 509 if (sc->sc_rxfifosz > 1) { 510 ns8250_flush(bas, what); 511 uart_setreg(bas, REG_FCR, ns8250->fcr); 512 uart_barrier(bas); 513 error = 0; 514 } else 515 error = ns8250_drain(bas, what); 516 uart_unlock(sc->sc_hwmtx); 517 return (error); 518 } 519 520 int 521 ns8250_bus_getsig(struct uart_softc *sc) 522 { 523 uint32_t new, old, sig; 524 uint8_t msr; 525 526 do { 527 old = sc->sc_hwsig; 528 sig = old; 529 uart_lock(sc->sc_hwmtx); 530 msr = uart_getreg(&sc->sc_bas, REG_MSR); 531 uart_unlock(sc->sc_hwmtx); 532 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 533 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 534 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 535 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 536 new = sig & ~SER_MASK_DELTA; 537 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 538 return (sig); 539 } 540 541 int 542 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 543 { 544 struct uart_bas *bas; 545 int baudrate, divisor, error; 546 uint8_t efr, lcr; 547 548 bas = &sc->sc_bas; 549 error = 0; 550 uart_lock(sc->sc_hwmtx); 551 switch (request) { 552 case UART_IOCTL_BREAK: 553 lcr = uart_getreg(bas, REG_LCR); 554 if (data) 555 lcr |= LCR_SBREAK; 556 else 557 lcr &= ~LCR_SBREAK; 558 uart_setreg(bas, REG_LCR, lcr); 559 uart_barrier(bas); 560 break; 561 case UART_IOCTL_IFLOW: 562 lcr = uart_getreg(bas, REG_LCR); 563 uart_barrier(bas); 564 uart_setreg(bas, REG_LCR, 0xbf); 565 uart_barrier(bas); 566 efr = uart_getreg(bas, REG_EFR); 567 if (data) 568 efr |= EFR_RTS; 569 else 570 efr &= ~EFR_RTS; 571 uart_setreg(bas, REG_EFR, efr); 572 uart_barrier(bas); 573 uart_setreg(bas, REG_LCR, lcr); 574 uart_barrier(bas); 575 break; 576 case UART_IOCTL_OFLOW: 577 lcr = uart_getreg(bas, REG_LCR); 578 uart_barrier(bas); 579 uart_setreg(bas, REG_LCR, 0xbf); 580 uart_barrier(bas); 581 efr = uart_getreg(bas, REG_EFR); 582 if (data) 583 efr |= EFR_CTS; 584 else 585 efr &= ~EFR_CTS; 586 uart_setreg(bas, REG_EFR, efr); 587 uart_barrier(bas); 588 uart_setreg(bas, REG_LCR, lcr); 589 uart_barrier(bas); 590 break; 591 case UART_IOCTL_BAUD: 592 lcr = uart_getreg(bas, REG_LCR); 593 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 594 uart_barrier(bas); 595 divisor = uart_getreg(bas, REG_DLL) | 596 (uart_getreg(bas, REG_DLH) << 8); 597 uart_barrier(bas); 598 uart_setreg(bas, REG_LCR, lcr); 599 uart_barrier(bas); 600 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 601 if (baudrate > 0) 602 *(int*)data = baudrate; 603 else 604 error = ENXIO; 605 break; 606 default: 607 error = EINVAL; 608 break; 609 } 610 uart_unlock(sc->sc_hwmtx); 611 return (error); 612 } 613 614 int 615 ns8250_bus_ipend(struct uart_softc *sc) 616 { 617 struct uart_bas *bas; 618 struct ns8250_softc *ns8250; 619 int ipend; 620 uint8_t iir, lsr; 621 622 ns8250 = (struct ns8250_softc *)sc; 623 bas = &sc->sc_bas; 624 uart_lock(sc->sc_hwmtx); 625 iir = uart_getreg(bas, REG_IIR); 626 627 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 628 (void)uart_getreg(bas, DW_REG_USR); 629 uart_unlock(sc->sc_hwmtx); 630 return (0); 631 } 632 if (iir & IIR_NOPEND) { 633 uart_unlock(sc->sc_hwmtx); 634 return (0); 635 } 636 ipend = 0; 637 if (iir & IIR_RXRDY) { 638 lsr = uart_getreg(bas, REG_LSR); 639 if (lsr & LSR_OE) 640 ipend |= SER_INT_OVERRUN; 641 if (lsr & LSR_BI) 642 ipend |= SER_INT_BREAK; 643 if (lsr & LSR_RXRDY) 644 ipend |= SER_INT_RXREADY; 645 } else { 646 if (iir & IIR_TXRDY) { 647 ipend |= SER_INT_TXIDLE; 648 uart_setreg(bas, REG_IER, ns8250->ier); 649 } else 650 ipend |= SER_INT_SIGCHG; 651 } 652 if (ipend == 0) 653 ns8250_clrint(bas); 654 uart_unlock(sc->sc_hwmtx); 655 return (ipend); 656 } 657 658 int 659 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 660 int stopbits, int parity) 661 { 662 struct ns8250_softc *ns8250; 663 struct uart_bas *bas; 664 int error, limit; 665 666 ns8250 = (struct ns8250_softc*)sc; 667 bas = &sc->sc_bas; 668 uart_lock(sc->sc_hwmtx); 669 /* 670 * When using DW UART with BUSY detection it is necessary to wait 671 * until all serial transfers are finished before manipulating the 672 * line control. LCR will not be affected when UART is busy. 673 */ 674 if (ns8250->busy_detect != 0) { 675 /* 676 * Pick an arbitrary high limit to avoid getting stuck in 677 * an infinite loop in case when the hardware is broken. 678 */ 679 limit = 10 * 1024; 680 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 681 --limit) 682 DELAY(4); 683 684 if (limit <= 0) { 685 /* UART appears to be stuck */ 686 uart_unlock(sc->sc_hwmtx); 687 return (EIO); 688 } 689 } 690 691 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 692 uart_unlock(sc->sc_hwmtx); 693 return (error); 694 } 695 696 int 697 ns8250_bus_probe(struct uart_softc *sc) 698 { 699 struct ns8250_softc *ns8250; 700 struct uart_bas *bas; 701 int count, delay, error, limit; 702 uint8_t lsr, mcr, ier; 703 704 ns8250 = (struct ns8250_softc *)sc; 705 bas = &sc->sc_bas; 706 707 error = ns8250_probe(bas); 708 if (error) 709 return (error); 710 711 mcr = MCR_IE; 712 if (sc->sc_sysdev == NULL) { 713 /* By using ns8250_init() we also set DTR and RTS. */ 714 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 715 } else 716 mcr |= MCR_DTR | MCR_RTS; 717 718 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 719 if (error) 720 return (error); 721 722 /* 723 * Set loopback mode. This avoids having garbage on the wire and 724 * also allows us send and receive data. We set DTR and RTS to 725 * avoid the possibility that automatic flow-control prevents 726 * any data from being sent. 727 */ 728 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 729 uart_barrier(bas); 730 731 /* 732 * Enable FIFOs. And check that the UART has them. If not, we're 733 * done. Since this is the first time we enable the FIFOs, we reset 734 * them. 735 */ 736 uart_setreg(bas, REG_FCR, FCR_ENABLE); 737 uart_barrier(bas); 738 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 739 /* 740 * NS16450 or INS8250. We don't bother to differentiate 741 * between them. They're too old to be interesting. 742 */ 743 uart_setreg(bas, REG_MCR, mcr); 744 uart_barrier(bas); 745 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 746 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 747 return (0); 748 } 749 750 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 751 uart_barrier(bas); 752 753 count = 0; 754 delay = ns8250_delay(bas); 755 756 /* We have FIFOs. Drain the transmitter and receiver. */ 757 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 758 if (error) { 759 uart_setreg(bas, REG_MCR, mcr); 760 uart_setreg(bas, REG_FCR, 0); 761 uart_barrier(bas); 762 goto describe; 763 } 764 765 /* 766 * We should have a sufficiently clean "pipe" to determine the 767 * size of the FIFOs. We send as much characters as is reasonable 768 * and wait for the overflow bit in the LSR register to be 769 * asserted, counting the characters as we send them. Based on 770 * that count we know the FIFO size. 771 */ 772 do { 773 uart_setreg(bas, REG_DATA, 0); 774 uart_barrier(bas); 775 count++; 776 777 limit = 30; 778 lsr = 0; 779 /* 780 * LSR bits are cleared upon read, so we must accumulate 781 * them to be able to test LSR_OE below. 782 */ 783 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 784 --limit) 785 DELAY(delay); 786 if (limit == 0) { 787 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 788 uart_setreg(bas, REG_IER, ier); 789 uart_setreg(bas, REG_MCR, mcr); 790 uart_setreg(bas, REG_FCR, 0); 791 uart_barrier(bas); 792 count = 0; 793 goto describe; 794 } 795 } while ((lsr & LSR_OE) == 0 && count < 130); 796 count--; 797 798 uart_setreg(bas, REG_MCR, mcr); 799 800 /* Reset FIFOs. */ 801 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 802 803 describe: 804 if (count >= 14 && count <= 16) { 805 sc->sc_rxfifosz = 16; 806 device_set_desc(sc->sc_dev, "16550 or compatible"); 807 } else if (count >= 28 && count <= 32) { 808 sc->sc_rxfifosz = 32; 809 device_set_desc(sc->sc_dev, "16650 or compatible"); 810 } else if (count >= 56 && count <= 64) { 811 sc->sc_rxfifosz = 64; 812 device_set_desc(sc->sc_dev, "16750 or compatible"); 813 } else if (count >= 112 && count <= 128) { 814 sc->sc_rxfifosz = 128; 815 device_set_desc(sc->sc_dev, "16950 or compatible"); 816 } else { 817 sc->sc_rxfifosz = 16; 818 device_set_desc(sc->sc_dev, 819 "Non-standard ns8250 class UART with FIFOs"); 820 } 821 822 /* 823 * Force the Tx FIFO size to 16 bytes for now. We don't program the 824 * Tx trigger. Also, we assume that all data has been sent when the 825 * interrupt happens. 826 */ 827 sc->sc_txfifosz = 16; 828 829 #if 0 830 /* 831 * XXX there are some issues related to hardware flow control and 832 * it's likely that uart(4) is the cause. This basicly needs more 833 * investigation, but we avoid using for hardware flow control 834 * until then. 835 */ 836 /* 16650s or higher have automatic flow control. */ 837 if (sc->sc_rxfifosz > 16) { 838 sc->sc_hwiflow = 1; 839 sc->sc_hwoflow = 1; 840 } 841 #endif 842 843 return (0); 844 } 845 846 int 847 ns8250_bus_receive(struct uart_softc *sc) 848 { 849 struct uart_bas *bas; 850 int xc; 851 uint8_t lsr; 852 853 bas = &sc->sc_bas; 854 uart_lock(sc->sc_hwmtx); 855 lsr = uart_getreg(bas, REG_LSR); 856 while (lsr & LSR_RXRDY) { 857 if (uart_rx_full(sc)) { 858 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 859 break; 860 } 861 xc = uart_getreg(bas, REG_DATA); 862 if (lsr & LSR_FE) 863 xc |= UART_STAT_FRAMERR; 864 if (lsr & LSR_PE) 865 xc |= UART_STAT_PARERR; 866 uart_rx_put(sc, xc); 867 lsr = uart_getreg(bas, REG_LSR); 868 } 869 /* Discard everything left in the Rx FIFO. */ 870 while (lsr & LSR_RXRDY) { 871 (void)uart_getreg(bas, REG_DATA); 872 uart_barrier(bas); 873 lsr = uart_getreg(bas, REG_LSR); 874 } 875 uart_unlock(sc->sc_hwmtx); 876 return (0); 877 } 878 879 int 880 ns8250_bus_setsig(struct uart_softc *sc, int sig) 881 { 882 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 883 struct uart_bas *bas; 884 uint32_t new, old; 885 886 bas = &sc->sc_bas; 887 do { 888 old = sc->sc_hwsig; 889 new = old; 890 if (sig & SER_DDTR) { 891 SIGCHG(sig & SER_DTR, new, SER_DTR, 892 SER_DDTR); 893 } 894 if (sig & SER_DRTS) { 895 SIGCHG(sig & SER_RTS, new, SER_RTS, 896 SER_DRTS); 897 } 898 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 899 uart_lock(sc->sc_hwmtx); 900 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 901 if (new & SER_DTR) 902 ns8250->mcr |= MCR_DTR; 903 if (new & SER_RTS) 904 ns8250->mcr |= MCR_RTS; 905 uart_setreg(bas, REG_MCR, ns8250->mcr); 906 uart_barrier(bas); 907 uart_unlock(sc->sc_hwmtx); 908 return (0); 909 } 910 911 int 912 ns8250_bus_transmit(struct uart_softc *sc) 913 { 914 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 915 struct uart_bas *bas; 916 int i; 917 918 bas = &sc->sc_bas; 919 uart_lock(sc->sc_hwmtx); 920 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 921 ; 922 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 923 uart_barrier(bas); 924 for (i = 0; i < sc->sc_txdatasz; i++) { 925 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 926 uart_barrier(bas); 927 } 928 if (broken_txfifo) 929 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 930 else 931 sc->sc_txbusy = 1; 932 uart_unlock(sc->sc_hwmtx); 933 if (broken_txfifo) 934 uart_sched_softih(sc, SER_INT_TXIDLE); 935 return (0); 936 } 937 938 void 939 ns8250_bus_grab(struct uart_softc *sc) 940 { 941 struct uart_bas *bas = &sc->sc_bas; 942 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 943 u_char ier; 944 945 /* 946 * turn off all interrupts to enter polling mode. Leave the 947 * saved mask alone. We'll restore whatever it was in ungrab. 948 * All pending interupt signals are reset when IER is set to 0. 949 */ 950 uart_lock(sc->sc_hwmtx); 951 ier = uart_getreg(bas, REG_IER); 952 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 953 uart_barrier(bas); 954 uart_unlock(sc->sc_hwmtx); 955 } 956 957 void 958 ns8250_bus_ungrab(struct uart_softc *sc) 959 { 960 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 961 struct uart_bas *bas = &sc->sc_bas; 962 963 /* 964 * Restore previous interrupt mask 965 */ 966 uart_lock(sc->sc_hwmtx); 967 uart_setreg(bas, REG_IER, ns8250->ier); 968 uart_barrier(bas); 969 uart_unlock(sc->sc_hwmtx); 970 } 971