1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/sysctl.h> 38 #include <machine/bus.h> 39 40 #ifdef FDT 41 #include <dev/fdt/fdt_common.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 #endif 45 46 #include <dev/uart/uart.h> 47 #include <dev/uart/uart_cpu.h> 48 #ifdef FDT 49 #include <dev/uart/uart_cpu_fdt.h> 50 #endif 51 #include <dev/uart/uart_bus.h> 52 #include <dev/uart/uart_dev_ns8250.h> 53 54 #include <dev/ic/ns16550.h> 55 56 #include "uart_if.h" 57 58 #define DEFAULT_RCLK 1843200 59 60 static int broken_txfifo = 0; 61 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 62 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 63 64 /* 65 * Clear pending interrupts. THRE is cleared by reading IIR. Data 66 * that may have been received gets lost here. 67 */ 68 static void 69 ns8250_clrint(struct uart_bas *bas) 70 { 71 uint8_t iir, lsr; 72 73 iir = uart_getreg(bas, REG_IIR); 74 while ((iir & IIR_NOPEND) == 0) { 75 iir &= IIR_IMASK; 76 if (iir == IIR_RLS) { 77 lsr = uart_getreg(bas, REG_LSR); 78 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 79 (void)uart_getreg(bas, REG_DATA); 80 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 81 (void)uart_getreg(bas, REG_DATA); 82 else if (iir == IIR_MLSC) 83 (void)uart_getreg(bas, REG_MSR); 84 uart_barrier(bas); 85 iir = uart_getreg(bas, REG_IIR); 86 } 87 } 88 89 static int 90 ns8250_delay(struct uart_bas *bas) 91 { 92 int divisor; 93 u_char lcr; 94 95 lcr = uart_getreg(bas, REG_LCR); 96 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 97 uart_barrier(bas); 98 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 99 uart_barrier(bas); 100 uart_setreg(bas, REG_LCR, lcr); 101 uart_barrier(bas); 102 103 /* 1/10th the time to transmit 1 character (estimate). */ 104 if (divisor <= 134) 105 return (16000000 * divisor / bas->rclk); 106 return (16000 * divisor / (bas->rclk / 1000)); 107 } 108 109 static int 110 ns8250_divisor(int rclk, int baudrate) 111 { 112 int actual_baud, divisor; 113 int error; 114 115 if (baudrate == 0) 116 return (0); 117 118 divisor = (rclk / (baudrate << 3) + 1) >> 1; 119 if (divisor == 0 || divisor >= 65536) 120 return (0); 121 actual_baud = rclk / (divisor << 4); 122 123 /* 10 times error in percent: */ 124 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 125 126 /* 3.0% maximum error tolerance: */ 127 if (error < -30 || error > 30) 128 return (0); 129 130 return (divisor); 131 } 132 133 static int 134 ns8250_drain(struct uart_bas *bas, int what) 135 { 136 int delay, limit; 137 138 delay = ns8250_delay(bas); 139 140 if (what & UART_DRAIN_TRANSMITTER) { 141 /* 142 * Pick an arbitrary high limit to avoid getting stuck in 143 * an infinite loop when the hardware is broken. Make the 144 * limit high enough to handle large FIFOs. 145 */ 146 limit = 10*1024; 147 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 148 DELAY(delay); 149 if (limit == 0) { 150 /* printf("ns8250: transmitter appears stuck... "); */ 151 return (EIO); 152 } 153 } 154 155 if (what & UART_DRAIN_RECEIVER) { 156 /* 157 * Pick an arbitrary high limit to avoid getting stuck in 158 * an infinite loop when the hardware is broken. Make the 159 * limit high enough to handle large FIFOs and integrated 160 * UARTs. The HP rx2600 for example has 3 UARTs on the 161 * management board that tend to get a lot of data send 162 * to it when the UART is first activated. 163 */ 164 limit=10*4096; 165 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 166 (void)uart_getreg(bas, REG_DATA); 167 uart_barrier(bas); 168 DELAY(delay << 2); 169 } 170 if (limit == 0) { 171 /* printf("ns8250: receiver appears broken... "); */ 172 return (EIO); 173 } 174 } 175 176 return (0); 177 } 178 179 /* 180 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 181 * drained. WARNING: this function clobbers the FIFO setting! 182 */ 183 static void 184 ns8250_flush(struct uart_bas *bas, int what) 185 { 186 uint8_t fcr; 187 188 fcr = FCR_ENABLE; 189 if (what & UART_FLUSH_TRANSMITTER) 190 fcr |= FCR_XMT_RST; 191 if (what & UART_FLUSH_RECEIVER) 192 fcr |= FCR_RCV_RST; 193 uart_setreg(bas, REG_FCR, fcr); 194 uart_barrier(bas); 195 } 196 197 static int 198 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 199 int parity) 200 { 201 int divisor; 202 uint8_t lcr; 203 204 lcr = 0; 205 if (databits >= 8) 206 lcr |= LCR_8BITS; 207 else if (databits == 7) 208 lcr |= LCR_7BITS; 209 else if (databits == 6) 210 lcr |= LCR_6BITS; 211 else 212 lcr |= LCR_5BITS; 213 if (stopbits > 1) 214 lcr |= LCR_STOPB; 215 lcr |= parity << 3; 216 217 /* Set baudrate. */ 218 if (baudrate > 0) { 219 divisor = ns8250_divisor(bas->rclk, baudrate); 220 if (divisor == 0) 221 return (EINVAL); 222 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 223 uart_barrier(bas); 224 uart_setreg(bas, REG_DLL, divisor & 0xff); 225 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 226 uart_barrier(bas); 227 } 228 229 /* Set LCR and clear DLAB. */ 230 uart_setreg(bas, REG_LCR, lcr); 231 uart_barrier(bas); 232 return (0); 233 } 234 235 /* 236 * Low-level UART interface. 237 */ 238 static int ns8250_probe(struct uart_bas *bas); 239 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 240 static void ns8250_term(struct uart_bas *bas); 241 static void ns8250_putc(struct uart_bas *bas, int); 242 static int ns8250_rxready(struct uart_bas *bas); 243 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 244 245 struct uart_ops uart_ns8250_ops = { 246 .probe = ns8250_probe, 247 .init = ns8250_init, 248 .term = ns8250_term, 249 .putc = ns8250_putc, 250 .rxready = ns8250_rxready, 251 .getc = ns8250_getc, 252 }; 253 254 static int 255 ns8250_probe(struct uart_bas *bas) 256 { 257 u_char val; 258 259 /* Check known 0 bits that don't depend on DLAB. */ 260 val = uart_getreg(bas, REG_IIR); 261 if (val & 0x30) 262 return (ENXIO); 263 /* 264 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 265 * chip, but otherwise doesn't seem to have a function. In 266 * other words, uart(4) works regardless. Ignore that bit so 267 * the probe succeeds. 268 */ 269 val = uart_getreg(bas, REG_MCR); 270 if (val & 0xa0) 271 return (ENXIO); 272 273 return (0); 274 } 275 276 static void 277 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 278 int parity) 279 { 280 u_char ier; 281 282 if (bas->rclk == 0) 283 bas->rclk = DEFAULT_RCLK; 284 ns8250_param(bas, baudrate, databits, stopbits, parity); 285 286 /* Disable all interrupt sources. */ 287 /* 288 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 289 * UARTs split the receive time-out interrupt bit out separately as 290 * 0x10. This gets handled by ier_mask and ier_rxbits below. 291 */ 292 ier = uart_getreg(bas, REG_IER) & 0xe0; 293 uart_setreg(bas, REG_IER, ier); 294 uart_barrier(bas); 295 296 /* Disable the FIFO (if present). */ 297 uart_setreg(bas, REG_FCR, 0); 298 uart_barrier(bas); 299 300 /* Set RTS & DTR. */ 301 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 302 uart_barrier(bas); 303 304 ns8250_clrint(bas); 305 } 306 307 static void 308 ns8250_term(struct uart_bas *bas) 309 { 310 311 /* Clear RTS & DTR. */ 312 uart_setreg(bas, REG_MCR, MCR_IE); 313 uart_barrier(bas); 314 } 315 316 static void 317 ns8250_putc(struct uart_bas *bas, int c) 318 { 319 int limit; 320 321 limit = 250000; 322 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 323 DELAY(4); 324 uart_setreg(bas, REG_DATA, c); 325 uart_barrier(bas); 326 limit = 250000; 327 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 328 DELAY(4); 329 } 330 331 static int 332 ns8250_rxready(struct uart_bas *bas) 333 { 334 335 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 336 } 337 338 static int 339 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 340 { 341 int c; 342 343 uart_lock(hwmtx); 344 345 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 346 uart_unlock(hwmtx); 347 DELAY(4); 348 uart_lock(hwmtx); 349 } 350 351 c = uart_getreg(bas, REG_DATA); 352 353 uart_unlock(hwmtx); 354 355 return (c); 356 } 357 358 static kobj_method_t ns8250_methods[] = { 359 KOBJMETHOD(uart_attach, ns8250_bus_attach), 360 KOBJMETHOD(uart_detach, ns8250_bus_detach), 361 KOBJMETHOD(uart_flush, ns8250_bus_flush), 362 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 363 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 364 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 365 KOBJMETHOD(uart_param, ns8250_bus_param), 366 KOBJMETHOD(uart_probe, ns8250_bus_probe), 367 KOBJMETHOD(uart_receive, ns8250_bus_receive), 368 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 369 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 370 KOBJMETHOD(uart_grab, ns8250_bus_grab), 371 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 372 { 0, 0 } 373 }; 374 375 struct uart_class uart_ns8250_class = { 376 "ns8250", 377 ns8250_methods, 378 sizeof(struct ns8250_softc), 379 .uc_ops = &uart_ns8250_ops, 380 .uc_range = 8, 381 .uc_rclk = DEFAULT_RCLK, 382 .uc_rshift = 0 383 }; 384 385 #ifdef FDT 386 static struct ofw_compat_data compat_data[] = { 387 {"ns16550", (uintptr_t)&uart_ns8250_class}, 388 {NULL, (uintptr_t)NULL}, 389 }; 390 UART_FDT_CLASS_AND_DEVICE(compat_data); 391 #endif 392 393 #define SIGCHG(c, i, s, d) \ 394 if (c) { \ 395 i |= (i & s) ? s : s | d; \ 396 } else { \ 397 i = (i & s) ? (i & ~s) | d : i; \ 398 } 399 400 int 401 ns8250_bus_attach(struct uart_softc *sc) 402 { 403 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 404 struct uart_bas *bas; 405 unsigned int ivar; 406 #ifdef FDT 407 phandle_t node; 408 pcell_t cell; 409 #endif 410 411 ns8250->busy_detect = 0; 412 413 #ifdef FDT 414 /* 415 * Check whether uart requires to read USR reg when IIR_BUSY and 416 * has broken txfifo. 417 */ 418 node = ofw_bus_get_node(sc->sc_dev); 419 if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 420 ns8250->busy_detect = cell ? 1 : 0; 421 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 422 broken_txfifo = cell ? 1 : 0; 423 #endif 424 425 bas = &sc->sc_bas; 426 427 ns8250->mcr = uart_getreg(bas, REG_MCR); 428 ns8250->fcr = FCR_ENABLE; 429 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 430 &ivar)) { 431 if (UART_FLAGS_FCR_RX_LOW(ivar)) 432 ns8250->fcr |= FCR_RX_LOW; 433 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 434 ns8250->fcr |= FCR_RX_MEDL; 435 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 436 ns8250->fcr |= FCR_RX_HIGH; 437 else 438 ns8250->fcr |= FCR_RX_MEDH; 439 } else 440 ns8250->fcr |= FCR_RX_MEDH; 441 442 /* Get IER mask */ 443 ivar = 0xf0; 444 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 445 &ivar); 446 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 447 448 /* Get IER RX interrupt bits */ 449 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 450 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 451 &ivar); 452 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 453 454 uart_setreg(bas, REG_FCR, ns8250->fcr); 455 uart_barrier(bas); 456 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 457 458 if (ns8250->mcr & MCR_DTR) 459 sc->sc_hwsig |= SER_DTR; 460 if (ns8250->mcr & MCR_RTS) 461 sc->sc_hwsig |= SER_RTS; 462 ns8250_bus_getsig(sc); 463 464 ns8250_clrint(bas); 465 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 466 ns8250->ier |= ns8250->ier_rxbits; 467 uart_setreg(bas, REG_IER, ns8250->ier); 468 uart_barrier(bas); 469 470 /* 471 * Timing of the H/W access was changed with r253161 of uart_core.c 472 * It has been observed that an ITE IT8513E would signal a break 473 * condition with pretty much every character it received, unless 474 * it had enough time to settle between ns8250_bus_attach() and 475 * ns8250_bus_ipend() -- which it accidentally had before r253161. 476 * It's not understood why the UART chip behaves this way and it 477 * could very well be that the DELAY make the H/W work in the same 478 * accidental manner as before. More analysis is warranted, but 479 * at least now we fixed a known regression. 480 */ 481 DELAY(200); 482 return (0); 483 } 484 485 int 486 ns8250_bus_detach(struct uart_softc *sc) 487 { 488 struct ns8250_softc *ns8250; 489 struct uart_bas *bas; 490 u_char ier; 491 492 ns8250 = (struct ns8250_softc *)sc; 493 bas = &sc->sc_bas; 494 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 495 uart_setreg(bas, REG_IER, ier); 496 uart_barrier(bas); 497 ns8250_clrint(bas); 498 return (0); 499 } 500 501 int 502 ns8250_bus_flush(struct uart_softc *sc, int what) 503 { 504 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 505 struct uart_bas *bas; 506 int error; 507 508 bas = &sc->sc_bas; 509 uart_lock(sc->sc_hwmtx); 510 if (sc->sc_rxfifosz > 1) { 511 ns8250_flush(bas, what); 512 uart_setreg(bas, REG_FCR, ns8250->fcr); 513 uart_barrier(bas); 514 error = 0; 515 } else 516 error = ns8250_drain(bas, what); 517 uart_unlock(sc->sc_hwmtx); 518 return (error); 519 } 520 521 int 522 ns8250_bus_getsig(struct uart_softc *sc) 523 { 524 uint32_t new, old, sig; 525 uint8_t msr; 526 527 do { 528 old = sc->sc_hwsig; 529 sig = old; 530 uart_lock(sc->sc_hwmtx); 531 msr = uart_getreg(&sc->sc_bas, REG_MSR); 532 uart_unlock(sc->sc_hwmtx); 533 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 534 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 535 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 536 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 537 new = sig & ~SER_MASK_DELTA; 538 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 539 return (sig); 540 } 541 542 int 543 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 544 { 545 struct uart_bas *bas; 546 int baudrate, divisor, error; 547 uint8_t efr, lcr; 548 549 bas = &sc->sc_bas; 550 error = 0; 551 uart_lock(sc->sc_hwmtx); 552 switch (request) { 553 case UART_IOCTL_BREAK: 554 lcr = uart_getreg(bas, REG_LCR); 555 if (data) 556 lcr |= LCR_SBREAK; 557 else 558 lcr &= ~LCR_SBREAK; 559 uart_setreg(bas, REG_LCR, lcr); 560 uart_barrier(bas); 561 break; 562 case UART_IOCTL_IFLOW: 563 lcr = uart_getreg(bas, REG_LCR); 564 uart_barrier(bas); 565 uart_setreg(bas, REG_LCR, 0xbf); 566 uart_barrier(bas); 567 efr = uart_getreg(bas, REG_EFR); 568 if (data) 569 efr |= EFR_RTS; 570 else 571 efr &= ~EFR_RTS; 572 uart_setreg(bas, REG_EFR, efr); 573 uart_barrier(bas); 574 uart_setreg(bas, REG_LCR, lcr); 575 uart_barrier(bas); 576 break; 577 case UART_IOCTL_OFLOW: 578 lcr = uart_getreg(bas, REG_LCR); 579 uart_barrier(bas); 580 uart_setreg(bas, REG_LCR, 0xbf); 581 uart_barrier(bas); 582 efr = uart_getreg(bas, REG_EFR); 583 if (data) 584 efr |= EFR_CTS; 585 else 586 efr &= ~EFR_CTS; 587 uart_setreg(bas, REG_EFR, efr); 588 uart_barrier(bas); 589 uart_setreg(bas, REG_LCR, lcr); 590 uart_barrier(bas); 591 break; 592 case UART_IOCTL_BAUD: 593 lcr = uart_getreg(bas, REG_LCR); 594 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 595 uart_barrier(bas); 596 divisor = uart_getreg(bas, REG_DLL) | 597 (uart_getreg(bas, REG_DLH) << 8); 598 uart_barrier(bas); 599 uart_setreg(bas, REG_LCR, lcr); 600 uart_barrier(bas); 601 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 602 if (baudrate > 0) 603 *(int*)data = baudrate; 604 else 605 error = ENXIO; 606 break; 607 default: 608 error = EINVAL; 609 break; 610 } 611 uart_unlock(sc->sc_hwmtx); 612 return (error); 613 } 614 615 int 616 ns8250_bus_ipend(struct uart_softc *sc) 617 { 618 struct uart_bas *bas; 619 struct ns8250_softc *ns8250; 620 int ipend; 621 uint8_t iir, lsr; 622 623 ns8250 = (struct ns8250_softc *)sc; 624 bas = &sc->sc_bas; 625 uart_lock(sc->sc_hwmtx); 626 iir = uart_getreg(bas, REG_IIR); 627 628 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 629 (void)uart_getreg(bas, DW_REG_USR); 630 uart_unlock(sc->sc_hwmtx); 631 return (0); 632 } 633 if (iir & IIR_NOPEND) { 634 uart_unlock(sc->sc_hwmtx); 635 return (0); 636 } 637 ipend = 0; 638 if (iir & IIR_RXRDY) { 639 lsr = uart_getreg(bas, REG_LSR); 640 if (lsr & LSR_OE) 641 ipend |= SER_INT_OVERRUN; 642 if (lsr & LSR_BI) 643 ipend |= SER_INT_BREAK; 644 if (lsr & LSR_RXRDY) 645 ipend |= SER_INT_RXREADY; 646 } else { 647 if (iir & IIR_TXRDY) { 648 ipend |= SER_INT_TXIDLE; 649 uart_setreg(bas, REG_IER, ns8250->ier); 650 } else 651 ipend |= SER_INT_SIGCHG; 652 } 653 if (ipend == 0) 654 ns8250_clrint(bas); 655 uart_unlock(sc->sc_hwmtx); 656 return (ipend); 657 } 658 659 int 660 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 661 int stopbits, int parity) 662 { 663 struct ns8250_softc *ns8250; 664 struct uart_bas *bas; 665 int error, limit; 666 667 ns8250 = (struct ns8250_softc*)sc; 668 bas = &sc->sc_bas; 669 uart_lock(sc->sc_hwmtx); 670 /* 671 * When using DW UART with BUSY detection it is necessary to wait 672 * until all serial transfers are finished before manipulating the 673 * line control. LCR will not be affected when UART is busy. 674 */ 675 if (ns8250->busy_detect != 0) { 676 /* 677 * Pick an arbitrary high limit to avoid getting stuck in 678 * an infinite loop in case when the hardware is broken. 679 */ 680 limit = 10 * 1024; 681 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 682 --limit) 683 DELAY(4); 684 685 if (limit <= 0) { 686 /* UART appears to be stuck */ 687 uart_unlock(sc->sc_hwmtx); 688 return (EIO); 689 } 690 } 691 692 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 693 uart_unlock(sc->sc_hwmtx); 694 return (error); 695 } 696 697 int 698 ns8250_bus_probe(struct uart_softc *sc) 699 { 700 struct ns8250_softc *ns8250; 701 struct uart_bas *bas; 702 int count, delay, error, limit; 703 uint8_t lsr, mcr, ier; 704 705 ns8250 = (struct ns8250_softc *)sc; 706 bas = &sc->sc_bas; 707 708 error = ns8250_probe(bas); 709 if (error) 710 return (error); 711 712 mcr = MCR_IE; 713 if (sc->sc_sysdev == NULL) { 714 /* By using ns8250_init() we also set DTR and RTS. */ 715 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 716 } else 717 mcr |= MCR_DTR | MCR_RTS; 718 719 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 720 if (error) 721 return (error); 722 723 /* 724 * Set loopback mode. This avoids having garbage on the wire and 725 * also allows us send and receive data. We set DTR and RTS to 726 * avoid the possibility that automatic flow-control prevents 727 * any data from being sent. 728 */ 729 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 730 uart_barrier(bas); 731 732 /* 733 * Enable FIFOs. And check that the UART has them. If not, we're 734 * done. Since this is the first time we enable the FIFOs, we reset 735 * them. 736 */ 737 uart_setreg(bas, REG_FCR, FCR_ENABLE); 738 uart_barrier(bas); 739 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 740 /* 741 * NS16450 or INS8250. We don't bother to differentiate 742 * between them. They're too old to be interesting. 743 */ 744 uart_setreg(bas, REG_MCR, mcr); 745 uart_barrier(bas); 746 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 747 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 748 return (0); 749 } 750 751 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 752 uart_barrier(bas); 753 754 count = 0; 755 delay = ns8250_delay(bas); 756 757 /* We have FIFOs. Drain the transmitter and receiver. */ 758 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 759 if (error) { 760 uart_setreg(bas, REG_MCR, mcr); 761 uart_setreg(bas, REG_FCR, 0); 762 uart_barrier(bas); 763 goto describe; 764 } 765 766 /* 767 * We should have a sufficiently clean "pipe" to determine the 768 * size of the FIFOs. We send as much characters as is reasonable 769 * and wait for the overflow bit in the LSR register to be 770 * asserted, counting the characters as we send them. Based on 771 * that count we know the FIFO size. 772 */ 773 do { 774 uart_setreg(bas, REG_DATA, 0); 775 uart_barrier(bas); 776 count++; 777 778 limit = 30; 779 lsr = 0; 780 /* 781 * LSR bits are cleared upon read, so we must accumulate 782 * them to be able to test LSR_OE below. 783 */ 784 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 785 --limit) 786 DELAY(delay); 787 if (limit == 0) { 788 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 789 uart_setreg(bas, REG_IER, ier); 790 uart_setreg(bas, REG_MCR, mcr); 791 uart_setreg(bas, REG_FCR, 0); 792 uart_barrier(bas); 793 count = 0; 794 goto describe; 795 } 796 } while ((lsr & LSR_OE) == 0 && count < 130); 797 count--; 798 799 uart_setreg(bas, REG_MCR, mcr); 800 801 /* Reset FIFOs. */ 802 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 803 804 describe: 805 if (count >= 14 && count <= 16) { 806 sc->sc_rxfifosz = 16; 807 device_set_desc(sc->sc_dev, "16550 or compatible"); 808 } else if (count >= 28 && count <= 32) { 809 sc->sc_rxfifosz = 32; 810 device_set_desc(sc->sc_dev, "16650 or compatible"); 811 } else if (count >= 56 && count <= 64) { 812 sc->sc_rxfifosz = 64; 813 device_set_desc(sc->sc_dev, "16750 or compatible"); 814 } else if (count >= 112 && count <= 128) { 815 sc->sc_rxfifosz = 128; 816 device_set_desc(sc->sc_dev, "16950 or compatible"); 817 } else { 818 sc->sc_rxfifosz = 16; 819 device_set_desc(sc->sc_dev, 820 "Non-standard ns8250 class UART with FIFOs"); 821 } 822 823 /* 824 * Force the Tx FIFO size to 16 bytes for now. We don't program the 825 * Tx trigger. Also, we assume that all data has been sent when the 826 * interrupt happens. 827 */ 828 sc->sc_txfifosz = 16; 829 830 #if 0 831 /* 832 * XXX there are some issues related to hardware flow control and 833 * it's likely that uart(4) is the cause. This basicly needs more 834 * investigation, but we avoid using for hardware flow control 835 * until then. 836 */ 837 /* 16650s or higher have automatic flow control. */ 838 if (sc->sc_rxfifosz > 16) { 839 sc->sc_hwiflow = 1; 840 sc->sc_hwoflow = 1; 841 } 842 #endif 843 844 return (0); 845 } 846 847 int 848 ns8250_bus_receive(struct uart_softc *sc) 849 { 850 struct uart_bas *bas; 851 int xc; 852 uint8_t lsr; 853 854 bas = &sc->sc_bas; 855 uart_lock(sc->sc_hwmtx); 856 lsr = uart_getreg(bas, REG_LSR); 857 while (lsr & LSR_RXRDY) { 858 if (uart_rx_full(sc)) { 859 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 860 break; 861 } 862 xc = uart_getreg(bas, REG_DATA); 863 if (lsr & LSR_FE) 864 xc |= UART_STAT_FRAMERR; 865 if (lsr & LSR_PE) 866 xc |= UART_STAT_PARERR; 867 uart_rx_put(sc, xc); 868 lsr = uart_getreg(bas, REG_LSR); 869 } 870 /* Discard everything left in the Rx FIFO. */ 871 while (lsr & LSR_RXRDY) { 872 (void)uart_getreg(bas, REG_DATA); 873 uart_barrier(bas); 874 lsr = uart_getreg(bas, REG_LSR); 875 } 876 uart_unlock(sc->sc_hwmtx); 877 return (0); 878 } 879 880 int 881 ns8250_bus_setsig(struct uart_softc *sc, int sig) 882 { 883 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 884 struct uart_bas *bas; 885 uint32_t new, old; 886 887 bas = &sc->sc_bas; 888 do { 889 old = sc->sc_hwsig; 890 new = old; 891 if (sig & SER_DDTR) { 892 SIGCHG(sig & SER_DTR, new, SER_DTR, 893 SER_DDTR); 894 } 895 if (sig & SER_DRTS) { 896 SIGCHG(sig & SER_RTS, new, SER_RTS, 897 SER_DRTS); 898 } 899 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 900 uart_lock(sc->sc_hwmtx); 901 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 902 if (new & SER_DTR) 903 ns8250->mcr |= MCR_DTR; 904 if (new & SER_RTS) 905 ns8250->mcr |= MCR_RTS; 906 uart_setreg(bas, REG_MCR, ns8250->mcr); 907 uart_barrier(bas); 908 uart_unlock(sc->sc_hwmtx); 909 return (0); 910 } 911 912 int 913 ns8250_bus_transmit(struct uart_softc *sc) 914 { 915 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 916 struct uart_bas *bas; 917 int i; 918 919 bas = &sc->sc_bas; 920 uart_lock(sc->sc_hwmtx); 921 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 922 ; 923 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 924 uart_barrier(bas); 925 for (i = 0; i < sc->sc_txdatasz; i++) { 926 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 927 uart_barrier(bas); 928 } 929 if (broken_txfifo) 930 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 931 else 932 sc->sc_txbusy = 1; 933 uart_unlock(sc->sc_hwmtx); 934 if (broken_txfifo) 935 uart_sched_softih(sc, SER_INT_TXIDLE); 936 return (0); 937 } 938 939 void 940 ns8250_bus_grab(struct uart_softc *sc) 941 { 942 struct uart_bas *bas = &sc->sc_bas; 943 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 944 u_char ier; 945 946 /* 947 * turn off all interrupts to enter polling mode. Leave the 948 * saved mask alone. We'll restore whatever it was in ungrab. 949 * All pending interupt signals are reset when IER is set to 0. 950 */ 951 uart_lock(sc->sc_hwmtx); 952 ier = uart_getreg(bas, REG_IER); 953 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 954 uart_barrier(bas); 955 uart_unlock(sc->sc_hwmtx); 956 } 957 958 void 959 ns8250_bus_ungrab(struct uart_softc *sc) 960 { 961 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 962 struct uart_bas *bas = &sc->sc_bas; 963 964 /* 965 * Restore previous interrupt mask 966 */ 967 uart_lock(sc->sc_hwmtx); 968 uart_setreg(bas, REG_IER, ns8250->ier); 969 uart_barrier(bas); 970 uart_unlock(sc->sc_hwmtx); 971 } 972