1 /*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include "opt_platform.h" 28 #include "opt_uart.h" 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/kernel.h> 38 #include <sys/sysctl.h> 39 #include <machine/bus.h> 40 41 #ifdef FDT 42 #include <dev/fdt/fdt_common.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 #endif 46 47 #include <dev/uart/uart.h> 48 #include <dev/uart/uart_cpu.h> 49 #ifdef FDT 50 #include <dev/uart/uart_cpu_fdt.h> 51 #endif 52 #include <dev/uart/uart_bus.h> 53 #include <dev/uart/uart_dev_ns8250.h> 54 #include <dev/uart/uart_ppstypes.h> 55 56 #include <dev/ic/ns16550.h> 57 58 #include "uart_if.h" 59 60 #define DEFAULT_RCLK 1843200 61 62 /* 63 * Set the default baudrate tolerance to 3.0%. 64 * 65 * Some embedded boards have odd reference clocks (eg 25MHz) 66 * and we need to handle higher variances in the target baud rate. 67 */ 68 #ifndef UART_DEV_TOLERANCE_PCT 69 #define UART_DEV_TOLERANCE_PCT 30 70 #endif /* UART_DEV_TOLERANCE_PCT */ 71 72 static int broken_txfifo = 0; 73 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RWTUN, 74 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 75 76 /* 77 * Clear pending interrupts. THRE is cleared by reading IIR. Data 78 * that may have been received gets lost here. 79 */ 80 static void 81 ns8250_clrint(struct uart_bas *bas) 82 { 83 uint8_t iir, lsr; 84 85 iir = uart_getreg(bas, REG_IIR); 86 while ((iir & IIR_NOPEND) == 0) { 87 iir &= IIR_IMASK; 88 if (iir == IIR_RLS) { 89 lsr = uart_getreg(bas, REG_LSR); 90 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 91 (void)uart_getreg(bas, REG_DATA); 92 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 93 (void)uart_getreg(bas, REG_DATA); 94 else if (iir == IIR_MLSC) 95 (void)uart_getreg(bas, REG_MSR); 96 uart_barrier(bas); 97 iir = uart_getreg(bas, REG_IIR); 98 } 99 } 100 101 static int 102 ns8250_delay(struct uart_bas *bas) 103 { 104 int divisor; 105 u_char lcr; 106 107 lcr = uart_getreg(bas, REG_LCR); 108 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 109 uart_barrier(bas); 110 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 111 uart_barrier(bas); 112 uart_setreg(bas, REG_LCR, lcr); 113 uart_barrier(bas); 114 115 /* 1/10th the time to transmit 1 character (estimate). */ 116 if (divisor <= 134) 117 return (16000000 * divisor / bas->rclk); 118 return (16000 * divisor / (bas->rclk / 1000)); 119 } 120 121 static int 122 ns8250_divisor(int rclk, int baudrate) 123 { 124 int actual_baud, divisor; 125 int error; 126 127 if (baudrate == 0) 128 return (0); 129 130 divisor = (rclk / (baudrate << 3) + 1) >> 1; 131 if (divisor == 0 || divisor >= 65536) 132 return (0); 133 actual_baud = rclk / (divisor << 4); 134 135 /* 10 times error in percent: */ 136 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 137 138 /* enforce maximum error tolerance: */ 139 if (error < -UART_DEV_TOLERANCE_PCT || error > UART_DEV_TOLERANCE_PCT) 140 return (0); 141 142 return (divisor); 143 } 144 145 static int 146 ns8250_drain(struct uart_bas *bas, int what) 147 { 148 int delay, limit; 149 150 delay = ns8250_delay(bas); 151 152 if (what & UART_DRAIN_TRANSMITTER) { 153 /* 154 * Pick an arbitrary high limit to avoid getting stuck in 155 * an infinite loop when the hardware is broken. Make the 156 * limit high enough to handle large FIFOs. 157 */ 158 limit = 10*1024; 159 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 160 DELAY(delay); 161 if (limit == 0) { 162 /* printf("ns8250: transmitter appears stuck... "); */ 163 return (EIO); 164 } 165 } 166 167 if (what & UART_DRAIN_RECEIVER) { 168 /* 169 * Pick an arbitrary high limit to avoid getting stuck in 170 * an infinite loop when the hardware is broken. Make the 171 * limit high enough to handle large FIFOs and integrated 172 * UARTs. The HP rx2600 for example has 3 UARTs on the 173 * management board that tend to get a lot of data send 174 * to it when the UART is first activated. 175 */ 176 limit=10*4096; 177 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 178 (void)uart_getreg(bas, REG_DATA); 179 uart_barrier(bas); 180 DELAY(delay << 2); 181 } 182 if (limit == 0) { 183 /* printf("ns8250: receiver appears broken... "); */ 184 return (EIO); 185 } 186 } 187 188 return (0); 189 } 190 191 /* 192 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 193 * drained. WARNING: this function clobbers the FIFO setting! 194 */ 195 static void 196 ns8250_flush(struct uart_bas *bas, int what) 197 { 198 uint8_t fcr; 199 200 fcr = FCR_ENABLE; 201 #ifdef CPU_XBURST 202 fcr |= FCR_UART_ON; 203 #endif 204 if (what & UART_FLUSH_TRANSMITTER) 205 fcr |= FCR_XMT_RST; 206 if (what & UART_FLUSH_RECEIVER) 207 fcr |= FCR_RCV_RST; 208 uart_setreg(bas, REG_FCR, fcr); 209 uart_barrier(bas); 210 } 211 212 static int 213 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 214 int parity) 215 { 216 int divisor; 217 uint8_t lcr; 218 219 lcr = 0; 220 if (databits >= 8) 221 lcr |= LCR_8BITS; 222 else if (databits == 7) 223 lcr |= LCR_7BITS; 224 else if (databits == 6) 225 lcr |= LCR_6BITS; 226 else 227 lcr |= LCR_5BITS; 228 if (stopbits > 1) 229 lcr |= LCR_STOPB; 230 lcr |= parity << 3; 231 232 /* Set baudrate. */ 233 if (baudrate > 0) { 234 divisor = ns8250_divisor(bas->rclk, baudrate); 235 if (divisor == 0) 236 return (EINVAL); 237 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 238 uart_barrier(bas); 239 uart_setreg(bas, REG_DLL, divisor & 0xff); 240 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 241 uart_barrier(bas); 242 } 243 244 /* Set LCR and clear DLAB. */ 245 uart_setreg(bas, REG_LCR, lcr); 246 uart_barrier(bas); 247 return (0); 248 } 249 250 /* 251 * Low-level UART interface. 252 */ 253 static int ns8250_probe(struct uart_bas *bas); 254 static void ns8250_init(struct uart_bas *bas, int, int, int, int); 255 static void ns8250_term(struct uart_bas *bas); 256 static void ns8250_putc(struct uart_bas *bas, int); 257 static int ns8250_rxready(struct uart_bas *bas); 258 static int ns8250_getc(struct uart_bas *bas, struct mtx *); 259 260 struct uart_ops uart_ns8250_ops = { 261 .probe = ns8250_probe, 262 .init = ns8250_init, 263 .term = ns8250_term, 264 .putc = ns8250_putc, 265 .rxready = ns8250_rxready, 266 .getc = ns8250_getc, 267 }; 268 269 static int 270 ns8250_probe(struct uart_bas *bas) 271 { 272 u_char val; 273 274 #ifdef CPU_XBURST 275 uart_setreg(bas, REG_FCR, FCR_UART_ON); 276 #endif 277 278 /* Check known 0 bits that don't depend on DLAB. */ 279 val = uart_getreg(bas, REG_IIR); 280 if (val & 0x30) 281 return (ENXIO); 282 /* 283 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 284 * chip, but otherwise doesn't seem to have a function. In 285 * other words, uart(4) works regardless. Ignore that bit so 286 * the probe succeeds. 287 */ 288 val = uart_getreg(bas, REG_MCR); 289 if (val & 0xa0) 290 return (ENXIO); 291 292 return (0); 293 } 294 295 static void 296 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 297 int parity) 298 { 299 u_char ier, val; 300 301 if (bas->rclk == 0) 302 bas->rclk = DEFAULT_RCLK; 303 ns8250_param(bas, baudrate, databits, stopbits, parity); 304 305 /* Disable all interrupt sources. */ 306 /* 307 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 308 * UARTs split the receive time-out interrupt bit out separately as 309 * 0x10. This gets handled by ier_mask and ier_rxbits below. 310 */ 311 ier = uart_getreg(bas, REG_IER) & 0xe0; 312 uart_setreg(bas, REG_IER, ier); 313 uart_barrier(bas); 314 315 /* Disable the FIFO (if present). */ 316 val = 0; 317 #ifdef CPU_XBURST 318 val |= FCR_UART_ON; 319 #endif 320 uart_setreg(bas, REG_FCR, val); 321 uart_barrier(bas); 322 323 /* Set RTS & DTR. */ 324 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 325 uart_barrier(bas); 326 327 ns8250_clrint(bas); 328 } 329 330 static void 331 ns8250_term(struct uart_bas *bas) 332 { 333 334 /* Clear RTS & DTR. */ 335 uart_setreg(bas, REG_MCR, MCR_IE); 336 uart_barrier(bas); 337 } 338 339 static void 340 ns8250_putc(struct uart_bas *bas, int c) 341 { 342 int limit; 343 344 limit = 250000; 345 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 346 DELAY(4); 347 uart_setreg(bas, REG_DATA, c); 348 uart_barrier(bas); 349 } 350 351 static int 352 ns8250_rxready(struct uart_bas *bas) 353 { 354 355 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 356 } 357 358 static int 359 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 360 { 361 int c; 362 363 uart_lock(hwmtx); 364 365 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 366 uart_unlock(hwmtx); 367 DELAY(4); 368 uart_lock(hwmtx); 369 } 370 371 c = uart_getreg(bas, REG_DATA); 372 373 uart_unlock(hwmtx); 374 375 return (c); 376 } 377 378 static kobj_method_t ns8250_methods[] = { 379 KOBJMETHOD(uart_attach, ns8250_bus_attach), 380 KOBJMETHOD(uart_detach, ns8250_bus_detach), 381 KOBJMETHOD(uart_flush, ns8250_bus_flush), 382 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 383 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 384 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 385 KOBJMETHOD(uart_param, ns8250_bus_param), 386 KOBJMETHOD(uart_probe, ns8250_bus_probe), 387 KOBJMETHOD(uart_receive, ns8250_bus_receive), 388 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 389 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 390 KOBJMETHOD(uart_grab, ns8250_bus_grab), 391 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 392 { 0, 0 } 393 }; 394 395 struct uart_class uart_ns8250_class = { 396 "ns8250", 397 ns8250_methods, 398 sizeof(struct ns8250_softc), 399 .uc_ops = &uart_ns8250_ops, 400 .uc_range = 8, 401 .uc_rclk = DEFAULT_RCLK, 402 .uc_rshift = 0 403 }; 404 405 #ifdef FDT 406 static struct ofw_compat_data compat_data[] = { 407 {"ns16550", (uintptr_t)&uart_ns8250_class}, 408 {"ns16550a", (uintptr_t)&uart_ns8250_class}, 409 {NULL, (uintptr_t)NULL}, 410 }; 411 UART_FDT_CLASS_AND_DEVICE(compat_data); 412 #endif 413 414 /* Use token-pasting to form SER_ and MSR_ named constants. */ 415 #define SER(sig) SER_##sig 416 #define SERD(sig) SER_D##sig 417 #define MSR(sig) MSR_##sig 418 #define MSRD(sig) MSR_D##sig 419 420 /* 421 * Detect signal changes using software delta detection. The previous state of 422 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the 423 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the 424 * new state of both the signal and the delta bits. 425 */ 426 #define SIGCHGSW(var, msr, sig) \ 427 if ((msr) & MSR(sig)) { \ 428 if ((var & SER(sig)) == 0) \ 429 var |= SERD(sig) | SER(sig); \ 430 } else { \ 431 if ((var & SER(sig)) != 0) \ 432 var = SERD(sig) | (var & ~SER(sig)); \ 433 } 434 435 /* 436 * Detect signal changes using the hardware msr delta bits. This is currently 437 * used only when PPS timing information is being captured using the "narrow 438 * pulse" option. With a narrow PPS pulse the signal may not still be asserted 439 * by time the interrupt handler is invoked. The hardware will latch the fact 440 * that it changed in the delta bits. 441 */ 442 #define SIGCHGHW(var, msr, sig) \ 443 if ((msr) & MSRD(sig)) { \ 444 if (((msr) & MSR(sig)) != 0) \ 445 var |= SERD(sig) | SER(sig); \ 446 else \ 447 var = SERD(sig) | (var & ~SER(sig)); \ 448 } 449 450 int 451 ns8250_bus_attach(struct uart_softc *sc) 452 { 453 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 454 struct uart_bas *bas; 455 unsigned int ivar; 456 #ifdef FDT 457 phandle_t node; 458 pcell_t cell; 459 #endif 460 461 #ifdef FDT 462 /* Check whether uart has a broken txfifo. */ 463 node = ofw_bus_get_node(sc->sc_dev); 464 if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 465 broken_txfifo = cell ? 1 : 0; 466 #endif 467 468 bas = &sc->sc_bas; 469 470 ns8250->mcr = uart_getreg(bas, REG_MCR); 471 ns8250->fcr = FCR_ENABLE; 472 #ifdef CPU_XBURST 473 ns8250->fcr |= FCR_UART_ON; 474 #endif 475 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 476 &ivar)) { 477 if (UART_FLAGS_FCR_RX_LOW(ivar)) 478 ns8250->fcr |= FCR_RX_LOW; 479 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 480 ns8250->fcr |= FCR_RX_MEDL; 481 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 482 ns8250->fcr |= FCR_RX_HIGH; 483 else 484 ns8250->fcr |= FCR_RX_MEDH; 485 } else 486 ns8250->fcr |= FCR_RX_MEDH; 487 488 /* Get IER mask */ 489 ivar = 0xf0; 490 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 491 &ivar); 492 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 493 494 /* Get IER RX interrupt bits */ 495 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 496 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 497 &ivar); 498 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 499 500 uart_setreg(bas, REG_FCR, ns8250->fcr); 501 uart_barrier(bas); 502 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 503 504 if (ns8250->mcr & MCR_DTR) 505 sc->sc_hwsig |= SER_DTR; 506 if (ns8250->mcr & MCR_RTS) 507 sc->sc_hwsig |= SER_RTS; 508 ns8250_bus_getsig(sc); 509 510 ns8250_clrint(bas); 511 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 512 ns8250->ier |= ns8250->ier_rxbits; 513 uart_setreg(bas, REG_IER, ns8250->ier); 514 uart_barrier(bas); 515 516 /* 517 * Timing of the H/W access was changed with r253161 of uart_core.c 518 * It has been observed that an ITE IT8513E would signal a break 519 * condition with pretty much every character it received, unless 520 * it had enough time to settle between ns8250_bus_attach() and 521 * ns8250_bus_ipend() -- which it accidentally had before r253161. 522 * It's not understood why the UART chip behaves this way and it 523 * could very well be that the DELAY make the H/W work in the same 524 * accidental manner as before. More analysis is warranted, but 525 * at least now we fixed a known regression. 526 */ 527 DELAY(200); 528 return (0); 529 } 530 531 int 532 ns8250_bus_detach(struct uart_softc *sc) 533 { 534 struct ns8250_softc *ns8250; 535 struct uart_bas *bas; 536 u_char ier; 537 538 ns8250 = (struct ns8250_softc *)sc; 539 bas = &sc->sc_bas; 540 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 541 uart_setreg(bas, REG_IER, ier); 542 uart_barrier(bas); 543 ns8250_clrint(bas); 544 return (0); 545 } 546 547 int 548 ns8250_bus_flush(struct uart_softc *sc, int what) 549 { 550 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 551 struct uart_bas *bas; 552 int error; 553 554 bas = &sc->sc_bas; 555 uart_lock(sc->sc_hwmtx); 556 if (sc->sc_rxfifosz > 1) { 557 ns8250_flush(bas, what); 558 uart_setreg(bas, REG_FCR, ns8250->fcr); 559 uart_barrier(bas); 560 error = 0; 561 } else 562 error = ns8250_drain(bas, what); 563 uart_unlock(sc->sc_hwmtx); 564 return (error); 565 } 566 567 int 568 ns8250_bus_getsig(struct uart_softc *sc) 569 { 570 uint32_t old, sig; 571 uint8_t msr; 572 573 /* 574 * The delta bits are reputed to be broken on some hardware, so use 575 * software delta detection by default. Use the hardware delta bits 576 * when capturing PPS pulses which are too narrow for software detection 577 * to see the edges. Hardware delta for RI doesn't work like the 578 * others, so always use software for it. Other threads may be changing 579 * other (non-MSR) bits in sc_hwsig, so loop until it can successfully 580 * update without other changes happening. Note that the SIGCHGxx() 581 * macros carefully preserve the delta bits when we have to loop several 582 * times and a signal transitions between iterations. 583 */ 584 do { 585 old = sc->sc_hwsig; 586 sig = old; 587 uart_lock(sc->sc_hwmtx); 588 msr = uart_getreg(&sc->sc_bas, REG_MSR); 589 uart_unlock(sc->sc_hwmtx); 590 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { 591 SIGCHGHW(sig, msr, DSR); 592 SIGCHGHW(sig, msr, CTS); 593 SIGCHGHW(sig, msr, DCD); 594 } else { 595 SIGCHGSW(sig, msr, DSR); 596 SIGCHGSW(sig, msr, CTS); 597 SIGCHGSW(sig, msr, DCD); 598 } 599 SIGCHGSW(sig, msr, RI); 600 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); 601 return (sig); 602 } 603 604 int 605 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 606 { 607 struct uart_bas *bas; 608 int baudrate, divisor, error; 609 uint8_t efr, lcr; 610 611 bas = &sc->sc_bas; 612 error = 0; 613 uart_lock(sc->sc_hwmtx); 614 switch (request) { 615 case UART_IOCTL_BREAK: 616 lcr = uart_getreg(bas, REG_LCR); 617 if (data) 618 lcr |= LCR_SBREAK; 619 else 620 lcr &= ~LCR_SBREAK; 621 uart_setreg(bas, REG_LCR, lcr); 622 uart_barrier(bas); 623 break; 624 case UART_IOCTL_IFLOW: 625 lcr = uart_getreg(bas, REG_LCR); 626 uart_barrier(bas); 627 uart_setreg(bas, REG_LCR, 0xbf); 628 uart_barrier(bas); 629 efr = uart_getreg(bas, REG_EFR); 630 if (data) 631 efr |= EFR_RTS; 632 else 633 efr &= ~EFR_RTS; 634 uart_setreg(bas, REG_EFR, efr); 635 uart_barrier(bas); 636 uart_setreg(bas, REG_LCR, lcr); 637 uart_barrier(bas); 638 break; 639 case UART_IOCTL_OFLOW: 640 lcr = uart_getreg(bas, REG_LCR); 641 uart_barrier(bas); 642 uart_setreg(bas, REG_LCR, 0xbf); 643 uart_barrier(bas); 644 efr = uart_getreg(bas, REG_EFR); 645 if (data) 646 efr |= EFR_CTS; 647 else 648 efr &= ~EFR_CTS; 649 uart_setreg(bas, REG_EFR, efr); 650 uart_barrier(bas); 651 uart_setreg(bas, REG_LCR, lcr); 652 uart_barrier(bas); 653 break; 654 case UART_IOCTL_BAUD: 655 lcr = uart_getreg(bas, REG_LCR); 656 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 657 uart_barrier(bas); 658 divisor = uart_getreg(bas, REG_DLL) | 659 (uart_getreg(bas, REG_DLH) << 8); 660 uart_barrier(bas); 661 uart_setreg(bas, REG_LCR, lcr); 662 uart_barrier(bas); 663 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 664 if (baudrate > 0) 665 *(int*)data = baudrate; 666 else 667 error = ENXIO; 668 break; 669 default: 670 error = EINVAL; 671 break; 672 } 673 uart_unlock(sc->sc_hwmtx); 674 return (error); 675 } 676 677 int 678 ns8250_bus_ipend(struct uart_softc *sc) 679 { 680 struct uart_bas *bas; 681 struct ns8250_softc *ns8250; 682 int ipend; 683 uint8_t iir, lsr; 684 685 ns8250 = (struct ns8250_softc *)sc; 686 bas = &sc->sc_bas; 687 uart_lock(sc->sc_hwmtx); 688 iir = uart_getreg(bas, REG_IIR); 689 690 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 691 (void)uart_getreg(bas, DW_REG_USR); 692 uart_unlock(sc->sc_hwmtx); 693 return (0); 694 } 695 if (iir & IIR_NOPEND) { 696 uart_unlock(sc->sc_hwmtx); 697 return (0); 698 } 699 ipend = 0; 700 if (iir & IIR_RXRDY) { 701 lsr = uart_getreg(bas, REG_LSR); 702 if (lsr & LSR_OE) 703 ipend |= SER_INT_OVERRUN; 704 if (lsr & LSR_BI) 705 ipend |= SER_INT_BREAK; 706 if (lsr & LSR_RXRDY) 707 ipend |= SER_INT_RXREADY; 708 } else { 709 if (iir & IIR_TXRDY) { 710 ipend |= SER_INT_TXIDLE; 711 uart_setreg(bas, REG_IER, ns8250->ier); 712 uart_barrier(bas); 713 } else 714 ipend |= SER_INT_SIGCHG; 715 } 716 if (ipend == 0) 717 ns8250_clrint(bas); 718 uart_unlock(sc->sc_hwmtx); 719 return (ipend); 720 } 721 722 int 723 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 724 int stopbits, int parity) 725 { 726 struct ns8250_softc *ns8250; 727 struct uart_bas *bas; 728 int error, limit; 729 730 ns8250 = (struct ns8250_softc*)sc; 731 bas = &sc->sc_bas; 732 uart_lock(sc->sc_hwmtx); 733 /* 734 * When using DW UART with BUSY detection it is necessary to wait 735 * until all serial transfers are finished before manipulating the 736 * line control. LCR will not be affected when UART is busy. 737 */ 738 if (ns8250->busy_detect != 0) { 739 /* 740 * Pick an arbitrary high limit to avoid getting stuck in 741 * an infinite loop in case when the hardware is broken. 742 */ 743 limit = 10 * 1024; 744 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 745 --limit) 746 DELAY(4); 747 748 if (limit <= 0) { 749 /* UART appears to be stuck */ 750 uart_unlock(sc->sc_hwmtx); 751 return (EIO); 752 } 753 } 754 755 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 756 uart_unlock(sc->sc_hwmtx); 757 return (error); 758 } 759 760 int 761 ns8250_bus_probe(struct uart_softc *sc) 762 { 763 struct ns8250_softc *ns8250; 764 struct uart_bas *bas; 765 int count, delay, error, limit; 766 uint8_t lsr, mcr, ier; 767 uint8_t val; 768 769 ns8250 = (struct ns8250_softc *)sc; 770 bas = &sc->sc_bas; 771 772 error = ns8250_probe(bas); 773 if (error) 774 return (error); 775 776 mcr = MCR_IE; 777 if (sc->sc_sysdev == NULL) { 778 /* By using ns8250_init() we also set DTR and RTS. */ 779 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 780 } else 781 mcr |= MCR_DTR | MCR_RTS; 782 783 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 784 if (error) 785 return (error); 786 787 /* 788 * Set loopback mode. This avoids having garbage on the wire and 789 * also allows us send and receive data. We set DTR and RTS to 790 * avoid the possibility that automatic flow-control prevents 791 * any data from being sent. 792 */ 793 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 794 uart_barrier(bas); 795 796 /* 797 * Enable FIFOs. And check that the UART has them. If not, we're 798 * done. Since this is the first time we enable the FIFOs, we reset 799 * them. 800 */ 801 val = FCR_ENABLE; 802 #ifdef CPU_XBURST 803 val |= FCR_UART_ON; 804 #endif 805 uart_setreg(bas, REG_FCR, val); 806 uart_barrier(bas); 807 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 808 /* 809 * NS16450 or INS8250. We don't bother to differentiate 810 * between them. They're too old to be interesting. 811 */ 812 uart_setreg(bas, REG_MCR, mcr); 813 uart_barrier(bas); 814 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 815 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 816 return (0); 817 } 818 819 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST; 820 #ifdef CPU_XBURST 821 val |= FCR_UART_ON; 822 #endif 823 uart_setreg(bas, REG_FCR, val); 824 uart_barrier(bas); 825 826 count = 0; 827 delay = ns8250_delay(bas); 828 829 /* We have FIFOs. Drain the transmitter and receiver. */ 830 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 831 if (error) { 832 uart_setreg(bas, REG_MCR, mcr); 833 val = 0; 834 #ifdef CPU_XBURST 835 val |= FCR_UART_ON; 836 #endif 837 uart_setreg(bas, REG_FCR, val); 838 uart_barrier(bas); 839 goto describe; 840 } 841 842 /* 843 * We should have a sufficiently clean "pipe" to determine the 844 * size of the FIFOs. We send as much characters as is reasonable 845 * and wait for the overflow bit in the LSR register to be 846 * asserted, counting the characters as we send them. Based on 847 * that count we know the FIFO size. 848 */ 849 do { 850 uart_setreg(bas, REG_DATA, 0); 851 uart_barrier(bas); 852 count++; 853 854 limit = 30; 855 lsr = 0; 856 /* 857 * LSR bits are cleared upon read, so we must accumulate 858 * them to be able to test LSR_OE below. 859 */ 860 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 861 --limit) 862 DELAY(delay); 863 if (limit == 0) { 864 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 865 uart_setreg(bas, REG_IER, ier); 866 uart_setreg(bas, REG_MCR, mcr); 867 val = 0; 868 #ifdef CPU_XBURST 869 val |= FCR_UART_ON; 870 #endif 871 uart_setreg(bas, REG_FCR, val); 872 uart_barrier(bas); 873 count = 0; 874 goto describe; 875 } 876 } while ((lsr & LSR_OE) == 0 && count < 130); 877 count--; 878 879 uart_setreg(bas, REG_MCR, mcr); 880 881 /* Reset FIFOs. */ 882 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 883 884 describe: 885 if (count >= 14 && count <= 16) { 886 sc->sc_rxfifosz = 16; 887 device_set_desc(sc->sc_dev, "16550 or compatible"); 888 } else if (count >= 28 && count <= 32) { 889 sc->sc_rxfifosz = 32; 890 device_set_desc(sc->sc_dev, "16650 or compatible"); 891 } else if (count >= 56 && count <= 64) { 892 sc->sc_rxfifosz = 64; 893 device_set_desc(sc->sc_dev, "16750 or compatible"); 894 } else if (count >= 112 && count <= 128) { 895 sc->sc_rxfifosz = 128; 896 device_set_desc(sc->sc_dev, "16950 or compatible"); 897 } else { 898 sc->sc_rxfifosz = 16; 899 device_set_desc(sc->sc_dev, 900 "Non-standard ns8250 class UART with FIFOs"); 901 } 902 903 /* 904 * Force the Tx FIFO size to 16 bytes for now. We don't program the 905 * Tx trigger. Also, we assume that all data has been sent when the 906 * interrupt happens. 907 */ 908 sc->sc_txfifosz = 16; 909 910 #if 0 911 /* 912 * XXX there are some issues related to hardware flow control and 913 * it's likely that uart(4) is the cause. This basically needs more 914 * investigation, but we avoid using for hardware flow control 915 * until then. 916 */ 917 /* 16650s or higher have automatic flow control. */ 918 if (sc->sc_rxfifosz > 16) { 919 sc->sc_hwiflow = 1; 920 sc->sc_hwoflow = 1; 921 } 922 #endif 923 924 return (0); 925 } 926 927 int 928 ns8250_bus_receive(struct uart_softc *sc) 929 { 930 struct uart_bas *bas; 931 int xc; 932 uint8_t lsr; 933 934 bas = &sc->sc_bas; 935 uart_lock(sc->sc_hwmtx); 936 lsr = uart_getreg(bas, REG_LSR); 937 while (lsr & LSR_RXRDY) { 938 if (uart_rx_full(sc)) { 939 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 940 break; 941 } 942 xc = uart_getreg(bas, REG_DATA); 943 if (lsr & LSR_FE) 944 xc |= UART_STAT_FRAMERR; 945 if (lsr & LSR_PE) 946 xc |= UART_STAT_PARERR; 947 uart_rx_put(sc, xc); 948 lsr = uart_getreg(bas, REG_LSR); 949 } 950 /* Discard everything left in the Rx FIFO. */ 951 while (lsr & LSR_RXRDY) { 952 (void)uart_getreg(bas, REG_DATA); 953 uart_barrier(bas); 954 lsr = uart_getreg(bas, REG_LSR); 955 } 956 uart_unlock(sc->sc_hwmtx); 957 return (0); 958 } 959 960 int 961 ns8250_bus_setsig(struct uart_softc *sc, int sig) 962 { 963 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 964 struct uart_bas *bas; 965 uint32_t new, old; 966 967 bas = &sc->sc_bas; 968 do { 969 old = sc->sc_hwsig; 970 new = old; 971 if (sig & SER_DDTR) { 972 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); 973 } 974 if (sig & SER_DRTS) { 975 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); 976 } 977 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 978 uart_lock(sc->sc_hwmtx); 979 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 980 if (new & SER_DTR) 981 ns8250->mcr |= MCR_DTR; 982 if (new & SER_RTS) 983 ns8250->mcr |= MCR_RTS; 984 uart_setreg(bas, REG_MCR, ns8250->mcr); 985 uart_barrier(bas); 986 uart_unlock(sc->sc_hwmtx); 987 return (0); 988 } 989 990 int 991 ns8250_bus_transmit(struct uart_softc *sc) 992 { 993 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 994 struct uart_bas *bas; 995 int i; 996 997 bas = &sc->sc_bas; 998 uart_lock(sc->sc_hwmtx); 999 if (sc->sc_txdatasz > 1) { 1000 if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 1001 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1002 } else { 1003 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 1004 DELAY(4); 1005 } 1006 for (i = 0; i < sc->sc_txdatasz; i++) { 1007 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 1008 uart_barrier(bas); 1009 } 1010 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 1011 uart_barrier(bas); 1012 if (broken_txfifo) 1013 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 1014 else 1015 sc->sc_txbusy = 1; 1016 uart_unlock(sc->sc_hwmtx); 1017 if (broken_txfifo) 1018 uart_sched_softih(sc, SER_INT_TXIDLE); 1019 return (0); 1020 } 1021 1022 void 1023 ns8250_bus_grab(struct uart_softc *sc) 1024 { 1025 struct uart_bas *bas = &sc->sc_bas; 1026 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1027 u_char ier; 1028 1029 /* 1030 * turn off all interrupts to enter polling mode. Leave the 1031 * saved mask alone. We'll restore whatever it was in ungrab. 1032 * All pending interrupt signals are reset when IER is set to 0. 1033 */ 1034 uart_lock(sc->sc_hwmtx); 1035 ier = uart_getreg(bas, REG_IER); 1036 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 1037 uart_barrier(bas); 1038 uart_unlock(sc->sc_hwmtx); 1039 } 1040 1041 void 1042 ns8250_bus_ungrab(struct uart_softc *sc) 1043 { 1044 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 1045 struct uart_bas *bas = &sc->sc_bas; 1046 1047 /* 1048 * Restore previous interrupt mask 1049 */ 1050 uart_lock(sc->sc_hwmtx); 1051 uart_setreg(bas, REG_IER, ns8250->ier); 1052 uart_barrier(bas); 1053 uart_unlock(sc->sc_hwmtx); 1054 } 1055